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NXP Semiconductors MSC8158E Reference Manual

Broadband wireless access six core dsp with security

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MSC8158E Reference Manual

Broadband Wireless Access Six Core DSP With Security

MSC8158ERM

Rev 2, January 2012

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Page 1 MSC8158E Reference Manual Broadband Wireless Access Six Core DSP With Security MSC8158ERM Rev 2, January 2012...
Page 2 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support North America: Freescale Semiconductor, Inc. Technical Sales and Commercial Support Information in this document is provided solely to enable system and software Periferico Sur #8110 implementers to use Freescale Semiconductor products. There are no express or Col.
Page 3 Overview SC3850 Core Overview External Signals Chip-Level Arbitration and Switching System (CLASS) Reset Boot Program Clocks General Configuration Registers Memory Map MSC8158 SC3850 DSP Subsystem Internal Memory Subsystem DDR-SDRAM Controller Interrupt Handling Direct Memory Access (DMA) Controller High Speed Serial Interface (HSSI) Serial RapidIO Controller and Enhance Message Complex Common Public Radio Interface (CPRI) QUICC Engine Subsystem...
Page 4 Overview SC3850 Core Overview External Signals Chip-Level Arbitration and Switching System (CLASS) Reset Boot Program Clocks General Configuration Registers Memory Map MSC8158 SC3850 DSP Subsystem Internal Memory Subsystem DDR-SDRAM Controller Interrupt Handling Direct Memory Access (DMA) Controller High Speed Serial Interface (HSSI) Serial RapidIO Controller and Enhance Message Complex Common Public Radio Interface (CPRI) QUICC Engine Subsystem...
Page 5: Table Of Contents
Organization ........... . lxx Other MSC8158E Documentation ........lxxiii Further Reading .
Page 6 OCE Event and JTAG Test Access Port Signals ......3-29 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 7 CLASS Profiling Control Register (C0PCR) ......4-32 4.7.17 CLASS Watch Point Control Registers (C0WPCR) ....4-33 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 8 Reset Configuration Word Low Register (RCWLR) ....5-16 5.3.2 Reset Configuration Word High Register (RCWHR)....5-20 MSC8158E Reference Manual, Rev. 2 viii Freescale Semiconductor...
Page 9 General Status Register 1 (GSR1)........8-6 8.2.4 High Speed Serial Interface Status Register (HSSI_SR) ....8-8 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 10 General Interrupt Register 6 (GIR6) ....... . 8-68 8.2.41 General Interrupt Enable Register 6 (GIER6_x)..... . . 8-71 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 11 QBus to MBus Interface Bridge ........10-11 MSC8158E Reference Manual, Rev. 2...
Page 12 Self-Refresh Mode Usage ........12-32 MSC8158E Reference Manual, Rev. 2...
Page 13 DDR SDRAM IP Block Revision 1 Register (DDR_IP_REV1) ..12-92 12.5.34 DDR SDRAM IP Block Revision 2 Register (DDR_IP_REV2) ..12-92 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor xiii...
Page 14 Programming Restrictions........13-30 MSC8158E Reference Manual, Rev. 2...
Page 15 DMA Time-To-Dead Line Registers x (DMAEDFTDLx) ....14-34 14.6.9 DMA EDF Control Register (DMAEDFCTRL)..... . 14-35 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 16 Basic DMA Mode Transfer ........15-16 MSC8158E Reference Manual, Rev. 2...
Page 17 15.9.13 CLASS1 Attributes Decoder 1 (C1ATD1) ......15-47 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 18 SRDS Bank 1 Reset Control Register (SRDSB1RSTCTL) ... . . 15-94 15.9.53 SRDS Bank 2 Reset Control Register (SRDSB2RSTCTL) ... . . 15-95 MSC8158E Reference Manual, Rev. 2 xviii Freescale Semiconductor...
Page 19 RapidIO Interface Activation ........16-9 16.1.6.1 Initialization for Booting the MSC8158E DSP ..... . 16-9 16.1.6.2 Initialization for Non-Boot Operation .
Page 20 Type6 Outbound SWrite Operation ......16-107 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 21 Size Mismatch Errors ......... . 16-129 MSC8158E Reference Manual, Rev. 2...
Page 22 Retry Response Condition ........16-154 MSC8158E Reference Manual, Rev. 2...
Page 23 (PELLCCSR) ..........16-190 MSC8158E Reference Manual, Rev. 2...
Page 24 (PnPECCSR2) ..........16-215 MSC8158E Reference Manual, Rev. 2...
Page 25 (PnROWBARx) ..........16-240 MSC8158E Reference Manual, Rev. 2...
Page 26 (IBmT9CnDOR)..........16-263 MSC8158E Reference Manual, Rev. 2...
Page 27 (IBmMQnEPAR) ......... . . 16-284 MSC8158E Reference Manual, Rev. 2...
Page 28 (OMQDSCR1) ..........16-314 MSC8158E Reference Manual, Rev. 2...
Page 29 Message Unit T9 Drop Counter Registers (MUT9DCR)... . . 16-343 16.4.2.100 Message Unit Error Capture MQ Register (MUECMQR)... . 16-344 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor xxix...
Page 30 CPRI DMA Controller ......... 17-28 17.3.3.1 Receive DMA and Transmit DMA Memories ..... . 17-29 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 31 CPRI Recovered HFN Counter (CPRIn_HFN) ..... 17-69 17.4.1.6 CPRI Hardware Reset from Control Word (CPRIn_HW_RESET) ..17-70 17.4.1.7 CPRI Control and Management Configuration (CPRIn_CM_CONFIG) . 17-71 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor xxxi...
Page 32 (CPRIn_HDLC_CONFIG_1)........17-92 17.4.1.37 HDLC Miscellaneous Configuration (CPRIn_HDLC_CONFIG_2) ..17-93 17.4.1.38 HDLC RX Packet Discard (CPRIn_HDLC_RX_CONTROL) ..17-94 MSC8158E Reference Manual, Rev. 2 xxxii Freescale Semiconductor...
Page 33 Transmit Control Register (CPRInTCR) ......17-121 17.4.3.3 Receive AxC Control Register (CPRInRACCR) ....17-122 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor xxxiii...
Page 34 Receive Chips Counter Register (CPRInRCCR) ....17-155 17.4.4.5 Receive VSS Buffer Displacement Register (CPRInRVSSBDR) ..17-156 MSC8158E Reference Manual, Rev. 2 xxxiv Freescale Semiconductor...
Page 35 Simple Recovery from Bus Error ....... . . 18-9 MSC8158E Reference Manual, Rev. 2...
Page 36 SPI as a Master Device........18-30 MSC8158E Reference Manual, Rev. 2...
Page 37 Device-Level Timers ..........20-1 MSC8158E Reference Manual, Rev. 2...
Page 38 Timer Channel Counter Registers (TMRnCNTRx) ....20-28 20.4.1.12 Timer_32b Channel x Compare 1 Registers (TMR_32b_n_CMP1_x) . . . 20-29 20.4.1.13 Timer_32b Channel x Compare 2 Registers (TMR_32b_n_CMP2_x) . . . 20-29 MSC8158E Reference Manual, Rev. 2 xxxviii Freescale Semiconductor...
Page 39 Clock Control ..........23-3 MSC8158E Reference Manual, Rev. 2...
Page 40 Instruction Decoding ..........24-5 24.1.4 Multi-Core JTAG and OCE Module Concept......24-9 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 41 Signalling a Debug Request ........24-12 24.1.10 EE_CTRL Modifications for the MSC8158E ......24-13 24.1.11 ESEL_DM and EDCA_CTRL Register Programming.
Page 42 BD Rings Done Indication Interrupts ......25-25 MSC8158E Reference Manual, Rev. 2...
Page 43 Feed Forward ..........25-59 MSC8158E Reference Manual, Rev. 2...
Page 44 Code Generation with Zero Padding ......25-101 MSC8158E Reference Manual, Rev. 2...
Page 45 Rate Matching ..........25-131 MSC8158E Reference Manual, Rev. 2...
Page 46 Interpolation x2: INT_MODE = 1 ......25-162 MSC8158E Reference Manual, Rev. 2...
Page 47 Despreading and Descrambling (DD) ......25-190 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 48 Initialization of CPRI Output Mode ......25-229 MSC8158E Reference Manual, Rev. 2...
Page 49 MAPLE-B2 Power Gating Scheme....... 25-259 MSC8158E Reference Manual, Rev. 2...
Page 50 CRPE General Parameter Description......25-294 25.5.3.4.1.1 MAPLE CRPE Reset Completion Indication Parameter (MCRRCIP) ..25-294 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 51 MAPLE CRPE-D1L Fast Channel <x> Parameter 0 (MCDLFCxP0) ..25-321 25.5.3.4.4.6 MAPLE CRPE-DL Fast Channel <x> Parameter 1 (MCDLFCxP1) ..25-322 25.5.3.4.4.7 MAPLE CRPE-DL Slot Channel <x> Parameter 2 (MCDLSCxP2) ..25-324 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 52 DEPE Header Structure for 3GLTE ......25-393 MSC8158E Reference Manual, Rev. 2...
Page 53 (CRUBGNOAxCR) ........25-453 25.5.5.4.5 CRPE-ULB Event Status Register (CRUBESR)....25-454 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor liii...
Page 54 CRPE-DL Start Control Register (CDSLR) ..... 25-494 25.5.5.6.16 CRPE-DL TPC Command Control Register (CDTCLR) ... 25-495 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 55 Arbitration Among Channels ........26-17 MSC8158E Reference Manual, Rev. 2...
Page 56 Scalar Point Multiply in Affine Coordinates (0x06) ....26-32 26.6.1.11.8 EC_FP_PROJ_PTMULT: Prime Field Elliptic Curve Scalar Point Multiply in Projective Coordinates (0x07)....26-33 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 57 DEU Key Registers ......... . 26-44 MSC8158E Reference Manual, Rev. 2...
Page 58 AFEU Key Size Register ........26-74 MSC8158E Reference Manual, Rev. 2...
Page 59 CRCU Context Register ........26-85 MSC8158E Reference Manual, Rev. 2...
Page 60 Descriptor Type 0001_0: common_nonsnoop....26-112 26.7.1.2.6 Descriptor Type 0010_0: hmac_snoop_no_afeu ....26-117 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 61 Polychannel ..........26-194 MSC8158E Reference Manual, Rev. 2...
Page 62 26.7.9.3 AESU Data Size Register (AESUDSR) ......26-238 MSC8158E Reference Manual, Rev. 2 lxii Freescale Semiconductor...
Page 63 KEU Status Register (KEUSR) ....... . 26-283 MSC8158E Reference Manual, Rev. 2...
Page 64 26.7.14.15 STEU Context Register 3 (STEUCR3) ......26-327 MSC8158E Reference Manual, Rev. 2 lxiv Freescale Semiconductor...
Page 65 RNGU Output FIFO ......... 26-341 MSC8158E Reference Manual, Rev. 2...
Page 66: Msc8158E Reference Manual,
Contents MSC8158E Reference Manual, Rev. 2 lxvi Freescale Semiconductor...
Page 67 About This Book The MSC8158E device is the fourth generation of Freescale high-end multicore DSP devices. builds upon the proven success of the previous multicore DSPs and is designed to support the 3G-LTE Its tool suite provides a full-featured (FDD and TDD), HSPA+, LTE-Advanced, and WiMAX markets.
Page 68: Before Using This Manual-Important Note
This manual is intended for software and hardware developers and applications programmers who want to develop products with the MSC8158E. It is assumed that you have a working knowledge of DSP technology and that you may be familiar with Freescale products based on StarCore technology.
Page 69: Notational Conventions And Definitions
For example, BRCGx refers to BRCG[1–8], and MxMR refers to the MAMR/MBMR/MCMR registers. On the MSC8158E device, the SC3850 cores are 16-bit DSP processors. The following table shows the SC3850 assembly language data types. For details, see the StarCore SC3850 DSP Core Reference Manual.
Page 70: Conventions For Registers
Chapter 4, Chip-Level Arbitration and Switching System (CLASS). Describes the system switch fabric that allows multi-initiator access to the internal memory and devices and enables high-bandwidth internal data transfers with few bottlenecks. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 71 Chapter 6, Boot Program. Describes the bootloader program that loads and executes source code to initialize the MSC8158E after it completes a reset sequence and programs its registers for the required mode of operation. This chapter covers selection of bootloader modes, normal sequence of events for bootloading a source program, and booting in a multi-processor environment.
Page 72 IEEE Std. 1149.6 documentation. The discussion covers the items that the standard requires to be defined and provides additional information specific to the MSC8158E implementation. Also includes debugging resources available in the SC3850 DSP core subsystem, including the OCE modules, and L2 ICache module.
Page 73: Other Msc8158E Documentation
Differences Between the MSC8157 and the MSC8158 DSPs (EB723). Indicates functional differences between the devices in the MSC8157 DSP family. Other documents. Application Notes and Engineering Bulletins that cover various board layout and programming topics related to the StarCore DSP core and the MSC8158E device. Further Reading...
Page 74: Document Change History
– Removed all references to special CPRI support. – Updated Section 20.1.5 to add detailed procedure. – Added note to Section 20.1.5.1. • Chapter 26, Security Engine (SEC) – Updated Section 26.6.8 and Section 26.7.4.4. MSC8158E Reference Manual, Rev. 2 lxxiv Freescale Semiconductor...
Page 75 SRDB1RSTCTL and SRDB2RSTCTL individually. – Updated FRATE_SEL settings description in Table 15-62. • Chapter 21, Timers – Added an updated version of Section 21.1.8, Special CPRI Support which had been removed in Rev. 1. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor lxxv...
Page 76 MSC8158E Reference Manual, Rev. 2 lxxvi Freescale Semiconductor...
Page 77: Overview
Overview The MSC8158E device is the fourth generation of Freescale high-end multicore DSP devices that target the communications infrastructure and delivers the industry’s highest level of performance and integration. It builds upon the proven success of the previous multicore DSPs and is designed to support the rapidly changing and expanding broadband wireless markets, with special support for UMTS and TD-SCDMA application processing.
Page 78: Features
Overview Features The MSC8158E includes the following features: StarCore DSP subsystem. The DSP subsystem includes: — StarCore SC3850 core • Running at up to 1 GHz • Up to 8000 16-bit MMACS. A MAC operation includes a multiply-accumulate command with the associated data moves and a pointer update.
Page 79 • Software coherency support with seamless transition from L1 cache coherency operation. — Memory management unit (MMU): • Highly flexible memory mapping capability • Provides virtual to physical address translation • Provides task protection MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 80 MAPLE-B2. This port is a write only port and is referred to as MBus Slave1 port. • Interrupt or RapidIO Door Bell generation and/or status bit indication on job or multiple jobs completion. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 81 • Various rates/puncturing cases — DFT/iDFT and FFT/iFFT processing using three eFTPE modules: 1.Viterbi and Turbo decoding share memories and share throughput; 100% throughput of Viterbi and 100% throughput of Turbo cannot be achieved simultaneously. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 82 + D + 1 — CRC16 with polynomial D — CRC16 with polynomial D — CRC32 with polynomial D + D + 1 — CRC18 with polynomial D — CRC12 with polynomial D MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 83 — Uplink Fast Processing for (E)DPCCH processing • Capacity of up to 400 Physical channels with up to 3200 total fingers from up to 24 antenna streams. • Input data precision of 16 bit {8I,8Q} complex chips. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 84 EU has buffer FIFOs of at least 256 bytes. EU types and features include the following: — Advanced Encryption Standard Unit (AESU) • Implements the Rijndael symmetric key cipher per U.S. National Institute of Standards and Technology FIPS 197. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 85 • Implements MD5 with 128-bit message digest (as specified by RFC 1321) • Implements HMAC computation with either message digest algorithm (as specified in RFC 2104 and FIPS-198) • Implements SSL MAC computation • ICV checking MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 86 • Optional DDR clock — Six PLLs: • Three system PLLs • Two SerDes PLLs • DDR Controller PLL — Clock ratios selected during reset via reset configuration pins. — Clock modes user-configurable after reset. MSC8158E Reference Manual, Rev. 2 1-10 Freescale Semiconductor...
Page 87 • 1D or 2–4D complex buffers, a combination of buffer types — Two external DMA request (DREQ) and two DONE signal lines that allow an external device to trigger DMA transfers. — High bandwidth — Optimized for DDR SDRAM MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 1-11...
Page 88 — 64 outbound queues allowing multi-core environment. — 16 concurrent inbound reassembly operations. One additional reserved reassembly for inbound unit 0 to carry session management protocol. — Multi unicast. • Each RapidIO DMA unit supports: MSC8158E Reference Manual, Rev. 2 1-12 Freescale Semiconductor...
Page 89 • Detection of all erroneous frames as defined by IEEE Std. 802.3-2002 • Multi-buffer data structure • Diagnostic modes: Internal and external loopback mode and echo mode • Serial management interface MDC/MDIO • Transmitter network management and diagnostics MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 1-13...
Page 90 • Controlled by the DSP cores and the QUICC Engine RISC processors according to user configuration. I/O Interrupt Concentrator consolidates all chip maskable interrupt and non-maskable interrupt sources and routes them to , and the cores. INT_OUT NMI_OUT UART MSC8158E Reference Manual, Rev. 2 1-14 Freescale Semiconductor...
Page 91 — Multi-master operational — Calling address identification interrupt — START and STOP signal generation/detection — Acknowledge bit generation/detection — Bus busy detection — Programmable clock frequency — On-chip filtering for spikes on the bus MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 1-15...
Page 92 — Low-power standby modes — Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent) Technology: The MSC8158E device is manufactured using CMOS 45 nm SOI technology. Flip Chip-Plastic Ball Grid Array (FC-PBGA), 783-ball, 1 mm pitch, 29 mm × 29 mm MSC8158E Reference Manual, Rev.
Page 93: Block Diagram
The MSC8158E architecture is carefully optimized to achieve the maximum channel density for a given device area, power, and cost. Also, the MSC8158E is a derivative of the same system internal platform Freescale uses to implement new DSPs. Therefore, Freescale can swiftly spin off DSP devices from the same platform and provide the customer with familiar modules and programming models.
Page 94: Starcore Sc3850 Dsp Subsystem
Cacheable write-through. Both the cache and the higher-level memory are updated during every write operation. In the StarCore SC3850 DSP subsystem, the write-through buffer is MSC8158E Reference Manual, Rev. 2 1-18 Freescale Semiconductor...
Page 95: Starcore Sc3850 Dsp Core
(SIMD) instructions working on 2-word or 4-byte operands packed in a register. This packing allows the core to perform 2 to 4 operations per instruction (a maximum of 10 to 18 operation per VLES including AGU operations). MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 1-19...
Page 96: L1 Instruction Cache
(DCU), the write-back buffer (WBB), and the write-through buffer (WTB). This two-way channel reads and writes information from the core to/from higher-level memory (M2 or L2) and control memory (internal blocks and external peripherals) spaces. MSC8158E Reference Manual, Rev. 2 1-20 Freescale Semiconductor...
Page 97: L2 Unified Cache/M2 Memory
1.4.6 Debug and Profiling Unit (DPU) The on-chip emulator (OCE) and the debug and profiling unit (DPU) are hardware blocks for debugging and profiling. The OCE performs the following tasks: MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 1-21...
Page 98: Extended Programmable Interrupt Controller
33 levels of interrupt priorities, of which 32 levels are maskable at the core and 1 level is NMI. 1.4.8 Timer The timer block includes two 32-bit general-purpose counters with pre-loading capability. It counts clocks at the core frequency. It is intended mainly for operating system use. MSC8158E Reference Manual, Rev. 2 1-22 Freescale Semiconductor...
Page 99: Maple-B2
The SEC includes a controller, four data channels, and eight execution units (EUs) including a shared random number generator (RNGU) that use a common interface to the MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 1-23...
Page 100: Chip-Level Arbitration And Switching System (Class)
The Chip Level Arbitration and Switching System (CLASS) is the central internal interconnect system for the MSC8158E device. The CLASS is a non-blocking, full-fabric interconnect that allows any initiator to access any target in parallel with another initiator-target couple. The CLASS uses a fully pipelined low latency design.
Page 101: Clocks
The DDR SDRAM interface is useful when the channel storage size is relatively big and also when more channels are required to supplement the internal memory. When the MSC8158E device works with channel data stored in the DDR SDRAM, the DMA controller can swap the data to and from the M2 memory, thus enabling the L1 DCache to fetch from M2 memory instead of accessing the DDR SDRAM memory directly.
Page 102: Dma Controller
The DMA controller supports smart arbitration algorithms such as round robin, bandwidth control, and a timer-based mechanism using an earliest deadline first (EDF) algorithm. MSC8158E Reference Manual, Rev. 2 1-26 Freescale Semiconductor...
Page 103: High Speed System Interface
The configurable arbitration features described in this chapter are for fine-tuning the system for specific application requirements. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 1-27...
Page 104: Ocn Fabric
OCN packets, negotiates with the OCN arbiter, and transmits/receives associated transactions. 1.12.4 DMA Controllers The MSC8158E includes two dedicated DMA controllers that transfer blocks of data between the serial RapidIO controller/PEX Controller and the local address space independent from the DSP cores.
Page 105: Protocol Converter
1.13 QUICC Engine Subsystem The MSC8158E QUICC Engine module is a versatile communications engine based on a subset of the MPC83XX QUICC Engine subsystem that integrates several communications peripheral controllers. The QUICC Engine module combines interface hardware and RISC firmware to support multimedia packet operations.
Page 106: Ethernet Controllers
The transmitter and receiver sections use the same clock, which is derived from the SPI baud rate generator in master mode and generated externally in slave mode. During an SPI transfer, data is sent and received simultaneously. MSC8158E Reference Manual, Rev. 2 1-30 Freescale Semiconductor...
Page 107: Global Interrupt Controller (Gic)
16-bit timers. The MSC8158E device also includes 8 software watchdog timers. Each of the software watchdog timers can be used by any of the cores within MSC8158E as well as by an external host. 1.17 Hardware Semaphores There are eight coded hardware semaphores.
Page 108: I 2 C Interface
1.21 Boot Options The boot program in the internal boot ROM initializes the MSC8158E after it completes a reset sequence. The MSC8158E device can boot from an external host through the serial RapidIO interface or download a user boot program through the I C, SPI, or Ethernet ports.
Page 109: Tools
Developer Environment 1.23.1 Tools The MSC8158E tool components include the following: Integrated development environment (IDE). Easy-to-use graphical user interface and project manager for configuring and managing multiple build configurations. C compiler with in-line assembly. The developer can generate highly optimized DSP code by exploiting the StarCore multiple-ALU architecture, with parallel fetch sets and high code density.
Page 110: Application Software
StarCore Libraries Rich set of StarCore software libraries, including: Math (Part 1 and 2), Signal, Complex vector, Control function, Frequency domain, Filter, Common, Image Processing, Communication, and Matrix. MSC8158E Reference Manual, Rev. 2 1-34 Freescale Semiconductor...
Page 111: Sc3850 Core Overview
See the SC3850 DSP Core Reference Manual for a detailed description of core functionality and instruction set. The manual is only available with a signed non-disclosure agreement. Contact your local Freescale sales office or representative for details. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 112: Core Architecture Features
Table 2-1. Multiplication Throughput Summary Figures for the SC3850 Operation Precision Instructions per Operation Result Throughput (4 ALUs) 16 × 16 Real multiply 16 × 32 32 × 32 16 × 16 Complex multiply 16 × 32 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 113 — Precise detection of PC breakpoints — PC tracing with filtering and compression options • Low Power Design — Low-power Wait and Stop instructions — A very low power design — Fully static logic MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 114: Starcore Sc3850 Core Architecture
128 Gbps between the core and the memory. The program sequencer manages the instruction fetching from the program memory, dispatching the VLES to the execution units, performing change of flow (COF) and HW loop management MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 115 The SC3850 also includes a 48-entry Branch Target Buffer (BTB) that improves performance by reducing the change of flow latency. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 116 SC3850 Core Overview MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 117 External Signals The MSC8158E external signals are organized into functional groups. Table 3-1 lists the functional groups and references the table that gives a detailed listing of signals within each group. Table 3-1. MSC8158E Functional Signal Groupings Functional Group Detailed Description...
Page 118 CPRI, SPI, timers, UART, and I C signals. The specific function is selected through configuration of the GPIO registers (see Chapter 20, GPIO for details). Figure 3-1 summarizes the various MSC8158E external signal multiplexing options. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 119 Dedicated signals: ← ↔ GPIO29/UART_TXD/CP_LOS2 RC17/RCW_LSEL0, RC18/RCW_LSEL1, → DFT_TEST Test RC19/RCW_LSEL2, RC20/RCW_LSEL3, RC21 Note: See the individual signal description tables for details about individual power supplies and grounds. Figure 3-1. MSC8158E External Signals MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 120: Power Signals
Provide adequate external decoupling capacitors. The external decoupling capacitors recommendations are listed in the 1.5 V MSC8158E Technical Data Sheet. SXPVDD SerDes Pad Power DDSXP A dedicated well-regulated power for the SerDes pad circuitry. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 121: Clock Signals
A ground for the SerDes Core circuitry. SXPVSS SerDes Pad Ground A ground for the SerDes Pad circuitry. Note: The external decoupling capacitors recommendations are listed in the MSC8158E Technical Data Sheet. Clock Signals Table 3-3. Clock Signals Signal Name...
Page 122: Reset And Configuration Signals
Hard Reset Output When asserted as an input, this signal causes the MSC8158E to abort all current internal and external transactions, set most registers to their default state, and enter the hard reset state. This signal must be asserted for at least 32 CLKIN cycles.
Page 123 CPRI Controller 1–3 Synchronization Signal Synchronization signals for CPRI controllers 1–3. Selected through GPIO configuration. For configuration details, see Chapter 20, GPIO. For functional details, see Chapter 18, Common Public Radio Interface (CPRI) Complex. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 124 CPRI Controller 4–6 Synchronization Signal Synchronization signals for CPRI controllers 4–6. Selected through GPIO configuration. For configuration details, see Chapter 20, GPIO. For functional details, see Chapter 18, Common Public Radio Interface (CPRI) Complex. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 125 Timer 5 Output Configured as input to the counter or output from the counter. Selected through the GPIO configuration. For configuration details, see Chapter 20, GPIO. For timer functional details, see Chapter 21, Timers. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 126 RCW_SRC[0–2] equals 000, the device loads all 64 bits of the RCW via RC[0–15] in four beats. In this case, RC[17–20] function as RCW_LSEL[0–3] outputs that are asserted to load the RCW 16 bits at a time and RC21 is ignored. See Chapter 5, Reset for details. MSC8158E Reference Manual, Rev. 2 3-10 Freescale Semiconductor...
Page 127: Memory Controller
MDQ[63–0] Input/ Data Bus Output The MSC8158E device drives the bus during write cycles and the external memory drives the bus during read cycles. MDM[8–0] Output DDR SDRAM Data Output Mask Masks unwanted data bytes transferred during a burst write.
Page 128: Sgmii Interfaces
For proper definition of serial RapidIO modes (x1/x2/x4), CPRI, and SGMII, configure the interfaces using the Reset Configuration Word settings. For details, see Chapter 5, Reset. Table 3-7 lists the interfaces supported by each SerDes lane. MSC8158E Reference Manual, Rev. 2 3-12 Freescale Semiconductor...
Page 129: Cpri Signals
CPRI Controller 1–3 Synchronization Signal Synchronization signals for CPRI controllers 1–3. Selected through GPIO configuration. For configuration details, see Chapter 20, GPIO. For functional details, see Chapter 18, Common Public Radio Interface (CPRI) Complex. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 3-13...
Page 130 For details, see the QUICC Engine Block Reference Manual with Protocol Interworking. CP_LOS3 Input CPRI Optical Loss of Signal Indication for Lane 3 This is the default option. The signal can also be configured on GPIO17. MSC8158E Reference Manual, Rev. 2 3-14 Freescale Semiconductor...
Page 131 For details, see the QUICC Engine Block Reference Manual with Protocol Interworking. CP_LOS6 Input CPRI Optical Loss of Signal Indication for Lane 6 This is the default option. The signal can also be configured on GPIO20. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 3-15...
Page 132: Ethernet Signals
For details, see the QUICC Engine Block Reference Manual with Protocol Interworking. CP_LOS3 Input CPRI Optical Loss of Signal Indication for Lane 3 This is the default option. The signal can also be configured on GPIO17. MSC8158E Reference Manual, Rev. 2 3-16 Freescale Semiconductor...
Page 133 Ethernet 1 Receive Control For details, see the QUICC Engine Block Reference Manual with Protocol Interworking. GE_MDC Output Ethernet Management Data Clock For details, see the QUICC Engine Block Reference Manual with Protocol Interworking. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 3-17...
Page 134: Serial Peripheral Interface (Spi) Signal Summary
When the SPI is a master, SPI_SCK is the clock input signal that shifts received data in from SPI_MOSI and transmitted data out through SPI_MISO. CP_LOS4 Input CPRI Optical Loss of Signal Indication for Lane 4 This is an optional configuration. The signal can also be configured on GE2_GTX_CLK. MSC8158E Reference Manual, Rev. 2 3-18 Freescale Semiconductor...
Page 135: Gpio/Maskable Interrupt Signal Summary
UART Receive Data Output For details, see Chapter 19, UART. CP_LOS1 Input CPRI Optical Loss of Signal Indication for Lane 1 This is an optional configuration. The signal can also be configured on GE2_RD2. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 3-19...
Page 136 Along with the RCW_SRC[0–1], this signal is sampled at the deassertion of PORESET to identify the source of the reset configuration word. The required signal level must be maintained as long as HRESET/HRESET_IN is asserted. MSC8158E Reference Manual, Rev. 2 3-20 Freescale Semiconductor...
Page 137 SPI_MOSI and transmitted data out through SPI_MISO. For details, see the QUICC Engine Block Reference Manual with Protocol Interworking. CP_LOS4 Input CPRI Optical Loss of Signal Indication for Lane 4 This is an optional configuration. The signal can also be configured on GE2_GTX_CLK. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 3-21...
Page 138 For details, see Chapter 14, Direct Memory Access (DMA) Controller, RC14 Input Reset Configuration Word Bit 14 Sampled during the assertion of PORESET to set part of the bits of the Reset Configuration Word Registers. MSC8158E Reference Manual, Rev. 2 3-22 Freescale Semiconductor...
Page 139 For details, see Chapter 14, Direct Memory Access (DMA) Controller, Input Reset Configuration Word Bit 3 Sampled during the assertion of PORESET to set part of the bits of the Reset Configuration Word Registers. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 3-23...
Page 140: Timer Signals
One of 32 GPIOs. For details, see Chapter 20, GPIO. RC16 Input Reset Configuration Word Bit 16 Sampled during the assertion of PORESET to set part of the bits of the Reset Configuration Word Registers. MSC8158E Reference Manual, Rev. 2 3-24 Freescale Semiconductor...
Page 141 Along with the RCW_SRC[0–1], this signal is sampled at the deassertion of PORESET to identify the source of the reset configuration word. The required signal level must be maintained as long as HRESET/HRESET_IN is asserted. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 3-25...
Page 142: Uart Signals
One of 32 GPIO pins used as GPIO or as a dedicated input or output. For details, see Chapter 20, GPIO. CP_LOS1 Input CPRI Optical Loss of Signal Indication for Lane 1 This is an optional configuration. The signal can also be configured on GE2_RD2. MSC8158E Reference Manual, Rev. 2 3-26 Freescale Semiconductor...
Page 143: I 2 C Signals
External line that can request a service routine via the internal interrupt controller. For details, see Chapter 13, Interrupt Handling. RC14 Input Reset Configuration Word Bit 14 Sampled during the assertion of PORESET to set part of the bits of the Reset Configuration Word Registers. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 3-27...
Page 144: Other Interrupt Signals
Type Description INT_OUT Output Interrupt Output An open-drain output driven from the MSC8158E virtual interrupt 24. Assertion of this output indicates that an unmasked interrupt is pending in the MSC8158E internal interrupt controller. CP_TX_INT Output CPRI Transmit Interrupt CPRI Transmit Interrupt. For Details see Chapter 18, Common Public Radio Interface (CPRI) Complex.
Page 145: Oce Event And Jtag Test Access Port Signals
3.15 OCE Event and JTAG Test Access Port Signals The MSC8158E uses two sets of debugging signals for the two types of internal debugging modules: OCE and the JTAG TAP controller. Each internal SC3850 core has an OCE module, but they are all accessed externally by the same two signals .
Page 146 External Signals MSC8158E Reference Manual, Rev. 2 3-30 Freescale Semiconductor...
Page 147: Chip-Level Arbitration And Switching System (Class)
The Chip Level Arbitration and Switching System (CLASS) is the central internal interconnect system for the MSC8158E device. The CLASS is a non-blocking, full-fabric interconnect that allows any initiator to access any target in parallel with another initiator-target couple. The CLASS uses a fully pipelined low latency design.
Page 148: Class Features
Controller system system system system system system Bridge Initiator Devices Figure 4-1. CLASS Initiators and Targets in the MSC8158E Device CLASS Features The CLASS modules implement the following features: Non blocking, full fabric interconnect. Full bandwidth utilization toward each of the targets.
Page 149: Functional Description
Section 4.2.2. Each multiplexer and arbiter module has a dedicated normalizer module that is used as the sampling stage on the target side. The normalizer can also be used for normalizing transactions. For more details about normalizer module see Section 4.2.3. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 150: Expander Module And Transaction Flow
(no priority upgrade ability by the initiator and auto priority upgrade in the expander module is disabled). When the Masking Priority is enabled, the arbiter dedicates slots for lower priority initiator in which the higher priority initiators are masked. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 151: Weighted Arbitration
The FIFO depth is 16, thus enabling the multiplexer and arbiter module to deal with 16 open transactions, which received their request acknowledge and are waiting for the end-of-data or end-of-transaction signals. The CLASS multiplexer is pure logic for the data path and does not cause any latency. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 152: Normalizer Module
CLASS delivers invalid data to the initiator. If, at the time of the error transaction, there are open transactions that did not receive the end-of-transaction, the expander module stalls all new transaction until all prior MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 153: Class Debug Profiling Unit
(CPRCR) starts counting the clock cycles. Read the CPISR[OVE] bit to verify that the measurement is complete and that the profiling counter values are valid. If the CPISR[OVE] is clear, read the profiling counters CPRCR and CPGCR and analyze the results. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 154: Watch Point Unit
— In time-out mode, read C0PRCR. — If C0PISR[OVE] is set or if C0PRCR is equal to C0PTOR, the results are not valid. — Read C0PGCRx to get the number of watch point events during the measurement. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 155: Event Selection
The resulting information can be used to redesign the code to minimize stalls related to real confirmations. Use of large transactions reduces the number of real confirmations because they are only required for the last beat of the transfer. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 156 Can be used to profile the number of data reads and writes. The amount of data that passes through the initiator port = [(NumberOfReadAck + NumberOfWriteAck) × W]. where W is the port width. Note that an access may be smaller than the port width. MSC8158E Reference Manual, Rev. 2 4-10 Freescale Semiconductor...
Page 157 Can be used to profile the number of data reads and writes to Target T. The amount of data that passes through the target port = [(NumberOfReadAck + NumberOfWriteAck) × W] where W is the port width.Note that an access can be less than the port width MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 4-11...
Page 158: Debug And Profiling Events
The CLASS configuration registers are reset as described in the table for each register in 4.7, Programming Model. 4.5.2 Hard Reset This reset brings all states machines to idle state and sets all CLASS registers to the reset values. MSC8158E Reference Manual, Rev. 2 4-12 Freescale Semiconductor...
Page 159: Limitations
Core subsystem 3 can only access its own M2 space and the M2 space of core subsystems 4 and 5. Core subsystems 4 and 5 can only access their own M2 space. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 4-13...
Page 160: Programming Model
CLASS Profiling Reference Counter Register (see page 4-40) CLASS Profiling General Counter Registers (see page 4-41) CLASS Arbitration Control Register (see page 4-42) Note: The base address for addressing CLASS registers is 0xFFF18000. MSC8158E Reference Manual, Rev. 2 4-14 Freescale Semiconductor...
Page 161: Class Priority Mapping Registers (C0Pmrx)
Priority 0 5–4 Holds the priority value assigned to Priority 1 transactions that arrive with a value of 1. Priority 2 Priority 3 — Reserved. Write to 0 for future compatibility. 3–2 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 4-15...
Page 162: Class Priority Auto Upgrade Value Registers (C0Pavrx)
• Priority 1: Bits 15–1 are loaded into bit 14–0 of the counter and a 0 into bit 15. • Priority 2: Bits 15–2 are loaded into bits 13–0 of the counter and 0 into bits 15 and 14. MSC8158E Reference Manual, Rev. 2 4-16...
Page 163: Class Priority Auto Upgrade Control Registers (C0Pacrx)
— Reserved. Write to 0 for future compatibility. 31–1 Auto-Upgrade Enable Auto-upgrade mechanism disabled. Enables/disables the auto-upgrade Auto-upgrade mechanism enabled. mechanism. Note: This bit can only be cleared by a hardware reset. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 4-17...
Page 164: Class Error Address Registers (C0Earx)
— C0EAR11 = DMA port 1. — C0EAR12 = Address generated by HSSI port 1 — C0EAR13 = Address generated by MAPLE-B2 port 2. — C0EAR14 = Address generated by MAPLE-B2 port 3. MSC8158E Reference Manual, Rev. 2 4-18 Freescale Semiconductor...
Page 165: Class Error Extended Address Registers (C0Eearx)
Reserved. Write to 0 for future compatibility. Supervisor Access Not supervisor. This field indicates whether the transaction that caused the Supervisor. error was in supervisor mode. — Reserved. Write to 0 for future compatibility. 13–9 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 4-19...
Page 166: Class Initiator Profiling Configuration Registers (C0Ipcrx)
PMM value in the associated C0IPCR and make sure all the other C0IPCR and the C0TPCR for that CLASS are cleared. Note: Only one PMM field among all C0IPCRx and C0TPCR can be greater than 0 during profiling. MSC8158E Reference Manual, Rev. 2 4-20 Freescale Semiconductor...
Page 167 DSP core subsystem 5 MAPLE port 0 MAPLE port 1 HSSI port 0 SEC, Ethernet, SPI, or Debug DMA port 0 DMA port 1 HSSI port 1 MAPLE port 2 MAPLE port 3 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 4-21...
Page 168: Class Initiator Watch Point Control Registers (C0Iwpcrx)
Reserved. Write to 0 for future compatibility. 31–1 WPEN Watch Point Enable The watch point is disabled. Enables/disables the auto-upgrade The watch point is enabled. mechanism. Note: This bit can only be cleared by a hardware reset. MSC8158E Reference Manual, Rev. 2 4-22 Freescale Semiconductor...
Page 169: Class Arbitration Weight Registers (C0Awrx)
Contains the arbitration weight assigned to the associated initiator. The reset values be changed by the designer according to the application requirements. See Table 4-30 for recommended initial settings for the CLASS Arbitration Control Register (C0ACR). MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 4-23...
Page 170: Class Start Address Decoder X (C0Sadx)
The 24 msb of the start address of the specified port window. The lsbs Port 7 = 0x0C0000 (M3_0 start) are all zeros. Port 8 = 0x0C0100 (M3_1 start) Port 9 = 0x0C0200 (M3_2 start) MSC8158E Reference Manual, Rev. 2 4-24 Freescale Semiconductor...
Page 171: Class End Address Decoder X (C0Eadx)
To ensure proper operation, never modify the contents of the register while the specific decoder is enabled. Always clear the associated CATDx[DEN] bit before changing the contents of C0EADx. Note: C0EAD2 is valid only if C0ATD1[SPRW] is clear (0). MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 4-25...
Page 172: Class Attributes Decoder 1 (C0Atd1)
However, any transaction that was acknowledged up to and including the cycle in which DEN is cleared continues normally until completed. Note: To ensure proper operation, do not enable the specific decoder before the start and end addresses are specified in the associated C0SADx and C0EADx. MSC8158E Reference Manual, Rev. 2 4-26 Freescale Semiconductor...
Page 173 Some accesses use Target 1 (defined by C0SAD1/C0EAD1). Some accesses use Target 2 (defined by C0SAD2/C0EAD2). Use for cases of unbalanced reads/writes or to split address space among different masters. Note: Target2 has a higher priority than Target1. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 4-27...
Page 174: Class Attributes Decoder X (C0Atdx)
Never write to these registers when there are open transactions being handled by the CLASS to the specified target controlled by the register. Note: C0ATD2 is valid only if C0ATD1[SPRW] is clear (0). MSC8158E Reference Manual, Rev. 2 4-28 Freescale Semiconductor...
Page 175: Class Irq Status Register (C0Isr)
No error. 14–0 A bit is set if for a received transaction Error detected. request, it does not belong to any port address space or falls inside one of the error areas. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 4-29...
Page 176: Class Irq Enable Register (C0Ier)
C0IPCRx are cleared. Note: For each CLASS module, you can only monitor one transaction. Therefore, only one PMM field in C0IPCRx and C0TPCR can be greater than 0 during profiling. MSC8158E Reference Manual, Rev. 2 4-30 Freescale Semiconductor...
Page 177 00 No profiling measurement. selected target. 01 Arbitration winner priority measurement. 10 Collisions measurement. 11 reserved. If TT = 1: 00 No profiling measurement. 01 Transaction splitting measurement. 10 Bandwidth measurement. 11 Stall measurement. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 4-31...
Page 178: Class Profiling Control Register (C0Pcr)
Time-out function disabled. Enables/disables the time-out mechanism. Time-out function enabled. — Reserved. Write to 0 for future compatibility. 3–1 Profiling Enable Profiling unit disabled. Enables/disables the debug profiling unit Profiling unit enabled. operation. MSC8158E Reference Manual, Rev. 2 4-32 Freescale Semiconductor...
Page 179: Class Watch Point Control Registers (C0Wpcr)
ATAE Atomic Access Compare Enable Atomic access type compare disabled. Enables/disables the atomic access type Atomic access type compare with C0WPACR comparison. enabled. — Reserved. Write to 0 for future compatibility. 7–4 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 4-33...
Page 180: Class Watch Point Access Configuration Register (C0Wpacr)
For every bit in C0WPAMR[ADDM] that is cleared, make sure the corresponding bit is cleared in the ADDR. The bit location in ADDM (b) corresponds to the b + 12 bit location in ADDR. MSC8158E Reference Manual, Rev. 2 4-34...
Page 181: Class Watch Point Extended Access Configuration Register
Target port 7 M3 memory port 0 0x10 Target port 8 M3 memory port 1 0x11 Target port 9 M3 memory port 2 All other values reserved. — Reserved. Write to 0 for future compatibility. 23–16 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 4-35...
Page 182: Class Watch Point Address Mask Registers (C0Wpamr)
— ADDM Type Reset C0WPAMR controls the address range monitored by the watch point unit. The register is reset only by a hardware reset. Table 4-23 lists the C0WPAMR bit field descriptions. MSC8158E Reference Manual, Rev. 2 4-36 Freescale Semiconductor...
Page 183: Class Profiling Time-Out Registers (C0Ptor)
Table 4-24 lists the C0PTOR bit field descriptions. Table 4-24. C0PTOR Bit Descriptions Name Reset Description 0xFFFFFFFF Time-Out 31–0 Holds the time-out value used to stop the profiling unit when the time-out function is enabled. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 4-37...
Page 184: Class Target Watch Point Control Registers (C0Twpcr)
Watch Point Enable 7–0 The watch point unit for the associated target is 7–0 Each bit enables monitoring of access by disabled. the associated target. The watch point unit for the associated target is enabled. MSC8158E Reference Manual, Rev. 2 4-38 Freescale Semiconductor...
Page 185: Class Profiling Irq Status Register (C0Pisr)
Enables monitoring of access by the Watch point event captured. associated target. Overflow Event No overflow occurred. Enables monitoring of access by the C0PRCR overflowed (reached 0xFFFFFFFF) associated target. during the last measurement. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 4-39...
Page 186: Class Profiling Irq Enable Register (C0Pier)
C0PRCR reaches the value stored in C0PTOR and TOE is set, which causes the CLASS to clear the PE bit to disable the profiling MSC8158E Reference Manual, Rev. 2 4-40...
Page 187: Class Profiling General Counter Registers (C0Pgcrx)
Table 4-29 lists the C0PGCR bit field descriptions. Table 4-29. C0PGCR Bit Descriptions Name Reset Description Counter 31–0 Holds the counter value of the selected measurement. Table 4-1 lists the measurements counted by each counter for each configuration combination. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 4-41...
Page 188: Class Arbitration Control Register (C0Acr)
M2 memory, DDR memory, and the M3 memory. This is just an initial value, and can be changed according to the application requirements and system traffic. MSC8158E Reference Manual, Rev. 2 4-42 Freescale Semiconductor...
Page 189: Reset
Most of these features are configured by loading a reset configuration word to the MSC8158E device that combine with a few direct configuration inputs sampled during the reset sequence. This section describes the various ways to reset and configure the MSC8158E device.
Page 190: Reset Sources
HRESET_IN is an input that permits a hard reset of an individual device without invoking a hard reset on other devices in a chain. The MSC8158E can detect an external assertion of HRESET or HRESET_IN only if it occurs while the MSC8158E is not asserting reset.
Page 191: Power-On Reset Flow
Initially, the reset configuration inputs are sampled to determine the configuration source and the input clock division mode. Next, the MSC8158E starts loading the reset configuration words. When the clock mode values in the reset configuration word low load, the PLLs begin to lock, after locking, each PLL distributes clock signals to the device.
Page 192 Chapter 8 General Configuration Registers for details. If enabled, the HSSI complex interfaces are now ready to accept external requests, and the core boot code fetch can proceed, if enabled. The MSC8158E is now in its ready state. Figure 5-1 shows a timing diagram of the power-on reset flow.
Page 193 Reset Configuration input signals RC[15:0] (input) End loading reset Start loading reset configuration words. configuration words RCW_LSEL_0 (output) RCW_LSEL_1 (output) RCW_LSEL_2 (output) RCW_LSEL_3 (output) Figure 5-2. Power-on Reset Flow for RCW_SRC = 000 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 194: Hreset Flow
Reset Configuration input signals Figure 5-3. Hard Reset Flow Reset Configuration The MSC8158E is initialized using two complementary methods. Initially, a small number of input signals ( ) are sampled during the first two CLKIN cycles after the deassertion RCW_SRC[0–2] (during the power-on reset flow).
Page 195: Reset Configuration Signals
Refer to the PORESET MSC8158E Technical Data Sheet for the recommended resistor values used to pull reset configuration signals high or low. The values loaded from these sampled inputs are accessible to software through memory-mapped registers described in Section 5.3.
Page 196: Reset Configuration Input Signal Selection And Reset Sequence Duration
Various device functions are initialized by loading the reset configuration words during the power-on reset flow. All configurable features are reconfigured only during a power-on reset flow. The MSC8158E decides which interface is used according to reset configuration input signals, as described in Section 5.2.2.
Page 197: Using The Boot Sequencer For Reset Configuration
Reset Configuration 5.2.5.1 Loading From an I C EEPROM (RCW_SRC[0–2] = 010) When a MSC8158E is configured by the reset configuration input signals to load the reset configuration words from an EEPROM via the I C interface, it uses the I C unit boot sequencer in a special mode.
Page 198: Loading Multiple Devices From A Single I
During the power on reset assertion, the master cannot drive the output bus STOP_BS because its role as master is not enabled yet. Pull-ups are required; refer to the MSC8158E Technical Data Sheet for appropriate resistor values to pull the slave input signal high.
Page 199 C EPROM Reset Logic I2C_SCL I2C_SCL A[0–2] HRESET_IN I2C_SDA I2C_SDA HRESET GPIO Decoder PORESET STOP_BS MSC8158E RCW_SRC[0–2] I2C_SCL I2C_SDA HRESET_IN HRESET PORESET STOP_BS Figure 5-5. Multi Device I C Reset Configuration Hardware MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 5-11...
Page 200 5.2.5.2 Loading Multiplexed RCW from External Pins (RCW_SRC[0–2] = 000) When the MSC8158E device is configured to use the multiplexed loading method, it latches all bits of the reset configuration word from the external pins. In this case, the sampled RCW bits are transferred with glue logic using the hardware shown in Figure 5-6.
Page 201: Loading Reduced Rcw From External Pins (Rcw_Src[0-2] = 011)
5.2.5.3 Loading Reduced RCW From External Pins (RCW_SRC[0–2] = 011) When the MSC8158E device is configured to use the reduced RCW, the MSC8158E latches some bits of the reset configuration word from external pins. The other bits of the RCWs are loaded from default hard coded values.
Page 202: Reduced External Reset Configuration Word High Field Values
Common transport type is Large System. 5.2.5.4 Default Reset Configuration Words (RCW_SRC[0–2] = 100 or 101) When the MSC8158E device is configured not to load the RCW from I C EEPROM or external pins, it can be initialized using one of the two hard-coded default options listed in Table 5-7 and Table 5-8.
Page 203: Hard Coded Reset Configuration Word High Field Values
Reserved. Should be cleared RapidIO Controller 1 does not accept all. RapidIO Controller 2 does not accept all. DEVID 000000 DEVID[5–4] = 00, DEVID[3–0] = RC[3–0] RIO2EB Enable RapidIO Controller 2 Enumeration Boundary Reached MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 5-15...
Page 204: Reset Programming Model
Chapter 7, Clocks for source clock definitions. — Reserved. Write to one for future compatibility. SerDes Protocol See Table 5-11 for setting descriptions. 28–22 Selects the SerDes protocols to use. MSC8158E Reference Manual, Rev. 2 5-16 Freescale Semiconductor...
Page 205 Defines the clock operating mode. Table 5-10. CLKO Selection RCWLR[CLKO] RCWLR[P3V] CLKOUT Source PLL0 output / 16 PLL1 output / 10 PLL2 output / 10 always low DDRPLL output / 8 reserved reserved reserved MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 5-17...
Page 206 Reset Table 5-11. MSC8158E HSSI Multiplexing SerDes Lanes RCWLR[SP] Mode Exceptions Protocol Select — — — — — — — — None 0000000 — — CPRI #6 CPRI #5 CPRI #4 CPRI #3 CPRI #2 CPRI #1 None 0000001 SGMII...
Page 207 Reset Programming Model Table 5-11. MSC8158E HSSI Multiplexing (Continued) SerDes Lanes RCWLR[SP] Mode Exceptions Protocol Select — — SGMII SGMII CPRI #2 CPRI #1 1, 2 0111101 #1(0) #1(1) — — CPRI #2 CPRI #1 None 1000001 #1(0) #1(1) #1(2) #1(3) —...
Page 208: Reset Configuration Word High Register (Rcwhr)
Pass-through disabled. (P0PTAACR[PTE] and Selects the reset value of P0PTAACR[PTE] and P1PTAACR[PTE] reset value is 0) P1PTAACR[PTE] which determines whether Pass-through enabled. (P0PTAACR[PTE] and pass-through is disabled or enabled. P1PTAACR[PTE] reset value is 1) MSC8158E Reference Manual, Rev. 2 5-20 Freescale Semiconductor...
Page 209 The value of fields in the reset configuration word registers (RCWLR and RCWHR) reflect only their state during the reset flow. Some of these parameters and modes can be modified by changing their values in other unit memory mapped registers. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 5-21...
Page 210: Reset Status Register (Rsr)
Indicates whether watchdog timer 6 expired. Software watchdog timer 6 expired. Software Watchdog Timer 7 Software watchdog timer 7 not expired. Indicates whether watchdog timer 7 expired. Software watchdog timer 7 expired. MSC8158E Reference Manual, Rev. 2 5-22 Freescale Semiconductor...
Page 211 RSR[RS] is set after a software watchdog reset. These must be cleared individually. RSR only returns to its complete reset value when a power-on reset occurs. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 5-23...
Page 212: Reset Protection Register (Rpr)
0x52535445 (“RSTE” in ASCII) to the RCPW to enable the RCR. When the RCR is enabled, the RCER[CRE] bit is set. Reading the RPR always returns all zeros. To disable write to the RCR, write a 1 to RCER[CRE]. MSC8158E Reference Manual, Rev. 2 5-24 Freescale Semiconductor...
Page 213: Reset Control Register (Rcr)
31–2 SWHR Software Hard Reset Normal operation. Setting this bit cause the MSC8158E to begin a Initiates a hard reset. hard reset flow. This bit returns to its reset state during the reset sequence, so reading it always returns a 0.
Page 214: Reset Control Enable Register (Rcer)
The enable value is written to the reset (RCR). Writing 1 to this bit disables the RCR protection register (RPR) to enable the RCR. and clears this bit. Writing zero has no effect. MSC8158E Reference Manual, Rev. 2 5-26 Freescale Semiconductor...
Page 215: Boot Program
Boot Program The boot program initializes the MSC8158E after it completes a reset sequence. The MSC8158E can boot from an external host through the RapidIO interface or download a user boot program through the I C, SPI, or Ethernet ports. The default boot code is located in an internal 96 KB ROM at 0xFEF00000–0xFEF17FFF and is accessible to all cores.
Page 216: Functional Description
C EEPROM. Boot mode select (core 0). This part includes downloading of code from one of the MSC8158E bootable ports as defined by the RCWHR[BPRT] field. Boot completion. All cores complete the boot operation and jump to a user-specified address.
Page 217: Private Configuration
— The necessary bits of P0CCSR and P1CCSR (RapidIO) are set to enable the port. QUICC Engine module priority is set to be 1 with emergency not masked (that is SDMR[EB1_PR] = 01). MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 218: Patch Mode
C Bus The MSC8158E can share the I C EEPROM device with other MSC8158E devices for loading the reset configuration word (RCW), as well as for reading configuration during boot loading and execution. When the bus is shared, the bus must distinguish among reset masters, reset slaves,...
Page 219 0x18 or 0x96 of the EEPROM or fails during the sequence of driving the RCW to the reset slaves, the core goes into a debug state and writes the appropriate error code to the M3 memory (see Section 6.5). MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 220: Example Configuration
MSC8158E #1 is a reset slave. The reset master uses {GPIO[0–3], GPIO[21]} to release the reset slaves. The MSC8158E boot supports up to 15 slaves on a single EEPROM (for RCW). There are two possibilities as to how the reset slave STOP_BS signals are handled: If there are 5 slaves or less, connect each GPIO line directly to one of the slaves.
Page 221 2. Drive corresponding slave RCWs 3. Disable time out counter RCWHR[BPRC] = I Last Slave? STOP_BS == 1 RCWHR[BPRC] = I All STOP_BS == 1 End of flow Figure 6-3. I C initialization and Multi Device Support MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 222 The following stages are performed to serve as the master chip on a multi-device board. The MSC8158E reads RSR register to determine if the reset is PORESET. If it is not PORESET, this section of the boot is bypassed entirely.
Page 223: Boot Modes
RCWLR[SP] is 0b0110000 (x4 SRIO1) 6.2.1 I C EEPROM The MSC8158E boot expects the I C EEPROM to be divided in to four sections: Reset words. This section starts at address 0x0000 of the EEPROM and includes the reset words for the reset master, an indication as to the number of reset slaves and the reset words for all the slaves.
Page 224 Reset Configuration Word High [31–24] Reset Configuration Word High of Slave 1 0x001E Reset Configuration Word High [23–16] 0x001F Reset Configuration Word High [15–8] 0x0020 Reset Configuration Word High [7–0] ........Figure 6-4. EEPROM Contents MSC8158E Reference Manual, Rev. 2 6-10 Freescale Semiconductor...
Page 225 0x021B 0x021C NBA[31–24] Next Block Address 0x021D NBA[23–16] 0x021E NBA[15–8] 0x021F NBA[7–0] 0x0220 Destination Address DA[31–24] 0x0221 DA[23–16] 0x0222 DA[15–8] 0x0223 DA[7–0] Payload Data CODE Figure 6-4. EEPROM Contents (Continued) MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 6-11...
Page 226 Block Control 3 bytes Block Size 4 bytes Next Block Address 4 bytes Destination Address Up to Payload Data 2^16 bytes 2 bytes Checksum 2 bytes Checksum Figure 6-5. EEPROM Data Format MSC8158E Reference Manual, Rev. 2 6-12 Freescale Semiconductor...
Page 227 (beginning with the Block Control byte) until the end of the block. The last byte of each block is not acknowledged by the MSC8158E. After the ninth unacknowledged bit, the boot code generates a STOP condition. Figure 6-6 describes the Software I C read access.
Page 228: Ethernet
Boot Program 6.2.2 Ethernet The MSC8158E device can load files through the Ethernet port using DHCP (Dynamic Host Configuration Protocol) and TFTP (Trivial File Transfer Protocol). Supports RGMII @1000 Mbps and SGMII @1000 Mbps full duplex. For DHCP, each client must have its own unique MAC (Media Access Control) address.
Page 229: Dhcp Client
The DHCP server confirms that the IP address has been allocated to the client by returning a DHCPACK unicast message to the client. There are two possibilities for setting the MSC8158E MAC address during the boot: User defined and read from an I C EEPROM.
Page 230: Tftp Client
The Ethernet bootloader supports up to 128 Mbytes of S-Record file size. The S-Record file structure is described in Figure 6-10. Start Record Data Record 1 Data Record 2 Data Record n End Record Figure 6-10. S-Record File Structure MSC8158E Reference Manual, Rev. 2 6-16 Freescale Semiconductor...
Page 231 The S0 record is composed as follows: S0. Indicating it is a starting record. 03. Hexadecimal 03 (decimal 3). Indicating that three character pairs (or ASCII bytes) follow. 0000. Information string (ignored) FC. Checksum field. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 6-17...
Page 232: Simple Ethernet Boot
RCWHR[SBETH] bit during the PORESET sequence (See Chapter 5, Reset for details). In this procedure, an Ethernet master waits for the MSC8158E boot program to finish its default initialization and then initializes the device by typically loading code and data to the on device memory.
Page 233: Simple Ethernet Boot Ports
For simple boot over Ethernet in SGMII mode the RCWHR[BPRT] and RCWLR[SP]. RCWLR[SP] field must have a valid SGMII option (See Chapter 5, Reset for details). Note: Booting over Ethernet in RGMII mode is enabled on UEC0 (UCC1) only. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 6-19...
Page 234: Boot File Format
<data> The memory loadable data or descriptive information Each Simple-Ethernet address field maps the data content to a memory location in MSC8158E. Core 0 moves the data to this address. The following code shows a typical Simple-Ethernet packet for End of handshake between Ethernet master...
Page 235: Serial Rapidio Interconnect
Boot Modes 6.2.4 Serial RapidIO Interconnect In this procedure a Serial RapidIO master waits for the MSC8158E boot program to finish its default initialization and then initializes the device by typically loading code and data to the on device memory.
Page 236: Serial Rapidio Interface With I2C Support
Multiple devices connected to a shared EEPROM see the same address/data pairs. 6.2.5 SPI The MSC8158E can boot from a Flash memory on the SPI. The boot expects a Flash memory that latches on the rising edge of the clock and on which data is valid after the falling edge. The chip-select should be a low signal.
Page 237: Jump To User Code
All NMIs will be configured as NMIs in the EPIC. VBA equals 0xFEF17000. Any interrupt in the EPIC puts the core in debug. EDC is enabled. Core register values are not guaranteed and should be initialized before use. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 6-23...
Page 238: Boot Errors
Lost arbitration on I C bus. 0x0027EFFD Time-out on I C acknowledge (9th clock). 0x0027EFFC Stuck I2C_SDA (I C bus). 0x00000000 Unexpected debug condition in the SC3850 Core (unexpected interrupt, EE0 asserted and so on) MSC8158E Reference Manual, Rev. 2 6-24 Freescale Semiconductor...
Page 239 Word (see Chapter 5, Reset for details). For the CPRI lanes, the initial configuration determines the starting frequency, but the actual connection frequency is negotiated and adjusted by dividers in the CPRI framer block (see Chapter 18, Common Public Radio Interface (CPRI) Complex for details). MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 240: Clock Generation Components And Modes
DDRPLL DDR Controller Figure 7-1. MSC8158E Clock Scheme Each PLL uses its input clock to generate a fast clock that is synchronized to the input clock. The fast clock is distributed to each of the clock dividers to generate the clocks that are distributed to the system blocks.
Page 241 Clock Generation Components and Modes The MSC8158E clock modes are listed in Table 7-1. Table 7-1. MSC8158E Clock Modes HSSI (CPRI, QUICC UART, DSP Core Engine MAPLE- Timers, Mode CLKIN MCLKIN PLL0 PLL1 PLL2 CLASS Sub- eTVPE DDR RapidIO Sub-...
Page 242: System Clock Control Register (Sccr)
Core Subsystem Clock Domain Disable Core Subsystem clock domain enabled. Used to disable the Core Subsystem controller Core Subsystem clock domain disabled. clock domain to conserve power. — Reserved. Write to zero for future compatibility. 7–0 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 243: Programming Model
General Configuration Registers The MSC8158E device includes a general configuration block that includes fifty-six 32-bit registers. This block provides sets of control and status registers for modules in the device that do not include their own control and status registers.
Page 244 Ethernet 2 High Resolution Delay Register (UCC3_DELAY_HR), see page 8-86 General Interrupt Register 8 (GIR8), see page 8-88 CPRI Interrupt to MAPLE External Request Enable (MAPLE_EXT_REQ_EN_1), see page 8-89 Note: The base address for the general configuration registers is: 0xFFF28000. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 245: Detailed Register Descriptions
Selects the signal for the internal clock multiplexer in MAPLE for MAPLE sync mode. — Reserved. Write to 0 for future compatibility. 25–17 UART_STOP UART Stop Normal operation. Stops the UART clock. UART clock stopped. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 246: General Configuration Register 1 (Gcr1)
PRESCALE_ SRIO_PRESCALE_CFG OV_EN Type Reset — DMA_DBG Type Reset CORE5_STP_ CORE4_STP_ CORE3_STP_ CORE2_STP_ CORE1_STP_ CORE0_STP_ — Type Reset — CORE5_DBG CORE4_DBG CORE3_DBG CORE2_DBG CORE1_DBG CORE0_DBG _REQ _REQ _REQ _REQ _REQ _REQ Type Reset MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 247 Core 1 Debug Request No debug request. Asserts a debug request to core 1 Debug request. subsystem. CORE0_DBG_REQ Core 0 Debug Request No debug request. Asserts a debug request to core 0 Debug request. subsystem. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 248: General Status Register 1 (Gsr1)
Reflects whether core 1 subsystem is in Core subsystem in Wait state. Wait state. CORE_WAIT_ACK0 Core Wait Acknowledge 0 Core subsystem not in Wait state. Reflects whether core 0 subsystem is in Core subsystem in Wait state. Wait state. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 249 Not in Debug mode. Reflects the mode of core 1 subsystem. In Debug mode. CORE_DBG_STS0 Core0 Debug Status 0 Not in Debug mode. Reflects the mode of core 0 subsystem. In Debug mode. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 250: High Speed Serial Interface Status Register (Hssi_Sr)
IDLE Type Reset HSSI_SR controls part of the SerDes operation for the MSC8158E device. The register is reset on a Table 8-4 lists the HSSI_SR bit Hard reset. Write accesses can only be performed in Supervisor mode. field descriptions. Table 8-4. HSSI_SR Bit Descriptions...
Page 251 Reserved. Write to 0 for future compatibility. EMSG_STOP_ACK RapidIO Enhanced Messaging Unit Stop Not stopped. Acknowledge Status Stop ACK issued. Indicates the EMSG Stop Acknowledge status. — Reserved. Write to 0 for future compatibility. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 252 — Reserved. Write to 0 for future compatibility. 3–1 EMSG_IDLE EMSG Idle Active. Indicates whether the EMSG is idle, that is, no Idle. transactions in progress. MSC8158E Reference Manual, Rev. 2 8-10 Freescale Semiconductor...
Page 253: Ddr General Control Register (Ddr_Gcr)
VALUE Type Reset DDR_GCR controls the DDR operation the MSC8158E device. The register is reset on a Hard reset. Table 8-5 lists the DDR_GCR bit field Write accesses can only be performed in Supervisor mode. descriptions. Table 8-5. DDR_GCR Bit Descriptions...
Page 254: High Speed Serial Interface Control Register 1 (Hssi_Cr1)
HSSI_CR1 controls various functions within the SerDes block for the MSC8158E device. The Table 8-6 register is reset on a hard reset. Write accesses can only be performed in Supervisor mode. lists the HSSI_CR1 bit field descriptions. MSC8158E Reference Manual, Rev. 2 8-12 Freescale Semiconductor...
Page 255 Serial RapidIO Port 1. SRIO0_ECC_ Serial RapidIO Port 0 Multi-Bit ECC Error Do not inject error. ERR_INJECT Inject Inject error. Indicates whether to inject a multibit error into the Serial RapidIO Port 0. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-13...
Page 256 1–0 Note: Doze mode is a special mode used by the MSC8158E to allow register reads/writes to continue and be acknowledged without changing or reporting any register contents while the peripheral clocking is stopped. Processing of reads/writes can continue after the peripheral has entered power down mode. Without Doze mode, the device could hang up waiting for a response from the peripheral.
Page 257: High Speed Serial Interface Control Register 2 (Hssi_Cr2)
Powers down the SRIO1 pipe interface to SerDes if the SerDes Power down SRIO1 PLL2 becomes unstable. pipe. PD_SRIO__0_TO_ SerDes Power Down No action. Powers down the SRIO0 pipe interface to SerDes if the SerDes Power down SRIO0 PLL1 becomes unstable. pipe. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-15...
Page 258: Quicc Engine Control Register (Qecr)
Reserved. Write to 0 for future compatibility. 8.2.8 QUICC Engine Control Register (QECR) QECR QUICC Engine Control Register Offset 0x1C — Type Reset — Type Reset — Type Reset — ENET_SGMII ENET_SGMII — _MODE1 _MODE0 Type Reset MSC8158E Reference Manual, Rev. 2 8-16 Freescale Semiconductor...
Page 259: Gpio Pull-Up Enable Register (Gpuer)
Type Reset PUE_B23 PUE_B22 PUE_B21 PUE_B20 PUE_B19 PUE_B18 PUE_B17 PUE_B16 Type Reset PUE_B15 PUE_B14 PUE_B13 PUE_B12 PUE_B11 PUE_B10 PUE_B9 PUE_B8 Type Reset PUE_B7 PUE_B6 PUE_B5 PUE_B4 PUE_B3 PUE_B2 PUE_B1 PUE_B0 Type Reset MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-17...
Page 260: Gpio Input Enable Register (Gier)
Table 8-10. GIER Bit Descriptions Name Reset Description Settings IE[31–0] Input Enable 31–0 Input is disabled. 31–0 Each bit in this field enables/disables the Input is enabled. individual GPIO corresponding to the bit index number. MSC8158E Reference Manual, Rev. 2 8-18 Freescale Semiconductor...
Page 261: System Part And Revision Id Register (Spridr)
31–16 Mask-programmed with a code corresponding to the device number. REVID 0x0000 Revision Identification 15–0 Mask-programmed with a code corresponding to the revision number of the part identified by the PARTID value. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-19...
Page 262: General Control Register 4 (Gcr4)
GCR4 controls the delay lines for UCC1 and UCC3. The register is reset on a Hard reset. Write accesses can only be performed in Supervisor mode. The MSC8158E Data Sheet includes recommended default values for this register to use with a standard RGMII PHY device. AN4134 RGMII Ethernet Timing in StarCore Based MSC8157 DSPs (available under NDA) provides guidelines for adjusting GCR4 values for specific applications, if required.
Page 263 00 No delay. 1–0 Adds a delay to the specified signal. 01 One delay unit. 10 Two delay units. 11 Three delay units. Note: The clock for the delay unit is the TX clock. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-21...
Page 264 200 mV. Selects the drowsy M3 memory voltage. 300 mV. — Reserved. Write to zero for future compatibility. DROWSY_M2 Drowsy M2 Voltage Select 200 mV. Selects the drowsy M2 memory voltage. 300 mV. MSC8158E Reference Manual, Rev. 2 8-22 Freescale Semiconductor...
Page 265 OCNDMA0 is stopped. OCNDMA0_ OCNDMA 0 Stop OCNDMA0 normal operation. STOP Makes the OCNDMA0 enter Stop mode. OCNDMA0 Stop mode. — Reserved. Write to zero for future compatibility. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-23...
Page 266: General Status Register 2 (Gsr2)
Reflects whether a core stop was requested. Core 5 stop requested. CORE_STOP_ Core 4 Stop Request Core 4 stop not requested. REQ4 Reflects whether a core stop was requested. Core 4 stop requested. MSC8158E Reference Manual, Rev. 2 8-24 Freescale Semiconductor...
Page 267 Active IDLE Reflects the current status of the OCNDMA0 block. Idle OCNDMA0_ OCNDMA0 Stop Acknowledge No stop ACK issued. STOP_ACK Indicates that the OCNDMA0 block acknowledged a Stop ACK issued. Stop request. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-25...
Page 268: Core Subsystem Slave Port Priority Control Register (Tsppcr)
SPP_P0_MAP Slave Port Mapping Priority 0 All transactions with priority 0 are assigned priority 0. Indicates the priority for the core slave port. All transactions with priority 0 are assigned priority 1. MSC8158E Reference Manual, Rev. 2 8-26 Freescale Semiconductor...
Page 269: General Status Register 3 (Gsr3)
Indicates whether the smallform-factor pluggable SFP device reported LOS. (SFP) optical transceiver connected to CPRI4 indicates a loss-of-signal (LOS) status, meaning that the received optical power is below the worst-case receiver sensitivity. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-27...
Page 270 Reflects the status of the MAPLE-B CRPE power. Power up. — Reserved. Write to zero for future compatibility. ERASE_DONE Erase Done Erase not done. Reflects the status of the erase operation. Erase done. MSC8158E Reference Manual, Rev. 2 8-28 Freescale Semiconductor...
Page 271: General Control Register 6 (Gcr6)
CP_LOSx signals. If the bit is set (1), it selects the RGMII2 signals. The remaining RGMII signals have dedicated connections that are not multiplexed. — Reserved. Write to zero for future compatibility. 1–0 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-29...
Page 272: General Control Register 7 (Gcr7)
Reserved. Write to zero for future compatibility. 7–6 TIMER_32B_0 Input Select for 32-bit Timer 0 See Table 8-19 for multiplexing _MUX0_SEL Selects the input (out of 64) for the timer. options. 5–0 MSC8158E Reference Manual, Rev. 2 8-30 Freescale Semiconductor...
Page 273 0x20 (32) CPRI1 Tx BFP Out 260 ns 0x21 (33) CPRI2 Tx BFP Out 260 ns 0x22 (34) CPRI3 Tx BFP Out 260 ns 0x23 (35) CPRI4 Tx BFP Out 260 ns MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-31...
Page 274 0x38 (56) reserved — 0x39 (57) reserved — 0x3A (58) reserved — 0x3B (59) reserved — 0x3C (60) reserved — 0x3D (61) reserved — 0x3E (62) reserved — 0x3F (63) reserved — MSC8158E Reference Manual, Rev. 2 8-32 Freescale Semiconductor...
Page 275: General Control Register 8 (Gcr8)
Input Select for 32-bit Timer 2 See Table 8-19 for multiplexing _MUX2_SEL Selects the input (out of 64) for the timer. options. 21–16 — Reserved. Write to zero for future compatibility. 15–14 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-33...
Page 276: General Control Register 10 (Gcr10)
Settings GPIO_SLEW_ GPIO Slew Rate Control Medium. RATE_ Used with GPIO signal to set the slew rate for the High. CONTROL signals. — 0x1FFFFFF Reserved. Write to ones for future compatibility. 30–6 MSC8158E Reference Manual, Rev. 2 8-34 Freescale Semiconductor...
Page 277: General Interrupt Register 1 (Gir1)
GIR1 General Interrupt Register 1 Offset 0x80 SWT7 SWT6 SWT5 SWT4 SWT3 SWT2 SWT1 SWT0 Type Reset O2M1_ERR O2M0_ERR — DMA_ERR CE_IECC CE_DECC — Type Reset — Type Reset — Type Reset MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-35...
Page 278 CE_DECC QUICC Engine DRAM Error Interrupt not asserted Reflects the status of the QUICC Engine DRAM Interrupt asserted ECC error interrupt. — Reserved. Write to zero for future compatibility. 17–0 MSC8158E Reference Manual, Rev. 2 8-36 Freescale Semiconductor...
Page 279: General Interrupt Enable Register 1 (Gier1_X)
SWT 4 Interrupt Enable Interrupt disabled Interrupt enabled SWT3_EN SWT 3 Interrupt Enable Interrupt disabled Interrupt enabled SWT2_EN SWT 2 Interrupt Enable Interrupt disabled Interrupt enabled SWT1_EN SWT 1 Interrupt Enable Interrupt disabled Interrupt enabled MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-37...
Page 280: General Interrupt Register 3 (Gir3)
GIR3 General Interrupt Register 3 Offset 0xA4 — CLS1_ERR CLS1_WP Type Reset CLS1_OV — DDR_ERR — MAPLE_ECC_ — Type Reset — MAPLE_GEN_ — Type Reset — CLS0_ERR — CLS0_WP CLS0_OV Type Reset MSC8158E Reference Manual, Rev. 2 8-38 Freescale Semiconductor...
Page 281 Detailed Register Descriptions GIR3 includes interrupt status of some debug/profiling events within MSC8158E. Those bits are not sticky but only sample the events. The GIR3 register is reset by a hard reset event. All bits are cleared on reset Table 8-24. GIR3 Bit Descriptions...
Page 282: General Interrupt Enable Register 3 For Cores 0-3 (Gier3_X)
Reset GIER3_[0–5] include interrupt enable bits for cores 0–5 for debug/profiling events within MSC8158E. GIER3_[0–5] are reset by a hard reset event. All bits are cleared on reset. Write accesses to this register can be performed only in supervisor mode Table 8-25.
Page 283 CLASS0 Error Interrupt Enable Interrupt disabled Interrupt enabled — Reserved. Write to zero for future compatibility. 3–2 CLS0_WP_EN CLASS0 Watchpoint Interrupt Enable Interrupt disabled Interrupt enabled CLS0_OV_EN CLASS0 Overrun Interrupt Enable Interrupt disabled Interrupt enabled MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-41...
Page 284: General Interrupt Register 5 (Gir5)
Type Reset GIR5 includes interrupt status of some internal events within MSC8158E. Those bits are sticky and cleared by writing a 1 to the bit. The GIR5 register is reset by a hard reset event. All bits are cleared on reset Write accesses to this register can only be performed in supervisor mode.
Page 285 Stop mode. T0_T1_AE Core 0 or Core 1 L2/M2 Access Error Interrupt Interrupt not asserted Reflects L2/M2 Access Error Interrupt which occurs Interrupt asserted when the referenced core is in Stop mode. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-43...
Page 286: General Interrupt Enable Register 5 (Gier5_X)
Reserved. Write to zero for future compatibility. 31–23 EMSG_ECC_ERR_EN EMSG ECC Error Enable Interrupt disabled Enables/disables the interrupt. Interrupt enabled DMA2OCN1_ECC_ERR DMA2OCN1 ECC Error Enable Interrupt disabled _ EN Enables/disables the interrupt. Interrupt enabled MSC8158E Reference Manual, Rev. 2 8-44 Freescale Semiconductor...
Page 287 Core 2 or Core 3 L2/M2 Access Error Interrupt disabled Interrupt Enable Interrupt enabled Enables/disables the interrupt. T0_T1_AE_EN Core 0 or Core 1 L2/M2 Access Error Interrupt disabled Interrupt Enable Interrupt enabled Enables/disables the interrupt. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-45...
Page 288: General Control Register 11 (Gcr11)
MBus System Fast Arbitration Initial Weight 0 Ranges from 0000 (lowest) to _FAST_INIT0_ Selects the initial fast arbitration weight for internal 1111 (highest weight—default) WEIGHT test and SEC (if present) accesses. 7–4 MSC8158E Reference Manual, Rev. 2 8-46 Freescale Semiconductor...
Page 289: General Control Register 13 (Gcr13)
Table 8-29. GCR13 Bit Descriptions Name Reset Description Settings MAPLE_PIO_ MAPLE Input Allows a master to write to registers available to the 31–8 MAPLE RISC engines. — Reserved. Write to zero for future compatibility. 7–0 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-47...
Page 290: General Status Register 8 (Gsr8)
Table 8-30. GSR8 Bit Descriptions Name Reset Description Settings MAPLE_PIO_ MAPLE Output Allows a master to read from registers available to 31–8 the MAPLE RISC engines. — Reserved. Write to zero for future compatibility. 7–0 MSC8158E Reference Manual, Rev. 2 8-48 Freescale Semiconductor...
Page 291: Dma Request0 Control Register (Gcr_Dreq0)
DREQ associated with Channel 15 source. DMA_DREQ0_ DMA DREQ0 Destination Channel 14 DREQ not associated with Associates the DREQ with the destination for Channel 14 destination. Channel 14. DREQ associated with Channel 14 destination. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-49...
Page 292 DREQ associated with Channel 9 destination. DMA_DREQ0_ DMA DREQ0 Source Channel 9 DREQ not associated with Associates the DREQ with the source for Channel Channel 9 source. DREQ associated with Channel 9 source. MSC8158E Reference Manual, Rev. 2 8-50 Freescale Semiconductor...
Page 293 DREQ associated with Channel 4 source. DMA_DREQ0_ DMA DREQ0 Destination Channel 3 DREQ not associated with Associates the DREQ with the destination for Channel 3 destination. Channel 3. DREQ associated with Channel 3 destination. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-51...
Page 294 DREQ associated with Channel 0 destination. DMA_DREQ0_ DMA DREQ0 Source Channel 0 DREQ not associated with Associates the DREQ with the source for Channel Channel 0 source. DREQ associated with Channel 0 source. MSC8158E Reference Manual, Rev. 2 8-52 Freescale Semiconductor...
Page 295: Dma Request1 Control Register (Gcr_Dreq1)
DREQ associated with Channel 15 source. DMA_DREQ1_ DMA DREQ1 Destination Channel 14 DREQ not associated with Associates the DREQ with the destination for Channel 14 destination. Channel 14. DREQ associated with Channel 14 destination. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-53...
Page 296 DREQ associated with Channel 9 destination. DMA_DREQ1_ DMA DREQ1 Source Channel 9 DREQ not associated with Associates the DREQ with the source for Channel Channel 9 source. DREQ associated with Channel 9 source. MSC8158E Reference Manual, Rev. 2 8-54 Freescale Semiconductor...
Page 297 DREQ associated with Channel 4 source. DMA_DREQ1_ DMA DREQ1 Destination Channel 3 DREQ not associated with Associates the DREQ with the destination for Channel 3 destination. Channel 3. DREQ associated with Channel 3 destination. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-55...
Page 298 DREQ associated with Channel 0 destination. DMA_DREQ1_ DMA DREQ1 Source Channel 0 DREQ not associated with Associates the DREQ with the source for Channel Channel 0 source. DREQ associated with Channel 0 source. MSC8158E Reference Manual, Rev. 2 8-56 Freescale Semiconductor...
Page 299: Dma Done Control Register (Gcr_Ddone)
Table 8-33. GCR_DDONE Bit Descriptions Name Reset Description Settings — Reserved. Write to zero for future compatibility. 31–14 Valid DONE1 DONE1_CH is not valid. Indicates whether the value of DONE1_CH is valid. DONE1_CH is valid. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-57...
Page 300 11010 Channel 13 source. 11011 Channel 13 destination. 11100 Channel 14 source. 11101 Channel 14 destination. 11110 Channel 15 source. 11111 Channel 15 destination. — Reserved. Write to zero for future compatibility. 7–6 MSC8158E Reference Manual, Rev. 2 8-58 Freescale Semiconductor...
Page 301 11000 Channel 12 source. 11001 Channel 12 destination. 11010 Channel 13 source. 11011 Channel 13 destination. 11100 Channel 14 source. 11101 Channel 14 destination. 11110 Channel 15 source. 11111 Channel 15 destination. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-59...
Page 302: Ddr Controller General Configuration Register (Ddrc_Gcr)
MBus Plus Source ID REF_SRC_ID Used to identify the source ID for profiling. 24–20 MBUS_PLUS_ MBus Plus Late Arbitration Control Do not enable late arbitration. LATE_ARB_ Enables/disables late arbitration. Enable late arbitration. MSC8158E Reference Manual, Rev. 2 8-60 Freescale Semiconductor...
Page 303 This step should be included as part of the initialization code. DDRC_ DDRC Power Down DDRC power up. POWER_ When set, powers down all DDR areas with gated clocks. DDRC power down. DOWN MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-61...
Page 304: Core Subsystem Slave Port General Configuration Register
Set the bit to 1 to disable accesses by the device Core 2 M2/L2 memory. peripherals (that is, DMAC, QUICC Engine module, Disable peripheral access to and so on) to M2/L2 in core 2. Core 2 M2/L2 memory. MSC8158E Reference Manual, Rev. 2 8-62 Freescale Semiconductor...
Page 305: Quicc Engine Input General Control Register (Qe_Pio_In_Gcr)
Name Reset Description Settings QE_PIO_IN QUICC Engine Input 31–8 Allows a master to write to registers available to the QUICC Engine RISC engines. — Reserved. Write to zero for future compatibility. 7–0 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-63...
Page 306: Quicc Engine Output General Status Register (Qe_Pio_Out_Gsr)
Name Reset Description Settings QE_PIO_OUT QUICC Engine Output 31–8 Allows a master to read from registers available to the QUICC Engine RISC engines. — Reserved. Write to zero for future compatibility. 7–0 MSC8158E Reference Manual, Rev. 2 8-64 Freescale Semiconductor...
Page 307: L2Q Arbitration Control For Core Subsystems 0 And 1
T_0_1_ L2Q Arbitration Control Enable Disabled UPGRADE_EN Controls whether priority auto-upgrade is enabled. Enabled T_0_1_ L2Q Arbitration Value UPGRADE_ Determines the value to use for priority auto upgrade VALUE when enabled. 15–0 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-65...
Page 308: L2Q Arbitration Control For Core Subsystems 2 And 3
T_2_3_ L2Q Arbitration Control Enable Disabled UPGRADE_EN Controls whether priority auto-upgrade is enabled. Enabled T_2_3_ L2Q Arbitration Value UPGRADE_ Determines the value to use for priority auto upgrade VALUE when enabled. 15–0 MSC8158E Reference Manual, Rev. 2 8-66 Freescale Semiconductor...
Page 309: L2Q Arbitration Control For Core Subsystems 4 And 5
T_4_5_ L2Q Arbitration Control Enable Disabled UPGRADE_EN Controls whether priority auto-upgrade is enabled. Enabled T_4_5_ L2Q Arbitration Value UPGRADE_ Determines the value to use for priority auto upgrade VALUE when enabled. 15–0 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-67...
Page 310: General Interrupt Register 6 (Gir6)
CPRI3 Transmit Control Interrupt Interrupt not asserted CTRL3 Reflects the status of the interrupt. Interrupt asserted CPRI_TX_ CPRI2 Transmit Control Interrupt Interrupt not asserted CTRL2 Reflects the status of the interrupt. Interrupt asserted MSC8158E Reference Manual, Rev. 2 8-68 Freescale Semiconductor...
Page 311 Reflects the status of the interrupt. Interrupt asserted TIMING2 CPRI_TX_ CPRI1 Transmit Frame Timing Interrupt Interrupt not asserted FRAME_ Reflects the status of the interrupt. Interrupt asserted TIMING1 — Reserved. Write to zero for future compatibility.v 7–6 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-69...
Page 312 Interrupt not asserted FRAME_ Reflects the status of the interrupt. Interrupt asserted TIMING2 CPRI_RX_ CPRI1 Receive Frame Timing Interrupt Interrupt not asserted FRAME_ Reflects the status of the interrupt. Interrupt asserted TIMING1 MSC8158E Reference Manual, Rev. 2 8-70 Freescale Semiconductor...
Page 313: General Interrupt Enable Register 6 (Gier6_X)
Reserved. Write to zero for future compatibility.v 31–30 CPRI_TX_ CPRI6 Transmit Control Interrupt Enable Interrupt disabled CTRL6 Enables/disables the interrupt. Interrupt enabled CPRI_TX_ CPRI5 Transmit Control Interrupt Enable Interrupt not asserted CTRL5 Enables/disables the interrupt. Interrupt asserted MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-71...
Page 314 CPRI_TX_ CPRI4 Transmit Frame Timing Interrupt Enable Interrupt disabled FRAME_ Enables/disables the interrupt. Interrupt enabled TIMING4 CPRI_TX_ CPRI3 Transmit Frame Timing Interrupt Enable Interrupt disabled FRAME_ Enables/disables the interrupt. Interrupt enabled TIMING3 MSC8158E Reference Manual, Rev. 2 8-72 Freescale Semiconductor...
Page 315 CPRI_RX_ CPRI2 Receive Frame Timing Interrupt Enable Interrupt disabled FRAME_ Enables/disables the interrupt. Interrupt enabled TIMING2 CPRI_RX_ CPRI1 Receive Frame Timing Interrupt Enable Interrupt disabled FRAME_ Enables/disables the interrupt. Interrupt enabled TIMING1 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-73...
Page 316: General Interrupt Register 7 (Gir7)
Type Reset GIR7 includes interrupt status of some internal events within MSC8158E. Those bits are not sticky, but only sample events. GIR7 is reset by a hard reset event. All bits are cleared on reset Table 8-43. GIR7 Bit Descriptions...
Page 317 Reserved. Write to zero for future compatibility.v 7–5 EMSG_BM_ EMSG Buffer Manager General Error Interrupt Interrupt not asserted GEN_ERR Reflects the status of the EMSG buffer manager Interrupt asserted general error interrupt. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-75...
Page 318: General Interrupt Enable Register 7 (Gier7_X)
EMSG_QM_ RX7_EN RX6_EN RX5_EN RX4_EN RX3_EN RX2_EN RX1_EN RX0_EN Type Reset EMSG_BM7_ EMSG_BM6_ EMSG_BM5_ EMSG_BM4_ EMSG_BM3_ EMSG_BM2_ EMSG_BM1_ EMSG_BM0_ Type Reset — EMSG_BM_ EMSG_QM_ — EMSG_GEN_ — GEN_ERR_ GEN_ERR_ ERR_EN Type Reset MSC8158E Reference Manual, Rev. 2 8-76 Freescale Semiconductor...
Page 319 Enables/disables the interrupt. Interrupt enabled EMSG_QM_ EMSG QM RX1 Interrupt Enable Interrupt disabled RX1_EN Enables/disables the interrupt. Interrupt enabled EMSG_QM_ EMSG QM RX0 Interrupt Enable Interrupt disabled RX0_EN Enables/disables the interrupt. Interrupt enabled MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-77...
Page 320 Reserved. Write to zero for future compatibility.v EMSG_GEN_ EMSG General Error Interrupt Enable Interrupt disabled ERR_EN Enables/disables the interrupt. Interrupt enabled CPRI_GEN_ CPRI General Error Interrupt Enable Interrupt disabled ERR_EN Enables/disables the interrupt. Interrupt enabled MSC8158E Reference Manual, Rev. 2 8-78 Freescale Semiconductor...
Page 321: Ddr View Through L2 Memory Core Subsystems 0-3 (L2Map_0_3)
Defines the core subsystem window seen by the DDR memory through the L2 cache. — Reserved. Write to zero for future compatibility. 7–6 L2MAP_0 L2 Map for Core Subsystem 0 5–0 Defines the core subsystem window seen by the DDR memory through the L2 cache. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-79...
Page 322: Ddr View Through L2 Memory Core Subsystems 4-5 (L2Map_4_5)
Defines the core subsystem window seen by the DDR memory through the L2 cache. — Reserved. Write to zero for future compatibility. 7–6 L2MAP_4 L2 Map for Core Subsystem 0 5–0 Defines the core subsystem window seen by the DDR memory through the L2 cache. MSC8158E Reference Manual, Rev. 2 8-80 Freescale Semiconductor...
Page 323: Emsg To Quicc Engine External Request Enable (Cpceer)
TX5_QE_ EN_1 External Request 1 Enable Interrupt asserted Enables/disables the interrupt. EMSG_QM_ EMSG QM TX4 Interrupt to QUICC Engine Interrupt disabled TX4_QE_ EN_1 External Request 1 Enable Interrupt enabled Enables/disables the interrupt. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-81...
Page 324 TX4_QE_ EN_0 External Request 0 Enable Interrupt enabled Enables/disables the interrupt. EMSG_QM_ EMSG QM TX3 Interrupt to QUICC Engine Interrupt disabled TX3_QE_ EN_0 External Request 0 Enable Interrupt enabled Enables/disables the interrupt. MSC8158E Reference Manual, Rev. 2 8-82 Freescale Semiconductor...
Page 325 RX1_QE_ EN_0 External Request 0 Enable Interrupt enabled Enables/disables the interrupt. EMSG_QM_ EMSG QM RX0 Interrupt to QUICC Engine Interrupt disabled RX0_QE_ EN_0 External Request 0 Enable Interrupt enabled Enables/disables the interrupt. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-83...
Page 326: Rgmii1 High Resolution Delay Register (Ucc1_Delay_Hr)
RGMII1 RX clock-in delay. UCC1TCLK1_ UCC1 TX Clock In Delay—Bypass Short 2 Enables the tap delay. BYPASSSHRT_2 Allows you to include/exclude a short tap delay to the Disables the tap delay. RGMII1 TX clock-in delay. MSC8158E Reference Manual, Rev. 2 8-84 Freescale Semiconductor...
Page 327 There are four high resolution tap delays that can be added for each signal line: two short delays and two medium delays. The sum of the stow short delays plus the two medium delays is equal to one long delay (see Table 8-12 for details on how the delays are combined). MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-85...
Page 328: Rgmii2 High Resolution Delay Register (Ucc3_Delay_Hr)
RGMII2 RX clock-in delay. UCC3TCLK1_ UCC3 TX Clock In Delay—Bypass Short 2 Enables the tap delay. BYPASSSHRT_2 Allows you to include/exclude a short tap delay to the Disables the tap delay. RGMII2 TX clock-in delay. MSC8158E Reference Manual, Rev. 2 8-86 Freescale Semiconductor...
Page 329 There are four high resolution tap delays that can be added for each signal line: two short delays and two medium delays. The sum of the stow short delays plus the two medium delays is equal to one long delay (see Table 8-12 for details on how the delays are combined). MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-87...
Page 330: General Interrupt Register 8 (Gir8)
Reflects the status of the interrupt. CPRI2 indicates a Interrupt asserted frame boundary detected. CPRI1 CPRI to MAPLE Interrupt 1 Interrupt not asserted Reflects the status of the interrupt. CPRI1 indicates Interrupt asserted as sub-slot (256 chips) detected. MSC8158E Reference Manual, Rev. 2 8-88 Freescale Semiconductor...
Page 331: Cpri To Maple External Request Enable (Maple_Ext_Req_En_1)
CPRI to MAPLE Interrupt 2 External Request Enable Interrupt disabled Enables/disables the interrupt. Interrupt enabled CPRI1_MPL_ EN CPRI to MAPLE Interrupt 1 External Request Enable Interrupt disabled Enables/disables the interrupt. Interrupt enabled MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 8-89...
Page 332 General Configuration Registers MSC8158E Reference Manual, Rev. 2 8-90 Freescale Semiconductor...
Page 333: Memory Map
Memory Map This section describes the memory map of MSC8158E. The MSC8158E incorporates four address spaces: Shared memory (M3, DDR, QUICC Engine subsystem, boot ROM, and MAPLE-B2) address space. Shared SC3850 DSP core subsystem M2/L2 memories SC3850 DSP core subsystem internal address space, accessible only by the SC3850 core.
Page 334: Shared Sc3850 Dsp Core Subsystem M2/L2 Memories
Core subsystem 3 can access the L2 memory of core subsystems 3, 4, and 5. Core subsystem 4 can only access the L2 memory of core subsystem 4 (itself). Core subsystem 5 can only access the L2 memory of core subsystem 5 (itself). MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 335 (40000000 + Y × 32 MB) to (41FFFFFF + Y × 32 MB). Y is the Core5 slave port 6-bit mapping from the GCR. Y = 0 to 63 and mapped to the DDR. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 336 16 M – 512 K 0x34000000–0x3407FFFF Core 4 M2 memory 512 K max. Not all of the 512 KB are always allocated as M2. The allocation and illegal access detection are controlled by the core subsystem. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 337: Sc3850 Dsp Core Subsystem Internal Address Space
CCSR Address Space The MSC8158E CCSR is mapped within a contiguous block of memory starting as 0xFFF10000. The size of the CCSR in MSC8158E is 956 KB. Table 9-4 details the CCSR address space. Table 9-4. CCSR Address Space Address...
Page 338 Dedicated DMA Controller 0 0xFFFA9000–0xFFFA9FFF DMA Controller 0 to OCN 0xFFFAA000–0xFFFAAFFF Dedicated DMA Controller 1 0xFFFAB000–0xFFFABFFF DMA Controller 1 to OCN 0xFFFAC000–0xFFFACFFF Reserved 0xFFFAD000–0xFFFAD7FF SerDes PHY 1 0xFFFAD800–0xFFFB6FFF Reserved 38 K 0xFFFB7000–0xFFFB7FFF Reserved MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 339: Initiators Views Of The System Address Space
Reserved for Core 2 index + 2) × 0x1000000) – 0x34000000–0x34FFFFFF Reserved for Core 3 1. For cores 4–5, the end 0x35000000–0x3FFFFFFF Reserved for Core 4 address is fixed. 0x36000000–0x3FFFFFFF Reserved for Core 5 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 340: Peripherals View Of The System Address Space
Reserved 9.5.2 Peripherals View of the System Address Space Table 9-6 describes the system address space as seen by the MSC8158E peripherals (RapidIO controllers, JTAG, QUICC Engine subsystem, DMA, and MAPLE-B–both MBus interfaces). Table 9-6. Peripherals View of the System Address Space...
Page 341: Detailed System Memory Map
CRPE-DL Output Mode Configuration Parameter. (programmed by API) CDOMCP 0xE000002F − 0xE0000030– CRPE-ULB Mode Configuration Parameter. (programmed by API) CUBMCP 0xE0000033 − 0xE0000034– reserved 0xE000003F − 0xE0000040– MAPLE CRPE Reset Completion Indication Parameter MCRRCIP 0xE0000043 − 0xE0000044– reserved 0xE000007F MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 342 MAPLE eTVPE BD Ring Low Priority B 2 Parameter MTVBRLPB2P 0xE00000D7 − 0xE00000D8– MAPLE eTVPE BD Ring Low Priority A 3 Parameter MTVBRLPA3P 0xE00000DB − 0xE00000DC– MAPLE eTVPE BD Ring Low Priority B 3 Parameter MTVBRLPB3P 0xE00000DF MSC8158E Reference Manual, Rev. 2 9-10 Freescale Semiconductor...
Page 343 MAPLE eFTPE_0 BD Ring High Priority B 6 Parameter MF0BRHPB6P 0xE0000137 − 0xE0000138– MAPLE eFTPE_0 BD Ring High Priority A 7 Parameter MF0BRHPA7P 0xE000013B − 0xE000013C– MAPLE eFTPE_0 BD Ring High Priority B 7 Parameter MF0BRHPB7P 0xE000013F MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-11...
Page 344 MAPLE eFTPE_1 BD Ring High Priority B 2 Parameter MF1BRHPB2P 0xE0000197 − 0xE0000198– MAPLE eFTPE_1 BD Ring High Priority A 3 Parameter MF1BRHPA3P 0xE000019B − 0xE000019C– MAPLE eFTPE_1 BD Ring High Priority B 3 Parameter MF1BRHPB3P 0xE000019F MSC8158E Reference Manual, Rev. 2 9-12 Freescale Semiconductor...
Page 345 MAPLE eFTPE_1 BD Ring Low Priority B 6 Parameter MF1BRLPB6P 0xE00001F7 − 0xE00001F8– MAPLE eFTPE_1 BD Ring Low Priority A 7 Parameter MF1BRLPA7P 0xE00001FB − 0xE00001FC– MAPLE eFTPE_1 BD Ring Low Priority B 7 Parameter MF1BRLPB7P 0xE00001FF MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-13...
Page 346 MAPLE eFTPE_2 BD Ring Low Priority B 2 Parameter MF2BRLPB2P 0xE0000257 − 0xE0000258– MAPLE eFTPE_2 BD Ring Low Priority A 3 Parameter MF2BRLPA3P 0xE000025B − 0xE000025C– MAPLE eFTPE_2 BD Ring Low Priority B 3 Parameter MF2BRLPB3P 0xE000025F MSC8158E Reference Manual, Rev. 2 9-14 Freescale Semiconductor...
Page 347 MAPLE DEPE BD Ring High Priority B 6 Parameter MDEBRHPB6P 0xE00002B7 − 0xE00002B8– MAPLE DEPE BD Ring High Priority A 7 Parameter MDEBRHPA7P 0xE00002BB − 0xE00002BC– MAPLE DEPE BD Ring High Priority B 7 Parameter MDEBRHPB7P 0xE00002BF MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-15...
Page 348 MAPLE CRCPE BD Ring High Priority B 2 Parameter MCRCBRHPB2P 0xE0000317 − 0xE0000318– MAPLE CRCPE BD Ring High Priority A 3 Parameter MCRCBRHPA3P 0xE000031B − 0xE000031C– MAPLE CRCPE BD Ring High Priority B 3 Parameter MCRCBRHPB3P 0xE000031F MSC8158E Reference Manual, Rev. 2 9-16 Freescale Semiconductor...
Page 349 MAPLE CRCPE BD Ring Low Priority B 6 Parameter MCRCBRLPB6P 0xE0000377 − 0xE0000378– MAPLE CRCPE BD Ring Low Priority A 7 Parameter MCRCBRLPA7P 0xE000037B − 0xE000037C– MAPLE CRCPE BD Ring Low Priority B 7 Parameter MCRCBRLPB7P 0xE000037F MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-17...
Page 350 MAPLE CONVPE BD Ring Low Priority A 2 Parameter MCONVBRLPA2P 0xE0000453 − 0xE0000454– MAPLE CONVPE BD Ring Low Priority B 2 Parameter MCONVBRLPB2P 0xE0000457 − 0xE0000458– MAPLE CONVPE BD Ring Low Priority A 3 Parameter MCONVBRLPA3P 0xE000045B MSC8158E Reference Manual, Rev. 2 9-18 Freescale Semiconductor...
Page 351 MAPLE Turbo Viterbi Puncturing Vector 5 High Configuration Parameter MTVPV5HCP 0x0000052B − 0x0000052C– MAPLE Turbo Viterbi Puncturing Vector 5 Low Configuration Parameter MTVPV5LCP 0x0000052F − 0x00000530– MAPLE Turbo Viterbi Puncturing Vector 6 High Configuration Parameter MTVPV6HCP 0x00000533 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-19...
Page 352 − 0xE0000608– eFTPE Data Size Set 1 Parameter 2 FTPEDSS1P2 0xE000060B − 0xE000060C– eFTPE Data Size Set 2 Parameter 0 FTPEDSS2P0 0xE000060F − 0xE0000610– eFTPE Data Size Set 2 Parameter 1 FTPEDSS2P1 0xE0000613 MSC8158E Reference Manual, Rev. 2 9-20 Freescale Semiconductor...
Page 353 MCUBPCH[0–415] SZP 0xE0000E83 − 0xE0000808– MAPLE CRPE ULB Physical Channel 0–415 Write Pointer Parameter MCUBPCH[0–415} WPP 0xE0000E87 − 0xE000080C– MAPLE CRPE ULB Physical Channel 0–415 Output Buffer Interrupt Config MCUBPCH[0–415} OBICP 0xE0000E8B Parameter MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-21...
Page 354 − 0xE0003074– Reserved 0xE000307F − 0x00003080– MAPLE CRPE-ULF Interpolation Bypass Group Attributes 0–7 parameter MCUFIBGA[0–7]P 0x0000309F − 0x000030A0– MAPLE CRPE-ULF Interpolation Bypass Ant Address 0–23 Parameter MCUFIBAA[0–23]P 0x000030FF − 0x00003100– reserved 0x000033FF MSC8158E Reference Manual, Rev. 2 9-22 Freescale Semiconductor...
Page 355 MAPLE CRPE-DL Number of Channels Limit Parameter MCDLNOCLP 0xE0008183 − 0xE0008184– reserved 0xE00087FF − 0xE0008800– reserved 0xE0009FFF − 0xE000A000– Buffer Descriptor (BD) Rings 0xE0011FFF − 0xE0012000– reserved 0xE003FFFF − 0xE0040000– eTVPE (register details begin on page 25-441) 0xE007FFFF MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-23...
Page 356 − 0xE00FE1A0 eFTPE_1 Configuration Register EFTPE1CR − 0xE00FE1A4– reserved 0xE00FE247 − 0xE00FE248 eFTPE_1 ECC Interrupt Status Register EFTPE1ECCISR − 0xE00BE24C– reserved 0xE00FFFFF − 0xE0100000– eFTPE_2 (register details begin on page 25-443) 0xE013FFFF MSC8158E Reference Manual, Rev. 2 9-24 Freescale Semiconductor...
Page 357 UL FAST Interpolation Configuration Register 5 ULFICR5 − 0xE023E098 UL FAST Interpolation Configuration Register 6 ULFICR6 − 0xE023E09C UL FAST Interpolation Configuration Register 7 ULFICR7 − 0xE023E0A0 UL FAST Interpolation Configuration Register 8 ULFICR8 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-25...
Page 358 − 0xE023E178 UL FAST Output Buffer 15 Base Configuration Register ULFOB15BCR − 0xE023E17C UL FAST Output Buffer 15 Attributes Configuration Register ULFOB15ACR − 0xE023E180 UL FAST Output Buffer 16 Base Configuration Register ULFOB16BCR MSC8158E Reference Manual, Rev. 2 9-26 Freescale Semiconductor...
Page 359 CRPE Downlink Event Status Register CDESR − 0x0023F104 CRPE Downlink Processing Stage Status Register CDPSSR − 0x0023F108 CRPE Downlink ECC Status Register CDECCSR − 0xE023F10C CRPE Downlink Rate Control Register CDRLR − 0xE023F110– reserved 0xE023F147 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-27...
Page 360 CRPE Uplink Batch Event Status Register CRUBESR − 0xE025F804– reserved 0xE025F81F − 0xE025F820 CRPE-ULB Output Sat Counter Status Register CRUBOSCSR − 0xE025F824 CRPE-ULB Interpolation Sat Counter Status Register CRUBGNOA0CR − 0xE025F828– reserved 0xE027FFFF − 0xE0280000– reserved 0xE03FFFFF MSC8158E Reference Manual, Rev. 2 9-28 Freescale Semiconductor...
Page 361 0xFEE0012F − 0xFEE00130 QUICC Engine Virtual Task Event Register CEVTER − 0xFEE00134 QUICC Engine Virtual Task Mask Register CEVTMR − 0xFEE00138 QUICC Engine RAM Control Register CERCR − 0xFEE0013C– reserved 0xFEE001B7 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-29...
Page 362 − 0xFEE0202C UCC 1 Transmit FIFO Base UTFB1 − 0xFEE02030 UCC 1 Transmit FIFO Size UTFS1 − 0xFEE02032– reserved 0xFEE02033 − 0xFEE02034 UCC 1 Transmit FIFO Emergency Threshold UTFET1 − 0xFEE02036– reserved 0xFEE02037 MSC8158E Reference Manual, Rev. 2 9-30 Freescale Semiconductor...
Page 363 Ethernet 1 Rx 65- to 127-byte Frames E1RX127 − 0xFEE02194 Ethernet 1 Rx 128- to 255-byte Frames E1RX255 − 0xFEE02198 Ethernet 1 Octet Transmitted OK E1TXOK − 0xFEE0219C Ethernet 1 Tx Pause Frames E1TXCF MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-31...
Page 364 − 0xFEE0223C UCC 3 Transmit Polling Timer UFPT3 − 0xFEE0223E– reserved 0xFEE0223F − 0xFEE02240 UCC 3 Retry Counter URTRY3 − 0xFEE02244– reserved 0xFEE0228F − 0xFEE02290 UCC 3 General Extended Mode Register GUEMR3 MSC8158E Reference Manual, Rev. 2 9-32 Freescale Semiconductor...
Page 365 − 0xFEE023AC Ethernet 2 Rx Octets OK E2RBYT − 0xFEE023B0 Ethernet 2 Rx Octets E2RXBOK − 0xFEE023B4 Ethernet 2 Multicast Frame Received OK E2RMCA − 0xFEE023B8 Ethernet 2 Broadcast Frames Received OK E2RBCA MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-33...
Page 366 DMA (see Chapter 14, Direct Memory Access (DMA) Controller) 0xFFF103FF − 0xFFF10000 DMA Buffer Descriptor Base Register 0 DMABDBR0 − 0xFFF10004 DMA Buffer Descriptor Base Register 1 DMABDBR1 − 0xFFF10008 DMA Buffer Descriptor Base Register 2 DMABDBR2 MSC8158E Reference Manual, Rev. 2 9-34 Freescale Semiconductor...
Page 367 − 0xFFF10204 DMA Channel Enable Register DMACHER − 0xFFF10208– Reserved 0xFFF1020B − 0xFFF1020C DMA Channel Disable Register DMACHDR − 0xFFF10210– Reserved 0xFFF10213 − 0xFFF10214 DMA Channel Freeze Register DMACHFR − 0xFFF10218– Reserved 0xFFF10223 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-35...
Page 368 DMA Debug Event Status Register DMADESR − 0xFFF10378– Reserved 0xFFF1037B − 0xFFF1037C DMA Round Robin Priority Group Update Register DMARRPGUR − 0xFFF10380 DMA Channel Active Status Register DMACHASTR − 0xFFF10384– Reserved 0xFFF10387 MSC8158E Reference Manual, Rev. 2 9-36 Freescale Semiconductor...
Page 369 CLASS Priority Auto Upgrade Value Register 12 C0PAVR12 − 0xFFF18874 CLASS Priority Auto Upgrade Value Register 13 C0PAVR13 − 0xFFF18878 CLASS Priority Auto Upgrade Value Register 14 C0PAVR14 − 0xFFF1887C– reserved 0xFFF1887F MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-37...
Page 370 CLASS Error Extended Address Register 4 C0EEAR4 − 0xFFF189D4 CLASS Error Extended Address Register 5 C0EEAR5 − 0xFFF189D8 CLASS Error Extended Address Register 6 C0EEAR6 − 0xFFF189DC CLASS Error Extended Address Register 7 C0EEAR7 MSC8158E Reference Manual, Rev. 2 9-38 Freescale Semiconductor...
Page 371 CLASS Initiator Watch Point Control Register 11 C0IWPCR11 − 0xFFF18A70 CLASS Initiator Watch Point Control Register 12 C0IWPCR12 − 0xFFF18A74 CLASS Initiator Watch Point Control Register 13 C0IWPCR13 − 0xFFF18A78 CLASS Initiator Watch Point Control Register 14 C0IWPCR14 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-39...
Page 372 − 0xFFF18C84 CLASS Attributes Decoder 1 C0ATD1 − 0xFFF18C88– reserved 0xFFF18C9B − 0xFFF18C9C CLASS Attributes Decoder 7 C0ATD7 − 0xFFF18CA0 CLASS Attributes Decoder 8 C0ATD8 − 0xFFF18CA4 CLASS Attributes Decoder 9 C0ATD9 MSC8158E Reference Manual, Rev. 2 9-40 Freescale Semiconductor...
Page 373 PSPICER0 − 0xFFF1D604 PSIF PIC Event Register 1 PSPICER1 − 0xFFF1D608 PSIF PIC Event Register 2 PSPICER2 − 0xFFF1D60C PSIF PIC Edge/Level Register PSPICELR − 0xFFF1D610 PSIF PIC Mask Register 0 PSPICMR0 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-41...
Page 374 DDR SDRAM Initialization Address Register DDR_INIT_ADDR − 0xFFF2014C DDR Initialization Enable Register DDR_INIT_EN − 0xFFF20150– reserved 0xFFF2015F − 0xFFF20160 DDR SDRAM Timing Configuration 4 Register TIMING_CFG_4 − 0xFFF20164 DDR SDRAM Timing Configuration 5 Register TIMING_CFG_5 MSC8158E Reference Manual, Rev. 2 9-42 Freescale Semiconductor...
Page 375 0xFFF20E1F − 0xFFF20E20 Memory Data Path Read Capture High CAPTURE_DATA_HI − 0xFFF20E24 Memory Data Path Read Capture Low CAPTURE-DATA_LO − 0xFFF20E28 Memory Data Path Read Capture ECC CAPTURE_ECC − 0xFFF20E2C– reserved 0xFFF20E3F MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-43...
Page 376 I2CFDR C Frequency Divider Register − 0xFFF24C08 I2CCR C Control Register − 0xFFF24C0C I2CSR C Status Register − 0xFFF24C10 I2CDR C Data Register − 0xFFF24C14 I2CDFSRR C Digital Filter Sampling Rate Register MSC8158E Reference Manual, Rev. 2 9-44 Freescale Semiconductor...
Page 377 − 0xFFF25300– reserved 0xFFF25303 − 0xFFF25304 System Watchdog Control Register 3 SWCRR3 − 0xFFF25308 System Watchdog Count Register 3 SWCNR3 − 0xFFF2530C– reserved 0xFFF2530D − 0xFFF2530E System Watchdog Service Register 3 SWSRR3 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-45...
Page 378 − 0xFFF25704 System Watchdog Control Register 7 SWCRR7 − 0xFFF25708 System Watchdog Count Register 7 SWCNR7 − 0xFFF2570C– reserved 0xFFF2570D − 0xFFF2570E System Watchdog Service Register 7 SWSRR7 − 0xFFF25710– reserved 0xFFF257FF MSC8158E Reference Manual, Rev. 2 9-46 Freescale Semiconductor...
Page 379 Timer 0 Channel 2 Compare Load 1 Register TMR0CMPLD12 − 0xFFF260A4 Timer 0 Channel 2 Compare Load 2 Register TMR0CMPLD22 − 0xFFF260A8 Timer 0 Channel 2 Comparator Status and Control Register TMR0COMSC2 − 0xFFF260AC– reserved 0xFFF260BF MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-47...
Page 380 Timer 1 Channel 1 Comparator Status and Control Register TMR1COMSC1 − 0xFFF2616C– reserved 0xFFF2617F − 0xFFF26180 Timer 1 Channel 2 Compare 1 Register TMR1CMP12 − 0xFFF26184 Timer 1 Channel 2 Compare 2 Register TMR1CMP22 MSC8158E Reference Manual, Rev. 2 9-48 Freescale Semiconductor...
Page 381 Timer 2 Channel 1 Compare 1 Register TMR2CMP11 − 0xFFF26244 Timer 2 Channel 1 Compare 2 Register TMR2CMP21 − 0xFFF26248 Timer 2 Channel 1 Capture Register TMR2CAP1 − 0xFFF2624C Timer 2 Channel 1 Load Register TMR2LOAD1 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-49...
Page 382 Timer 3 Channel 0 Capture Register TMR3CAP0 − 0xFFF2630C Timer 3 Channel 0 Load Register TMR3LOAD0 − 0xFFF26310 Timer 3 Channel 0 Hold Register TMR3HOLD0 − 0xFFF26314 Timer 3 Channel 0 Counter Register TMR3CNTR0 MSC8158E Reference Manual, Rev. 2 9-50 Freescale Semiconductor...
Page 383 Timer 3 Channel 3 Counter Register TMR3CNTR3 − 0xFFF263D8 Timer 3 Channel 3 Control Register TMR3CTL3 − 0xFFF263DC Timer 3 Channel 3 Status and Control Register TMR3SCTL3 − 0xFFF263E0 Timer 3 Channel 3 Load 1 Register TMR3CMPLD13 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-51...
Page 384 − 0xFFF264A0 Timer_32b 0 Channel 2 Load 1 Register TMR_32b_0_CMPLD12 − 0xFFF264A4 Timer_32b 0 Channel 2 Load 2 Register TMR_32b_0_CMPLD22 − 0xFFF264A8 Timer_32b 0 Channel 2 Comparator Status and Control Register TMR_32b_0_COMSC2 MSC8158E Reference Manual, Rev. 2 9-52 Freescale Semiconductor...
Page 385 Timer_32b 1 Channel 1 Load Register TMR_32b_1_LOAD1 − 0xFFF26650 Timer_32b 1 Channel 1 Hold Register TMR_32b_1_HOLD1 − 0xFFF26654 Timer_32b 1 Channel 1 Counter Register TMR_32b_1_CNTR1 − 0xFFF26658 Timer_32b 1 Channel 1 Control Register TMR_32b_1_CTL1 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-53...
Page 386 TMR_32b_1_SAF3 − 0xFFF2670C Timer_32b 1 Timer Clear Lock Register TMR_32b_1_CLRL • 0xFFF26710– reserved 0xFFF26BFF • 0xFFF26C00– UART (see Chapter 19, UART) 0xFFF26C3F − 0xFFF26C00 SCI Baud-Rate Register SCIBR − 0xFFF26C04– reserved 0xFFF26C07 MSC8158E Reference Manual, Rev. 2 9-54 Freescale Semiconductor...
Page 387 − 0xFFF27124– reserved 0xFFF27127 − 0xFFF27128 Hardware Semaphore Register 5 HSMPR5 − 0xFFF2712C– reserved 0xFFF2712F − 0xFFF27130 Hardware Semaphore Register 6 HSMPR6 − 0xFFF27134– reserved 0xFFF27137 − 0xFFF27138 Hardware Semaphore Register 7 HSMPR7 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-55...
Page 388 − 0xFFF28038 General Status Register 2 GSR2 − 0xFFF2803C Core Subsystem Slave Port Priority Control Register TSPPCR − 0xFFF28040– reserved 0xFFF2804F − 0xFFF28050 General Status Register 3 GSR3 − 0xFFF28054– reserved 0xFFF28060 MSC8158E Reference Manual, Rev. 2 9-56 Freescale Semiconductor...
Page 389 General Control Register 13 GCR13 − 0xFFF2811C General Status Register 8 GSR8 − 0xFFF28120 DMA Request0 Control Register GCR_DREQ0 − 0xFFF28124 DMA Request1 Control Register GCR_DREQ1 − 0xFFF28128 DMA Done Control Register GCR_DDONE MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-57...
Page 390 − 0xFFF281E4 RGMII2 High Resolution Delay Register UCC3_DELAY_HR − 0xFFF281E8 General Interrupt Register 8 GIR8 − 0xFFF281EC– reserved 0xFFF281EF − 0xFFF281F0 CPRI to MAPLE External Request Enable MAPLE_EXT_REQ_EN_1 − 0xFFF281F4– reserved 0xFFF281FF MSC8158E Reference Manual, Rev. 2 9-58 Freescale Semiconductor...
Page 391 Ethernet LSB of MAC Address (32 bits) ETH_ADDR_LSB • 0xFFF40234 Ethernet Small 32 Entries Hash Table to Filter Multicast Traffic ETH_HASH_TABLE • 0xFFF40244 Ethernet Configuration 3 ETH_CONFIG_3 • 0xFFF40248 Ethernet Receive Frame Counter ETH_CNT_RX_FRAME • 0xFFF4024C Reserved MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-59...
Page 392 Tx Control Table Insert Enable 1 CPRInTCTIE1 • 0xFFF404C0 Tx Control Table Insert Enable 2 CPRInTCTIE2 • 0xFFF404C8 Timer Configuration CPRInTMRC • 0xFFF404CC Receive Frame Pulse Width CPRInRFPW • 0xFFF404D0 Transmit Frame Pulse Width CPRInTFPW Control Registers MSC8158E Reference Manual, Rev. 2 9-60 Freescale Semiconductor...
Page 393 CPRI Auxiliary Control Register CPRInAUXCR Status Registers • 0xFFF40800 Receive IQ Buffer Displacement Register CPRInRIQBDR • 0xFFF40804 Receive IQ Buffer Second Destination Displacement Register CPRInRIQSDBDR • 0xFFF40808 Transmit IQ Buffer Displacement Register CPRInTIQBDR MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-61...
Page 394 Inbound Block 0 Classification Unit 0 IB0CU0 0xFFF6003C The individual message type classification registers use this space. • 0xFFF60040– QMLite Inbound Block 0 Message Queue 0 QIB0MQ0 0xFFF6007C The inbound message queue registers use this space. MSC8158E Reference Manual, Rev. 2 9-62 Freescale Semiconductor...
Page 395 Inbound Block 0 Classification Unit 6 IB0CU6 0xFFF60063C The individual message type classification registers use this space. • 0xFFF60640– QMLite Inbound Block 0 Message Queue 6 QIB0MQ6 0xFFF6067C The inbound message queue registers use this space. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-63...
Page 396 • 0xFFF60C10 Pool 0 Hardware Portal Depletion Entry Threshold Register POOL0_HWDET • 0xFFF60C14 Pool 0 Hardware Portal Depletion Exit Threshold Register POOL0_HWDXT • 0xFFF60C18 Pool 0 Hardware Portal Depletion Count Register POOL0_HDCNT MSC8158E Reference Manual, Rev. 2 9-64 Freescale Semiconductor...
Page 397 • 0xFFF60EA8 FBPR Free Pool Depletion Interrupt Threshold Register FBPR_FP_THRES • 0xFFF60EAC Dynamic Power Management Configuration Register DPM_CFG • 0xFFF60EB0 Error Interrupt Status Register ERR_ISR • 0xFFF60EB4 Error Interrupt Enable Register ERR_IER MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-65...
Page 398 Message Unit Outbound Interleaving Mask Register MUOIMR • 0xFFF60F58– reserved 0xFFF60F6F • 0xFFF60F70 Message Unit Segmentation Execution Privilege Register 0 MUSEPR0 • 0xFFF60F74 Message Unit Segmentation Execution Privilege Register 1 MUSEPR1 • 0xFFF60F78– reserved 0xFFF60F7F MSC8158E Reference Manual, Rev. 2 9-66 Freescale Semiconductor...
Page 399 0xFFF6147C The inbound message queue registers use this space. • 0xFFF61480– reserved 0xFFF614BC • 0xFFF614C0– QMLite Outbound Block 1 Message Queue 4 QOB1MQ4 0xFFF614FC The outbound message queue registers use this space. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-67...
Page 400 QIB2MQ1 0xFFF6217C The inbound message queue registers use this space. • 0xFFF62180– reserved 0xFFF621BC • 0xFFF621C0– QMLite Outbound Block 2 Message Queue1 QOB2MQ1 0xFFF621FC The outbound message queue registers use this space. MSC8158E Reference Manual, Rev. 2 9-68 Freescale Semiconductor...
Page 401 0xFFF6277C The inbound message queue registers use this space. • 0xFFF62780– reserved 0xFFF627BC • 0xFFF627C0– QMLite Outbound Block 2 Message Queue 7 QOB2MQ7 0xFFF627FC The outbound message queue registers use this space. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-69...
Page 402 0xFFF6347C The inbound message queue registers use this space. • 0xFFF63480– reserved 0xFFF634BC • 0xFFF634C0– QMLite Outbound Block 3 Message Queue 4 QOB3MQ4 0xFFF634FC The outbound message queue registers use this space. MSC8158E Reference Manual, Rev. 2 9-70 Freescale Semiconductor...
Page 403 QIB4MQ1 0xFFF6417C The inbound message queue registers use this space. • 0xFFF64180– reserved 0xFFF641BC • 0xFFF641C0– QMLite Outbound Block 4 Message Queue1 QOB4MQ1 0xFFF641FC The outbound message queue registers use this space. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-71...
Page 404 0xFFF6477C The inbound message queue registers use this space. • 0xFFF64780– reserved 0xFFF647BC • 0xFFF647C0– QMLite Outbound Block 4 Message Queue 7 QOB4MQ7 0xFFF647FC The outbound message queue registers use this space. MSC8158E Reference Manual, Rev. 2 9-72 Freescale Semiconductor...
Page 405 0xFFF6547C The inbound message queue registers use this space. • 0xFFF65480– reserved 0xFFF654BC • 0xFFF654C0– QMLite Outbound Block 5 Message Queue 4 QOB5MQ4 0xFFF654FC The outbound message queue registers use this space. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-73...
Page 406 QIB6MQ1 0xFFF6617C The inbound message queue registers use this space. • 0xFFF66180– reserved 0xFFF661BC • 0xFFF661C0– QMLite Outbound Block 6 Message Queue1 QOB6MQ1 0xFFF661FC The outbound message queue registers use this space. MSC8158E Reference Manual, Rev. 2 9-74 Freescale Semiconductor...
Page 407 0xFFF6677C The inbound message queue registers use this space. • 0xFFF66780– reserved 0xFFF667BC • 0xFFF667C0– QMLite Outbound Block 6 Message Queue 7 QOB6MQ7 0xFFF667FC The outbound message queue registers use this space. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-75...
Page 408 0xFFF6747C The inbound message queue registers use this space. • 0xFFF67480– reserved 0xFFF674BC • 0xFFF674C0– QMLite Outbound Block 7 Message Queue 4 QOB7MQ4 0xFFF674FC The outbound message queue registers use this space. MSC8158E Reference Manual, Rev. 2 9-76 Freescale Semiconductor...
Page 409 Data Streaming Information Capability Register DSICAR − 0xFFF80040– reserve 0xFFF80047 − 0xFFF80048 Data Streaming Logical Layer Control Command and Status Register DSLLCCSR − 0xFFF8004C Processing Element Logical Layer Control Command and Status Register PELLCCSR MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-77...
Page 410 Logical/Transport Layer Address Capture Command and Status Register LTLACCSR − 0xFFF80618 Logical/Transport Layer Device ID Capture Command and Status Register LTLDIDCCSR − 0xFFF8061C Logical/Transport Layer Control Capture Command and Status Register LTLCCCSR MSC8158E Reference Manual, Rev. 2 9-78 Freescale Semiconductor...
Page 411 − 0xFFF90024– reserved 0xFFF9007F − 0xFFF90080 Physical Retry Error Threshold Configuration Register PRETCR − 0xFFF90084– reserved 0xFFF900FF − 0xFFF90100 Port 1 Alternate Device ID Command and Status Register P1ADIDCSR − 0xFFF90104– reserved 0xFFF9011F MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-79...
Page 412 − 0xFFF901E8 Port 2 Arbitration 1 Tx Configuration Register P2A1TxCR − 0xFFF901EC Port 2 Arbitration 2 Tx Configuration Register P2A2TxCR − 0xFFF901F0 Port 2 Message Request Tx Buffer Allocation Configuration Register 0 P2MReqTxBACR0 MSC8158E Reference Manual, Rev. 2 9-80 Freescale Semiconductor...
Page 413 Port 1 RapidIO Outbound Window Segment 3 Register 3 P1ROWS3R3 − 0xFFF90C80 Port 1 RapidIO Outbound Window Translation Address Register 4 P1ROWTAR4 − 0xFFF90C84 Port 1 RapidIO Outbound Window Translation Extended Address Register 4 P1ROWTEAR4 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-81...
Page 414 Port 1 RapidIO Outbound Window Segment 1 Register 8 P1ROWS1R8 − 0xFFF90D18 Port 1 RapidIO Outbound Window Segment 2 Register 8 P1ROWS2R8 − 0xFFF90D1C Port 1 RapidIO Outbound Window Segment 3 Register 8 P1ROWS3R8 MSC8158E Reference Manual, Rev. 2 9-82 Freescale Semiconductor...
Page 415 Port 1 RapidIO Inbound Window Attributes Register 0 P1RIWAR0 − 0xFFF90DF4– reserved 0xFFF92DFF − 0xFFF90E00 Port 2 RapidIO Outbound Window Translation Address Register 0 P2ROWTAR0 − 0xFFF90E04 Port 2 RapidIO Outbound Window Translation Extended Address Register 0 P2ROWTEAR0 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-83...
Page 416 Port 2 RapidIO Outbound Window Segment 2 Register 4 P2ROWS2R4 − 0xFFF90E9C Port 2 RapidIO Outbound Window Segment 3 Register 4 P2ROWS3R4 − 0xFFF90EA0 Port 2 RapidIO Outbound Window Translation Address Register 5 P2ROWTAR5 MSC8158E Reference Manual, Rev. 2 9-84 Freescale Semiconductor...
Page 417 − 0xFFF90F60 Port 2 RapidIO Inbound Window Translation Address Register 4 P2RIWTAR4 − 0xFFF90F64– reserved 0xFFF90F67 − 0xFFF90F68 Port 2 RapidIO Inbound Window Base Address Register 4 P2RIWBAR4 − 0xFFF90F6C– reserved 0xFFF90F6F MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-85...
Page 418 HSSI OCN Crossbar Switch to MBus0 (see Chapter 15, High Speed Serial Interface (HSSI) Subsystem) 0xFFFA103F • 0xFFFA1040– HSSI OCN Crossbar Switch to MBus1 (see Chapter 15, High Speed Serial Interface (HSSI) Subsystem) 0xFFFA107F MSC8158E Reference Manual, Rev. 2 9-86 Freescale Semiconductor...
Page 419 DMA 1 Current List Descriptor Address Register D0CLSDAR1 − 0xFFFA81B8 DMA 1 Next List Descriptor Extended Address Register D0ENLSDAR1 − 0xFFFA81BC DMA 1 Next List Descriptor Address Register D0NLSDAR1 − 0xFFFA81C0 DMA 1 Source Stride Register D0SSR1 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-87...
Page 420 DMA 3 Next List Descriptor Extended Address Register D0ENLSDAR3 − 0xFFFA82BC DMA 3 Next List Descriptor Address Register D0NLSDAR3 − 0xFFFA82C0 DMA 3 Source Stride Register D0SSR3 − 0xFFFA82C4 DMA 3 Destination Stride Register D0DSR3 MSC8158E Reference Manual, Rev. 2 9-88 Freescale Semiconductor...
Page 421 Local Access Window Attributes Register 5 D0LAWAR5 − 0xFFFA9CB4– reserved 0xFFFA9CC7 − 0xFFFA9CC8 Local Access Window Base Address Register 6 D0LAWBAR6 − 0xFFFA9CCC– reserved 0xFFFA9CCF − 0xFFFA9CD0 Local Access Window Attributes Register 6 D0LAWAR6 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-89...
Page 422 DMA 0 Next List Descriptor Extended Address Register D1ENLSDAR0 − 0xFFFAA13C DMA 0 Next List Descriptor Address Register D1NLSDAR0 − 0xFFFAA140 DMA 0 Source Stride Register D1SSR0 − 0xFFFAA144 DMA 0 Destination Stride Register D1DSR0 MSC8158E Reference Manual, Rev. 2 9-90 Freescale Semiconductor...
Page 423 DMA 2 Next List Descriptor Extended Address Register D1ENLSDAR2 − 0xFFFAA23C DMA 2 Next List Descriptor Address Register D1NLSDAR2 − 0xFFFAA240 DMA 2 Source Stride Register D1SSR2 − 0xFFFAA244 DMA2 Destination Stride Register D1DSR2 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-91...
Page 424 D1LAWAR1 − 0xFFFABC34– reserved 0xFFFABC47 − 0xFFFABC48 Local Access Window Base Address Register 2 D1LAWBAR2 − 0xFFFABC4C– reserved 0xFFFABC4F − 0xFFFABC50 Local Access Window Attributes Register 2 D1LAWAR2 − 0xFFFABC54– reserved 0xFFFABC67 MSC8158E Reference Manual, Rev. 2 9-92 Freescale Semiconductor...
Page 425 Local Access Window Base Address Register 9 D1LAWBAR9 − 0xFFFABD2C– reserved 0xFFFABD2F − 0xFFFABD30 Local Access Window Attributes Register 9 D1LAWAR9 − 0xFFFABD34– reserved 0xFFFA8FFF • 0xFFFAB000– DMA Controller 1 to OCN 0xFFFABFFF • 0xFFFAC000– reserved 0xFFFACFFF MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-93...
Page 426 LCTECR0 • 0xFFFAD29C– reserved 0xFFFAD2BB • 0xFFFAD2BC Lane C Test Control/Status Register 3 LCTCSR3 • 0xFFFAD2C0 Lane D General Control Register 0 LDGCR0 • 0xFFFAD2C4 Lane D General Control Register 1 LDGCR1 MSC8158E Reference Manual, Rev. 2 9-94 Freescale Semiconductor...
Page 427 LGTECR0 • 0xFFFAD39C– reserved 0xFFFAD3BB • 0xFFFAD3BC Lane G Test Control/Status Register 3 LGTCSR3 • 0xFFFAD3C0 Lane H General Control Register 0 LHGCR0 • 0xFFFAD3C4 Lane H General Control Register 1 LHGCR1 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-95...
Page 428 − 0xFFFBA808 CLASS1 Priority Mapping Register 2 C1PMR2 − 0xFFFBA80C CLASS1 Priority Mapping Register 3 C1PMR3 − 0xFFFBA810 CLASS1 Priority Mapping Register 4 C1PMR4 − 0xFFFBA814 CLASS1 Priority Mapping Register 5 C1PMR5 MSC8158E Reference Manual, Rev. 2 9-96 Freescale Semiconductor...
Page 429 − 0xFFFBAA10 CLASS1 Initiator Profiling Configuration Register 4 C1IPCR4 − 0xFFFBAA14 CLASS1 Initiator Profiling Configuration Register 5 C1IPCR5 − 0xFFFBAA18– reserved 0xFFFBAA3F − 0xFFFBAA40 CLASS1 Initiator Watch Point Control Register 0 C1IWPCR0 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-97...
Page 430 − 0xFFFBAE18 CLASS1 Profiling Time-Out Register C1PTOR − 0xFFFBAE1C CLASS1 Target Watch Point Control Register C1TWPCR − 0xFFFBAE20 CLASS1 Profiling IRQ Status Register C1PISR − 0xFFFBAE24 CLASS1 Profiling IRQ Enable Register C1PIER MSC8158E Reference Manual, Rev. 2 9-98 Freescale Semiconductor...
Page 431 Performance Monitor Local Control Register A4 PMLCA4 − 0xFFFBB854 Performance Monitor Local Control Register B4 PMLCB4 − 0xFFFBB858 Performance Monitor Counter 4 PMC4 − 0xFFFBB85C– reserved 0xFFFBB85F − 0xFFFBB860 Performance Monitor Local Control Register A5 PMLCA5 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-99...
Page 432 0xFFFD01BF − 0xFFFD01C0– Channel 1 Gather Link Tables — 0xFFFD01DF − 0xFFFD01E0– Channel 1 Scatter Link Tables — 0xFFFD01FF − 0xFFFD0200– SEC Channel 2 Secondary Addresses (used if MCR[RCA2] = 1) 0xFFFD02FF MSC8158E Reference Manual, Rev. 2 9-100 Freescale Semiconductor...
Page 433 CCR4 − 0xFFFD0410 Channel 4 Status Register CSR4 − 0xFFFD0418– reserved 0xFFFD043F − 0xFFFD0440 Channel 4 Current Descriptor Pointer Register CDPR4 − 0xFFFD0448 Channel 4 Fetch FIFO CFF4 − 0xFFFD0450– reserved 0xFFFD047F MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-101...
Page 434 0xFFFD11FF − 0xFFFD1200– SEC Channel 2 Primary Addresses (used if MCR[RCA2] = 0) 0xFFFD12FF − 0xFFFD1200– reserved 0xFFFD1207 − 0xFFFD1208 Channel 2 Configuration Register CCR2 − 0xFFFD1210 Channel 2 Status Register CSR2 MSC8158E Reference Manual, Rev. 2 9-102 Freescale Semiconductor...
Page 435 Channel 4 Current Descriptor Pointer Register CDPR4 − 0xFFFD1448 Channel 4 Fetch FIFO CFF4 − 0xFFFD1450– reserved 0xFFFD147F − 0xFFFD1480– Channel 4 Descriptor Buffer 0xFFFD14BF − 0xFFFD14C0– Channel 4 Gather Link Tables — 0xFFFD14DF MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-103...
Page 436 DEU Key 2 Register DEUKR2 − 0xFFFD2410 DEU Key 3 Register DEUKR3 − 0xFFFD2418– reserved 0xFFFD27FF − 0xFFFD2800– DEU Input FIFO/Output FIFO — 0xFFFD2FFF − 0xFFFD3000– reserved 0xFFFD3FFF − 0xFFFD4000– AESU 0xFFFD4FFF MSC8158E Reference Manual, Rev. 2 9-104 Freescale Semiconductor...
Page 437 0xFFFD5FFF − 0xFFFD6000– MDEU 0xFFFD6FFF − 0xFFFD6000 MDEU Mode Register MDEUMR − 0xFFFD6008 MDEU Key Size Register MDEUKSR − 0xFFFD6010 MDEU Data Size Register MDEUDSR − 0xFFFD6018 MDEU Reset Control Register MDEURCR MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-105...
Page 438 − 0xFFFD8100– AFEU Context Memory — 0xFFFD81FF − 0xFFFD8200 AFEU Context Memory Pointer Register AFEUCMPR − 0xFFFD8208– reserved 0xFFFD83FF − 0xFFFD8400 AFEU Key Register 1 AFEUKR1 − 0xFFFD8408 AFEU Key Register 2 AFEUKR2 MSC8158E Reference Manual, Rev. 2 9-106 Freescale Semiconductor...
Page 439 0xFFFDBFFF − 0xFFFDC000– PKEU 0xFFFDCFFF − 0xFFFDC000 PKEU Mode Register PKEUMR − 0xFFFDC008 PKEU Key Size Register PKEUKSR − 0xFFFDC010 PKEU Data Size Register PKEUDSR − 0xFFFDC018 PKEU Reset Control Register PKEURCR MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-107...
Page 440 STEUDSR − 0xFFFDD018 STEU Reset Control Register STEURCR − 0xFFFDD020– reserved 0xFFFDD027 − 0xFFFDD028 STEU Status Register STEUSR − 0xFFFDD030 STEU Interrupt Status Register STEUISR − 0xFFFDD038 STEU Interrupt Mask Register STEUIMR MSC8158E Reference Manual, Rev. 2 9-108 Freescale Semiconductor...
Page 441 KEU Reset Control Register KEURCR − 0xFFFDE020– reserved 0xFFFDE027 − 0xFFFDE028 KEU Status Register KEUSR − 0xFFFDE030 KEU Interrupt Status Register KEUISR − 0xFFFDE038 KEU Interrupt Mask Register KEUIMR − 0xFFFDE040– reserved 0xFFFDE047 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-109...
Page 442 CRCU ICV Size Register CRCUICVSR − 0xFFFDF048– reserved 0xFFFDF04F − 0xFFFDF050 CRCU End_of_Message Register CRCUEOMR − 0xFFFDF058– reserved 0xFFFDF0FF − 0xFFFDF100 CRCU Context Register CRCUCXR − 0xFFFDF108– reserved 0xFFFDF3FF − 0xFFFDF400 CRCU Key Register CRCUKR MSC8158E Reference Manual, Rev. 2 9-110 Freescale Semiconductor...
Page 443 Detailed System Memory Map Table 9-8. Detailed System Memory Map (Continued) Address Name/Status Acronym − 0xFFFDF408– reserved 0xFFFDF7FF − 0xFFFDF800– CRCU Input FIFO — 0xFFFDFFFF • 0xFFFE0000– reserved 0xFFFFEFFF 0xFFFFF000– reserved 0xFFFFFFFF MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 9-111...
Page 444 Memory Map MSC8158E Reference Manual, Rev. 2 9-112 Freescale Semiconductor...
Page 445: Sc3850 Dsp Subsystem
Interrupts DMA Bus Master MBus M2 DMA Bus (128 bits wide) DMA Bridge L2 Cache EPIC Debug Support Timer Instruction Data Channel Channel Write Queue SC3850 Core Figure 10-1. DSP Core Subsystem MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 10-1...
Page 446: Sc3850 Dsp Core Subsystem Features
Unified L2 cache: — 512 KB — 8 ways with 1024 indices — 64-byte line size — Physically addressed — Maximum user flexibility for real-time support through address partitioning of the cache MSC8158E Reference Manual, Rev. 2 10-2 Freescale Semiconductor...
Page 447: Sc3850 Core
StarCore architectures, including the SC140/SC140e and SC3400. The SC3850 core is organized the same way as the StarCore architectures. See Chapter 2, SC3850 Core Overview and the SC3850 DSP Core Reference Manual for details on the SC3850 core. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 10-3...
Page 448: Instruction Channel
The cache array itself can be either read or written. This information is accessed through the JTAG interface in Debug processing state. MSC8158E Reference Manual, Rev. 2 10-4 Freescale Semiconductor...
Page 449: Instruction Fetch Unit
A pseudo-LRU (PLRU) replacement algorithm selects the line to be replaced. If the line to be replaced contains MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 450: Data Fetch Unit
The programmer can control the burst size, as well as turn the HW line prefetch mechanism on or off. To minimize the time that the core stalls, the DFU implements critical word first external access and also supports prefetch hit. MSC8158E Reference Manual, Rev. 2 10-6 Freescale Semiconductor...
Page 451: Write-Back Buffer
WTB, and the trace writes from the TWB) and the read transactions of the DFU. The DCU transfers the transactions to the data QBus after mastership on the bus is obtained or directly when it accesses the internal subsystem memory-mapped registers. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 10-7...
Page 452: Write Queue
The same virtual addresses can be reused between tasks without a need to flush the caches between tasks because the caches store the task ID in their line tags and thus have a unique MSC8158E Reference Manual, Rev. 2 10-8...
Page 453: L2 Cache
— Adaptive write policy (AWP). Cacheable WB on hit and NC on miss. WB composed of eight 32-byte entries Full ECC support The main components of the L2 cache are as follows: MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 10-9...
Page 454: On-Chip Emulator And Debug And Profiling Unit
The DPU has the following characteristics: Enables parallel counting of subsystem events in six dedicated counters, from more than 40 events Filters, processes, and adds task ID and profiling information on the OCE PC trace information MSC8158E Reference Manual, Rev. 2 10-10 Freescale Semiconductor...
Page 455: Extended Programmable Interrupt Controller
L2 Cache slave port. The bridge is placed between two different asynchronous clock domains: Internal, SC3850 DSP subsystem clock domain External (out of subsystem) clock domain, which is slower or equal to the internal clock domain. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 10-11...
Page 456: Entering And Exiting Wait And Stop States Safely
Make sure that the appropriate Stop ACK is asserted in GSR1. If not, assert the bit. (see Section 8.2.3, General Status Register 1 (GSR1), on page 8-6 for details). Issue a command to the specified core. stop MSC8158E Reference Manual, Rev. 2 10-12 Freescale Semiconductor...
Page 457: Procedure For Exiting The Stop State Safely
CORE_SLV_GCR (see Section 8.2.38, Core Subsystem Slave Port General Configuration Register (CORE_SLV_GCR), on page 8-66). 10.12 Programming Restrictions The MSC8158E has the following programming restrictions when using the SC3850 DSP Subsystem: A write hit in the cache combined with DFLUSH/DSYNC can be lost for the following scenarios: —...
Page 458 SC3850 DSP Subsystem MSC8158E Reference Manual, Rev. 2 10-14 Freescale Semiconductor...
Page 459: Internal Memory Subsystem
Note: The MMU, L1 ICache, L1 DCache, and L2 Cache/M2 memory are part of the MSC8158E SC3850 DSP core subsystem. For detailed programming and functional information, refer to the SC3850 DSP Core Reference Manual, available with a signed non-disclosure agreement. Contact your local Freescale dealer or sales representative for more information.
Page 460: Memory Management Unit (Mmu)
— A burst size of 1, 2, or 4 for the data fetch unit (DFU) and instruction fetch unit (IFU). — Hardware line prefetch enable. — Hardware next line prefetch enable (instruction only) — System/shared attributes — Write policy for data memory — L2 cache policy MSC8158E Reference Manual, Rev. 2 11-2 Freescale Semiconductor...
Page 461: Instruction Channel (Icache And Ifu)
Whenever an instruction is addressed from a non-cacheable area, the IFU fetches it directly to the P bus of the core without writing it to the cache. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 462 — XP non-cacheable hit access. This exception indicates that an access is a hit access, even though the MMU classifies it as a non-cacheable access. This type of situation can occur if the memory space attributes changed in the MMU without invalidating the MSC8158E Reference Manual, Rev. 2 11-4 Freescale Semiconductor...
Page 463: Data Channel And Write Queue (Dcache)
Write-through accesses do not allocate a new line in the cache for a write-miss access. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 11-5...
Page 464 . The DCache writes back and invalidates a cache line belonging to the DFLUSH specified address of the M3 or external memory. — . The DCache writes back a cache line belonging to the specified address of the DSYNC M3 or external memory. MSC8158E Reference Manual, Rev. 2 11-6 Freescale Semiconductor...
Page 465 SYNCIO — WA/WB double match: This is an error that occurs when a task-shared access has an address that matches a non-shared cache line. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 11-7...
Page 466: L2 Unified Cache/M2 Memory
64-byte Valid Bit Resolution (VBR) and Dirty Bit Resolution (DBR). Fetches the whole line at once. Writes back the whole line at once when a dirty line is thrashed from the cache. 8192 cache lines (TAGs). MSC8158E Reference Manual, Rev. 2 11-8 Freescale Semiconductor...
Page 467 — The maximum accumulative burst size is 64 bytes. The number of beats in the burst is equal to the burst size divided by the bus size.The maximum accumulative burst size is 64 bytes which is made in 4 beats of 128 bits. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 11-9...
Page 468 — Supports reading and writing memory mapped registers through memory mapped bank0. Supports user-initiated SW-PF (L2 software prefetch) operation. This operation enables PF of a specific (two-dimensional) address space as programmed in the cache registers. MSC8158E Reference Manual, Rev. 2 11-10 Freescale Semiconductor...
Page 469 — M2 non-mapped access error: This interrupt indicates that an access intended to access the L2 cache as M2, has exceeded the M2 boundaries indicating an issue with memory mapping to M2 configuration. Disabled on reset. Cannot be disabled after enabled. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 11-11...
Page 470: M3 Memory
11.6 Internal Boot ROM The MSC8158E device includes 96 KB of boot ROM accessible from all of the cores. This ROM provides the basic loading programming that allows the device to complete its initialization and load additional configuration and booting from external sources.
Page 471: Ddr Sdram Memory Controller
Delay chain MDQS[0:8] MDQS[0:8] Data from FIFO Data Signals SDRAM MDQ[0:63] MECC[0:7] SDRAM Control Data from master Clocks Clock MCK[0:2] Control MCK[0:2] Figure 12-1. DDR SDRAM Memory Controller Simplified Block Diagram MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-1...
Page 472: Ddr Memory Controller Features
SDRAM. Auto-precharge mode. Clearing DDR_SDRAM_INTERVAL[BSTOPRE] causes the memory controller to issue an auto-precharge command with every read or write transaction. Auto-precharge mode can be enabled for separate chip selects by setting CSn_CONFIG[AP_n_EN]. MSC8158E Reference Manual, Rev. 2 12-2 Freescale Semiconductor...
Page 473: Ddr Controller Functional Description
To Error Delay Chain MDQS[0:8] Signals Management MDQS[0:8] Data from FIFO Data Signals SDRAM MDQ[0:63] MECC[0:7] FIFO Clocks MCK[0:2] Data from SDRAM Master MCK[0:2] Control Figure 12-2. DDR Memory Controller Block Diagram MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-3...
Page 474 When ECC is enabled, 1 clock cycle is added to the read path to check ECC and correct single-bit errors. ECC generation does not add a cycle to the write path. MSC8158E Reference Manual, Rev. 2 12-4...
Page 475 ECC checking function. Certain address and control lines may require buffering. Analysis of the device AC timing specifications, desired memory operating frequency, capacitive loads, and board routing loads can assist the system designer in deciding signal buffering requirements. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-5...
Page 476 3. Buffering may be needed if large memory arrays are used. 4. MCK[0:5] may be apportioned among all memory devices. Complementary bus is not shown. Figure 12-5. Example 64-Mbyte DDR SDRAM Configuration MSC8158E Reference Manual, Rev. 2 12-6 Freescale Semiconductor...
Page 477: Ddr Sdram Interface Operation
Data Bus 64-Bit Mode 0 (MSB) MDM[0] MDQS[0] MDQ[0:7] MDM[1] MDQS[1] MDQ[8:15] MDM[2] MDQS[2] MDQ[16:23] MDM[3] MDQS[3] MDQ[24:31] MDM[4] MDQS[4] MDQ[32:39] MDM[5] MDQS[5] MDQ[40:47] MDM[6] MDQS[6] MDQ[48:55] 7 (LSB) MDM[7] MDQS[7] MDQ[56:63] MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-7...
Page 478: Supported Ddr Sdram Organizations
— Note: The MSC8158E controller supports a total of 2 Gbyte of DDR SDRAM using one or two banks of memory. If a transaction request is issued to the DDR memory controller and the address does not lie within any of the programmed address ranges for an enabled chip select, a memory select error is flagged.
Page 479 When interleaving is enabled, the chip selects being interleaved must use the same size of memory. One extra bit in the address decode is used for the interleaving to determine which chip select to access. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-9...
Page 480 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2 1 0 MCAS 9 8 7 6 5 4 3 2 1 0 13 x 10 MRAS 12 11 10 9 2 1 0 MCAS MSC8158E Reference Manual, Rev. 2 12-10 Freescale Semiconductor...
Page 481: Jedec Standard Ddr Sdram Interface Commands
The amount of data transferred is determined by the data masks and the burst size, which is set to 8 by the DDR memory controller. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-11...
Page 482 Read Logical bank select Column Read with Logical bank select Column auto-precharge Write Logical bank select Column Write with Logical bank select Column auto-precharge Mode register set Opcode Opcode Opcode and mode MSC8158E Reference Manual, Rev. 2 12-12 Freescale Semiconductor...
Page 483: Ddr Sdram Interface Timing
Depending on DDR_SDRAM_CFG_2[NUM_PR], some number of rows are refreshed in each SDRAM bank during each refresh cycle. The value of REFINT depends on the specific SDRAMs used and the frequency of the interface as t MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-13...
Page 484 These figures assume the CLK_ADJUST is set to 1/2 DRAM cycle, an additive latency of 0 DRAM cycles is used, and the write latency is 1 DRAM cycle. MSC8158E Reference Manual, Rev. 2 12-14 Freescale Semiconductor...
Page 485 Figure 12-6. DDR SDRAM Burst Read Timing—ACTTORW = 3, MCAS Latency = 2 SDRAM Clock ACTTORW PRECHARGE MRAS MCAS WRREC PRETOACT A10=0 MDQn D0 D1 D2 D3 MDQS MDM[0:7] FF FF FF FF Figure 12-7. DDR SDRAM Single-Beat (64 bit) Write Timing—ACTTORW = 3 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-15...
Page 486: Clock Distribution
PCB traces for DDR clock signals should be short, all on the same layer, and of equal length and loading. DDR SDRAM manufacturers provide detailed information on PCB layout and termination issues. MSC8158E Reference Manual, Rev. 2 12-16 Freescale Semiconductor...
Page 487: Ddr Sdram Mode-Set Command Timing
ESDMODE code; the second corresponds to SDMODE. The Mode Register Set cycle time is set to 2 DRAM cycles. SDRAM Clock MRAS MCAS Code Code MBAn MDQn MDQS Figure 12-10. DDR SDRAM Mode-Set Command Timing MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-17...
Page 488: Ddr Sdram Registered Dimm Mode
RCWs. Disable automatic CPO by ensuring that TIMING_CFG_2[CPO] is not set to all 1s. Write 0x00000400 to the register at address 0xFFF20F08. Disable ZQ calibration by clearing DDR_ZQ_CNTL[ZQ_EN]. MSC8158E Reference Manual, Rev. 2 12-18 Freescale Semiconductor...
Page 489: Ddr Sdram Write Timing Adjustments
DIMM to a fully populated system with two DIMMs. TIMING_CFG_2[WR_DATA_DELAY] specifies how much to delay the launching of DQS and MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-19...
Page 490: Ddr Sdram Refresh
REFINT be less than that required by the SDRAM. When a refresh cycle is required, the DDR memory controller does the following: MSC8158E Reference Manual, Rev. 2 12-20 Freescale Semiconductor...
Page 491: Ddr Sdram Refresh Timing
Figure 12-13. DDR SDRAM Bank Staggered Auto Refresh Timing System software is responsible for optimal configuration of TIMING_CFG_1 [REFREC] and TIMING_CFG_3[EXT_REFREC] at reset. Configuration must be completed before DDR SDRAM accesses are attempted. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-21...
Page 492: Ddr Sdram Refresh And Power-Saving Modes
TIMING_CFG_0[ACT_PD_EXIT] and TIMING_CFG_0[PRE_PD_EXIT]. A penalty of 1 cycle is shown in Figure 12-14. Mem Bus Clock COMMAND Figure 12-14. DDR SDRAM Power-Down Mode MSC8158E Reference Manual, Rev. 2 12-22 Freescale Semiconductor...
Page 493: Self-Refresh In Sleep Mode
MCKE MRAS MCAS (High Impedance) MDQn MDQS Figure 12-15. DDR SDRAM Self-Refresh Entry Timing SDRAM Clock MCKE MRAS MCAS (High Impedance) MDQn MDQS 200 Cycles Figure 12-16. DDR SDRAM Self-Refresh Exit Timing MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-23...
Page 494: Ddr Data Beat Ordering
12.3.13 Error Checking and Correcting (ECC) The DDR memory controller supports error checking and correcting (ECC) for the data path between the core master and system memory. The memory detects all double-bit errors, detects MSC8158E Reference Manual, Rev. 2 12-24 Freescale Semiconductor...
Page 495 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-25...
Page 496: Error Management
Single-bit errors are counted and reported based on the ERR_SBE value. When a single-bit error is detected, the DDR memory controller does the following: Corrects the data Increments the single-bit error counter ERR_SBE[SBEC] MSC8158E Reference Manual, Rev. 2 12-26 Freescale Semiconductor...
Page 497: Initialization/Application Information
At system reset, initialization software (boot code) must set up the programmable parameters in the memory interface configuration registers. See Section 12.5, Memory Controller Programming Model, on page 12-33 for detailed descriptions of the configuration registers. These parameters are shown in Table 12-14. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-27...
Page 498 ESDMODE 12.5.10/12-57 SDMODE DDR_SDRAM_MODE_2 Mode configuration ESDMODE2 12.5.11/12-58 ESDMODE3 DDR_SDRAM_INTERVAL Interval configuration REFINT 12.5.13/12-61 BSTOPRE DDR_DATA_INIT Data initialization configuration INIT_VALUE 12.5.14/12-62 register DDR_SDRAM_CLK_CNTL Clock adjust CLK_ADJUST 12.5.15/12-63 DDR_INIT_ADDR Initialization address INIT_ADDR 12.5.16/12-64 MSC8158E Reference Manual, Rev. 2 12-28 Freescale Semiconductor...
Page 499 Self refresh control SR_IT 12.5.24/12-81 DDR_SDRAM_RCW_1 Register control words configuration RCW0 12.5.25/12-82 RCW1 RCW2 RCW3 RCW4 RCW5 RCW6 RCW7 DDR_SDRAM_RCW_2 Register control words configuration RCW8 12.5.26/12-83 RCW9 RCW10 RCW11 RCW12 RCW13 RCW14 RCW15 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-29...
Page 500: Programming Summary
Should be set according to the specifications for the memory 12.5.6/12-45 used (t ACTTOACT Activate A to Activate B Should be set according to the specifications for the memory 12.5.6/12-45 used (t RRD) MSC8158E Reference Manual, Rev. 2 12-30 Freescale Semiconductor...
Page 501 Should typically be set to 0100 in burst chop mode (on-the-fly 12.5.18/12-66 same chip select (in or fixed). TIMING_CFG_4) Write-to-write turnaround for Should typically be set to 0100 in burst chop mode (on-the-fly 12.5.18/12-66 same chip select (in or fixed). TIMING_CFG_4) MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-31...
Page 502: Ddr Sdram Initialization Sequence
Mode Configuration 2 Register (DDR_SDRAM_MODE_2) for a description of this register. It is expected that a critical interrupt routine triggered by an external voltage sensing device will have time to set this bit. MSC8158E Reference Manual, Rev. 2 12-32 Freescale Semiconductor...
Page 503: Bypassing Re-Initialization During Battery-Backed Operation
DDR SDRAM Mode Configuration Register (DDR_SDRAM_MODE), page 12-57. DDR SDRAM Mode Configuration 2 Register (DDR_SDRAM_MODE_2), page 12-58. DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL), page 12-58. DDR SDRAM Interval Configuration Register (DDR_SDRAM_INTERVAL), page 12-61. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-33...
Page 504 Memory Error Attributes Capture Register (CAPTURE_ATTRIBUTES), page 12-103. Memory Error Address Capture Register (CAPTURE_ADDRESS), page 12-104. Single-Bit ECC Memory Error Management Register (ERR_SBE), page 12-105. Note: DDR controller 1 (M1 registers) uses base address: 0xFFF20000 MSC8158E Reference Manual, Rev. 2 12-34 Freescale Semiconductor...
Page 505: Chip-Select X Bounds Register (Csx_Bnds)
Reserved. Cleared to zero for future compatibility. 15–8 Ending Address 7–0 Specifies the ending address for chip select (bank) x. This value is compared against the 8 MSBs of the 32-bit address. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-35...
Page 506: Chip-Select X Configuration Register (Csx_Config)
CSx. latency must be at least 3 cycles for ODT_RD_CFG Assert ODT only during reads to to be enabled. other chip selects. Reserved. Assert ODT for all reads. 101– Reserved. MSC8158E Reference Manual, Rev. 2 12-36 Freescale Semiconductor...
Page 507 9 column bits. 2–0 Specifies the number of column bits for SDRAM on 10 column bits. chip select x. See Table 12-7 and Table 12-8 for 11 column bits. details. 100– Reserved. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-37...
Page 508: Chip-Select X Configuration Register 2 (Csx_Config_2)
(see Section 12.5.11), — Reserved. Write to zero for future compatibility. 23–0 MSC8158E Reference Manual, Rev. 2 12-38 Freescale Semiconductor...
Page 509: Ddr Sdram Timing Configuration 3 Register (Timing_Cfg_3)
Note that a 5-bit value of 0_0000 is the same as a 5-bit value of 1_0000. Both values represent 16 cycles. — Reserved. Write to zero for future compatibility. 23–21 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-39...
Page 510 TIMING_CFG_1[CASLAT] to obtain a 5-bit value for the total CAS latency. Note that if this bit is set, then 8 clocks are added to the programmed value in TIMING_CFG_1[CASLAT]. — Reserved. Write to zero for future compatibility. 11–3 MSC8158E Reference Manual, Rev. 2 12-40 Freescale Semiconductor...
Page 511 2 platform cycles later than the other DRAM address and control signals. MODT[0:1], MCS[0:1], and MCKE[0:1] will be launched 5/2 platform cycles later than the other DRAM address and control signals. 110– Reserved MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-41...
Page 512: Ddr Sdram Timing Configuration Register 0 (Timing_Cfg_0)
3 clocks for the turnaround. Selecting a value other than 00 adds extra cycles to this predefined value according to the selection When DDR works in 8 beat burst the default is 5 clock cycles. MSC8158E Reference Manual, Rev. 2 12-42 Freescale Semiconductor...
Page 513 10101 26 clocks 11110 11 clocks 10111 27 clocks 11000 12 clocks 11001 28 clocks 11010 13 clocks 11011 29 clocks 11100 14 clocks 11101 30 clocks 11110 15 clocks 11111 31 clocks MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-43...
Page 514 1000 8 clock cycles. 1001 9 clock cycles. 1010 10 clock cycles. 1011 11 clock cycles. 1100 12 clock cycles. 1101 13 clock cycles. 1110 14 clock cycles. 1111 15 clock cycles. MSC8158E Reference Manual, Rev. 2 12-44 Freescale Semiconductor...
Page 515: Ddr Sdram Timing Configuration Register 1 (Timing_Cfg_1)
This field must be programmed for proper operation of the DDR For any value of Controller. TIMING_CFG_3 [EXT_ACTTOPRE]: 0100 4 clock cycles. 0101 5 clock cycles. 0110 6 clock cycles. 0111 7 clock cycles. … 1111 15 clock cycles. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-45...
Page 516 18 clock cycles. indicates a maximum refresh to activate interval in ns. 1011 19 clock cycles. 1100 20 clock cycles. 1101 21 clock cycles. 1110 22 clock cycles. 1111 23 clock cycles. MSC8158E Reference Manual, Rev. 2 12-46 Freescale Semiconductor...
Page 517 1000 8 clock cycles 1001 9 clock cycle. 1010 10 clock cycles. 1011 11 clock cycles. 1100 12 clock cycles. 1101 13 clock cycles. 1110 14 clock cycles. 1111 15 clock cycles MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-47...
Page 518: Ddr Sdram Timing Configuration Register 2 (Timing_Cfg_2)
7 clock cycles 1000 8 clock cycles. 1001 9 clock cycles. 1010 10 clock cycles. 1011 11 clock cycles. 1100 12 clock cycles. 1101 13 clock cycles. 1110 14 clock cycles. 1111 Reserved. MSC8158E Reference Manual, Rev. 2 12-48 Freescale Semiconductor...
Page 519 10 clock cycles. 1011 11 clock cycles. 1100 12 clock cycles. 1101 13 clock cycles. 1110 14 clock cycles. 1111 15 clock cycles. — Reserved. Write to zero for future compatibility. 18–17 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-49...
Page 520 3 clock cycles. Note: This is applied to DDR3 with eight logical banks only. 000100 4 clock cycles. 011110 30 clock cycles. 011111 31 clock cycles. 100000 32 clock cycles. 100001– 111111 Reserved. MSC8158E Reference Manual, Rev. 2 12-50 Freescale Semiconductor...
Page 521 Dynamic power management mode Enabled/disables dynamic power management is disabled. mode. When this bit is set and there is no on-going Dynamic power management mode memory activity, the SDRAM CKE signal is is enabled. deasserted. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-51...
Page 522 , DDR Control Section Driver Register 1 (DDRCDR_1) and 12.5.32 , DDR Control Driver Register 2 (DDRCDR_2) Clear this bit if using automatic hardware calibration. — Reserved. Write to zero for future compatibility. MSC8158E Reference Manual, Rev. 2 12-52 Freescale Semiconductor...
Page 523 For details on avoiding ECC errors in this mode, see the discussion of the DDR SDRAM Initialization Address Register on page 12-64. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-53...
Page 524: Ddr Sdram Control Configuration Register (Ddr_Sdram_Cfg)
DRAM. Assert ODT to internal I/O only during reads to DRAM. Always keep ODT asserted to internal I/O. — Reserved. Write to zero for future compatibility. 20–16 MSC8158E Reference Manual, Rev. 2 12-54 Freescale Semiconductor...
Page 525 This data initialization bit should only be set when the controller is idle. The value in DDR_DATA_INIT register will be used to initialize memory — Reserved. Write to zero for future compatibility. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-55...
Page 526 DRAM. The controller assumes that CS1 and CS3 are the ‘mirrored’ ranks of memory. The following signals are mirrored (MBA0 versus MBA1; MA3 versus MA4; MA5 versus MA6; MA7 versus MA8). MSC8158E Reference Manual, Rev. 2 12-56 Freescale Semiconductor...
Page 527: Ddr Sdram Mode Configuration Register (Ddr_Sdram_Mode)
SDMODE[8] to certain values depending upon the state of the initialization sequence (for resetting the SDRAM DLL) which is mapped to MA8; the memory controller ignores the corresponding bits of this field. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-57...
Page 528: Ddr Sdram Mode Control Register (Ddr_Sdram_Md_Cntl)
12.5.12 DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL) DDR_SDRAM_MD_CNTL DDR SDRAM Mode Control Register Offset 0x0120 CS_ SEL — MD_SEL SET_ SET_ CKE_CNTL WRC — Type Reset MD_VALUE Type Reset DDR_SDRAM_MD_CNTL register allows software to initiate the following tasks: MSC8158E Reference Manual, Rev. 2 12-58 Freescale Semiconductor...
Page 529 Register 3 • During a refresh command, this field is ignored. Note that MD_SEL contains the value that is presented to the memory bank address pins (MBAn) of the DDR controller. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-59...
Page 530 PRECHARGE ALL command, as follows: Issue a command; PRECHARGE MD_SEL selects the logical bank to be precharged Issue a PRECHARGE ALL command; all logical banks are precharged All other values are not valid. MSC8158E Reference Manual, Rev. 2 12-60 Freescale Semiconductor...
Page 531: Ddr Sdram Interval Configuration Register (Ddr_Sdram_Interval)
The value for REFINT depends on the specific SDRAMs used and the interface clock frequency. Refreshes are not issued when REFINT is cleared to all 0s. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-61...
Page 532: Ddr Sdram Data Initialization Register (Ddr_Data_Init)
DDR_DATA_INIT register provides the value to initialize memory if DDR_SDRAM_CFG_2[D_INIT] is set. Table 12-30. DDR_DATA_INIT Bit Descriptions Bits Reset Description INIT_VALUE Initialization Value 31–0 Specifies the initialization value for the DRAM if DDR_SDRAM_CFG_2[D_INIT] is set. MSC8158E Reference Manual, Rev. 2 12-62 Freescale Semiconductor...
Page 533: Ddr Sdram Clock Control Configuration Register (Ddr_Sdram_Clk_Cntl)
0110 Clock launched 3/4 applied cycle after address/command. 0111 Clock launched 7/8 applied cycle after address/command. 1000 Clock launched 1 applied cycle after address/command. 1001–1111Reserved. — Reserved. Write to zero for future compatibility. 22–0 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-63...
Page 534: Ddr Sdram Initialization Address Register (Ddr_Init_Addr)
Initialization Address 31–0 Provides the address used for the data strobe to data skew adjustment and automatic CAS to preamble calibration after setting DDR_SDRAM_CFG[MEM_EN]. This address is written during the initialization sequence. MSC8158E Reference Manual, Rev. 2 12-64 Freescale Semiconductor...
Page 535: Ddr Initialization Enable Register (Ddr_Init_En)
This will be the first valid address in the first enabled chip select. Use the initialization address programmed in DDR_INIT_ADDR. — Reserved. Write to zero for future compatibility. 30–0 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-65...
Page 536: Ddr Sdram Timing Configuration 4 Register (Timing_Cfg_4)
1001 9 clocks TIMING_CFG_0[WRT] will also be met before issuing a read 1010 10 clocks command. 1011 11 clocks 1100 12 clocks 1101 13 clocks 1110 14 clocks 1111 15 clocks MSC8158E Reference Manual, Rev. 2 12-66 Freescale Semiconductor...
Page 537 512 clocks to lock at power-on reset and after exiting self refresh. The controller Reserved will wait the specified number of cycles before issuing any commands Reserved after exiting POR or self refresh. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-67...
Page 538: Ddr Sdram Timing Configuration 5 Register (Timing_Cfg_5)
11000 23 clocks 11001 24 clocks 11010 25 clocks 11011 26 clocks 11100 27 clocks 11101 28 clocks 11110 29 clocks. 11111 30 clocks — Reserved. Write to zero for future compatibility. MSC8158E Reference Manual, Rev. 2 12-68 Freescale Semiconductor...
Page 539 2 clocks ODT signal(s) asserted for 3 DRAM cycles. 3 clocks 4 clocks Recommended value is 4 cycles. 5 clocks 6 clocks 7 clocks — Reserved. Write to zero for future compatibility. 7–0 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-69...
Page 540: Ddr Zq Calibration Control Register (Ddr_Zq_Cntl)
DDR controller exits self refresh. A ZQCS command is issued every 32 refresh sequences to account for VT variations. — Reserved. Write to zero for future compatibility. 30–28 MSC8158E Reference Manual, Rev. 2 12-70 Freescale Semiconductor...
Page 541 0101 32 clocks command may be issued. 0110 64 clocks 0111 128 clocks 1000 256 clocks 1001 512 clocks All other values reserved. — Reserved. Write to zero for future compatibility. 7–0 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-71...
Page 542: Ddr Write Leveling Control Register (Ddr_Wrlvl_Cntl)
4 clocks greater than t 8 clocks This field is only relevant when DDR_WRLVL_CNTL[WRLVL_EN] is 16 clocks set. 32 clocks 64 clocks 128 clocks — Reserved. Write to zero for future compatibility. MSC8158E Reference Manual, Rev. 2 12-72 Freescale Semiconductor...
Page 543 2 clocks 10–8 during write leveling. This field is only relevant when 4 clocks DDR_WRLVL_CNTL[WRLVL_EN] is set. The recommended value is 8 clocks 64 clocks 16 clocks 32 clocks 64 clocks 128 clocks MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-73...
Page 544 13/8 clock delay 01110 7/4 clock delay 01111 15/8 clock delay 10000 2 clock delay 10001 17/8 clock delay 10010 9/4 clock delay 10011 19/8 clock delay 10100 5/2 clock delay 10101– 11111 Reserved MSC8158E Reference Manual, Rev. 2 12-74 Freescale Semiconductor...
Page 545: Ddr Write Leveling Control 2 Register (Ddr_Wrlvl_Cntl_2)
13/8 clock delay 01110 7/4 clock delay 01111 15/8 clock delay 10000 2 clock delay 10001 17/8 clock delay 10010 9/4 clock delay 10011 19/8 clock delay 10100 5/2 clock delay 10101– 11111 Reserved MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-75...
Page 546 13/8 clock delay 01110 7/4 clock delay 01111 15/8 clock delay 10000 2 clock delay 10001 17/8 clock delay 10010 9/4 clock delay 10011 19/8 clock delay 10100 5/2 clock delay 10101– 11111 Reserved MSC8158E Reference Manual, Rev. 2 12-76 Freescale Semiconductor...
Page 547 13/8 clock delay 01110 7/4 clock delay 01111 15/8 clock delay 10000 2 clock delay 10001 17/8 clock delay 10010 9/4 clock delay 10011 19/8 clock delay 10100 5/2 clock delay 10101– 11111 Reserved MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-77...
Page 548: Ddr Write Leveling Control 3 Register (Ddr_Wrlvl_Cntl_3)
10000 2 clock delay 10001 17/8 clock delay 10010 9/4 clock delay 10011 19/8 clock delay 10100 5/2 clock delay 10101– 11111 Reserved — Reserved. Write to zero for future compatibility. 23–21 MSC8158E Reference Manual, Rev. 2 12-78 Freescale Semiconductor...
Page 549 13/8 clock delay 01110 7/4 clock delay 01111 15/8 clock delay 10000 2 clock delay 10001 17/8 clock delay 10010 9/4 clock delay 10011 19/8 clock delay 10100 5/2 clock delay 10101– 11111 Reserved MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-79...
Page 550 13/8 clock delay 01110 7/4 clock delay 01111 15/8 clock delay 10000 2 clock delay 10001 17/8 clock delay 10010 9/4 clock delay 10011 19/8 clock delay 10100 5/2 clock delay 10101– 11111 Reserved MSC8158E Reference Manual, Rev. 2 12-80 Freescale Semiconductor...
Page 551: Ddr Self Refresh Counter Register (Ddr_Sr_Cntr)
DRAM clocks issued to the DDR controller, regardless of the 1010 DRAM clocks reason self refresh was initially entered. 1011 DRAM clocks 1100-1111 Reserved — Reserved. Write to zero for future compatibility. 15–0 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-81...
Page 552: Ddr Sdram Register Control Words 1 Register (Ddr_Sdram_Rcw_1)
6. RCW7 Register Control Word 7 3–0 Represents the value that will be placed on MBA[1], MBA[0], MA[4], and MA[3] during writes to register control word 7. MSC8158E Reference Manual, Rev. 2 12-82 Freescale Semiconductor...
Page 553: Ddr Sdram Register Control Words 2 Register (Ddr_Sdram_Rcw_2)
14. RCW15 Register Control Word 15 3–0 Represents the value that will be placed on MBA[1], MBA[0], MA[4], and MA[3] during writes to register control word 15. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-83...
Page 554 SDMODE[8] to certain values depending upon the state of the initialization sequence (for resetting the SDRAM DLL) which is mapped to MA8; the memory controller ignores the corresponding bits of this field. MSC8158E Reference Manual, Rev. 2 12-84 Freescale Semiconductor...
Page 555 When this value is driven onto the address bus during DDR SDRAM initialization, MA0 presents the LSB of ESDMODE3, which corresponds to DDR_SDRAM_MODE_4 bit 0. The MSB of the SDRAM extended mode 3 register value must be stored at DDR_SDRAM_MODE_4 bit 15. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-85...
Page 556: Ddr Debug Status Register 1 (Ddrdsr_1)
Current Setting of PFET Driver Command Impedance 15–12 Current Setting of NFET Driver Command Impedance 11–8 Current Setting of PFET Driver Data Impedance 7–4 Current Setting of NFET Driver Data Impedance 3–0 MSC8158E Reference Manual, Rev. 2 12-86 Freescale Semiconductor...
Page 557: Ddr Debug Status Register 2 (Ddrdsr_2)
The fields in DDRCDR_1, except DDRCDR_1[ODT], are used to enable driver calibration with the MDIC pins. This can be used to calibrate the DDR drivers to 36 Ω; however, this should only MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-87...
Page 558 Set DDRCDR_1[DSO_MDIC_EN] and ensure that DDRCDR_1[DHC_EN] is cleared Set the highest impedance (value 0000) for DDRCDR_1[DSO_MDICPZ] Set DDRCDR_1[DSO_MDIC_PZ_OE] to enable the output enable for MDIC[0] MSC8158E Reference Manual, Rev. 2 12-88 Freescale Semiconductor...
Page 559 After at least 4 cycles, read DDRDSR_1[1]. If the value is 1, then use the next lowest impedance, and read DDRDSR_1[1] again. Once a value of 0 is detected, then leave DDRCDR_1[DSO_MDICNZ] at the calibrated value Clear DDRCDR_1[DSO_MDIC_NZ_OE] MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-89...
Page 560 The legal impedance values (from highest impedance to lowest impedance) for DDR3 (1.5 V) are: 0000 lowest strength/highest impedance 0001 0011 0010 0110 0111 half strength 0101 0100 1100 1101 1111 1110 1010 1011 1001 1000 highest strength/lowest impedance MSC8158E Reference Manual, Rev. 2 12-90 Freescale Semiconductor...
Page 561: Ddr Control Driver Register 2 (Ddrcdr_2)
This is combined with DDRCDR_1[ODT] to 60 Ω determine the termination value. The termination 50 Ω value is based on concatenating these 2 fields 150 Ω (DDRCDR_1[ODT]|DDRCDR_2[ODT]). 43 Ω 120 Ω Reserved MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-91...
Page 562: Ddr Sdram Ip Block Revision 1 Register (Ddr_Ip_Rev1)
DDR_IP_REV2 register provides read-only fields with the IP block integration and configuration options. Table 12-50. DDR_IP_REV2 Bit Descriptions Reset Description — Reserved. Write to zero for future compatibility. 31–24 IP_INT IP Block Integration Options 23–16 MSC8158E Reference Manual, Rev. 2 12-92 Freescale Semiconductor...
Page 563: Ddr Memory Test Control Register (Ddr_Mtcr)
This field determines the type of test: write only, read only, or read/write. Do 01 Write only. not use the read-only test unless memory is already initialized. 10 Read only 11 Reserved. — Reserved. Write to zero for future compatibility. 23–20 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-93...
Page 564: Ddr Data Memory Test Pattern X Register (Ddr_Mtpx)
DDR Data Memory Test Pattern 7 Register Offset 0x0D3C DDR_MTP8 DDR Data Memory Test Pattern 8 Register Offset 0x0D40 DDR_MTP9 DDR Data Memory Test Pattern 9 Register Offset 0x0D44 DDR_PATT Type Reset DDR_PATT Type Reset MSC8158E Reference Manual, Rev. 2 12-94 Freescale Semiconductor...
Page 565: Ddr Sdram Memory Data Path Error Injection Mask High Register (Data_Err_Inject_Hi)
Tests ECC by forcing errors on the high 32 bits of the data path. When error injection is enabled, setting a bit causes the corresponding data path bit to be inverted during memory bus writes. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-95...
Page 566: Ddr Sdram Memory Data Path Error Injection Mask Low Register (Data_Err_Inject_Lo)
Tests ECC by forcing errors on the low 32 bits of the data path. When the Error Injection is enabled, setting a bit causes the corresponding data path bit to be inverted during memory bus writes. MSC8158E Reference Manual, Rev. 2 12-96 Freescale Semiconductor...
Page 567: Ddr Sdram Memory Data Path Error Injection Mask Ecc Register
ECC mask bits. DDR_SDRAM_CFG[MEM_EN] EEIM ECC Error Injection Mask (0–7) 7–0 Setting a mask bit causes the corresponding ECC bit to be inverted during memory bus writes. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-97...
Page 568: Ddr Sdram Memory Data Path Read Capture Data High Register (Capture_Data_Hi)
CAPTURE_DATA_LO register stores the low 32 bits of the read data path during error capture. Table 12-57. CAPTURE_DATA_LO Bit Descriptions Reset Description ECLD Error Capture Low Data Path 31–0 Captures the low 32 bits of the data path when errors are detected. MSC8158E Reference Manual, Rev. 2 12-98 Freescale Semiconductor...
Page 569: Ddr Sdram Memory Data Path Read Capture Ecc Register
1 to it. System software can determine the type of memory error by examining the contents of this register. If an error is disabled with ERR_DISABLE, the corresponding error is never detected or captured in ERR_DETECT. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-99...
Page 570 Memory Select Error Memory select error not detected. Indicates whether a memory select error has been Memory select error detected. detected. This bit is cleared by software writing a 1 to it. MSC8158E Reference Manual, Rev. 2 12-100 Freescale Semiconductor...
Page 571: Ddr Sdram Memory Error Disable Register (Err_Disable)
Single-bit ECC errors detection is disabled. Reserved. Write to zero for future compatibility. MSED Memory Select Error Disable Memory select errors detection is Enables/disables memory select errors detection. enabled. Memory select errors detection is disabled. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-101...
Page 572: Ddr Sdram Memory Error Interrupt Enable Register (Err_Int_En)
Reserved. Write to zero for future compatibility. MSEE Memory Select Error Interrupt Enable Memory select errors do not generate Specifies whether memory select errors generate interrupts. interrupts. Memory select errors generate interrupts. MSC8158E Reference Manual, Rev. 2 12-102 Freescale Semiconductor...
Page 573: Ddr Sdram Memory Error Attributes Capture Register (Capture_Attributes)
11 Read-modify-write. — Reserved. Write to zero for future compatibility. 11–1 Valid No valid information captured Set as soon as valid information is captured in the error Valid information captured capture registers. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-103...
Page 574: Ddr Sdram Memory Error Address Capture Register (Capture_Address)
CAPTURE_ADDRESS register holds the 32-bit of the transaction address when a DDR ECC error is detected. Table 12-63. CAPTURE_ADDRESS Bit Descriptions Reset Description Settings CADDR Captured Address 31–0 Captures the 32 bits of the transaction address when an error is detected. MSC8158E Reference Manual, Rev. 2 12-104 Freescale Semiconductor...
Page 575: Ddr Sdram Single-Bit Ecc Memory Error Management Register
Indicates the number of single-bit errors detected and corrected since the last error report. If single-bit error reporting is enabled, an error is reported when this value cross the SBET value. SBEC is automatically cleared when the threshold value is reached. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 12-105...
Page 576 DDR SDRAM Memory Controller MSC8158E Reference Manual, Rev. 2 12-106 Freescale Semiconductor...
Page 577: Interrupt Handling
Routes SEC and Serial RapidIO interrupts directly to the QUICC Engine processors with programmable masking of the each interrupt source for the QUICC Engine processors. The MSC8158E supports both internal and external interrupt sources as well as allowing for the generation of an interrupt to external devices.
Page 578 Interrupt Handling There are five device level interrupt handlers in the MSC8158E: Global interrupt controller. Allows for the generation of virtual interrupt requests (VIRQ) as well as virtual non-maskable interrupts (VNMI) towards the cores as well as generates interrupts to external devices.
Page 579: Global Interrupt Controller (Gic)
The core that services the interrupt may clear this status bit by writing a value of one to it, or it may ignore this bit and work locally. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 580: General Configuration Block
General Configuration Block The general configuration block performs services for rare and debug interrupts generated throughout the MSC8158E before they reach the SC3850 EPICs. These services include: Generating ORed interrupt signals towards the SC3850 cores (see Section 13.2.1). Providing an interrupt enable bit for each interrupt source for each SC3850 core (see Section 13.5.2, General Interrupt Configuration, on page 13-29).
Page 581: Interrupt Groups Toward The Sc3850 Cores
MEX addr IMEM multi-bit error error Timer 7 Core2–3 MEX addr error Core4–5 OCN0 to MBus MEX addr error OCN1 to MBus MAPLE multi-bit error OCN0 DMA multi-bit error OCN1 DMA double error MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 13-5...
Page 582: Interrupt Groups Toward Quicc Engine Processors
Interrupt Source #2 can be configured to pass on only the interrupt for Queue Manager 13.2.3 External Interrupts The MSC8158E allows a number of external interrupt inputs to be multiplexed with the GPIO signals to enable external devices to interrupt the cores (see Chapter 20, GPIO). There are also dedicated external interrupt pins.
Page 583: Interrupt Groups Directed Toward Maple-B2
General Configuration Block Table 13-4. MSC8158E External Interrupt Pins (Continued) Name GPIO Direction IRQ2 GPIO2 IRQ3 GPIO3 IRQ4 GPIO4 IRQ5 GPIO5 IRQ6 GPIO6 IRQ7 GPIO7 IRQ8 GPIO8 IRQ9 GPIO9 IRQ10 GPIO10 IRQ11 GPIO11 IRQ12 GPIO12 IRQ13 GPIO13 IRQ14 GPIO14 IRQ15 GPIO15 INT_OUT is asserted when VIRQ_24 is asserted.
Page 584: Interrupt Handling
Interrupt Handling 13.2.5 Interrupt Handling The MSC8158E interrupts sources can be grouped in to four basic types: Interrupts that represent a single interrupt source and are routed directly to the cores (for example, the DMA channel 0 EOB interrupt). Interrupts that represent multiple interrupt sources and are routed directly to the cores (for example, all I C interrupts).
Page 585: Interrupt Mapping
(priority 32). The first 34 interrupt sources are used internally by the SC3850 DSP cores. The core-to-core interrupt mesh uses another 12 interrupts for core-to-core communication. All other interrupts are used by the MSC8158E device. The MSC8158E does not implement all of these possible sources.
Page 586 Interrupt Handling Table 13-5. MSC8158E Interrupt Table (Continued) Interrupt Description Level Edge index From Core Subsystem 2 – From Core Subsystem 2 – From Core Subsystem 3 – From Core Subsystem 3 – From Core Subsystem 4 – From Core Subsystem 4 –...
Page 587 Interrupt Mapping Table 13-5. MSC8158E Interrupt Table (Continued) Interrupt Description Level Edge index Timer 32b 0 Timer 32b 0 Channel 0 — Timer 32b 0 Channel 1 — Timer 32b 0 Channel 2 — Timer 32b 0 Channel 3 —...
Page 588 Interrupt Handling Table 13-5. MSC8158E Interrupt Table (Continued) Interrupt Description Level Edge index Ethernet 2 Rx 4 — Ethernet 2 Rx 5 — Ethernet 2 Rx 6 — Ethernet 2 Rx 7 — Ethernet 2 Tx 0 — Ethernet 2 Tx 1 —...
Page 589 Interrupt Mapping Table 13-5. MSC8158E Interrupt Table (Continued) Interrupt Description Level Edge index Timer 0 Channel 0 — Timer 0 Channel 1 — Timer 0 Channel 2 — Timer 0 Channel 3 — Timer 1 Timer 1 Channel 0 —...
Page 590 Interrupt Handling Table 13-5. MSC8158E Interrupt Table (Continued) Interrupt Description Level Edge index Virtual Non Maskable Interrupt 3 — Virtual Non Maskable Interrupt 4 — Virtual Non Maskable Interrupt 5 — Virtual Non Maskable Interrupt 6 — Virtual Non Maskable Interrupt 7 —...
Page 591 Interrupt Mapping Table 13-5. MSC8158E Interrupt Table (Continued) Interrupt Description Level Edge index External IRQs IRQ0 (see note) IRQ1 (see note) IRQ2 (see note) IRQ3 (see note) IRQ4 (see note) IRQ5 (see note) IRQ6 (see note) IRQ7 (see note) IRQ8 (see note)
Page 592 0x180 64 B Reserved — — — 0x1C0 64 B I_MIFER Master interface errors 0x200 16 B from the MMU (NMI) I_SIFER Slave interface errors 0x210 16 B from the MMU (NMI) MSC8158E Reference Manual, Rev. 2 13-16 Freescale Semiconductor...
Page 593 0x15 0x350 16 B Reserved — 0x1E 0x16 0x360 16 B Reserved — 0x1F 0x17 0x370 16 B Reserved — 0x20 0x18 0x380 16 B Reserved — 0x21 0x19 0x390 16 B MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 13-17...
Page 594 16 B IRQ58 MAPLE BD 24 0x42 0x3A 1440 0x5A0 16 B IRQ59 MAPLE BD 25 0x43 0x3B 1456 0x5B0 16 B IRQ60 MAPLE BD 26 0x44 0x3C 1472 0x5C0 16 B MSC8158E Reference Manual, Rev. 2 13-18 Freescale Semiconductor...
Page 595 16 B eMSG Queue Manager Transmit Interrupt IRQ88 ORed Serial RapidIO 0x60 0x58 1920 0x780 16 B eMSG Buffer Manager Interrupt IRQ89 ORed CPRI Receive 0x61 0x59 1936 0x790 16 B Control Interrupt MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 13-19...
Page 596 Ethernet 2 Tx 3 0x81 0x79 2448 0x990 16 B IRQ122 Ethernet 2 Tx 4 0x82 0x7A 2464 0x9A0 16 B IRQ123 Ethernet 2 Tx 5 0x83 0x7B 2480 0x9B0 16 B MSC8158E Reference Manual, Rev. 2 13-20 Freescale Semiconductor...
Page 597 DMA channel 5 EOB 0x9D 0x95 2896 0xB50 16 B IRQ150 DMA channel 6 EOB 0x9E 0x96 2912 0xB60 16 B IRQ151 DMA channel 7 EOB 0x9F 0x97 2928 0xB70 16 B MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 13-21...
Page 598 16 B IRQ184 Virtual Interrupt 7 0xC0 0xB8 3456 0xD80 16 B IRQ185 Virtual Interrupt 8 0xC1 0xB9 3472 0xD90 16 B IRQ186 Virtual Interrupt 9 0xC2 0xBA 3488 0xDA0 16 B MSC8158E Reference Manual, Rev. 2 13-22 Freescale Semiconductor...
Page 599 IRQ212 MAPLE BD 3 0xDC 0xD4 3744 0xEA0 IRQ213 MAPLE BD 4 0xDD 0xD5 3752 0xEA8 IRQ214 MAPLE BD 5 0xDE 0xD6 3760 0xEB0 IRQ215 MAPLE BD 6 0xDF 0xD7 3768 0xEB8 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 13-23...
Page 600 ORed Watch Dog Timer 0xFE 0xF6 4016 0xFB0 Interrupts IRQ247 ORed MAPLE Interrupts 0xFF 0xF7 4024 0xFB8 IRQ248 Channel 0 Interrupt 0x100 0xF8 4032 0xFC0 IRQ249 Channel 1 Interrupt 0x101 0xF9 4040 0xFC8 MSC8158E Reference Manual, Rev. 2 13-24 Freescale Semiconductor...
Page 601: Core Interrupt Mesh
13.4 Core Interrupt Mesh To enhance communication between the six SC3850 DSP core subsystems, the MSC8158E has a core interrupt mesh. This mesh is built by connecting two interrupts from each of the SC3850 core subsystems to each of the DSP core subsystems (including itself). Table 13-7 describes the interrupt names connecting the DSP core subsystems: Table 13-7.
Page 602: Programming Model
Interrupt Handling 13.5 Programming Model The MSC8158E interrupt program model includes configuration of the global interrupt controller and the general configuration block interrupt registers. Note: See the SC3850 DSP Core Subsystem Reference Manual for configuration and programming of the EPIC registers.
Page 603: Virtual Interrupt Status Register (Visr)
Interrupt asserted VS18 Virtual Interrupt 18 Status Interrupt not asserted Reflects the status of VNMI_2. Interrupt asserted VS17 Virtual Interrupt 17 Status Interrupt not asserted Reflects the status of VNMI_1. Interrupt asserted MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 13-27...
Page 604 Interrupt not asserted Reflects the status of the core virtual interrupt 1. Interrupt asserted Virtual Interrupt 0 Status Interrupt not asserted Reflects the status of the core virtual interrupt 0. Interrupt asserted MSC8158E Reference Manual, Rev. 2 13-28 Freescale Semiconductor...
Page 605: General Interrupt Configuration
QUICC Engine Third External Request Multiplex Register (CPCE3R), see page 8-29 QUICC Engine Fourth External Request Multiplex Register (CPCE4R), see page 8-30 Note: The general interrupt configuration registers use a base address of: 0xFFF28000. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 13-29...
Page 606: Programming Restrictions
If the interrupt is not resolved and cleared, an endless loop can occur and cause a deadlock. For details, see the SC3850 DSP Subsystem Reference Manual, Appendix C: Error Handling. MSC8158E Reference Manual, Rev. 2 13-30 Freescale Semiconductor...
Page 607: Direct Memory Access (Dma) Controller
(EDF) algorithm. The DMA controller also supports a Debug mode and profiling for application development and testing. Figure 14-1 shows the DMAC block diagram. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 14-1...
Page 608: Operating Modes
— MBus is in debug mode and each of its ports gracefully stops its transaction. — Channel logic in debug mode. The arbitration mechanism masks all channels requests. The last serviced channel gets is fully serviced. MSC8158E Reference Manual, Rev. 2 14-2 Freescale Semiconductor...
Page 609: Buffer Types
Updates the multi-dimension parameters (multi dimension-buffers) The sections that follow provide examples of several types of buffers. The BD_ATTR fields listed for each example are only those that do not have zero values. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 14-3...
Page 610: One-Dimensional Simple Buffer
Generate interrupt when buffer ends. CONT Non-continuous mode: the buffer closes when the size reaches zero. Increment BD_ADDR when the size reaches zero. BTSZ Maximum transfer size is one burst of 64 bytes. MSC8158E Reference Manual, Rev. 2 14-4 Freescale Semiconductor...
Page 611: One-Dimensional Cyclic Buffer
Continuous mode: the buffer is not closed when the size reaches zero. Reinitialize BD_ADDR to original value when the size reaches zero. BTSZ Maximum transfer size is one burst of 64 bytes. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 14-5...
Page 612: One-Dimensional Chained Buffer
Buffer base size of cyclic buffer. BD_ATTR Generate interrupt when buffer ends. CONT Non-continuous mode. Close the buffer when size reaches zero. Non-cyclic mode. BTSZ Maximum transfer size is one burst of 64 bytes. MSC8158E Reference Manual, Rev. 2 14-6 Freescale Semiconductor...
Page 613: One-Dimensional Incremental Buffer
Generate interrupt when buffer ends. CONT Continuous mode. Do not close the buffer when size reaches zero. Increment BD_ADDRESS when size reaches zero. Next request calls buffer 0 when size reaches zero. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 14-7...
Page 614: One-Dimensional Complex Buffers With Dual Cyclic Buffers
Continuous mode. Do not shut down the channel when size reaches zero Reinitialize BD_ADDRESS to original value when size reaches zero When size reaches zero, the next request calls buffer 0 BTSZ Maximum transfer size is one burst of 64 bytes MSC8158E Reference Manual, Rev. 2 14-8 Freescale Semiconductor...
Page 615: Two-Dimensional Simple Buffer
0x40 bytes. The second dimension is composed of 0x80 lines of 0x40 bytes each. The offset between each 0x40 byte transaction is 0x1c0. The channel closes when the transfer completes after 0x80 iterations, and an interrupt is generated. Burst transactions are used on the bus. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 14-9...
Page 616 Third dimension iterations left. M3D_BCOUNT Third dimension base number of iterations. M3D_OFFSET Third dimension offset between two consecutive iterations. BD_MD_4D M4D_COUNT Fourth dimension iterations left. M4D_OFFSET Fourth dimension offset between two consecutive iterations. MSC8158E Reference Manual, Rev. 2 14-10 Freescale Semiconductor...
Page 617: Three-Dimensional Simple Buffer
0x10. The offset between each two-dimensional buffers is –0xF4BB0 (0x1090 – 0xE5040). The channel closes when the transfer completes after 0x100 executions of the two-dimensional buffers, and an interrupt is generated. Burst transactions are used on the bus. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 14-11...
Page 618: Four-Dimensional Simple Buffer
All MxD_COUNT must be set to their corresponding dimension parameter. All MxD_OFFSET must be set to the next address offset for the corresponding dimension loop. The MxD_OFFSET is written in twos-complement form. Figure 14-9 shows an example four-dimensional simple buffer. MSC8158E Reference Manual, Rev. 2 14-12 Freescale Semiconductor...
Page 619 –0xF3FB0 (0x1090 – 0xF5040). The channel closes when the transfer completes after 0x80 iterations of the three-dimensional buffer, and an interrupt is generated. Burst transactions are used on the bus. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 14-13...
Page 620 0x100 Third dimension base number of iterations. M3D_OFFSET 0xF3FB0 Third dimension offset between two consecutive iterations. BD_MD_4D M4D_COUNT 0x80 Fourth dimension iterations left. M4D_OFFSET 0x24050 Fourth dimension offset between two consecutive iterations. MSC8158E Reference Manual, Rev. 2 14-14 Freescale Semiconductor...
Page 621: Multi-Dimensional Chained Buffer
There is no constraint on the port used by each chained buffer. However, if the buffers use different ports, the DMA logic masks requests until data is out of the source or in the destination. This operation prevents out-of-sequence transactions at the ports. Table 14-9 shows the channel MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 14-15...
Page 622 0x100 Third dimension base number of iterations. M3D_OFFSET –0xF3FB0 Third dimension offset between two consecutive iterations. BD_MD_4D M4D_COUNT 0x80 Fourth dimension iterations left. M4D_OFFSET 0x24050 Fourth dimension offset between two consecutive iterations. MSC8158E Reference Manual, Rev. 2 14-16 Freescale Semiconductor...
Page 623: Two-Dimensional Cyclic Buffer
Third dimension iterations left. M3D_BCOUNT Third dimension base number of iterations. M3D_OFFSET –0xF040 Third dimension offset between two consecutive iterations. BD_MD_4D M4D_COUNT Fourth dimension iterations left. M4D_OFFSET Fourth dimension offset between two consecutive iterations. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 14-17...
Page 624: Three-Dimensional Cyclic Buffer
0x10. The offset between each two-dimensional buffer is –0xF3FB0 (0x1090 – 0xF5040). The base address of the channel is restored when the transfer completes after 0x100 executions of the two-dimensional buffers, and an interrupt is generated. MSC8158E Reference Manual, Rev. 2 14-18 Freescale Semiconductor...
Page 625: Arbitration Types
Fixed-priority among round-robin groups. Each channel is assigned to one of the four priority groups as defined by the DCHCRx[RRPG] bit. Each priority group can contain from 0 (empty) to all 16 channels. Pending requests from the highest-priority group are serviced first. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 14-19...
Page 626: Edf Arbitration
Counter is enabled/disabled when channel is activated/deactivated. Two options for continued buffer: — Continuous mode. Continues the deadline counter and channel with no action by the EDF logic. — Reset mode. Reloads the counter. MSC8158E Reference Manual, Rev. 2 14-20 Freescale Semiconductor...
Page 627: Issuing Interrupts
If a counter value equals the threshold value, EDF logic sets the corresponding sticky bit in the pending register. 14.3.2.2 Counter Control The EDF field in the source BD_ATTR of the channel defines the EDF logic behavior when source BD_SIZE reached zero. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 14-21...
Page 628: Clock Source To The Counters
For each error source, a bit in the DMA Error Register (DMAERR) indicates the error source. DMAERR also samples the first channel that caused the first bus error and the first channel that caused the first parity error. MSC8158E Reference Manual, Rev. 2 14-22 Freescale Semiconductor...
Page 629: Dma Peripheral Interface
Peripheral to peripheral. Both the source and destination transactions are controlled by DRQn. They can be controlled by the same done signal or by different done signals. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 14-23...
Page 630: Configuration And Control Registers
Configuration Registers: GCR DMA Request 0 (GCR_DREQ0) GCR DMA Request 1 (GCR_DREQ1) GCR DMA Done (GCR_DDONE) For details about the layout and structure of these registers, see Chapter 8, General Configuration Registers. MSC8158E Reference Manual, Rev. 2 14-24 Freescale Semiconductor...
Page 631: Functional Description
After the done signal is asserted, additional requests for the channel are ignored until the request signal is deasserted, the done signal is deasserted, and the request signal is reasserted. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 14-25...
Page 632: Using The Dma Peripheral Interface Block
GCR_DREQ1, and GCR_DDONE. See Chapter 8, General Configuration Registers for details. Enable the channel. After the MSC8158E has set up the DMA controller, the peripheral must perform the following steps: Deassert the input signal until the peripheral is ready to initiate the transfer.
Page 633: Dma Programming Model
GPIO block to enable the multiplexing of the handshaking signals and configure the associated channel information in the General Configuration Registers. See Section 14.5.4, Using the DMA Peripheral Interface Block, on page 14-26 for details. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 14-27...
Page 634: Dma Buffer Descriptor Base Registers X (Dmabdbrx)
0111 Destination table offset is 0x800. 1000 Destination table offset is 0x1000. 1001 Destination table offset is 0x2000. 1010 Destination table offset is 0x3000. 1011 Destination table offset is 0x4000. 11xx Reserved. MSC8158E Reference Manual, Rev. 2 14-28 Freescale Semiconductor...
Page 635: Dma Controller Channel Configuration Registers X (Dmachcrx)
The source can be either one-dimensional or Source is multi-dimensional. multi-dimensional. Written by: User DMDC Destination Multi-Dimensional Channel Destination is one-dimensional. The destination can be either one-dimensional or multi- Destination is dimensional multi-dimensional. Written by: User MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 14-29...
Page 636 The maximum number of one-dimensional BDs per destination is 1024. The maximum number of multi-dimensional BDs per destination is 512. For details on BD address calculation, see Section 14.6.21. Written by: User, DMA controller MSC8158E Reference Manual, Rev. 2 14-30 Freescale Semiconductor...
Page 637: Dma Controller Global Configuration Register (Dmagcr)
Section 14.3, Arbitration Types, on page 14-19 for details on arbitration. Written by: User 14.6.4 DMA Channel Enable Register (DMACHER) DMACHER DMA Channel Enable Register Offset 0x204 — Type Reset EN15 EN14 EN13 EN12 EN11 EN10 Type Reset MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 14-31...
Page 638: Dma Channel Disable Register (Dmachdr)
The interrupt latency in the system must be considered as well. When you are sure that the channel is disabled and there is no previous pending interrupts, the channel can be activated. MSC8158E Reference Manual, Rev. 2 14-32 Freescale Semiconductor...
Page 639: Dma Channel Freeze Register (Dmachfr)
This register is write only; writing a 1 to a bit toggles its value (that is, if the value is 0, it sets the bit and if it is 1, it clears the bit). Writing a zero to the bits has no effect. The DMACHDFR bits MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 640: Dma Time-To-Dead Line Registers X (Dmaedftdlx)
When the DMA reinitializes the counter it reloads the counter with BASE_COUNT. The BASE_COUNT maximum value is 0xff and the minimum is 0. Note: Do not change the base count value of active channels. MSC8158E Reference Manual, Rev. 2 14-34 Freescale Semiconductor...
Page 641: Dma Edf Control Register (Dmaedfctrl)
Reset: Each bit in the DMAEDFMR corresponds to an interrupt request bit in the DMAEDFSTR. When a bit is set, it enables the generation of an interrupt request of the corresponding counter. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 14-35...
Page 642: Dma Edf Mask Update Register (Dmaedfmur)
Channel Number 000000–001111 Channel number. 23–18 Indicate the channel number of the DMAEDFMR to 01xxxx Reserved. change. 1xxxxx Reserved. User New Channel Mask Value Not masked. Stores the new value of DMAEDFMR[MASK_CH2]. Masked. MSC8158E Reference Manual, Rev. 2 14-36 Freescale Semiconductor...
Page 643 Stores the new value of DMAEDFMR[MASK_CH0]. Masked. User Enable Mask/Unmask Updating Update occurred. When set, updates DMAEDFMR[MASK_CH0 Perform update. according to NM3. When DMAEDFMR[MASK_CH0] is updated, the DMA controller clears this bit. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 14-37...
Page 644: Dma Edf Status Register (Dmaedfstr)
Note: Setting the Sn bits has no effect because in the MSC8158E, only unidirectional destination channel interrupts are implemented as described in Section 14.4.1.
Page 645: Dma Mask Update Register (Dmamur)
NM2. Then the DMA controller clears this bit. Written by: User, DMA controller MASKCH1 Channel Number 00000–01111: Channel number. 15–11 The channel number to which DMAMR should be 1xxxx: Reserved changed. Written by: User MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 14-39...
Page 646: Dma Status Register (Dmastr)
Writing zero does not affect a bit value. Several bits can be cleared at one time. Note: You must clear the Dx and Sx bits before enabling the channel. MSC8158E Reference Manual, Rev. 2 14-40 Freescale Semiconductor...
Page 647: Dma Error Register (Dmaerr)
Port 1 Transfer Error Indication No transfer error acknowledged on Indicates whether there is an acknowledged transfer port 1. error on port 1. Transfer error acknowledged on port 1. — Reserved, write zero for future compatibility. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 14-41...
Page 648 Indicates by which channel the last parity error was 10xxxx Reserved. caused. PRTYD Parity Error Destination Source transaction error. Indicates whether the first parity error was caused Destination transaction error. by a channel source or destination. MSC8158E Reference Manual, Rev. 2 14-42 Freescale Semiconductor...
Page 649: Dma Debug Event Status Register (Dmadesr)
DMARRPGR is a special register that allows you to modify the DMACHCR[RRPG] bit without a read-modify-write operation. Note: Do not modify this register while the DMA controller is in EDF mode (DMAGCR[AT] is set—see page 14-31). MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 14-43...
Page 650: Dma Channel Active Status Register (Dmachastr)
14.6.20 DMA Channel Freeze Status Register (DMACHFSTR) DMACHFSTR DMA Channel Freeze Status Register Offset 0x388 D15 S15 D14 S14 Type Reset Type Reset MSC8158E Reference Manual, Rev. 2 14-44 Freescale Semiconductor...
Page 651: Dma Channel Buffer Descriptors
Source BD = BDT_BASE + DMACHCR[SRCBDPT] × 16 × (DMACHCR[SMDC] + 1) Destination BD: BDT_BASE + offset + DMACHCR[DESBDPT] × 16 × (DMACHCR[DMDC] + 1) Offset is the decoded value of DMABDBR[DESO] MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 14-45...
Page 652 BDs and multi-dimensional BDs are chained only to multi-dimensional BDs. The types of source and destination BDs are defined in the DMACHCR (see page 14-29). Table 14-27 lists the channel parameters for a one-dimensional BD. MSC8158E Reference Manual, Rev. 2 14-46 Freescale Semiconductor...
Page 653 This 32-bit parameter describes the attributes of the channel handling this buffer. The fields of the BD_ATTR parameter are described in Table 14-28. BD_BSIZE Buffer Base Size 31–0 Holds the base size of the buffer. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 14-47...
Page 654: Buffer Attributes (Bd_Attr)
BD_SIZE field. — Reserved. Write to zero for future compatibility. Next Buffer 25–16 When size reaches zero and CONT is set, the next request calls the buffer to which NBD points. MSC8158E Reference Manual, Rev. 2 14-48 Freescale Semiconductor...
Page 655 Typically, in continuous buffers, the channel should not destination. be masked. However, there is an automatic mask when continuous buffers switch between ports. The DMA controller unmasks the requests when the last data reaches the destination. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 14-49...
Page 656 This 52-bit parameter holds the two-dimensional parameters of the channel handling this buffer. It holds the base count value, current count, and address offset. The Multi Dimension fields are described in Table 14-31BD_MD_2D Field Descriptions, on page 14>-54. MSC8158E Reference Manual, Rev. 2 14-50 Freescale Semiconductor...
Page 657: Multi-Dimensional Buffer Attributes (Bd_Md_Attr)
This field must not be set for four dimensional buffers. This field is not valid for BD_MD_ATTR[CONTD]<BD_MD+ATTTR[BD]. CONT Continuous Buffer Mode Buffer closes. Specifies whether the buffer closes when CONTD dimension Buffer continues operating. count reaches zero. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 14-51...
Page 658 32 bytes. 0111 64 bytes. 1000 128 bytes. 1001 256 bytes. 1010 512 bytes. 1011 1024 bytes. 1100 2048 bytes. 1101 4096 bytes. 111x Reserved. — Reserved. Write to zero for future compatibility. MSC8158E Reference Manual, Rev. 2 14-52 Freescale Semiconductor...
Page 659 FRZ is set in the BD_MD_ATTR. 10 Mask and freeze channel when third dimension ends. 11 Mask and freeze channel when fourth dimension ends. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 14-53...
Page 660 If the buffer is more than two dimensional, this field cannot be 0. M2D_OFFSET Second Dimension Offset 27–0 Written in two’s complement. The offset is added to the BD_MD_ADDR each time BD_MD_SIZE reaches zero. MSC8158E Reference Manual, Rev. 2 14-54 Freescale Semiconductor...
Page 661 If the buffer is four dimensional, then this field cannot be 0. M4D_OFFSET Fourth Dimension Offset 27–0 Written in two’s complement. The offset is added to the BD_MD_ADDR each time BD_MD_SIZE, M2D_COUNT, and M3D_COUNT reach zero. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 14-55...
Page 662 Direct Memory Access (DMA) Controller MSC8158E Reference Manual, Rev. 2 14-56 Freescale Semiconductor...
Page 663: High Speed Serial Interface (Hssi) Subsystem
One 8-channel SerDes PHY that multiplexes the RapidIO, CPRI, and SGMII signals for external connection. These communication interfaces allow the cores to execute the data processing code and be relieved from the data transfer and handling overhead for processing serial data flow. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-1...
Page 664: Hssi Subsystem Block Diagram
The actual signal multiplexed for each channel in the PHY is determined by the SerDes configuration field contents in the lower 32 bits of the reset configuration word, which are recorded in RCWLR[SP]. See Chapter 5, Reset for details. Figure 15-1. HSSI Block Diagram MSC8158E Reference Manual, Rev. 2 15-2 Freescale Semiconductor...
Page 665: Class1
Init. Port 12 Target Ports Chip Level Arbitration and Switching System (CLASS1) Initiator Ports CPRI1 O2M0 AXI2M1 O2M1 CPRI0 AXI2M0 Initiator Devices Figure 15-2. CLASS1 Initiators and Targets in the MSC8158E Device MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-3...
Page 666: Functional Description
The multiplexer and arbiter module block is a pure logic data path design, that supports up to 16 initiators, performs an arbitration, and concentrates them towards a specific target normalizer module. MSC8158E Reference Manual, Rev. 2 15-4 Freescale Semiconductor...
Page 667: Class Arbiter
— For priority 1 requests, priority is upgraded to priority 2 after AUV/2 cycles. — For priority 2 requests, priority is upgraded to priority 3 (highest) after AUV/4 cycles. The upgrade process continues until the request is processed or it reaches priority 3. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-5...
Page 668: Class Multiplexer
Note: If the associated AEIx bit in the C1ISR is already set when the illegal address is identified (due to a prior illegal address), then the new error address is not stored. MSC8158E Reference Manual, Rev. 2 15-6 Freescale Semiconductor...
Page 669: Class Debug Profiling Unit
The CDPU is deactivated by: Writing a 0 to the C1PCR[PE] bit. Configuring a watch point event in C1PCR[WPEC] field. Reaching a time-out in the C1PTOR when the C1PCR[TOE] bit is set. C1PRCR overflow. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-7...
Page 670: Watch Point Unit
— In time-out mode, read C1PRCR. — If C1PISR[OVE] is set or if C1PRCR is equal to C1PTOR, the results are not valid. — Read C1PGCRx to get the number of watch point events during the measurement. MSC8158E Reference Manual, Rev. 2 15-8 Freescale Semiconductor...
Page 671: Event Selection
Stall at the initiator does not mean that the initiator target data phase is idle; it indicates the delay after which the next access from the initiator starts at the target after a WAR or TS event. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor...
Page 672 = [(NumberOfReadAck + NumberOfWriteAck) × W]. where W is the port width. Note that an access may be smaller than the port width. MSC8158E Reference Manual, Rev. 2 15-10 Freescale Semiconductor...
Page 673 Watch point event scan be snooped on any initiator and any target. It can be used for debug and also for triggering profiling counts that are pre-configured, this is non-intrusive (eliminating the need to write to the registers in the middle of an application) MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-11...
Page 674: Debug And Profiling Events
The On-Chip Network (OCN) fabric is a non-blocking high speed interconnect used for embedded system devices. The MSC8158E DSP HSSI uses an 8-port OCN to connect between the Serial RapidIO Controllers, the two OCN-to-MBus bridges (O2M[0–1]) that connect to the CLASS1 module, and the two supporting dedicated DMA controllers.
Page 675: Ocn-To-Mbus (O2M) Bridges
15.5 DMA Controllers The MSC8158E includes two dedicated DMA controllers that transfer blocks of data between the serial RapidIO controller/PEX Controller and the local address space independent from the DSP cores. Figure 15-3 shows the block diagram of each dedicated DMA controller.
Page 676: Overview
The ATMU translates a request address into a logical device source/destination. 15.5.3 Modes of Operation Each MSC8158E dedicated DMA controller has two modes of operation: basic and extended. Basic mode is the DMA legacy mode. It does not support advanced features. Extended mode supports advanced features like striding and flexible descriptor structures.
Page 677 Refer to Section 15.5, DMA Controllers for details on these modes. Figure 15-4 shows the general DMA operational flow chart. Software Sets 1st Link Process Link Advance Link Last Link? Chain or Extended Mode? Last List? Done — DMA Halts Advance List Figure 15-4. DMA Operational Flow Chart MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-15...
Page 678: Dma Channel Operation
This mode is primarily included for backward compatibility with existing DMA controllers which use a simple programming model. This is the default mode out of reset. The different modes of operation under the basic mode are explained in the following sections. MSC8158E Reference Manual, Rev. 2 15-16 Freescale Semiconductor...
Page 679: Basic Direct Mode
Poll the channel state (see Table 15-3), to confirm that the specific DMA channel is idle. Initialize the source attributes (SATRn), DATRn, and BCRn registers. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-17...
Page 680: Basic Chaining Mode
SRn[CB] is automatically cleared by the DMA controller after finishing the transfer of the last descriptor segment, or if the transfer is aborted (MRn[CA] transitions from a 0 to 1), or if an error occurs during any of the transfers. MSC8158E Reference Manual, Rev. 2 15-18 Freescale Semiconductor...
Page 681: Basic Chaining Single-Write Start Mode
Striding on the source address can be accomplished by setting SATRn[SSME] and setting the desired stride size and distance in SSRn. Striding on the destination address can be accomplished by setting DATRn[DSME] and setting the desired stride size and distance in DSRn. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-19...
Page 682: Extended Direct Single-Write Start Mode
Setting MRn[CDSM/SWSM] causes MRn[CS] to be set automatically when CLSDARn is written. The sequence of events to start and complete an extended chain using single-write start mode is as follows: MSC8158E Reference Manual, Rev. 2 15-20 Freescale Semiconductor...
Page 683: Channel Continue Mode For Cascading Transfer Chains
If EOLND or EOLSD is still set for their respective modes, the DMA controller remains in the idle state. If the EOLND or EOLSD bits are not set, the DMA controller continues the transfer by refetching the new descriptor. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-21...
Page 684: Basic Mode
However, if only one channel is busy, hardware overrides the specified bandwidth control size value. The DMA controller allows a channel to transfer up to 1 Kbyte at a time when no other channel is active. MSC8158E Reference Manual, Rev. 2 15-22 Freescale Semiconductor...
Page 685: Channel State
This sequence repeats until the amount of data transferred equals the transfer size. Stride Distance Stride Size Base Address New Base Address New Base Address Figure 15-5. Stride Size and Stride Distance MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-23...
Page 686: Dma Transfer Interfaces
For each link descriptor in the chain, the DMA controller starts a new DMA transfer with the control parameters specified by that descriptor. Table 15-4 summarizes the DMA list descriptors. MSC8158E Reference Manual, Rev. 2 15-24 Freescale Semiconductor...
Page 687 Reserved 0x04 Next List Descriptor Address 0x08 Reserved 0x0c First Link Descriptor Address 0x10 Source Stride 0x14 Destination Stride 0x18 Reserved 0x1c Reserved Figure 15-6. List Descriptor Format (Used for 32-bit devices) MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-25...
Page 688 Source Attributes 0x04 Source Address 0x08 Destination Attributes 0x0c Destination Address 0x10 Reserved 0x14 Next Link Descriptor Address 0x18 Byte Count 0x1c Reserved Figure 15-8. Link Descriptor Format (Used for 32-bit devices MSC8158E Reference Manual, Rev. 2 15-26 Freescale Semiconductor...
Page 689: Local Access Atmu Registers
MRn[SAHTS]. The source address must be aligned to a size specified by SAHTS. If MRn[DAHE] is set, the destination interface transfer size capability must be greater than or equal to MRn[DAHTS]. The destination address must be aligned to the size specified by DAHTS. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-27...
Page 690: Serial Rapidio Complex
(see Section 8.2.6 and Section 8.2.7 in Chapter 8, General Configuration Registers). Control of the individual lanes is done through the SRDS Control Registers described in Section 15.9.56 through Section 15.9.59. MSC8158E Reference Manual, Rev. 2 15-28 Freescale Semiconductor...
Page 691: Serdes Banks And Pll
5 GHz (SRIO at 5 Gbps, 2.5 Gbps and/or SRIO/SGMII at 1.25Gbps) 125 MHz: 6.125 GHz (SRIO at 3.125 Gbps) 122.88 MHz: 6.144 GHz (CPRI at 6.144Gbps, 3.072Gbps) 122.88 MHz: 4.9152 (CPRI at 4.9152 Gbps, 2.4576 Gbps,1.2288 Gbps) MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-29...
Page 692: Serdes Pll Multiplexing
8 SerDes ports. The BLUE lines indicate PLL1 support and the RED lines indicate PLL2 support. In the case of the 8x0 configuration, PLL2 is off. Figure 15-10. 8x0 PLL Multiplexing Figure 15-11. 6x2 PLL Multiplexing Figure 15-12. 4x4 PLL Multiplexing MSC8158E Reference Manual, Rev. 2 15-30 Freescale Semiconductor...
Page 693: Serdes Clocks
Transmit/Receive clock frequencies for the different data rates. Table 15-6. SerDes Clocks to Controllers Data Rate (Gbps) TBI ClocK (MHz) 1.2500 125.00 2.5000 250.00 3.1250 312.50 5.0000 500.00 6.1440 614.40 4.9152 491.52 3.0720 307.20 2.4576 245.76 1.2288 122.88 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-31...
Page 694: Hssi Programming Model
0xFFFAA000. — Dn DMA 0–3 Mode Registers (DnMR[0–3]), page 15-67 — Dn DMA 0–3 Status Registers (DnSR[0–3]), page 15-70 — Dn DMA 0–3 Current Link Descriptor Extended Address Registers (DnECLNDAR[0–3], page 15-72 MSC8158E Reference Manual, Rev. 2 15-32 Freescale Semiconductor...
Page 695 — Lane A–J General Control Register 0 (L[A–J]GCR0), page 15-98 — Lane A–J Receive Equalization Control Register 0 (L[A–J]RECR0), page 15-100 — Lane A–J Transmit Equalization Control Register 0 (L[A–J]TECR0), page 15-102 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-33...
Page 696 General Status Register 3 (GSR3), page 8-27 General Interrupt Register 5 (GIR5), page 8-42 General Interrupt Enable Register 5 (GIER5_[0–5]), page 8-44 General Interrupt Register 7 (GIR7), page 8-74 General Interrupt Enable Register 7 (GIER7_[0–5]), page 8-76 MSC8158E Reference Manual, Rev. 2 15-34 Freescale Semiconductor...
Page 697: Class1 Priority Mapping Registers (C1Pmrx)
Reserved. Write to 0 for future compatibility. 7–6 Priority Mapping 1 Priority 0 5–4 Holds the priority value assigned to Priority 1 transactions that arrive with a value of 1. Priority 2 Priority 3 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-35...
Page 698: Class1 Priority Auto Upgrade Value Registers (C1Pavrx)
• Priority 1: Bits 15–1 are loaded into bit 14–0 of the counter and a 0 into bit 15. • Priority 2: Bits 15–2 are loaded into bits 13–0 of the counter and 0 into bits 15 and 14. MSC8158E Reference Manual, Rev. 2 15-36...
Page 699: Class1 Priority Auto Upgrade Control Registers (C1Pacrx)
— Reserved. Write to 0 for future compatibility. 31–1 Auto-Upgrade Enable Auto-upgrade mechanism disabled. Enables/disables the auto-upgrade Auto-upgrade mechanism enabled. mechanism. Note: This bit can only be cleared by a hardware reset. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-37...
Page 700: Class1 Error Address Registers (C1Earx)
— C1EAR3 = Address generated by OCN-to-MBus port 1 (O2M1) — C1EAR4 = Address generated by CPRI MBus port 0 — CPRI write — C1EAR5 = Address generated by AXI-to-MBus port 0 (AXI2M0)—eMSG write. MSC8158E Reference Manual, Rev. 2 15-38 Freescale Semiconductor...
Page 701: Class1 Error Extended Address Registers (C1Eearx)
CPRI MBus Port 0 — CPRI write 10100 AXI-to-MBus port 0 (AXI2M0)—eMSG write ERR_ADD Error Address 3–0 This field stores the 4 msbs of the address of the internal transaction that caused the error. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-39...
Page 702: Class1 Initiator Profiling Configuration Registers (C1Ipcrx)
Target 1 bandwidth. 10010– 11111 reserved Table 15-13. Initiator Numbers Initiator Initiator Module Number OCN-to-MBus Port 0 (O2M0) CPRI MBus Port 1— CPRI read AXI-to-MBus port 1 (AXI2M1)—eMSG read OCN-to-MBus Port 1 (O2M1) MSC8158E Reference Manual, Rev. 2 15-40 Freescale Semiconductor...
Page 703: Class1 Initiator Watch Point Control Registers (C1Iwpcrx)
Reserved. Write to 0 for future compatibility. 31–1 WPEN Watch Point Enable The watch point is disabled. Enables/disables the auto-upgrade The watch point is enabled. mechanism. Note: This bit can only be cleared by a hardware reset. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-41...
Page 704: Class1 Arbitration Weight Registers (C1Awrx)
As a general rule, these recommended settings select a weighted arbitration of 3. Also, see Table 15-37 for recommended initial settings for the CLASS1 Arbitration Control Register (C1ACR). MSC8158E Reference Manual, Rev. 2 15-42 Freescale Semiconductor...
Page 705: Class1 Start Address Decoder 1 (C1Sad1)
The 24 msb of the start address of the specified port window. The lsbs are all zeros. Note: Never write to this register when there are open transactions being handled by the CLASS to the specified target controlled by the register. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-43...
Page 706: Class1 Start Address Decoder 2(C1Sad2)
The 24 msb of the start address of the specified port window. The lsbs are all zeros. Never write to this register when there are open transactions being handled by the CLASS to the specified target controlled by the register. MSC8158E Reference Manual, Rev. 2 15-44 Freescale Semiconductor...
Page 707: Class1 End Address Decoder 1 (C1Ead1)
4 Kbytes. Note: Never write to this register when there are open transactions being handled by the CLASS1 to the specified target controlled by the register. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-45...
Page 708: Class1 End Address Decoder 1 (C1Ead2)
4 Kbytes. Never write to this register when there are open transactions being handled by the CLASS1 to the specified target controlled by the register. MSC8158E Reference Manual, Rev. 2 15-46 Freescale Semiconductor...
Page 709: Class1 Attributes Decoder 1 (C1Atd1)
DEN is cleared continues normally until completed. Note: To ensure proper operation, do not enable the specific decoder before the start and end addresses are specified in the associated C1SAD1 and C1EAD1. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-47...
Page 710 (defined by C0SAD2/C0EAD2). Use for cases of unbalanced reads/writes or to split address space among different HSSI masters. Note: A hit in C1SAD2/C1EAD2 has a higher priority than a hit in C1SAD1/C1EAD1 window. MSC8158E Reference Manual, Rev. 2 15-48 Freescale Semiconductor...
Page 711: Class1 Attributes Decoder 1 (C1Atd2)
Disables the decoder. Enables/disables the specified decoder. Enables the decoder. Never write to this register when there are open transactions being handled by the CLASS1 to the specified target controlled by the register. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-49...
Page 712: Class1 Irq Status Register (C1Isr)
Address Error Interrupt 2 No error. A bit is set if for a received transaction Error detected. request, it does not belong to any port address space or falls inside one of the error areas. MSC8158E Reference Manual, Rev. 2 15-50 Freescale Semiconductor...
Page 713 Address Error Interrupt 0 No error. A bit is set if for a received transaction Error detected. request, it does not belong to any port address space or falls inside one of the error areas. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-51...
Page 714: Class1 Irq Enable Register (C1Ier)
Interrupt masked. Used to enable/disable the address error Interrupt enabled. interrupt for an initiator. AEI0 Address Error0 Interrupt Enable Interrupt masked. Used to enable/disable the address error Interrupt enabled. interrupt for an initiator. MSC8158E Reference Manual, Rev. 2 15-52 Freescale Semiconductor...
Page 715: Class1 Target Profiling Configuration Register (C1Tpcr)
00 No profiling measurement. selected target. 01 Arbitration winner priority measurement. 10 Collisions measurement. 11 reserved. If TT = 1: 00 No profiling measurement. 01 Transaction splitting measurement. 10 Bandwidth measurement. 11 Stall measurement. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-53...
Page 716: Class1 Profiling Control Register (C1Pcr)
Time-out function disabled. Enables/disables the time-out mechanism. Time-out function enabled. — Reserved. Write to 0 for future compatibility. 3–1 Profiling Enable Profiling unit disabled. Enables/disables the debug profiling unit Profiling unit enabled. operation. MSC8158E Reference Manual, Rev. 2 15-54 Freescale Semiconductor...
Page 717: Class1 Watch Point Control Registers (C1Wpcr)
Enables/disables the atomic access type Atomic access type compare with C1WPACR comparison. enabled. Read-Safe Access Compare Enable Read-safe type compare disabled. Enables/disables the read-safe type Read-safe type compare with C1WPACR comparison. enabled. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-55...
Page 718 Enables/disables comparison of the Address compare with C1WPACR enabled. access address. Count Enable Counter 1 disabled for watch point events. Enables/disables the counter for watch Counter 1 enabled for watch point events. point events. MSC8158E Reference Manual, Rev. 2 15-56 Freescale Semiconductor...
Page 719: Class1 Watch Point Access Configuration Register (C1Wpacr)
For every bit in C1WPAMR[ADDM] that is cleared, make sure the corresponding bit is cleared in the ADDR. The bit location in ADDM (b) corresponds to the b + 12 bit location in ADDR. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-57...
Page 720: Class1 Watch Point Extended Access Configuration Register
11 Priority 3 (lowest) Byte Count The byte count to monitor can be from 1 to 511 8–0 This field defines the value of the byte bytes. count that the watch point unit monitors. MSC8158E Reference Manual, Rev. 2 15-58 Freescale Semiconductor...
Page 721: Class1 Watch Point Address Mask Registers (C1Wpamr)
11111110 Aligned with a range of 8 KB. sure the corresponding 11111111 Aligned with a range of 4 KB. bit is cleared in the All other values are reserved. C1WPACR. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-59...
Page 722: Class1 Profiling Time-Out Registers (C1Ptor)
Table 15-31 lists the C1PTOR bit field descriptions. Table 15-31. C1PTOR Bit Descriptions Name Reset Description 0xFFFFFFFF Time-Out 31–0 Holds the time-out value used to stop the profiling unit when the time-out function is enabled. MSC8158E Reference Manual, Rev. 2 15-60 Freescale Semiconductor...
Page 723: Class1 Target Watch Point Control Registers (C1Twpcr)
The watch point unit for the associated target is 2–1 Each bit enables monitoring of access by disabled. the associated target. The watch point unit for the associated target is enabled. — Reserved. Write to 0 for future compatibility. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-61...
Page 724: Class1 Profiling Irq Status Register (C1Pisr)
Enables monitoring of access by the Watch point event captured. associated target. Overflow Event No overflow occurred. Enables monitoring of access by the C1PRCR overflowed (reached 0xFFFFFFFF) associated target. during the last measurement. MSC8158E Reference Manual, Rev. 2 15-62 Freescale Semiconductor...
Page 725: Class1 Profiling Irq Enable Register (C1Pier)
Watch Point Event Enable Watch point interrupt is masked. Enables/disables a watch point interrupt. Watch point interrupt is enabled. OVEE Overflow Event Enable Overflow interrupt is masked. Enables/disables an overflow interrupt. Overflow interrupt is enabled. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-63...
Page 726: Class1 Profiling Reference Counter Register (C1Prcr)
When PE clears, the CLASS1 stops all profiling counters. The register is reset only by a hardware reset only. Table 15-35 lists the C1PRCR bit field descriptions. Table 15-35. C1PRCR Bit Descriptions Name Reset Description Counter 31–0 Holds the reference counter for the profilers. MSC8158E Reference Manual, Rev. 2 15-64 Freescale Semiconductor...
Page 727: Class1 Profiling General Counter Registers (C1Pgcrx)
Table 15-36 lists the C1PGCR bit field descriptions. Table 15-36. C1PGCR Bit Descriptions Name Reset Description Counter 31–0 Holds the counter value of the selected measurement. Table 15-1 lists the measurements counted by each counter for each configuration combination. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-65...
Page 728: Class1 Arbitration Control Register (C1Acr)
This value assigns late arbitration to system CLASS accesses. This is just an initial value, and can be changed according to the application requirements and system traffic. — Reserved. Write to 0 for future compatibility. MSC8158E Reference Manual, Rev. 2 15-66 Freescale Semiconductor...
Page 729: Mode Registers 0-3 (Dnmr[0-3])
11 8 bytes. based on the size. The defined size must be equal to or small than the value of MR[BWC] to avoid undefined behavior. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-67...
Page 730 Extended Chaining Enable (CTM = 0 only) Extended chaining disabled. When set, enables extended chaining mode. Extended chaining enabled. Note: This bit is reserved in direct mode. MSC8158E Reference Manual, Rev. 2 15-68 Freescale Semiconductor...
Page 731 Starts the DMA process if the channel is idle (SR[CB] is cleared). Setting the bit while the channel is busy continues the current transfer from the point at which it stopped. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-69...
Page 732: Status Registers (Dnsrn)
Write a 1 to this bit to clear it. Channel Busy Channel is idle, DMA transfer Indicates the current status of the channel. completed, error occurred, or a channel abort occurred. DMA transfer is in progress. MSC8158E Reference Manual, Rev. 2 15-70 Freescale Semiconductor...
Page 733 After transferring the last block of data in the last list End-of-list interrupt. descriptor, if MR[EOLSIE] is set, then this bit is set and an interrupt is generated. Note: Write a 1 to this bit to clear it. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-71...
Page 734: Current Link Descriptor Extended Address Registers (Dneclndarn)
If EOLSD is set, all DMA transfers are complete and the DMA controller halts. Table 15-40 describes the DnECLNDAR fields. Table 15-40. DnECLNDAR Field Descriptions Bits Reset Description Setting — Reserved. Write to zero for future compatibility. 31–4 MSC8158E Reference Manual, Rev. 2 15-72 Freescale Semiconductor...
Page 735: Current Link Descriptor Address Registers (Dnclndarn)
Note: This field is used for all transfers. For RapidIO transactions, it is the lower portion of the 36-bit address formed by combining with the ECLNDA for use with RapidIO transaction types. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-73...
Page 736: Source Attributes Registers (Dnsatrn)
Specifies the source transaction type. processor. Note: Writing a reserved value to this field causes a All other values reserved. programming error to be detected and indicated in SR[PE] for the specified channel. MSC8158E Reference Manual, Rev. 2 15-74 Freescale Semiconductor...
Page 737: Source Address Registers (Dnsarn)
DMA write operation unless the final stride of a striding operation is less than the stride size, it which case it remains equal to the address from with the last stride began. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-75...
Page 738: Destination Attributes Registers (Dndatrn)
Destination Stride Register (DSR) for the specified channel. Note: This bit is ignored in basic mode (MR[EFE] is cleared (0). — Reserved. Write to zero for future compatibility. 23–20 MSC8158E Reference Manual, Rev. 2 15-76 Freescale Semiconductor...
Page 739: Destination Address Registers (Dndarn)
DMA write operation unless the final stride of a striding operation is less than the stride size, it which case it remains equal to the address from with the last stride began. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-77...
Page 740: Byte Count Registers (Dnbcrn)
31–26 Byte Count 25–0 Contains the number of bytes to transfer. The value in this field is decremented after each DMA read operation. The maximum transfer size is 2 – 1 bytes. MSC8158E Reference Manual, Rev. 2 15-78 Freescale Semiconductor...
Page 741: Extended Next Link Descriptor Address Registers (Dnenlndarn)
31–4 ENLNDA Next Link Descriptor Extended Address 3–0 Contains the most significant 4 bits of the 36-bit address used with RapidIO transactions only. Note: This field is not used for local transactions. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-79...
Page 742: Next Link Descriptor Address Registers (Dnnlndarn)
Enables/disables the next descriptor Generate next descriptor end-of-segment interrupt when the current DMA end-of-segment interrupt when transfer for the current link descriptor completes. transfer is complete. — Reserved. Write to zero for future compatibility. 2–1 MSC8158E Reference Manual, Rev. 2 15-80 Freescale Semiconductor...
Page 743: Extended Current List Descriptor Address Registers (Dneclsdarn)
31–4 ECLSDA Current List Descriptor Extended Address 3–0 Contains the most significant 4 bits of the 36-bit address used with RapidIO transactions only. Note: This field is not used for local transactions. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-81...
Page 744: Current List Descriptor Address Registers (Dnclsdarn)
RapidIO transactions, it is the lower portion of the 36-bit address formed by combining with the ECLSDA for use with RapidIO transaction types. — Reserved. Write to zero for future compatibility. 4–0 MSC8158E Reference Manual, Rev. 2 15-82 Freescale Semiconductor...
Page 745: Extended Next List Descriptor Address Registers (Dnenlsdarn)
31–4 ENLSDA Next List Descriptor Extended Address 3–0 Contains the most significant 4 bits of the 36-bit address used with RapidIO transactions only. Note: This field is not used for local transactions. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-83...
Page 746: Next List Descriptor Address Registers (Dnnlsdarn)
Last list descriptor in memory. descriptor in memory. When the bit is set, the DMA controller halts after the last link descriptor transaction finishes. Note: This bit is ignored in direct mode. MSC8158E Reference Manual, Rev. 2 15-84 Freescale Semiconductor...
Page 747: Source Stride Registers (Dnssrn)
Holds the number of bytes to transfer before jumping to the next address as specified in the source stride distance field. Source Stride Distance 11–0 The source stride distance in bytes from the start byte to the end byte. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-85...
Page 748: Destination Stride Registers (Dndsrn)
Holds the number of bytes to transfer before jumping to the next address as specified in the destination stride distance field. Destination Stride Distance 11–0 The destination stride distance in bytes from the start byte to the end byte. MSC8158E Reference Manual, Rev. 2 15-86 Freescale Semiconductor...
Page 749: Dma General Status Register (Dndgsr))
Channel 1 Programming Error Detected Normal operation. Indicates whether a programming error was Programming error detected. detected. EOLNI1 Channel 1 End-of-Links Interrupt Normal operation. Indicates whether an end-of-links interrupt End-of-links interrupt occurred. occurred. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-87...
Page 750 Channel 3 End-of-Segment Interrupt Normal operation. Indicates whether an end-of-segment interrupt End-of-segment interrupt occurred. occurred. EOLSI3 Channel 3 End-of-Lists/Direct Interrupt Normal operation. Indicates whether an end-of lists/direct interrupt End-of-list/direct interrupt occurred. occurred. MSC8158E Reference Manual, Rev. 2 15-88 Freescale Semiconductor...
Page 751: Local Access Window Base Address Registers 0-9 (Dnlawbar[0-9])
• Bits 23–20 correspond to the value of SATRx[ESAD]/DATRx[EDAD] • Bits 19–0 correspond to bits 31–12 of SARx[SAD]/DARx[DAD] Note: For local transactions, the most significant 4 bits in this field must be 0s. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-89...
Page 752: Local Access Window Attributes Registers 0-9 (Dnlawar[0-9])
SRIO Port 0 value defaults to local address space. 1101 SRIO Port 1 1111 OCN to MBus Bridge 1 for local space. All others reserved. — Reserved. Write to zero for future compatibility. 19–6 MSC8158E Reference Manual, Rev. 2 15-90 Freescale Semiconductor...
Page 753 When using the same OCN-to-MBus (O2M) for Read and Write transactions, the write transactions may write incorrect data for specific access sequences. To preclude this scenario, use one bridge for Write transactions and the other bridge for read transactions. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-91...
Page 754: Cprin Pcvtr Control Register 0(Pcvtrcprincr0)
Reset. 0x02F1 4.9152 Gbps Every time that software preforms a SerDes reset request, the register values are overwritten 0x0265 6.1440 Gbps based on the recommended settings for each link rate. MSC8158E Reference Manual, Rev. 2 15-92 Freescale Semiconductor...
Page 755: Cprin Pcvtr Control Register 1(Pcvtrcprincr1)
Reset. 0x03B1 4.9152 Gbps Every time that software preforms a SerDes reset request, the register values are overwritten 0x02FF 6.1440 Gbps based on the recommended settings for each link rate. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-93...
Page 756: Srds Bank 1 Reset Control Register (Srdsb1Rstctl)
Software can only set this bit but not clear it. If the bit cleared before reset is complete, the reset state machine ignores the change. — Reserved. Write to zero for future compatibility. 30–0 MSC8158E Reference Manual, Rev. 2 15-94 Freescale Semiconductor...
Page 757: Srds Bank 2 Reset Control Register (Srdsb2Rstctl)
Invokes an internal signal that resets the PLL lock detection and test PLL Reset. circuitry. It is used in CPRI auto rate negotiation. — Reserved. Write to zero for future compatibility. 6–0 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-95...
Page 758: Srds Bank 1-2 Pll Control Register 0 (Srdsb[1-2]Pllcr0)
Reserved. specified protocol limits. 4.915 GHz 6.144 GHz (valid on SRDSB2PLLCR0 only) All other values reserved. — Reserved. Write to zero for future compatibility. 15–0 MSC8158E Reference Manual, Rev. 2 15-96 Freescale Semiconductor...
Page 759: Srds Bank 1-2 Pll Control Register 1 (Srdsb[1-2]Pllcr1)
10 Common mode is high impedance, Rx termination is uncalibrated 120 Ω differential. 11 Common mode is 0.7*xcorevdd through 3 KΩ, Rx termination is uncalibrated 120 Ω differential. — Reserved. Write to zero for future compatibility. 7–0 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-97...
Page 760: Lane C-J General Control Register 0 (L[C-J]Gcr0)
Reserved. Write to zero for future compatibility. 27–26 TRAT_ Configured Transmitter Speed Selection Full speed by Reset Selects the lane receiver speed Half speed 25–24 Quarter speed reserved — Reserved. Write to zero for future compatibility. 23–0 MSC8158E Reference Manual, Rev. 2 15-98 Freescale Semiconductor...
Page 761: Lane C-J General Control Register 1 (L[C-J]Gcr1)
Tx Output Pad Control Signal for Transmitter enabled. by Reset Common Mode Force transmitter output to common mode. Selects the transmitter common mode. — Reserved. Write to zero for future compatibility. 25–0 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-99...
Page 762: Lane C-J Receive Equalization Control Register 0 (L[C-J]Recr0)
• CPRI 4.915 Gbps = 10000 • CPRI 3.072 Gbps = 00000 • CPRI 2.4576 Gbps = 00000 • CPRI 1.2288 Gbps = 01111 — Reserved. Write to zero for future compatibility. 23–20 MSC8158E Reference Manual, Rev. 2 15-100 Freescale Semiconductor...
Page 763 Configured Adaptive Equalization Offset Override 000000 +Maximum imposed offset 5–0 by Reset Value overrides the adaptive equalization 011111 0 imposed offset (recommended) offset control. 111111 –Maximum imposed offset All other values reserved. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-101...
Page 764: Lane C-J Transmit Equalization Control Register 0 (L[C-J]Tecr0)
(recommended for all others) 10 3 Levels of Tx Equalization (+1 pre-cursor and +1 post-cursor) 11 4 Levels of Tx Equalization (+1 pre-cursor and +2 post-cursors) — Reserved. Write to zero for future compatibility. 27–20 MSC8158E Reference Manual, Rev. 2 15-102 Freescale Semiconductor...
Page 765 • Serial RapidIO 3.125/2.5 Gbps short run 10100 0.5x full swing = 001000 All other values represent intermediate values. • Serial RapidIO 3.125/2.5 Gbps long run = 000000 • SGMII 1.25 Gbps = 001011 • CPRI = 000000 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 15-103...
Page 766: Lane C-J Test Control/Status Register 3 (L[C-J]Tcsr3)
01 Digital loopback. the Rx amplifier to allow for on-chip system 10 Reserved. check. 11 Reserved. The recommended settings for all protocols is 00. — Reserved. Write to zero for future compatibility. 27–0 MSC8158E Reference Manual, Rev. 2 15-104 Freescale Semiconductor...
Page 767: Serial Rapidio Controller And Enhanced Message Complex
Data throughput is managed using a buffer manager (BMLite) and a frame manager (FMLite). The MSC8158E device can connect directly to a host, another MSC8158E device, or a serial RapidIO switch. Each port in the switch is point-to-point connected to the MSC8158E device through a serial RapidIO link that typically carries packets in both directions.
Page 768 It handshakes with the software running on a DSP core through buffer descriptors (BDs) that are messaged from the DSP core to the host. The host can put all the data buffers into its memory and have the MSC8158E access the data.
Page 769 The actual signal multiplexed for each channel in the PHY is determined by the SerDes configuration field contents in the lower 32 bits of the reset configuration word, which are recorded in RCWLR[SP]. See Chapter 5, Reset for details. Figure 16-1. HSSI Block Diagram MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-3...
Page 770: Serial Rapidio And Emsg Complex Overview
Revision 1.3, Part 6: 1x/rx LP-Serial Physical Layer Specification. Register and register bit extensions as described in the RapidIO Interconnect Specification, Revision 1.2, Part VIII: Error Management Extensions Specification. Hot swap ATOMIC set/clr/inc/dec for read-modify-write operations MSC8158E Reference Manual, Rev. 2 16-4 Freescale Semiconductor...
Page 771: Emsg Unit
RapidIO Interconnect Specification Revision 1.3, Part 10: Data Streaming Logical Specification. RapidIO Interconnect Specification Revision 2.0, Part 10: Stream Management Flow Control. Basic stream management flow control (XON/XOFF) using extended header message format. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-5...
Page 772 One or more Type8 port-write inbound classification units with the following features: — transaction steering through port-write header classification. — data payloads of 4 to 64 bytes. One or more Type8 outbound port-write units with data payloads of 4 to 64 bytes. MSC8158E Reference Manual, Rev. 2 16-6 Freescale Semiconductor...
Page 773: Internal Processing Support
Using PI/CI values that are one bit wider than needed to address the ring entries means that the (PI/CI) mod (index–width) gives the correct fit of the ring buffer over the entire range where full can be distinguished from empty. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-7...
Page 774: Operating Modes
Primary input pads. — SD_RX[0–3] Serial data input for x1 or x4 link. One differential pair Asynchronous inputs. input per link. This implementation supports data rates of 1.25, 2.5, 3.125, or 5 Gbaud. MSC8158E Reference Manual, Rev. 2 16-8 Freescale Semiconductor...
Page 775: Rapidio Interface Activation
Non-boot operation 16.1.6.1 Initialization for Booting the MSC8158E DSP When the RapidIO interface is use to boot the MSC8158E, the serial RapidIO master device waits for the boot program to complete the default initialization and then initializes the interface by loading code and data into the device memory. For details, see Section 6.2.4, Serial RapidIO Interconnect, on page 6-21.
Page 776: Initialize Link
Set SERDES LmGCR0BnGCRm0 [RRST]=1 for each bank n and lane m in step 3 Read SERDES LmGCR0BnGCRm0 for each bank n and lane m in step 3 ≥ Wait 300 ns. Write 1s to clear all bits in SRIO PnSLCSR Set SRIO PnCCSR[PD]=0. MSC8158E Reference Manual, Rev. 2 16-10 Freescale Semiconductor...
Page 777: Software Retraining
State Machine per port to distinguish between a x2 port (transmitting striped data) and a x1 port (transmitting identical data on lanes 0 and 1). The Freescale RapidIO controller may fail to MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-11...
Page 778: Rapidio Interface Basics
0001 Maintenance write MAINT read response 0010 0000 Done maintenance read response 0111 Error response MAINT write response 0011 0000 Done maintenance write response 0111 Error response MAINT port-write 0100 Maintenance port-write MSC8158E Reference Manual, Rev. 2 16-12 Freescale Semiconductor...
Page 779 Table 16-2. RapidIO I/O Transactions (Continued) IO Transaction FTYPE TTYPE Status Description RESPONSE without data 1101 0000 0000 I/O done response 0111 I/O error response RESPONSE with data 1000 0000 I/O done response with data MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-13...
Page 780: Message Passing
Data Streaming Header Type FTYPE Start Description START 1001 Start segment packet. SINGLE 1001 Single segment packet. CONTINUATION 1001 Continuation segment packet. 1001 End segment packet. FLOW CONTROL 1001 Flow Control packet. MSC8158E Reference Manual, Rev. 2 16-14 Freescale Semiconductor...
Page 781: Rapidio Gsm Transactions
RapidIO endpoint limits configuration read and write requests to 32-bit data accesses. The large transport field packet format extends the destination and source IDs to 16-bits each. The MSC8158E supports small and large transport fields (large at default), so, for large transport, the destination and source IDs are 16-bits wide according to the direction of the transaction.RapidIO Control Symbol Summary...
Page 782 DATA crf prio ftype dest rsv(2), length hword 0 -> hword n STREAMING xtype(3), (Flow Control) xh(1)=1, rsv(2) 1. src TID[3] of [0:7] bus must be set to ‘1’ for doorbell accesses. MSC8158E Reference Manual, Rev. 2 16-16 Freescale Semiconductor...
Page 783: Rapidio Control Symbol Summary
00000 Expecting ackID 0 00001 Expecting ackID 1 00010 Expecting ackID 2 00011 Expecting ackID 3 00100 Expecting ackID 4 00101 Expecting ackID 5 00110 Expecting ackID 6 00111 Expecting ackID 7 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-17...
Page 784: Accessing Configuration Registers Via Rapidio Packets
16.2.7.1 Inbound Maintenance Accesses There are two recommended methods by which RapidIO transactions can target RapidIO configuration register space in local memory. MSC8158E Reference Manual, Rev. 2 16-18 Freescale Semiconductor...
Page 785: Guidelines
Please see Section 16.1.2, eMSG Unit, on page 16-5 for details on the message passing architecture. There are both inbound (Rx) and outbound (Tx) interfaces with the message unit, in addition to the Rx and Tx interfaces with the system and link. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-19...
Page 786: Inbound (Rx)
The RapidIO controller contains buffers for Tx message unit packets. The buffers are separated into two categories... Tx message unit request packets Tx message unit response / flow control packets Note: Figure 16-5 shows the buffers for Tx message unit packets within the RapidIO controller. MSC8158E Reference Manual, Rev. 2 16-20 Freescale Semiconductor...
Page 787: Tx Message Unit Request Packets
Section 16.4.1.53, Port n Message Request Tx Buffer Allocation Configuration Register 0 (PnMReqTxBACR0), on page 16-232 Section 16.4.1.54, Port n Message Request Tx Buffer Allocation Configuration Register 1 (PnMReqTxBACR1), on page 16-233 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-21...
Page 788: Tx Message Unit Response/Flow Control Packets
There are only 16 buffers that hold message unit response and flow control packets. The total value of the fields within the register mentioned above, must not exceed 16 (undefined behavior will result). MSC8158E Reference Manual, Rev. 2 16-22 Freescale Semiconductor...
Page 789: Arbitration
Strict priority arbitration is used to select the winner. Tx message unit request packets of arbitration group 0 are the highest priority, and Tx message unit request packets of arbitration group 7 are the lowest. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-23...
Page 790: Arbitration Point 1
For both inbound and outbound translation, the smallest window size is 4 K and the largest window size is 16 G for inbound translation and 64 G for outbound translation. MSC8158E Reference Manual, Rev. 2 16-24 Freescale Semiconductor...
Page 791: Rapidio Outbound Atmu
The RapidIO endpoint implementation allows up to a 34-bit (0–33) RapidIO address and a 36-bit (0–35) internal interconnection address. The MSC8158E is confined to 32-bit internal addresses, therefore the top 4 bits (0–3) of the Inbound translation address and the outbound base address should be set to all 0;...
Page 792 = 0x00000101 1 Kbyte x = 1 1 Kbyte 4 Kbyte window with 2 segments of 2 subsegments target deviceID = 0x00001000 1 Kbyte target deviceID = 0x00001001 Figure 16-8. Multi-Targeting Example MSC8158E Reference Manual, Rev. 2 16-26 Freescale Semiconductor...
Page 793: Outbound Windows
The ATMU window hit definition and RapidIO address translation are as follows: 4K window size (smallest window size) — A window hit is defined as {BEXADD[0–3], BADD[0–19]} matching internal address [0–23] — RapidIO addr[0–30] = {TREXAD[8–9], TRAD[0–19], internal address[24–32]} MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-27...
Page 794 There are two reasons for using a segmented ATMU window: allow a single ATMU window to generate different transactions types; allow a single ATMU window to generate multiple RapidIO target IDs. MSC8158E Reference Manual, Rev. 2 16-28 Freescale Semiconductor...
Page 795 [15–10] = PnROWAR0 PnROWTAR0 PnROWTEAR0 {TREXAD] [LTGTID], [9–8] = PnROWTAR0 [LTGTID], [7–0] = PnROWTAR0 [TREXAD] [7–0] = [15–10] = PnROWS1R1 PnROWS1R1 PnROWTEAR0 [SGTGTDID] [LTGTID], [9–8] = PnROWTAR0 [LTGTID], [7–0] = PnROWS1R1 [SGTGTDID] MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-29...
Page 796 [LTGTID], [7–0] = PnROWS2R1 [SGTGTDID] [7–0] = [15–10] = PnROWS3R1 PnROWS3R1 PnROWTEAR0 [SGTGTDID] [LTGTID], [9:8] = PnROWTAR0 [LTGTID], [7–0] = PnROWS3R1 [SGTGTDID] Not supported Not supported Not supported Not supported Not supported MSC8158E Reference Manual, Rev. 2 16-30 Freescale Semiconductor...
Page 797 [9–8] = PnROWTAR0 [LTGTID], [7–1] = PnROWS1R1 [SGTGTDID], 0 = 0b0 [7–1] = [15–10] = PnROWS1R1 PnROWTEAR0 [SGTGTDID], [LTGTID], 0 = 0b1 [9–8] = PnROWTAR0 [LTGTID], [7–1] = PnROWS1R1 [SGTGTDID], 0 = 0b1 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-31...
Page 798 [9–8] = PnROWTAR0 [LTGTID], [7–2] = PnROWTAR0 [TREXAD], [1–0] = 0b10 [7–2] = [15–10] = PnROWTAR0 PnROWTEAR0 [TREXAD], [LTGTID], [1–0] = 0b11 [9–8] = PnROWTAR0 [LTGTID], [7–2] = PnROWTAR0 [TREXAD], [1–0] = 0b11 MSC8158E Reference Manual, Rev. 2 16-32 Freescale Semiconductor...
Page 799 [9–8] = PnROWTAR0 [LTGTID], [7–2] = PnROWS1R1 [SGTGTDID], 0 = 0b10 [7–2] = [15–10] = PnROWS1R1 PnROWTEAR0 [SGTGTDID], [LTGTID], 0 = 0b11 [9–8] = PnROWTAR0 [LTGTID], [7–2] = PnROWS1R1 [SGTGTDID], 0 = 0b11 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-33...
Page 800 [9–8] = PnROWTAR0 [LTGTID], [7–3] = PnROWTAR0 [TREXAD], 0 = 0b010 [7–3] = [15–10] = PnROWTAR0 PnROWTEAR0 [TREXAD], [LTGTID], 0 = 0b011 [9–8] = PnROWTAR0 [LTGTID], [7–3] = PnROWTAR0 [TREXAD], 0 = 0b011 MSC8158E Reference Manual, Rev. 2 16-34 Freescale Semiconductor...
Page 801 [9–8] = PnROWTAR0 [LTGTID], [7–3] = PnROWTAR0 [TREXAD], 0 = 0b110 [7–3] = [15–10] = PnROWTAR0 PnROWTEAR0 [TREXAD], [LTGTID], 0 = 0b111 [9–8] = PnROWTAR0 [LTGTID], [7–3] = PnROWTAR0 [TREXAD], 0 = 0b111 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-35...
Page 802 [9–8] = PnROWTAR0 [LTGTID], [7–3] = PnROWS1R1 [SGTGTDID], 0 = 0b010 [7–3] = [15–10] = PnROWS1R1 PnROWTEAR0 [SGTGTDID], [LTGTID], 0 = 0b011 [9–8] = PnROWTAR0 [LTGTID], [7–3] = PnROWS1R1 [SGTGTDID], 0 = 0b011 MSC8158E Reference Manual, Rev. 2 16-36 Freescale Semiconductor...
Page 803 [9–8] = PnROWTAR0 [LTGTID], [7–3] = PnROWS1R1 [SGTGTDID], 0 = 0b110 [7–3] = [15–10] = PnROWS1R1 PnROWTEAR0 [SGTGTDID], [LTGTID], 0 = 0b111 [9–8] = PnROWTAR0 [LTGTID], [7–3] = PnROWS1R1 [SGTGTDID], 0 = 0b111 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-37...
Page 804 [9–8] = PnROWTAR0 [LTGTID], [7–1] = PnROWS1R1 [SGTGTDID], 0 = 0b0 [7–1] = [15–10] = PnROWS1R1 PnROWTEAR0 [SGTGTDID], [LTGTID], 0 = 0b1 [9–8] = PnROWTAR0 [LTGTID], [7–1] = PnROWS1R1 [SGTGTDID], 0 = 0b1 MSC8158E Reference Manual, Rev. 2 16-38 Freescale Semiconductor...
Page 805 [9–8] = PnROWTAR0 [LTGTID], [7–1] = PnROWS3R1 [SGTGTDID], 0 = 0b0 [7–1] = [15–10] = PnROWS3R1 PnROWTEAR0 [SGTGTDID], [LTGTID], 0 = 0b1 [9–8] = PnROWTAR0 [LTGTID], [7–1] = PnROWS3R1 [SGTGTDID], 0 = 0b1 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-39...
Page 806 [9–8] = PnROWTAR0 [LTGTID], [7–2] = PnROWTAR0 [TREXAD], [1–0] = 0b10 [7–2] = [15–10] = PnROWTAR0 PnROWTEAR0 [TREXAD], [LTGTID], [1–0] = 0b11 [9–8] = PnROWTAR0 [LTGTID], [7–2] = PnROWTAR0 [TREXAD], [1–0] = 0b11 MSC8158E Reference Manual, Rev. 2 16-40 Freescale Semiconductor...
Page 807 [9–8] = PnROWTAR0 [LTGTID], [7–2] = PnROWS1R1 [SGTGTDID], 0 = 0b10 [7–2] = [15–10] = PnROWS1R1 PnROWTEAR0 [SGTGTDID], [LTGTID], 0 = 0b11 [9–8] = PnROWTAR0 [LTGTID], [7–2] = PnROWS1R1 [SGTGTDID], 0 = 0b11 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-41...
Page 808 [9–8] = PnROWTAR0 [LTGTID], [7–2] = PnROWS2R1 [SGTGTDID], 0 = 0b10 [7–2] = [15–10] = PnROWS2R1 PnROWTEAR0 [SGTGTDID], [LTGTID], 0 = 0b11 [9–8] = PnROWTAR0 [LTGTID], [7–2] = PnROWS2R1 [SGTGTDID], 0 = 0b11 MSC8158E Reference Manual, Rev. 2 16-42 Freescale Semiconductor...
Page 809 [9–8] = PnROWTAR0 [LTGTID], [7–2] = PnROWS3R1 [SGTGTDID], 0 = 0b10 [7–2] = [15–10] = PnROWS3R1 PnROWTEAR0 [SGTGTDID], [LTGTID], 0 = 0b11 [9–8] = PnROWTAR0 [LTGTID], [7–2] = PnROWS3R1 [SGTGTDID], 0 = 0b11 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-43...
Page 810 [9–8] = PnROWTAR0 [LTGTID], [7–3] = PnROWTAR0 [TREXAD], 0 = 0b010 [7–3] = [15–10] = PnROWTAR0 PnROWTEAR0 [TREXAD], [LTGTID], 0 = 0b011 [9–8] = PnROWTAR0 [LTGTID], [7–3] = PnROWTAR0 [TREXAD], 0 = 0b011 MSC8158E Reference Manual, Rev. 2 16-44 Freescale Semiconductor...
Page 811 [9–8] = PnROWTAR0 [LTGTID], [7–3] = PnROWTAR0 [TREXAD], 0 = 0b110 [7–3] = [15–10] = PnROWTAR0 PnROWTEAR0 [TREXAD], [LTGTID], 0 = 0b111 [9–8] = PnROWTAR0 [LTGTID], [7–3] = PnROWTAR0 [TREXAD], 0 = 0b111 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-45...
Page 812 [9–8] = PnROWTAR0 [LTGTID], [7–3] = PnROWS1R1 [SGTGTDID], 0 = 0b010 [7–3] = [15–10] = PnROWS1R1 PnROWTEAR0 [SGTGTDID], [LTGTID], 0 = 0b011 [9–8] = PnROWTAR0 [LTGTID], [7–3] = PnROWS1R1 [SGTGTDID], 0 = 0b011 MSC8158E Reference Manual, Rev. 2 16-46 Freescale Semiconductor...
Page 813 [9–8] = PnROWTAR0 [LTGTID], [7–3] = PnROWS1R1 [SGTGTDID], 0 = 0b110 [7–3] = [15–10] = PnROWS1R1 PnROWTEAR0 [SGTGTDID], [LTGTID], 0 = 0b111 [9–8] = PnROWTAR0 [LTGTID], [7–3] = PnROWS1R1 [SGTGTDID], 0 = 0b111 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-47...
Page 814 [9–8] = PnROWTAR0 [LTGTID], [7–3] = PnROWS2R1 [SGTGTDID], 0 = 0b010 [7–3] = [15–10] = PnROWS2R1 PnROWTEAR0 [SGTGTDID], [LTGTID], 0 = 0b011 [9–8] = PnROWTAR0 [LTGTID], [7–3] = PnROWS2R1 [SGTGTDID], 0 = 0b011 MSC8158E Reference Manual, Rev. 2 16-48 Freescale Semiconductor...
Page 815 [9–8] = PnROWTAR0 [LTGTID], [7–3] = PnROWS2R1 [SGTGTDID], 0 = 0b110 [7–3] = [15–10] = PnROWS2R1 PnROWTEAR0 [SGTGTDID], [LTGTID], 0 = 0b111 [9–8] = PnROWTAR0 [LTGTID], [7–3] = PnROWS2R1 [SGTGTDID], 0 = 0b111 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-49...
Page 816 [9–8] = PnROWTAR0 [LTGTID], [7–3] = PnROWS3R1 [SGTGTDID], 0 = 0b010 [7–3] = [15–10] = PnROWS3R1 PnROWTEAR0 [SGTGTDID], [LTGTID], 0 = 0b011 [9–8] = PnROWTAR0 [LTGTID], [7–3] = PnROWS3R1 [SGTGTDID], 0 = 0b011 MSC8158E Reference Manual, Rev. 2 16-50 Freescale Semiconductor...
Page 817 The use of segmented windows impacts only the RapidIO transaction type or the destination ID. The internal address translation is a function of the Port n Outbound Window Translation Address Register and the translation window size. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-51...
Page 818: Valid Hits To Multiple Atmu Windows
Window #1 Window #2 Transaction start address Transaction end address Figure 16-10. Valid Hit that Extends Beyond the Window Boundary MSC8158E Reference Manual, Rev. 2 16-52 Freescale Semiconductor...
Page 819: Window Boundary Crossing Errors
The outbound request is discarded. Window #3 Window #2 Transaction start address Transaction end address Figure 16-12. Boundary Crossing Error Due to Extension Beyond the Higher Priority Window Boundary MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-53...
Page 820: Rapidio Inbound Atmu
An external processor should not assume that a write to any ATMU register is complete until a response is received. Table 16-9 describes the registers for configuring the window parameters, along with the number of the page where each register is described in detail. MSC8158E Reference Manual, Rev. 2 16-54 Freescale Semiconductor...
Page 821 {TREXAD[0–3], TRAD[0–18], RapidIO Internal interconnection addr[0–32] = address[21–30]}. 16 KB window size: — A window hit is defined as {BEXADD[0–1], BADD[0–17]} matching RapidIO address [0–19]. — {TREXAD[0–3], TRAD[0–17], RapidIO Internal interconnection addr[0–32] = address[20–30]}. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-55...
Page 822: Hits To Multiple Atmu Windows
If a request hits (base address match) an ATMU window (1–4, default) and the transaction end address extends into another ATMU window with a higher priority, an ATMU crossed boundary error is generated and logged. MSC8158E Reference Manual, Rev. 2 16-56 Freescale Semiconductor...
Page 823: Generating Link-Request/Reset-Device
Disable the input port receiver (IPD bit = 1 in the Port n Control Command and Status Register). This will allow the four consecutive link-request/reset-device control symbols to be generated with only idle control symbols between the link-request/reset-device control symbols. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-57...
Page 824: Outbound Drain Mode
Failed Threshold does not cause any packet acknowledgements to be dropped. If a discarded packet in the outgoing data stream requires a logical response, a packet response time-out will occur if the packet response timer is enabled (PRTOCCSR is non 0). MSC8158E Reference Manual, Rev. 2 16-58 Freescale Semiconductor...
Page 825: Input Port Disable Mode
MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-59...
Page 826: Errors And Error Handling
1–2 Error Enable CSR) is captured in the Port 1–2 Error Capture CSRs. No interrupt is generated or actions required for a recoverable error. Recoverable errors are detected only in the physical layer. MSC8158E Reference Manual, Rev. 2 16-60 Freescale Semiconductor...
Page 827: Physical Layer Rapidio Errors
PnEDCSR bit is set when the error is detected (see page 16-210). Table 16-11 shows the RapidIO endpoint behavior after certain preset limits are exceeded (degraded threshold, failed threshold, retry threshold). Table 16-12 shows the threshold response. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-61...
Page 828 CRC Received packet which Enter input error 7/31: General Received exceeds the maximum allowed stopped. error packet size by the RapidIO spec. exceeds 276 Bytes MSC8158E Reference Manual, Rev. 2 16-62 Freescale Semiconductor...
Page 829 [TV] > 0 stopped. time-out interval. enables detect. A Link response is not PLTOCCSR (re-) Enter output received within the specified [TV] > 0 error stopped. time-out interval enables detect. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-63...
Page 830: Logical Layer Rapidio Errors
Otherwise, no error response is sent. For multiple errors, a discard of a packet has a higher priority than an error response. For misaligned transactions, the error management extension registers are updated with each child. MSC8158E Reference Manual, Rev. 2 16-64 Freescale Semiconductor...
Page 831 16 bytes for large transport packet. is set Large transport packet has 14 valid bytes and two bytes of padding of 0s. Padding of 0s is not checked. PayloadSize Not Applicable. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-65...
Page 832 Reserved transaction type for this ftype LTLEECSR[ITD] packet is is set. dropped. RdSize Yes if LTLEDCSR[ITD] Read/Write request size is not for 4 bytes. LTLEECSR[ITD] is set. SrcTID Not checked for error. MSC8158E Reference Manual, Rev. 2 16-66 Freescale Semiconductor...
Page 833 • LTLDIDCCSR[DID] gets packet bits 24–31. • LTLDIDCCSR[SIDMSB] gets bits 32–39. • LTLDIDCCSR[SID] gets packet bits 40–47. • LTLCCCSR[FT] gets packet bits 12–15. • LTLCCCSR[TT] gets packet bits 48–51. • LTLCCCSR[MI] gets 0s. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-67...
Page 834 Not Checked for error. Address:WdPtr:Xambs Yes if LTLEECSR[ITD] is LTLEDCSR[ITD] Yes for NWRITE_R address matches set. NWRITE_R. LCSBA1CSR with a request that is not a 32-bit read. Performed only for NWRITE_R packet. MSC8158E Reference Manual, Rev. 2 16-68 Freescale Semiconductor...
Page 835 • LTLDIDCCSR[DID] gets packet bits 24–31. • LTLDIDCCSR[SIDMSB] gets packet bits 32–39. • LTLDIDCCSR[SID] gets packet bits 40–47. • LTLCCCSR[FT] gets packet bits 12–15. • LTLCCCSR[TT] gets packet bits 48–51. • LTLCCCSR[MI] gets 0s. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-69...
Page 836 16.2.9.4.2, Window Boundary Crossing Errors, on page 16-56. Address:WdPtr:Xambs Yes if LTLEECSR[ITD] is set. LTLEDCSR[ITD] RapidIO Request hits a protected ATMU packet is window or the local configuration dropped. space window. MSC8158E Reference Manual, Rev. 2 16-70 Freescale Semiconductor...
Page 837 • LTLDIDCCSR[DID] gets packet bits 24–31. • LTLDIDCCSR[SIDMSB] gets packet bits 32–39. • LTLDIDCCSR[SID] gets packet bits 40–47. • LTLCCCSR[FT] gets packet bits 12–15. • LTLCCCSR[TT] gets packet bits 48–51. • LTLCCCSR[MI] gets 0s. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-71...
Page 838 12 bytes for small transport packet or is less than 16 bytes for large transport packet. Padding of 0s for small or large transport packet is not verified. MSC8158E Reference Manual, Rev. 2 16-72 Freescale Semiconductor...
Page 839 • LTLDIDCCSR[DID] gets packet bits 24–31. • LTLDIDCCSR[SIDMSB] gets bits 32–39. • LTLDIDCCSR[SID] gets bits 40–47. • LTLCCCSR[FT] gets packet bits 12–15. • LTLCCCSR[TT] gets packet bits 48–51. • LTLCCCSR[MI] gets 0s. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-73...
Page 840 [ITTE] is set dropped DeviceID is disabled or and ignored DestId does not match either Alternate DeviceID or DeviceId if Alternate DeviceID is enabled. Error valid when (passthrough or accept_all) is false MSC8158E Reference Manual, Rev. 2 16-74 Freescale Semiconductor...
Page 841 IO Error Response [IER] is set generated requestor. TargetTID Yes if LTLEDCSR Same as first entry RapidIO No outstanding transaction LTLEECSR [UR] packet is for this TargetTID [UR] is set dropped ignored. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-75...
Page 842 The misaligned GSM request has had one to four (cumulative for the corresponding child requests) more than configured number of retries. MSC8158E Reference Manual, Rev. 2 16-76 Freescale Semiconductor...
Page 843 LTLEDCSR Same as first entry RapidIO Not UR LTLEECSR [ITD] packet is Done response, Retry [ITD] is set dropped response, or Error response is after Done_Intervention ignored. response or Data_only is received. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-77...
Page 844 Reserved ssize field. Yes if LTLEECSR[MFE] LTLEDCSR[MFE] Yes if priority If priority is is set. is not 3. Else 3, packet is packet is dropped. dropped. MSC8158E Reference Manual, Rev. 2 16-78 Freescale Semiconductor...
Page 845 • LTLDIDCCSR[DID] gets packet bits 24–31. • LTLDIDCCSR[SIDMSB] gets packet bits 32–39. • LTLDIDCCSR[SID] gets packet bits 40–47. • LTLCCCSR[FT] gets packet bits 12–15. • LTLCCCSR[TT] gets packet bits 48–51. • LTLCCCSR[MI] gets packet bits 56–63. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-79...
Page 846 • LTLCCCSR[FT] gets packet bits 12–15. • LTLCCCSR[TT] gets packet bits 48–51. • LTLCCCSR[MI] gets packet bits 56–63. For all entries except the first, the capture registers are loaded from the response RapidIO packet. MSC8158E Reference Manual, Rev. 2 16-80 Freescale Semiconductor...
Page 847 • LTLDIDCCSR[DID] gets packet bits 24–31. • LTLDIDCCSR[SIDMSB] gets packet bits 32–39. • LTLDIDCCSR[SID] gets packet bits 40–47. • LTLCCCSR[FT] gets packet bits 12–15. • LTLCCCSR[TT] gets packet bits 48–51. • LTLCCCSR[MI] gets 0s. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-81...
Page 848 DMA response. Header size is not 8 bytes for small is set. dropped and transport packet or not 12 bytes for large transport ignored. packet. Two byte padding of 0s in a large transport field packet is not checked. MSC8158E Reference Manual, Rev. 2 16-82 Freescale Semiconductor...
Page 849 • LTLDIDCCSR[DID] gets packet bits 24–31. • LTLDIDCCSR[SIDMSB] gets packet bits 32–39. • LTLDIDCCSR[SID] gets packet bits 40–47. • LTLCCCSR[FT] gets packet bits 12–15. • LTLCCCSR[TT] gets packet bits 48–51. • LTLCCCSR[MI] gets 0s. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-83...
Page 850 24, 32, 40, 48, 56, or 64 bytes). Payload size is greater than the value defined by wr_size. Payload size is not 64-bit aligned when the wr_size is not 4 bytes. MSC8158E Reference Manual, Rev. 2 16-84 Freescale Semiconductor...
Page 851 • LTLDIDCCSR[DID] gets packet bits 24–31. • LTLDIDCCSR[SIDMSB] gets packet bits 32–39. • LTLDIDCCSR[SID] gets packet bits 40–47. • LTLCCCSR[FT] gets packet bits 12–15. • LTLCCCSR[TT] gets packet bits 48–51. • LTLCCCSR[MI] gets 0s. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-85...
Page 852 DeviceID if Alternate [ITTE] is dropped DeviceID is disabled or and ignored DestId does not match either Alternate DeviceID or DeviceId if Alternate DeviceID is enabled. Error valid when (passthrough or accept_all) is false MSC8158E Reference Manual, Rev. 2 16-86 Freescale Semiconductor...
Page 853 • LTLDIDCCSR[DID] gets packet bits 24–31. • LTLDIDCCSR[SIDMSB] gets packet bits 32–39. • LTLDIDCCSR[SID] gets packet bits 40–47. • LTLCCCSR[FT] gets packet bits 12–15. • LTLCCCSR[TT] gets packet bits 48–51. • LTLCCCSR[MI] gets 0s. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-87...
Page 854 • LTLDIDCCSR[DID] gets packet bits 24–31. • LTLDIDCCSR[SIDMSB] gets packet bits 32–39. • LTLDIDCCSR[SID] gets packet bits 40–47. • LTLCCCSR[FT] gets packet bits 12–15. • LTLCCCSR[TT] gets packet bits 48–51. • LTLCCCSR[MI] gets 0s. MSC8158E Reference Manual, Rev. 2 16-88 Freescale Semiconductor...
Page 855 • LTLDIDCCSR[SIDMSB] gets packet bits 32–39. • LTLDIDCCSR[SID] gets packet bits 40–47. • LTLCCCSR[FT] gets packet bits 12–15. • LTLCCCSR[TT] gets packet bits 48–51. • LTLCCCSR[MI] gets 0s. • LTLCCCSR[MI] gets 0s. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-89...
Page 856: Rapidio Enhanced Message Unit (Emsg) Communication
PDUs can also be queued in the consumer’s memory while software processes them sequentially. The depths of the queues at the producer and consumer are configurable by software. Basic stream management flow control is also supported in Type9. MSC8158E Reference Manual, Rev. 2 16-90 Freescale Semiconductor...
Page 857 Message Queues 0–7 Outbound Message Queues Outbound Block 0 Segmentation Message Queues 0–7 Unit 0 RapidIO Outbound Traffic Outbound Block 7 Message Segmentation Queues 0–7 Unit 5 Figure 16-14. eMSG Block Diagram MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-91...
Page 858: Modes Of Operation
CoS: 2 Rule 2 mbox: 2 Type11 Message Queue 3 [Block 3] mbox: 2-3 letter: 0-3 HW Context Matching Rule N Type10 Message Queue 4 [Block 7] Figure 16-15. Inbound Traffic Classification MSC8158E Reference Manual, Rev. 2 16-92 Freescale Semiconductor...
Page 859: Command Descriptor Format
Requirements. 63–61 FORMAT Format (bits 60–32) 000 Single buffer frame, 9-bit offset, 20-bit length 100 Scatter/Gather table, 9-bit offset, 20-bit length. Valid for RapidIO Type9 only. All other values reserved or unused. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-93...
Page 860 Message format error Duplicate, out of range, inconsistent segment number or illegal RapidIO priority or segment size received. Inbound Type10/11 only Size mismatch error Inbound length or byte count mismatch. Inbound Type9 only MSC8158E Reference Manual, Rev. 2 16-94 Freescale Semiconductor...
Page 861: Outbound Command Descriptor Format
Format (bits 60–32) 000 Single buffer frame, 9-bit offset, 20-bit length 100 Scatter/Gather table, 9-bit offset, 20-bit length. Valid for RapidIO Type5, Type6 and Type9 only All other values reserved or unused. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-95...
Page 862: Outbound Completion Queues
(BR = 1) is performed successfully, the effective length field indicates zero. It is the responsibility of the outbound completion queue consumer to deallocate buffers as needed when the command descriptor length field is non-zero. If transaction or descriptor error status has MSC8158E Reference Manual, Rev. 2 16-96 Freescale Semiconductor...
Page 863: Scatter/Gather Tables
Table 16-29 describes the scatter/gather table entry fields. Table 16-29. Scatter/Gather Table Entry Field Descriptions Bits Name Description 127–96 — Reserved 95–64 ADDRESS 32-bit byte address to data buffer or discontinued scatter/gather table entry, depending on E bit setting. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-97...
Page 864 Current and subsequent S/G table pointer(s) are not released If software requires all pointers to be released, the final bit must be set for the last data entry as determined by the length field. MSC8158E Reference Manual, Rev. 2 16-98 Freescale Semiconductor...
Page 865: Type5 Nwrite Unit Functional Description
The message descriptor points to a data buffer containing the descriptor and NWrite data payload. Figure 16-20 shows the format of an outbound NWrite descriptor. Reserved fields must be cleared. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-99...
Page 866 — Reserved Word 1—Address 223–192 ADDRESS Byte aligned address of write transaction This address represents the RapidIO Type5 logical address without any address translation. Word 2—Reserved 191–160 — Reserved Word 3—Destination Port MSC8158E Reference Manual, Rev. 2 16-100 Freescale Semiconductor...
Page 867 All other values are reserved. Figure 16-21 shows the format for Type5 scatter/gather tables usage. The first entry of the scatter/gather table holds the 32-byte descriptor. The data offset is specified through the MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-101...
Page 868: Type5 Outbound Nwrite Operation
NWrite descriptor as appropriate and enqueue the command descriptor. The message unit dequeues the command descriptor, determines the type, and proceeds to read the NWrite descriptor. MSC8158E Reference Manual, Rev. 2 16-102 Freescale Semiconductor...
Page 869: Nwrite Initialization
BR than message enqueued setting descriptor payload byte count NWrite Request Invalid FTYPE Descriptor error in No buffers released command descriptor regardless of BR enqueued setting MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-103...
Page 870: Descriptor Error
— After the segmentation operation completes, the internal transaction error bit in the TE field in the command descriptor is set. — The message descriptor is enqueued onto the completion message queue if the message descriptor error status bit (ES) is set. MSC8158E Reference Manual, Rev. 2 16-104 Freescale Semiconductor...
Page 871: Type6 Streaming Write Functional Description
All other values are reserved. Buffer release enable 0 No hardware buffer releases performed. 1 Hardware buffer releases performed. If TE/DE error status was reported, not all buffers may have been released successfully. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-105...
Page 872 121–120 — Reserved 119–116 TINT Target interface 0000 RapidIO Port 1 0001 RapidIO Port 2 All other values reserved. 115–96 — Reserved Word 5—Reserved 95–64 — Reserved Word 6—Reserved 63–32 — Reserved MSC8158E Reference Manual, Rev. 2 16-106 Freescale Semiconductor...
Page 873: Type6 Outbound Swrite Operation
Concurrent processing may also occur between any number of message queues as long as the outbound ordering rules apply; see Section 16.3.14.2, Outbound Ordering Rules. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-107...
Page 874: Work Scheduling
Set the message descriptor completion (CS) or error (ES) status bit. Software should observe the status field of the command descriptor after it has been written to the completion queue to determine success. MSC8158E Reference Manual, Rev. 2 16-108 Freescale Semiconductor...
Page 875: Descriptor Error
— The message descriptor is enqueued onto the completion message queue if the message descriptor error status (ES) bit is set. 16.3.6.2.4.2 Transaction Errors When an transaction error occurs during a local memory data read by the message unit the following occurs. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-109...
Page 876: Type8 Port-Write Functional Description
144 143 Word 3 EDID — 125 124 116 115 Word 4 — FLOWLVL — TINT — Word 5 — Word 6 — Word 7 — Figure 16-24. Type8 Outbound Port-Write Descriptor MSC8158E Reference Manual, Rev. 2 16-110 Freescale Semiconductor...
Page 877 110 Next highest priority transaction request flow 111 Highest priority transaction request flow 121–120 — Reserved 119–116 TINT Target interface. 0000 RapidIO Port 1 0001 RapidIO Port 2 All other values reserved. 115–96 — Reserved MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-111...
Page 878: Type8 Inbound Port-Write Descriptor Format
Type8 port-write data payload. The starting location of the port-write data payload is calculated by adding the data offset to the command descriptor address. The data offset is programmable through IBmT8CnDOR. MSC8158E Reference Manual, Rev. 2 16-112 Freescale Semiconductor...
Page 879: Type8 Outbound Port-Write Operation
— For all other fields, see Section 16.3.7.1, Type8 Outbound Port-Write Descriptor Format. Add the Portwrite descriptor to a command descriptor and set FTYPE=0b1000 to indicate port-write type. Enqueue the command descriptor onto the message queue. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-113...
Page 880: Port-Write Initialization
Only 4, 8, 16, command descriptor regardless of BR 32 and 64 bytes enqueued. setting. allowed. Port-Write Invalid FTYPE. Descriptor error in No buffers released Request command descriptor regardless of BR enqueued. setting. MSC8158E Reference Manual, Rev. 2 16-114 Freescale Semiconductor...
Page 881: Descriptor Error
— The message descriptor is enqueued onto the completion message queue if the message descriptor error status (ES) bit is set. Buffer release (BR = 1) — No further buffers are released once a TE error is detected. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-115...
Page 882: Type8 Inbound Port-Write Operation
Memory transaction Message unit error if Transaction error in Possibly Port-write is invalid. error. MUIER[ITEIE] set. command descriptor enqueued and message unit error detect register MUEDR[ITE]. Address captured in MUECAR. MSC8158E Reference Manual, Rev. 2 16-116 Freescale Semiconductor...
Page 883: Buffer Size Errors
16.3.8.1 Type9 Segmentation Descriptor Format The Type9 outbound descriptor contains information for the message unit to send a PDU. The message unit receives the outbound packet descriptor by dequeueing a command descriptor from MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-117...
Page 884 0 Status message queue is not updated when PDU aborted due to error. 1 Status message queue is updated when PDU aborted due to error. 247–224 — Reserved Word 1—Reserved 223–192 — Reserved MSC8158E Reference Manual, Rev. 2 16-118 Freescale Semiconductor...
Page 885 All other values reserved. Figure 16-28 shows the format for Type9 scatter/gather tables usage. The first entry of the scatter/gather table holds the 32-byte descriptor. The data offset is specified through the MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-119...
Page 886: Type9 Reassembly Descriptor Format
Set register bit MUMR[OSID] = 1 to disable segmentation interleaving on a destination ID basis. However, this affect all supported types and may affect performance. Figure 16-29 shows the format of an inbound PDU descriptor. Reserved fields must be cleared. MSC8158E Reference Manual, Rev. 2 16-120 Freescale Semiconductor...
Page 887 Source ID. Contains the source ID field of the transaction (Device ID of the source). 143–128 STREAMID Value from the “streamID” field in the DATA STREAMING packets. In case of CSE/ESE, the stream ID is invalid. Word 4—Source Attributes 127–125 — Reserved MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-121...
Page 888 0x0FFFF64 Kbytes-1 0x1000064 Kbytes Figure 16-30 shows the format for Type9 scatter/gather tables usage. The first entry of the scatter/gather table also holds the 32-byte descriptor. The first data offset is programmable MSC8158E Reference Manual, Rev. 2 16-122 Freescale Semiconductor...
Page 889: Type9 Outbound Segmentation Operation
A producer may add new PDUs to any message queue owned by the message unit. The producer needs to allocate buffer space for the PDU descriptor, scatter/gather table(s) and data as appropriate and enqueue the command descriptor. The message unit dequeues the command MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-123...
Page 890: Segmentation Initialization
Set the message descriptor completion (CS) or error (ES) status bit. Software should observe the status field of the command descriptor after it has been written to the completion queue to determine success. MSC8158E Reference Manual, Rev. 2 16-124 Freescale Semiconductor...
Page 891: Descriptor Error
— The message descriptor is enqueued onto the completion message queue if the message descriptor error status (ES) bit is set. 16.3.8.3.4.2 Transaction Errors When an transaction error occurs during a local memory data read by the message unit the following occurs. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-125...
Page 892: Type9 Reassembly Operation
The message unit reports errors, utilizing the inbound message queue, by setting the status field in the command descriptor before enqueueing the descriptor onto the designated inbound message queue. The consumer should read the status bits before processing the packet to determine the appropriate action. MSC8158E Reference Manual, Rev. 2 16-126 Freescale Semiconductor...
Page 893 PDU is defective. error if in command Buffer may have MUIER[ITE] set. descriptor been lost if enqueued and scatter/gather table Message unit error could not be detect register updated. MUEDR[ITE]. Address captured in MUECAR. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-127...
Page 894: Single/Start Segment Error
When the end segment error is detected by the message unit the following occurs. Segment is discarded. The message unit sets the end segment error bit, ESE in the command descriptor. After the reassembly operation completes, the command descriptor is enqueued onto the message queue. MSC8158E Reference Manual, Rev. 2 16-128 Freescale Semiconductor...
Page 895: Segment Request Timeout Errors
After the reassembly operation completes, the command descriptor is enqueued onto the message queue. 16.3.8.4.4.8 Transaction Errors When an internal transaction error occurs, due to insufficient buffer resources or local memory write error, by the message unit the following occurs. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-129...
Page 896: Flow Control Management
When stream management flow control is enabled, only certain combinations of class-of-service and stream ID rule mask fields are permitted for inbound classification. Specific stream in a specific class for specific destination: <DestID><CoS><StreamID> MSC8158E Reference Manual, Rev. 2 16-130 Freescale Semiconductor...
Page 897: Sending Flow Control Messages
(no other combination supported): <DestID><CoS><StreamID> + <wild cards> + <Mask> The following operands are generated by the message unit: Specific stream (classification rule with no stream wildcard): <DestID><CoS><StreamID> + <wc=000> + <Mask=0x00> MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-131...
Page 898: Type10 Doorbell Functional Description
The message unit receives the outbound doorbell descriptor by dequeueing a command descriptor from the outbound message queue. The command descriptor points to a data buffer containing the descriptor and doorbell data. MSC8158E Reference Manual, Rev. 2 16-132 Freescale Semiconductor...
Page 899 1 Status message queue is updated when doorbell completes normally. Error status 0 Status message queue is not updated when doorbell aborted due to error. 1 Status message queue is updated when doorbell aborted due to error. 247–232 — Reserved MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-133...
Page 900 Target interface 0000 RapidIO Port 1 0001 RapidIO Port 2 All other values reserved. 115–96 — Reserved Word 5—Reserved 95–64 — Reserved Word 6—Reserved 63–32 — Reserved Word 7—Reserved 31–0 — Reserved MSC8158E Reference Manual, Rev. 2 16-134 Freescale Semiconductor...
Page 901: Type10 Inbound Doorbell Descriptor Format
— 125 124 122 121 120 119 116 115 Word 4 — FLOWLVL — SINT — Word 5 EDID — Word 6 — Word 7 — Figure 16-34. Type10 Inbound Doorbell Descriptor MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-135...
Page 902 Most significant byte of a 16-bit destination ID when operating in large transport mode. Reserved when operating in small transport mode. 87–80 Destination ID Contains the destination ID field of the transaction (Device ID of the destination). 79–64 — Reserved Word 6—Reserved 63–32 — Reserved MSC8158E Reference Manual, Rev. 2 16-136 Freescale Semiconductor...
Page 903: Type10 Outbound Doorbell Operation
The message unit dequeues the command descriptor, determines the type, and proceeds to read the doorbell descriptor. A producer should follow the guidelines below to add a new doorbell to a message queue: MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-137...
Page 904: Doorbell Initialization
Multiple errors can be checked at an error checking level. Once an error is detected, no additional error checking beyond the current error level is performed. MSC8158E Reference Manual, Rev. 2 16-138 Freescale Semiconductor...
Page 905: Descriptor Error
— The segmentation process is halted and the descriptor error bit DE in the command descriptor is set. — The message descriptor is enqueued onto the completion message queue if the message descriptor error status (ES) bit is set. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-139...
Page 906: Doorbell Error Response Errors
Command descriptor captured in M ECCDR0–3. Global message unit error detect register M EDR[OTE] set. Completion message Queue — After the doorbell operation completes the internal transaction error bit, TE, in the command descriptor is set. MSC8158E Reference Manual, Rev. 2 16-140 Freescale Semiconductor...
Page 907: Type10 Inbound Doorbell Operation
Message unit did not have a matching classification rule. Message unit has detected a buffer size error. Message unit has detected a transaction error when allocating buffer resources or performing a local memory write. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-141...
Page 908: Error Handling
16.3.9.4.5.1 Buffer Size Errors When a buffer size error is detected by the message unit, the following occurs. Doorbell is discarded and an error response is returned for the segment. MSC8158E Reference Manual, Rev. 2 16-142 Freescale Semiconductor...
Page 909: Transaction Errors
The command descriptor points to a data buffer containing the descriptor and message data. Figure 16-36 shows the format of an outbound message descriptor. Reserved fields must be cleared. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-143...
Page 910 RETRY response is received from the target. 0x00 Disabled 0x01 Message segment retransmitted only 1 time 0x02 Message segment retransmitted up to 2 times 0xFF Message segment retransmitted up to 255 times Word 1—Reserved MSC8158E Reference Manual, Rev. 2 16-144 Freescale Semiconductor...
Page 911 101 Highest priority transaction request flow 110 Reserved 111 Reserved 121–120 — Reserved 119–116 TINT Target interface. 0000 RapidIO Port 1 0000 RapidIO Port 2 All other values reserved. 115–96 — Reserved Word 5—Multicast Group MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-145...
Page 912 Number of segments is determined by the byte count divided by the segment size (256 bytes). Figure 16-37 shows the command descriptor referencing a single buffer directly. The data payload offset is specified using the command descriptor offset field. MSC8158E Reference Manual, Rev. 2 16-146 Freescale Semiconductor...
Page 913: Type11 Inbound Message Descriptor Format
Table 16-46 describes the Type11 inbound message descriptor fields. Table 16-46. Type11 Inbound Message Descriptor Field Descriptions Bits Name Description Word 0—Header 255–252 FTYPE Descriptor type select. 1011 Type11 All other values reserved. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-147...
Page 914 Reserved when operating in small transport mode. 87–80 Destination ID. Contains the destination ID field of the transaction (Device ID of the destination). 79–64 — Reserved Word 6—Reserved 63–32 — Reserved Word 7—Byte Count MSC8158E Reference Manual, Rev. 2 16-148 Freescale Semiconductor...
Page 915: Type11 Outbound Message Operation
Work Scheduling The message unit receives all work from the outbound message queues. A producer or producers enqeueue work onto the outbound message queues owned by the message unit. To maintain any MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-149...
Page 916: Adding Messages To A Message Queue
Table 16-47 indicates the possible error conditions and the outcome when detected. The error checking level indicates the order in which errors are checked. Multiple errors can be checked at MSC8158E Reference Manual, Rev. 2 16-150 Freescale Semiconductor...
Page 917 BR MUEDR[OTE]. Command setting. descriptor captured in MUECCDR0–3. Message Message error Message response error in Message Response response. command descriptor incomplete. enqueued. If MM=1, multicast error also set. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-151...
Page 918: Descriptor Error
— The message descriptor is enqueued onto the completion message queue if the message descriptor error status (ES) bit is set. 16.3.10.3.4.4 Retry Threshold Exceeded Errors When a retry threshold exceeded error is detected for a message segment the following occurs. MSC8158E Reference Manual, Rev. 2 16-152 Freescale Semiconductor...
Page 919: Multicast Errors
Command descriptor captured in M ECCDR0–3. Global message unit error detect register M EDR[OTE] set. Completion message queue — After the message operation completes the internal transaction error bit, TE, in the command descriptor is set. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-153...
Page 920: Type11 Inbound Message Operation
The conditions to generate a logical layer error response are: Message unit did not have a matching classification rule. Message unit has detected a buffer size error. Message unit has detected a message format error. MSC8158E Reference Manual, Rev. 2 16-154 Freescale Semiconductor...
Page 921: Error Handling
Insufficient buffer Buffer size error in Error Message is pool size. command defective. descriptor enqueued. Duplicate Message format Error Message is segment error in command defective. received. descriptor Segment enqueued. counted. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-155...
Page 922: Segment Request Time-Out Errors
The message unit sets the segment request time-out error bit, SRT in the command descriptor. All message segments that have not yet been received are considered complete. The command descriptor is enqueued onto the message queue. MSC8158E Reference Manual, Rev. 2 16-156 Freescale Semiconductor...
Page 923: Buffer Size Errors
The RapidIO Session Management Protocol Specification permits a session manager to establish, manage and remove connections between two end points. Section 16.3.11.1, Classification, describes how a session manager can establish connections with other end-points. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-157...
Page 924: Classification
Type11 data messages. A Type10 doorbell carries a 16-bit info field but no data and is always a single RapidIO packet. When a packet carries a data payload, the maximum size of this payload is 256 bytes. MSC8158E Reference Manual, Rev. 2 16-158 Freescale Semiconductor...
Page 925: Segmentation And Reassembly
Type11 transactions cause hardware to issue a logical retry, with the expectation that resources will become available soon. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-159...
Page 926 Type11 messages are logically retried and Type9 messages are dropped. In all situations, Type9 packets are dropped only if the number of interleaved messages exceeds the allocation budgeted by the system. MSC8158E Reference Manual, Rev. 2 16-160 Freescale Semiconductor...
Page 927 Type9 packet loss, but may cause more frequent link-level retries. Note that these retries can cause brief performance loss for higher priority streams carried by the link. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-161...
Page 928: Examples
— Segments of only 23 messages are accepted at any given moment. — All others are logically retried. — No control at the receive endpoint over which streams are accepted and which are retried is possible. MSC8158E Reference Manual, Rev. 2 16-162 Freescale Semiconductor...
Page 929 — No more than 23 messages are reassembled at one time. — All others messages are dropped. — No control at the receive endpoint over which streams are accepted and which are dropped is possible. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-163...
Page 930 — Memory congestion beyond tolerance eventually results in link-level retries. Example 16-7. Inbound Traffic Types — 15 segment interleaved multi-segment Type11 streams over Flow A — 16 single segment Type9 streams over Flow B MSC8158E Reference Manual, Rev. 2 16-164 Freescale Semiconductor...
Page 931 All segments of Type9 message streams 1–5 always accepted — Tolerant of memory congestion because recommended 8 entries are allocated for congestion management — Memory congestion beyond tolerance eventually results in Type11 logical retries, link-level retries or both. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-165...
Page 932: Address Alignment Requirements
— NWrites with the same Source ID + Destination ID + Flow are transmitted in order, if from the same message queue. Outbound Type6 streaming writes — SWrites with the same Source ID + Destination ID + Flow are transmitted in order, if from the same message queue. MSC8158E Reference Manual, Rev. 2 16-166 Freescale Semiconductor...
Page 933: Outbound Segmentation Interleaving
While this may increase the performance on the transmit side, additional hardware reassembly resources may be needed on the receive side. Outbound segmentation interleaving can be controlled per destination by setting the register bit M MR[OSI]. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-167...
Page 934: Transaction Priorities
IBmMQnCMR[EXIT_WM]. The classification rule could also be disabled to clear the condition, but it is not recommended unless the queue level is also dealt with. MSC8158E Reference Manual, Rev. 2 16-168 Freescale Semiconductor...
Page 935: Interrupts
Initialize the inbound Buffer Pool ID and data offset registers, for all types, used to build the scatter/gather tables and data structures in memory for inbound transactions. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-169...
Page 936 — Set the message queue target register IBmT11CnMQR. — Set the inbound unit type, IBmT11CnMR[FTYPE]=4b1011. — Enable the classification rule, IBmT11CnMR[CUE]=1 after the target queue has been initialized. MSC8158E Reference Manual, Rev. 2 16-170 Freescale Semiconductor...
Page 937: Dynamically Changing Rules
Initialize the inbound message queue pointers, IBmMQn(E)DPAR and IBmMQn(E)EPAR to match. Initialize the flow control watermark levels, IBmMQnCMR. For data streaming, flow control must be enabled (DSLLCCSR[TME] = 1) to generate outbound flow control messages. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-171...
Page 938: Initializing Outbound Message Queues
— Data Streaming Information Capability Register (DSICAR), page 16-188 — Data Streaming Logical Layer Control Command and Status Register (DSLLCCSR), page 16-189 — Processing Element Logical Layer Control Command and Status Register (PELLCCSR), page 16-190 MSC8158E Reference Manual, Rev. 2 16-172 Freescale Semiconductor...
Page 939 — Port 1–2 Error Rate Enable Command and Status Register (PnERECSR), page 16-211 — Port 1–2 Error Capture Attributes Command and Status Register (PnECACSR), page 16-212 — Port 1–2 Packet/Control Symbol Error Capture Command and Status Register (PnPCSECCSR0), page 16-213 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-173...
Page 940 — Port 1–2 Message Response/Flow Control Tx Buffer Allocation Configuration Register (PnMRspFcTxBACR), page 16-236 Revision Control Registers — IP Block Revision Register 1 (IPBRR1), page 16-237 — IP Block Revision Register 2 (IPBRR2), page 16-238 MSC8158E Reference Manual, Rev. 2 16-174 Freescale Semiconductor...
Page 941 • Inbound Block m Type8 Classification Unit n Data Buffer Pool Register (IBmT8CnDBPR), page 16-253 • Inbound Block m Type8 Classification Unit n Data Offset Register (IBmT8CnDOR), page 16-255 — Type9 Registers (IBmT9CnMR[FTYPE]=0b1001 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-175...
Page 942 (IBmT10CnRVR1), page 16-267 • Inbound Block m Type10 Classification Unit n Rule Mask Register 0 (IBmT10CnRMR0), page 16-269 • Inbound Block m Type10 Classification Unit n Rule Mask Register 1 (IBmT10CnRMR1), page 16-269 MSC8158E Reference Manual, Rev. 2 16-176 Freescale Semiconductor...
Page 943 — Inbound Block m Message Queue n Interrupt Enable Register (IBmMQnIER), page 16-286 — Inbound Block m Message Queue n Interrupt Detect Register (IBmMQnIDR), page 16-288 — Inbound Block m Message Queue n Interrupt Coalescing Register (IBmMQnICR), page 16-289 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-177...
Page 944 — Software Portal n Acquire Consumer Index k Register (SWPn_ACQ_CI_RINGk), page 16-309 — Software Portal n Release Producer Index k Register (SWPn_REL_PI_RINGk), page 16-310 — Software Portal n Acquire Producer Index k Register (SWPn_ACQ_PI_RINGk), page 16-311 MSC8158E Reference Manual, Rev. 2 16-178 Freescale Semiconductor...
Page 945 — Error Interrupt Force Register (ERR_IFR), page 16-332 — Single Bit ECC Error Threshold Register (SBET), page 16-333 — Single Bit ECC Error Count Register (SBEC), page 16-333 — External Memory Access Error Capture Register (EMAI_ECR), page 16-334 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-179...
Page 946: Message Unit Reassembly Context Assignment Registers
— IP Block Revision Register 1 for eMSG (IPBRR1), page 16-352 Note: The base address for the RapidIO registers is: 0xFFF80000. The base address for the eMSG, BMLite, and QMLite registers is: 0xFFF60000. MSC8158E Reference Manual, Rev. 2 16-180 Freescale Semiconductor...
Page 947: Rapidio Registers
0x1828 Device Identity 31–16 Uniquely identifies the type of device from the vendor specified by DVI. The values for DI are assigned and managed by the respective vendor. The value for the MSC8158E = 0x1828. 0x0002 Device Vendor Identity 15–0 Identifies the vendor that manufactures the device containing the processing element.
Page 948: Device Information Capability Register (Dicar)
AIDCAR is a read-only register. The assembly vendor identity field (AVI) identifies the vendor that manufactured the assembly or subsystem containing the device. A value for AVI is uniquely assigned to an assembly vendor by the registration authority of the RapidIO Trade Association. MSC8158E Reference Manual, Rev. 2 16-182 Freescale Semiconductor...
Page 949: Assembly Information Capability Register (Aicar)
AICAR contains additional information on the assembly and the pointer to the first entry in the extended features list. Table 16-53. AICAR Field Descriptions Reset Description 0x0000 Assembly Revision 31–16 0x0100 Extended Features Pointer 15–0 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-183...
Page 950: Processing Element Features Capability Register (Pefcar)
PEFCAR identifies the major functionality provided by the processing element. Table 16-54. PEFCAR Field Descriptions Reset Description Settings Bridge Specifies whether the MSC8158E can bridge to another interface. Memory Specifies whether the MSC8158E has physically addressable local address space and can be accessed as an endpoint through non-maintenance operations.
Page 951: Source Operations Capability Register (Socar)
RESET SW NWR — — — TYPE RESET SOCAR defines the set of RapidIO logical operations that can be issued by the MSC8158E. Table 16-55. SOCAR Field Descriptions Reset Description Read Operation MSC8158E does not support. IRead Operation MSC8158E does not support.
Page 952: Destination Operations Capability Register (Docar)
RESET SW NWR — — — TYPE RESET DOCAR defines the set of RapidIO I/O operations that the MSC8158E can support as a target. Table 16-56. DOCAR Field Descriptions Reset Description Read Operation MSC8158E does not support. IRead Operation MSC8158E does not support.
Page 953 Atomic-Inc Operation MSC8158E does not support. Atomic-Dec Operation MSC8158E does not support. Atomic-Set Operation MSC8158E does not support. Atomic-Clr Operation MSC8158E does not support. — Reserved. Write to zero for future compatibility. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-187...
Page 954: Data Streaming Information Capability Register (Dsicar)
Specifies the maximum PDU size supported by the destination end point (MaxPDU = 0x0000) SegSupport 0x0018 Segment Support 0x0018 24 segmentation contexts. 15–0 Indicates the number of segmentation contexts supported by the destination end point. MSC8158E Reference Manual, Rev. 2 16-188 Freescale Semiconductor...
Page 955 Support for the entire range is required. 0x0A 40 byte block size 0x0B 44 byte block size 0x0C 48 byte block size 0x3F 252 byte block size 0x40 256 byte block size 0x41– 0xFF Reserved. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-189...
Page 956 This register allows configuration and maintenance of an RapidIO block through regular read and write operations rather than maintenance operations. The double-word offset is right justified in the register. This window has priority over MSC8158E Reference Manual, Rev. 2 16-190 Freescale Semiconductor...
Page 957: Base Device Id Command And Status Register (Bdidcsr)
13 bits of LBDID are cleared and the lowest 3 bits are equal to the lowest three bits of the RCWHR[DEVID] field (see Section 5.3.2, Reset Configuration Word High Register (RCWHR), on page 5-20). If the RapidIO controller is configured as an agent, LBDID = 0xFFFF. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-191...
Page 958: Component Tag Command And Status Register (Ctcsr)
Offset 0x0006C TYPE RESET TYPE RESET CTCSR contains a component tag value for the processing element that software can assign when the device is initialized. It is unused internally in RapidIO Endpoint. MSC8158E Reference Manual, Rev. 2 16-192 Freescale Semiconductor...
Page 959: Port Maintenance Block Header 0 (Pmbh0)
Therefore, the RapidIO Endpoint is defined here as not supporting software-assisted error recovery. Table 16-64. PMBH0 Field Descriptions Reset Description EFPTR 0x0600 Extended Features Pointer 31–15 EFID 0x0001 Extended Features ID 16–31 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-193...
Page 960 — TYPE RESET PRTOCCSR contains the time-out timer count for all ports. This time-out is for sending a request packet to receive the corresponding response packet.The reset value is the maximum time-out MSC8158E Reference Manual, Rev. 2 16-194 Freescale Semiconductor...
Page 961: Port General Control Command And Status Register (Pgccsr)
RESET PGCCSR contains control register bits for the RapidIO interface. The user must initialize the value of M to 1. Otherwise, no outbound transactions are initiated by the MSC8158E, including messages and doorbells. Table 16-67. PGCCSR Field Descriptions Reset Description...
Page 962 Contains the link request command to send. If read, this field returns the last written value. If written with a value other than 0x011 (reset device) or 0b100 (input status), the resulting operation is undefined. All other values are reserved in the RapidIO specification. MSC8158E Reference Manual, Rev. 2 16-196 Freescale Semiconductor...
Page 963 Reserved. Write as zero for future compatibility. 30–10 AckID_Status 9–5 This field holds the AckID status field from the link response. Link Status 4–0 This field holds the link status field from the link response. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-197...
Page 964: Port 1–2 Local Ackid Command And Status Register (Pnlascr)
Outbound ackID Output Port Next Transmitted ackID Value 4–0 This can be written by software but only if there are no outstanding unacknowledged packets. If there are, a newly-written value will be ignored MSC8158E Reference Manual, Rev. 2 16-198 Freescale Semiconductor...
Page 965: Port 1–2 Error And Status Command And Status Register (Pnescsr)
OR is set when ORS is set and cleared when a packet-accepted or packet-not-accepted control symbol is received. Read only. Output Stop The output port stops due to a retry. Read only. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-199...
Page 966: Port 1–2 Control Command And Status Register (Pnccsr)
Port 1–2 Control Command and Status Register Offset 0x0015C P2CCSR Offset 0x0017C — — TYPE RESET — TYPE RESET PnCCSR contains control register bits for the RapidIO port. This register is for serial implementation only. MSC8158E Reference Manual, Rev. 2 16-200 Freescale Semiconductor...
Page 967 OPE = 0, disable any LAWs with a RapidIO target to prevent outbound request packets from being sent to the RapidIO controller. The initial value of OPE is read from configuration pins. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-201...
Page 968 This bit is hard-wired to 0. Error checking and recovery is disabled. Multicast Event Participant This bit is hard-wired to 0. The MSC8158E does not participate in multicast events. — Reserved. Write to zero for future compatibility. Enumeration Boundary No enumeration boundary checking.
Page 969: Error Reporting Block Header (Erbh)
Message Unit has captured an enabled Logical/Transport layer error until the detected error is cleared, and likewise, the Message Unit’s LTLEDCSR cannot detect any errors if the Message Unit or any port has captured an enabled Logical/Transport layer error. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-203...
Page 970 A start or single data streaming segment was received for an already open segmentation context. LDSS Long Data Streaming Segment Received a data streaming segment with a payload size greater than the MTU. MSC8158E Reference Manual, Rev. 2 16-204 Freescale Semiconductor...
Page 971: Status Register
LTLEECSR contains the bits that control whether an error condition locks the logical/transport layer error detect and capture registers and is reported to the system host. LTLEECSR is stored in all ports and the message unit. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-205...
Page 972 CAR (that is, the tt value is reserved or indicates a common transport system unsupported by this device). PTTL Packet Time-to-Live Error Enable Enables reporting of a packet time-to-live error. Capture and lock the result. — Reserved. Write to zero for future compatibility. 2–0 MSC8158E Reference Manual, Rev. 2 16-206 Freescale Semiconductor...
Page 973 Extended Address MSBs 1–0 Normally the extended address bits of the address associated with the error (for requests, responses, if available). For details, see Section 16.2.14.3, Logical Layer RapidIO Errors, on page 16-64. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-207...
Page 974 Normally, the source ID (or least significant byte of the source ID if large transport system) associated with the error. For details, see Section 16.2.14.3, Logical Layer RapidIO Errors, on page 16-64. MSC8158E Reference Manual, Rev. 2 16-208 Freescale Semiconductor...
Page 975 (message errors only). For details, see Section 16.2.14.3, Logical Layer RapidIO Errors, on page 16-64. Encoded Port Number 15–12 Indicates the port from which the error information was captured. — Reserved. Write to zero for future compatibility. 11–0 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-209...
Page 976: Port 1–2 Error Detect Command And Status Register (Pnedcsr)
Received unaligned /SC/ or /PD/ or undefined code-group. Unsolicited Control Symbol An unsolicited acknowledge control symbol was received. Link Time-Out An acknowledge or link-response control symbol is not received within the specified time-out interval. MSC8158E Reference Manual, Rev. 2 16-210 Freescale Semiconductor...
Page 977 Unsolicited Control Symbol Enable error rate counting of unexpected acknowledge control symbols. Link Time-Out Enable error rate counting of an acknowledge or link-response control symbol not received within the specified time-out interval. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-211...
Page 978 Reserved. Write to zero for future compatibility. Error 28–24 The encoded value of the bit in the Port 1–2 error detect CSR that describes the error captured in the Port 1–2 error capture CSRs. MSC8158E Reference Manual, Rev. 2 16-212 Freescale Semiconductor...
Page 979 Undefined results occur if this register is written while actual physical layer errors are detected by the port. Software should verify that the PnECACSR[CVI] bit is set before reading the capture registers to ensure that the error is properly captured. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-213...
Page 980 PnECACSR[CVI] bit is set before reading the capture registers to ensure that the error is properly captured. Table 16-83. PnPECCSR1 Field Descriptions Reset Description Capture 1 31–0 Contains bytes 4–7 of the packet header. MSC8158E Reference Manual, Rev. 2 16-214 Freescale Semiconductor...
Page 981 Software should verify that the PnECACSR[CVI] bit is set before reading the capture registers to ensure that the error has been properly captured. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-215...
Page 982: Port 1–2 Error Rate Command And Status Register (Pnercsr)
Do not limit increments above the settings of ERR and the failed threshold trigger imply error rate count. that it would. Peak Error Rate 15–8 Contains the peak value attained by the error rate counter. MSC8158E Reference Manual, Rev. 2 16-216 Freescale Semiconductor...
Page 983 PnESCSR[ODE] bit is set if PnERCSR[ERC] exceeds the ERDTT value. 0x02 Set the error reporting threshold to 0xFF Set the error reporting threshold to 255. — Reserved. Write to zero for future compatibility. 15–0 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-217...
Page 984: Logical Layer Configuration Register (Llcr)
EPWISR contains status bits of the interrupts generated by the port or the message unit for physical or logical/transport layer errors or inbound port-writes. Because errors from the port are reported to the SC3850 core with one interrupt signal, this register provides the core with quick MSC8158E Reference Manual, Rev. 2 16-218 Freescale Semiconductor...
Page 985: Logical Retry Error Threshold Configuration Register (Lretcr)
Set the error reporting threshold to 1. consecutive logical retries received for a given packet that causes the RAPIDIO ENDPOINT to 0xFF Set the error reporting threshold to 255. report an error condition. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-219...
Page 986: Physical Retry Error Threshold Configuration Register (Pretcr)
16>-195). Therefore, when the PGCCSR bit is enabled, all other devices in the RapidIO system (including switches) send and receive packets from the device ID in PnADIDCSR instead of the device ID in BDIDCSR. When the alternate deviceID is enabled, inbound RapidIO MSC8158E Reference Manual, Rev. 2 16-220 Freescale Semiconductor...
Page 987 Reserved. Write to zero for future compatibility. 30–24 ADID Alternate Device ID 23–16 Alternate device ID in a small transport system. LADID Large Alternate Device ID 15–0 Alternate device ID for the device in a large transport system. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-221...
Page 988 The pass-through packet will be looped back from RapidIO Port2 to same RapidIO Port2 The pass-through packet will be passed from RapidIO Port2 to RapidIO Port1 — Reserved. Write to zero for future compatibility. 27–2 MSC8158E Reference Manual, Rev. 2 16-222 Freescale Semiconductor...
Page 989 (acknowledged with an accept by the link partner at the physical level). The value of this register should always be larger than the link time-out value (PLTOCCSR). The MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-223...
Page 990 This bit is set again if another retry is received and the number of consecutive retries continues to exceed the retry error threshold. — Reserved. Write to zero for future compatibility. 30–0 MSC8158E Reference Manual, Rev. 2 16-224 Freescale Semiconductor...
Page 991: Port 1–2 Physical Configuration Register (Pnpcr)
— Reserved. Write to zero for future compatibility. 1–0 MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-225...
Page 992: Port 1–2 Serial Link Command And Status Register (Pnslcsr)
PnSLEICR controls the injection of bit errors into the transmit bit stream and is used to generate pseudo-random errors into the outbound serial RapidIO data stream. If the EIC field is non-zero, error injection is enabled and, at pseudo-random intervals, an error is injected by inverting a MSC8158E Reference Manual, Rev. 2 16-226 Freescale Semiconductor...
Page 993: Port N Arbitration 0 Tx Configuration Register (Pna0Txcr)
Offset 0x101E4 — TYPE RESET — SPSA_TH_MSCREQ[9–0] TYPE RESET PnA0TxCR is used to control the arbitration of packets within the serial RapidIO controller transmit logic (Tx), specifically at arbitration point 0. Please see MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-227...
Page 994 0x3FF Count of 1023. Strict priority with starvation avoidance enabled. A low priority message unit request packet may lose strict priority arbitration 1023 consecutive times before it promotes to highest priority (starvation avoidance). MSC8158E Reference Manual, Rev. 2 16-228 Freescale Semiconductor...
Page 995: Port N Arbitration 1 Tx Configuration Register (Pna1Txcr)
Weight of 2. 2 consecutive message unit Sets the threshold (weight) for response packets before considering other message unit response packets. packets. Weight of 16: 16 consecutive message unit response packets before considering other packets. MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-229...
Page 996: Port N Arbitration 2 Tx Configuration Register (Pna2Txcr)
— WRR_TH_SYS[3–0] TYPE RESET — SPSA_TH_SRIO[4–0] TYPE RESET PnA2TxCR is used to control the arbitration of packets within the serial RapidIO controller transmit logic (Tx), specifically at arbitration point 2. Please see MSC8158E Reference Manual, Rev. 2 16-230 Freescale Semiconductor...
Page 997 0x1F Count of 31. Strict priority with starvation avoidance enabled. A low priority RapidIO packet may lose strict priority arbitration 31 consecutive times before it promotes to highest priority (starvation avoidance). MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-231...
Page 998 One dedicated buffer allocated for Group 0 request packets. message unit request packets. Fifteen dedicated buffers allocated for Group 0 message unit request packets. — Reserved. Write to zero for future compatibility. 23–20 MSC8158E Reference Manual, Rev. 2 16-232 Freescale Semiconductor...
Page 999 The Port n Message Request Tx Buffer Allocation Configuration Register 1 (PnMReqTxBACR1) is used to control the buffer allocation of message unit request packets within the serial RapidIO controller transmit logic (Tx). MSC8158E Reference Manual, Rev. 2 Freescale Semiconductor 16-233...
Page 1000 0 message unit One dedicated buffer allocated for Group 7 request packets. message unit request packets. Fifteen dedicated buffers allocated for Group 7 message unit request packets. MSC8158E Reference Manual, Rev. 2 16-234 Freescale Semiconductor...