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NXP Semiconductors freescale semiconductor MC13212 Reference Manual (372 pages)

ZigBee- Compliant Platform 2.4 GHz Low Power Transceiver for the IEEE 802.15.4 Standard plus Microcontroller

Brand: NXP Semiconductors | Category: Transceiver | Size: 5 MB

Table of Contents
3
Audience
15
Organization
15
Revision History
16
References
18
Chapter 1 Mc1321X Introduction

19
- Ordering Information
  21
- General Platform Features
  21
- Microcontroller Features
  22
- RF Modem Features
  23
- Software Solutions
  23
- Simple Media Access Controller (SMAC)
  23
- IEEE 802.15.4 2006 Standard-Compliant MAC
  23
- Synkrorf Platform
  24
- Beestack Consumer
  24
- Zigbee-Compliant Network Stack
  25
- System Block Diagram
  26
- Modem Overview
  27
- Modem Block Diagram
  27
- Modem Data Transfer Modes
  27
- Modem Packet Structure
  28
- Modem Receive Path Description
  28
- Modem Transmit Path Description
  29
- Radio Usage
  30
- MCU Overview
  30
- MCU Block Diagram
  31
- HCS08 Central Processing Unit (CPU)
  32
- MCU Peripheral Modules
  32
- MCU Internal Clock Distribution
  33
- System Clock Configuration
  34
Chapter 2 Mc1321X Pins and Connections

35
- Device Pin Assignment
  35
- Pin Definitions
  36
Chapter 3 System Considerations

41
Chapter 4 Mc1321X Serial Peripheral Interface (SPI)

77
- Sip Level SPI Pin Connections
  77
- Features
  78
- SPI System Block Diagram
  78
- Modem SPI Overview
  79
- Modem SPI Basic Operation
  79
- Modem SPI Pin Definition
  79
- Modem SPI Byte Burst Operation
  81
- MCU SPI Block Diagrams
  82
- MCU SPI Module Block Diagram
  82
- MCU SPI Baud Rate Generation
  83
- MCU SPI Functional Description
  83
- SPI Clock Formats
  84
- MCU SPI Pin Controls
  85
- MCU SPI Interrupts
  85
- Mode Fault Detection
  86
- MCU SPI Registers and Control Bits
  86
- SPI Control Register 1 (SPI1C1)
  87
- SPI Control Register 2 (SPI1C2)
  88
- SPI Baud Rate Register (SPI1BR)
  89
- SPI Status Register (SPI1S)
  90
- SPI Data Register (SPI1D)
  91
- Modem SPI Singular Transactions
  91
- SPI Singular Transaction Signalling
  91
- SPI Singular Transaction Protocol
  92
- Modem Symbol/Data Format
  93
- Modem SPI Recursive Transactions
  94
- Recursive SPI Register Read
  94
- Recursive SPI Register Write
  94
- Special Case - Packet RAM Access
  95
- Modem Program Reset (Writing Address 0X00)
  98
- Configuring MCU Registers for Proper SPI Operation
  98
- Set SPI Module Mode
  98
- SPI Baud Rate Control
  99
Chapter 5 Modem SPI Register Descriptions

101
- Overview
  101
- Register Model and Description Details
  102
- Reset - Register 00
  105
- Rx_Pkt_Ram - Register 01
  105
- Tx_Pkt_Ram - Register 02
  106
- Tx_Pkt_Ctl - Register 03
  107
- Cca_Thresh - Register 04
  107
- Irq_Mask - Register 05
  108
- Control_A - Register 06
  110
- Control_B - Register 07
  110
- Control_C - Register 09
  111
- Clko_Ctl - Register 0A
  115
- Gpio_Dir - Register 0B
  116
- Gpio_Data_Out - Register 0C
  117
- Lo1_Int_Div - Register 0F
  118
- Lo1_Num - Register 10
  119
- Pa_Lvl - Register 12
  120
- Tmr_Cmp1_A - Register 1B
  120
- Tmr_Cmp1_B - Register 1C
  121
- Tmr_Cmp2_A - Register 1D
  122
- Tmr_Cmp2_B - Register 1E
  123
- Tmr_Cmp3_A - Register 1F
  123
- Tmr_Cmp3_B - Register 20
  124
- Tmr_Cmp4_B - Register 22
  125
- Tc2_Prime - Register 23
  126
- Irq_Status - Register 24
  126
- Rst_Ind - Register 25
  129
- Current_Time_A - Register 26
  130
- Current_Time_B - Register 27
  130
- Gpio_Data_In - Register 28
  131
- Chip_Id - Register 2C
  132
- Rx_Status - Register 2D
  132
- Timestamp_A - Register 2E
  133
- Timestamp_B - Register 2F
  134
- Ber_Enable - Register 30
  134
- Psm_Mode - Register 31
  135
- Reserved - Register 34
  136
Chapter 6 Modem Timer Information

137
- Event Timer Block
  137
- Event Timer Time Base
  138
- Setting Current Time
  138
- Reading Current Time
  139
- Latching the Timestamp
  139
- Event Timer Comparators
  139
- Timer Compare Fields
  139
- Timer Disable Bits
  140
- Timer Status Flags
  140
- Timer Interrupt Masks
  140
- Setting Compare Values
  140
- Intended Event Timer Usage
  141
- Generating Time-Based Interrupts
  141
- Using Tmr_Cmp2[23:0] to Exit Doze Mode
  142
- Timer-Triggered Transceiver Events
  142
Chapter 7 Modem Modes of Operation

145
- Modem Operational Modes Summary
  145
- Low Power Modes
  148
- Off Mode
  148
- Hibernate Mode
  148
- Doze Mode
  148
- Active Modes
  149
- Idle Mode
  149
- Controlling Transition to Other Active Modes from Idle
  150
- Packet Mode Data Transfer TX and RX Operation
  150
- Stream Mode Data Transfer TX and RX Operation
  153
- Clear Channel Assessment (CCA) Modes (Including Link Quality Indication)
  157
- Frequency of Operation
  162
- Transmit Power Adjustment
  163
- Ghz PLL Out-Of-Lock Interrupt
  164
Chapter 8 Modem Interrupt Description

167
- Modem Interrupts
  167
- Modem Interrupt Sources
  167
- Output Pin IRQ
  169
- Pll_Lock_Irq Status Bit and Operation
  169
- Attn_Irq Status Bit and Interrupt Operation
  170
- Interrupts from Exiting Low Power Modes
  170
- Exiting off Mode (Reset)
  170
- Exiting Hibernate Mode
  170
- Exiting Doze Mode(S)
  171
Chapter 9 Modem Miscellaneous Functions

173
- Reset Function
  173
- Input Pin M_RSTB
  173
- Software Reset (Writing to Register 00)
  173
- Reset Indicator Bit (Rst_Ind Register 25, Bit 7)
  173
- General Purpose Input/Output
  174
- Configuring GPIO Direction
  174
- Setting GPIO Output Drive Strength
  174
- Programming GPIO Output Value
  174
- Reading GPIO Input State
  174
- GPIO1 and GPIO2 as Stream Mode Status Indicators
  175
- GPIO in Off, Hibernate, and Doze Modes
  175
- Crystal Oscillator
  175
- Crystal Requirements
  176
- Crystal Trim Operation
  176
- Output Clock Pin CLKO
  177
- Enable CLKO (Clko_En, Control_C Register 09, Bit 5)
  177
- Setting CLKO Frequency (Clko_Rate[2:0], Clko_Ctl Register 0A, Bits 2-0)
  177
- Enable CLKO During Doze Mode (Clko_Doze_En, Control_B Register 07, Bit 9)
  178
- Setting CLKO Output Drive Strength
  178
- Input Pin ATTN
  178
Chapter 10 MCU Modes of Operation

179
- Introduction
  179
- Features
  179
- Run Mode
  179
- Active Background Mode
  179
- Wait Mode
  180
- Stop Modes
  181
- Stop1 Mode
  181
- Stop2 Mode
  182
- Stop3 Mode
  182
- Active BDM Enabled in Stop Mode
  183
- LVD Enabled in Stop Mode
  183
- On-Chip Peripheral Modules in Stop Modes
  184
Chapter 11 MCU Memory

187
- HCS08 Memory Map
  187
- Reset and Interrupt Vector Assignments
  188
- Register Addresses and Bit Assignments
  189
- Ram
  194
- Flash
  195
- Features
  195
- Program and Erase Times
  195
- Program and Erase Command Execution
  196
- Burst Program Execution
  197
- Access Errors
  198
- FLASH Block Protection
  199
- Vector Redirection
  200
- Security
  200
- FLASH Registers and Control Bits
  201
- FLASH Clock Divider Register (FCDIV)
  201
- FLASH Options Register (FOPT and NVOPT)
  203
- FLASH Configuration Register (FCNFG)
  204
- FLASH Protection Register (FPROT and NVPROT)
  204
- FLASH Status Register (FSTAT)
  205
- FLASH Command Register (FCMD)
  206
Chapter 12 MCU Resets, Interrupts, and System Configuration

209
- Introduction
  209
- Features
  209
- MCU Reset
  210
- Computer Operating Properly (COP) Watchdog
  210
- Interrupts
  211
- Interrupt Stack Frame
  212
- External Interrupt Request (IRQ) Pin
  212
- Low-Voltage Detect (LVD) System
  214
- Power-On Reset Operation
  215
- LVD Reset Operation
  215
- LVD Interrupt Operation
  215
- Low-Voltage Warning (LVW)
  215
- Real-Time Interrupt (RTI)
  215
- Interrupt Pin Request Status and Control Register (IRQSC)
  216
- System Reset Status Register (SRS)
  217
- System Background Debug Force Reset Register (SBDFR)
  219
- System Options Register (SOPT)
  219
- System Device Identification Register (SDIDH, SDIDL)
  220
- System Real-Time Interrupt Status and Control Register (SRTISC)
  221
- System Power Management Status and Control 1 Register (SPMSC1)
  222
- System Power Management Status and Control 2 Register (SPMSC2)
  223
Chapter 13 MCU Parallel Input/Output

225
- Introduction
  225
- Features
  227
- Pin Descriptions
  227
- Port a and Keyboard Interrupts
  227
- Port B and Analog to Digital Converter Inputs
  228
- Port C and SCI2, IIC, and High-Current Drivers
  228
- Port D, TPM1 and TPM2
  229
- Port E, SCI1, and SPI
  229
- Port F and High-Current Drivers
  230
- Port G, BKGD/MS, and Oscillator
  230
- Parallel I/O Controls
  231
- Data Direction Control
  231
- Internal Pullup Control
  231
- Slew Rate Control
  231
- Stop Modes
  232
- Parallel I/O Registers and Control Bits
  232
- Port a Registers (PTAD, PTAPE, PTASE, and PTADD)
  232
- Port B Registers (PTBD, PTBPE, PTBSE, and PTBDD)
  234
- Port C Registers (PTCD, PTCPE, PTCSE, and PTCDD)
  235
- Port D Registers (PTDD, PTDPE, PTDSE, and PTDDD)
  237
- Port E Registers (PTED, PTEPE, PTESE, and PTEDD)
  238
- Port F Registers (PTFD, PTFPE, PTFSE, and PTFDD)
  240
- Port G Registers (PTGD, PTGPE, PTGSE, and PTGDD)
  241
Chapter 14 MCU Internal Clock Generator (ICG)

245
- Introduction
  245
- Features
  246
- Modes of Operation
  247
- Oscillator Pins
  247
- EXTAL- External Reference Clock / Oscillator Input
  247
- XTAL- Oscillator Output
  248
- External Clock Connections
  248
- External Crystal/Resonator Connections
  248
- Functional Description
  249
- Off Mode (Off)
  249
- Self-Clocked Mode (SCM)
  249
- FLL Engaged, Internal Clock (FEI) Mode
  251
- FLL Bypassed, External Clock (FBE) Mode
  251
- FLL Engaged, External Clock (FEE) Mode
  252
- FLL Lock and Loss-Of-Lock Detection
  252
- FLL Loss-Of-Clock Detection
  253
- Clock Mode Requirements
  254
- Fixed Frequency Clock
  255
- 14.3.10 High Gain Oscillator
  255
- Initialization/Application Information
  256
- Introduction
  256
- Example #1: External Crystal = 32 Khz, Bus Frequency = 4.19 Mhz
  257
- Example #2: External Crystal = 4 Mhz, Bus Frequency = 20 Mhz
  259
- Example #3: no External Crystal Connection, 5.4 Mhz Bus Frequency
  260
- Example #4: Internal Clock Generator Trim
  262
- ICG Registers and Control Bits
  263
- Control Register 1 (C1)
  263
- Control Register 2 (C2)
  264
- Status Register 1 (S1)
  265
- Status Register 2 (S2)
  266
- Filter Registers (FLTU, ICGFLTL)
  267
- Trim Register (TRM)
  268
Chapter 15 MCU Central Processor Unit (CPU)

269
- Introduction
  269
- Features
  269
- Programmer's Model and CPU Registers
  270
- Accumulator (A)
  270
- Index Register (H:X)
  270
- Stack Pointer (SP)
  271
- Program Counter (PC)
  271
- Condition Code Register (CCR)
  271
- Addressing Modes
  272
- Inherent Addressing Mode (INH)
  273
- Relative Addressing Mode (REL)
  273
- Immediate Addressing Mode (IMM)
  273
- Direct Addressing Mode (DIR)
  273
- Extended Addressing Mode (EXT)
  273
- Indexed Addressing Mode
  273
- Special Operations
  274
- Reset Sequence
  275
- Interrupt Sequence
  275
- Wait Mode Operation
  276
- Stop Mode Operation
  276
- BGND Instruction
  276
- HCS08 Instruction Set Summary
  277
Chapter 16 MCU Keyboard Interrupt (KBI)

289
- Introduction
  289
- KBI Block Diagram
  289
- Register Definitions
  289
- KBI Status and Control Register (KBISC)
  290
- KBI Pin Enable Register (KBIPE)
  291
- Functional Description
  291
- Pin Enables
  291
- Edge and Level Sensitivity
  291
- KBI Interrupt Controls
  292
Chapter 17 MCU Timer/Pwm (TPM Module)

293
- Introduction
  293
- TPM Block Diagram
  293
- Pin Descriptions
  295
- External TPM Clock Sources
  295
- Tpm1Chn - TPM1 Channel N I/O Pins
  295
- Functional Description
  295
- Counter
  296
- Channel Mode Selection
  297
- Center-Aligned PWM Mode
  298
- TPM Interrupts
  299
- Clearing Timer Interrupt Flags
  300
- Timer Overflow Interrupt Description
  300
- Channel Event Interrupt Description
  300
- PWM End-Of-Duty-Cycle Events
  300
- TPM Registers and Control Bits
  301
- Timer X Status and Control Register (TPM1SC)
  301
- Timer X Counter Registers (TPM1CNTH:TPM1CNTL)
  303
- Timer X Counter Modulo Registers (TPM1MODH:TPM1MODL)
  304
- Timer X Channel N Status and Control Register (Tpm1Cnsc)
  304
- Timer X Channel Value Registers (Tpm1Cnvh:tpm1Cnvl)
  306
Chapter 18 MCU Serial Communications Interface (SCI)

309
- Features
  309
- SCI System Description
  309
- Baud Rate Generation
  309
- Transmitter Functional Description
  310
- Transmitter Block Diagram
  310
- Send Break and Queued Idle
  311
- Receiver Functional Description
  311
- Receiver Block Diagram
  312
- Data Sampling Technique
  313
- Receiver Wakeup Operation
  314
- Interrupts and Status Flags
  314
- Additional SCI Functions
  315
- 8-Bit and 9-Bit Data Modes
  315
- Stop Mode Operation
  316
- Loop Mode
  316
- Single-Wire Operation
  316
- SCI Registers and Control Bits
  316
- SCI1 Baud Rate Registers (Scixbdh, Scixbdl)
  317
- SCI1 Control Register 1 (Scixc1)
  318
- SCI1 Control Register 2 (Scixc2)
  319
- SCI1 Status Register 1 (Scixs1)
  321
- SCI1 Status Register 2 (Scixs2)
  323
- SCI1 Control Register 3 (Scixc3)
  323
- SCI1 Data Register (Scixd)
  324
Chapter 19 Inter-Integrated Circuit (IIC)

325
- Introduction
  325
- Features
  325
- Modes of Operation
  325
- Block Diagram
  326
- Signal Description
  326
- External Signal Description
  327
- SCL - Serial Clock Line
  327
- SDA - Serial Data Line
  327
- Register Definitions
  327
- Module Memory Map
  327
- Register Descriptions
  328
- IIC Address Register (IIC1A)
  328
- IIC Frequency Divider Register (IIC1F)
  328
- IIC Control Register (IIC1C)
  331
- IIC Status Register (IIC1S)
  332
- IIC Data I/O Register (IIC1D)
  333
- Functional Description
  333
- IIC Protocol
  333
- Resets
  337
- Interrupts
  337
- Byte Transfer Interrupt
  337
- Address Detect Interrupt
  337
- Arbitration Lost Interrupt
  337
Chapter 20 Analog to Digital (ATD) Module

339
- Introduction
  339
- Features
  339
- Modes of Operation
  339
- Block Diagram
  340
- Signal Description
  341
- Overview
  341
- Functional Description
  341
- Mode Control
  342
- Sample and Hold
  342
- Analog Input Multiplexer
  344
- ATD Module Accuracy Definitions
  344
- Resets
  347
- Interrupts
  347
- Mc1321X Reference Manual, Rev
  347
- ATD Registers and Control Bits
  347
- ATD Control (ATDC)
  348
- ATD Status and Control (ATD1SC)
  350
- ATD Result Data (ATD1RH, ATD1RL)
  351
- ATD Pin Enable (ATD1PE)
  352
Chapter 21 Development Support

353
- Features
  353
- Background Debug Controller (BDC)
  354
- BKGD Pin Description
  355
- Communication Details
  355
- BDC Commands
  357
- Coding Structure Nomenclature
  357
- BDC Hardware Breakpoint
  360
- On-Chip Debug System (DBG)
  360
- Comparators a and B
  360
- Bus Capture Information and FIFO Operation
  361
- Change-Of-Flow Information
  362
- Tag Vs. Force Breakpoints and Triggers
  362
- Trigger Modes
  362
- Hardware Breakpoints
  364
- Register Definition
  364
- BDC Registers and Control Bits
  364
- System Background Debug Force Reset Register (SBDFR)
  367
- DBG Registers and Control Bits
  367

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NXP Semiconductors freescale semiconductor MC13212 Manuals

NXP Semiconductors freescale semiconductor MC13212 Reference Manual (372 pages)

Table of Contents

Chapter 1 Mc1321X Introduction

Chapter 2 Mc1321X Pins and Connections

Chapter 3 System Considerations

Chapter 4 Mc1321X Serial Peripheral Interface (SPI)

Chapter 5 Modem SPI Register Descriptions

Chapter 6 Modem Timer Information

Chapter 7 Modem Modes of Operation

Chapter 8 Modem Interrupt Description

Chapter 9 Modem Miscellaneous Functions

Chapter 10 MCU Modes of Operation

Chapter 11 MCU Memory

Chapter 12 MCU Resets, Interrupts, and System Configuration

Chapter 13 MCU Parallel Input/Output

Chapter 14 MCU Internal Clock Generator (ICG)

Chapter 15 MCU Central Processor Unit (CPU)

Chapter 16 MCU Keyboard Interrupt (KBI)

Chapter 17 MCU Timer/Pwm (TPM Module)

Chapter 18 MCU Serial Communications Interface (SCI)

Chapter 19 Inter-Integrated Circuit (IIC)

Chapter 20 Analog to Digital (ATD) Module

Chapter 21 Development Support

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