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NXP Semiconductors freescale MK51DX256ZCMC10 Reference Manual (1611 pages)

Brand: NXP Semiconductors | Category: Microcontrollers | Size: 18 MB

Table of Contents
3
About this Document
53
Overview
53
Purpose
53
Audience
53
Conventions
53
Numbering Systems
53
Typographic Notation
54
Special Terms
54
Introduction
55
Overview
55
K50 Family Introduction
55
Module Functional Categories
55
ARM Cortex-M4 Core Modules
57
System Modules
57
Memories and Memory Interfaces
58
Clocks
59
Security and Integrity Modules
59
Analog Modules
60
Timer Modules
60
Communication Interfaces
61
Human-Machine Interfaces
62
Orderable Part Numbers
62
Chip Configuration
65
Introduction
65
Core Modules
65
ARM Cortex-M4 Core Configuration
65
Nested Vectored Interrupt Controller (NVIC) Configuration
68
Asynchronous Wake-Up Interrupt Controller (AWIC) Configuration
74
JTAG Controller Configuration
75
System Modules
76
SIM Configuration
76
Mode Controller Configuration
77
PMC Configuration
77
Low-Leakage Wake-Up Unit (LLWU) Configuration
78
MCM Configuration
80
Crossbar Switch Configuration
80
Memory Protection Unit (MPU) Configuration
82
Peripheral Bridge Configuration
85
DMA Request Multiplexer Configuration
87
DMA Controller Configuration
90
External Watchdog Monitor (EWM) Configuration
91
Watchdog Configuration
92
Clock Modules
93
MCG Configuration
93
OSC Configuration
94
RTC OSC Configuration
95
Memories and Memory Interfaces
95
Flash Memory Configuration
95
Flash Memory Controller Configuration
99
SRAM Configuration
100
SRAM Controller Configuration
103
System Register File Configuration
104
VBAT Register File Configuration
105
Ezport Configuration
106
Security
107
CRC Configuration
107
Analog
107
16-Bit SAR ADC with PGA Configuration
107
CMP Configuration
115
12-Bit DAC Configuration
117
Op-Amp Configuration
118
TRIAMP Configuration
120
VREF Configuration
121
Timers
122
PDB Configuration
122
Flextimer Configuration
126
PIT Configuration
129
Low-Power Timer Configuration
130
CMT Configuration
132
RTC Configuration
133
Communication Interfaces
134
Universal Serial Bus (USB) Subsystem
134
SPI Configuration
139
I2C Configuration
142
UART Configuration
143
SDHC Configuration
145
I2S Configuration
146
Human-Machine Interfaces (HMI)
148
GPIO Configuration
148
TSI Configuration
149
Segment LCD Configuration
152
Memory Map
155
Introduction
155
System Memory Map
155
Aliased Bit-Band Regions
156
Flash Memory Map
157
Alternate Non-Volatile IRC User Trim Description
158
SRAM Memory Map
158
Peripheral Bridge (AIPS-Lite0 and AIPS-Lite1) Memory Maps
159
Peripheral Bridge 0 (AIPS-Lite 0) Memory Map
159
Peripheral Bridge 1 (AIPS-Lite 1) Memory Map
163
Private Peripheral Bus (PPB) Memory Map
167
Clock Distribution
169
Introduction
169
Programming Model
169
High-Level Device Clocking Diagram
169
Clock Definitions
170
Device Clock Summary
171
Internal Clocking Requirements
173
Clock Divider Values after Reset
174
VLPR Mode Clocking
174
Clock Gating
174
Module Clocks
174
PMC 1-Khz LPO Clock
176
WDOG Clocking
176
Debug Trace Clock
177
PORT Digital Filter Clocking
177
LPTMR Clocking
178
USB FS OTG Controller Clocking
178
UART Clocking
179
SDHC Clocking
179
I2S Clocking
180
TSI Clocking
180
Reset and Boot
183
Introduction
183
Reset
183
Power-On Reset (POR)
184
System Resets
184
Debug Resets
188
Boot
189
Boot Sources
189
Boot Options
189
FOPT Boot Options
189
Boot Sequence
190
Power Management
193
Introduction
193
Power Modes
193
Entering and Exiting Power Modes
195
Power Mode Transitions
196
Power Modes Shutdown Sequencing
197
Module Operation in Low Power Modes
197
Clock Gating
200
Security
201
Introduction
201
Flash Security
201
Security Interactions with Other Modules
202
Security Interactions with Ezport
202
Security Interactions with Debug
202
Introduction
203
References
205
The Debug Port
205
JTAG-To-SWD Change Sequence
206
JTAG-To-Cjtag Change Sequence
206
Debug Port Pin Descriptions
207
System TAP Connection
207
IR Codes
208
JTAG Status and Control Registers
208
MDM-AP Control Register
209
MDM-AP Status Register
211
Debug Resets
212
Ahb-Ap
213
Itm
214
Core Trace Connectivity
214
Embedded Trace Macrocell V3.5 (ETM)
214
Coresight Embedded Trace Buffer (ETB)
215
Performance Profiling with the ETB
215
ETB Counter Control
216
Tpiu
216
Dwt
216
Debug in Low Power Modes
217
Debug Module State in Low Power Modes
218
Debug & Security
218
Signal Multiplexing and Signal Descriptions
219
Introduction
219
Signal Multiplexing Integration
219
Port Control and Interrupt Module Features
220
Clock Gating
220
Signal Multiplexing Constraints
220
Pinout
221
K51 Signal Multiplexing and Pin Assignments
221
K51 Pinouts
226
Module Signal Description Tables
227
Core Modules
228
System Modules
228
Clock Modules
229
Memories and Memory Interfaces
229
Analog
230
Communication Interfaces
232
Human-Machine Interfaces (HMI)
236
Port Control and Interrupts (PORT)
237
Introduction
237
Overview
237
Features
237
Modes of Operation
238
External Signal Description
239
Detailed Signal Descriptions
239
Memory Map and Register Definition
239
Pin Control Register N (Portx_Pcrn)
246
Global Pin Control Low Register (Portx_Gpclr)
248
Global Pin Control High Register (Portx_Gpchr)
249
Interrupt Status Flag Register (Portx_Isfr)
249
Digital Filter Enable Register (Portx_Dfer)
250
Digital Filter Clock Register (Portx_Dfcr)
251
Digital Filter Width Register (Portx_Dfwr)
251
Functional Description
252
Pin Control
252
Global Pin Control
252
External Interrupts
253
Digital Filter
254
System Integration Module (SIM)
255
Introduction
255
Features
255
Modes of Operation
255
SIM Signal Descriptions
256
Memory Map and Register Definition
256
System Options Register 1 (SIM_SOPT1)
258
System Options Register 2 (SIM_SOPT2)
260
System Options Register 4 (SIM_SOPT4)
262
System Options Register 5 (SIM_SOPT5)
264
System Options Register 6 (SIM_SOPT6)
266
System Options Register 7 (SIM_SOPT7)
267
System Device Identification Register (SIM_SDID)
269
System Clock Gating Control Register 1 (SIM_SCGC1)
270
System Clock Gating Control Register 2 (SIM_SCGC2)
271
System Clock Gating Control Register 3 (SIM_SCGC3)
272
System Clock Gating Control Register 4 (SIM_SCGC4)
273
System Clock Gating Control Register 5 (SIM_SCGC5)
276
System Clock Gating Control Register 6 (SIM_SCGC6)
278
System Clock Gating Control Register 7 (SIM_SCGC7)
280
System Clock Divider Register 1 (SIM_CLKDIV1)
281
System Clock Divider Register 2 (SIM_CLKDIV2)
283
Flash Configuration Register 1 (SIM_FCFG1)
284
Flash Configuration Register 2 (SIM_FCFG2)
286
Unique Identification Register High (SIM_UIDH)
287
Unique Identification Register MID-High (SIM_UIDMH)
288
Unique Identification Register MID Low (SIM_UIDML)
288
Unique Identification Register Low (SIM_UIDL)
289
Functional Description
289
Mode Controller
291
Introduction
291
Features
291
Modes of Operation
291
MCU Reset
302
Mode Control Memory Map/Register Definition
305
System Reset Status Register High (MC_SRSH)
306
System Reset Status Register Low (MC_SRSL)
307
Power Mode Protection Register (MC_PMPROT)
308
Power Mode Control Register (MC_PMCTRL)
310
Power Management Controller
313
Introduction
313
Features
313
Low-Voltage Detect (LVD) System
313
LVD Reset Operation
314
LVD Interrupt Operation
314
Low-Voltage Warning (LVW) Interrupt Operation
314
PMC Memory Map/Register Definition
315
Low Voltage Detect Status and Control 1 Register (PMC_LVDSC1)
315
Low Voltage Detect Status and Control 2 Register (PMC_LVDSC2)
316
Regulator Status and Control Register (PMC_REGSC)
318
Low-Leakage Wake-Up Unit (LLWU)
321
Introduction
321
Features
322
Modes of Operation
322
Block Diagram
323
LLWU Signal Descriptions
324
Memory Map/Register Definition
325
LLWU Pin Enable 1 Register (LLWU_PE1)
325
LLWU Pin Enable 2 Register (LLWU_PE2)
326
LLWU Pin Enable 3 Register (LLWU_PE3)
328
LLWU Pin Enable 4 Register (LLWU_PE4)
329
LLWU Module Enable Register (LLWU_ME)
330
LLWU Flag 1 Register (LLWU_F1)
331
LLWU Flag 2 Register (LLWU_F2)
333
LLWU Flag 3 Register (LLWU_F3)
335
LLWU Control and Status Register (LLWU_CS)
336
Functional Description
337
LLS Mode
338
VLLS Modes
338
Initialization
339
Low Power Mode Recovery
339
Miscellaneous Control Module (MCM)
341
Introduction
341
Features
341
Memory Map/Register Descriptions
341
Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)
342
Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)
342
SRAM Arbitration and Protection (MCM_SRAMAP)
343
Interrupt Status Register (MCM_ISR)
344
ETB Counter Control Register (MCM_ETBCC)
345
ETB Reload Register (MCM_ETBRL)
346
ETB Counter Value Register (MCM_ETBCNT)
347
Functional Description
347
Interrupts
347
Crossbar Switch (AXBS)
349
Introduction
349
Features
349
Memory Map / Register Definition
350
Priority Registers Slave (Axbs_Prsn)
351
Control Register (Axbs_Crsn)
354
Master General Purpose Control Register (Axbs_Mgpcrn)
356
Functional Description
357
General Operation
357
Register Coherency
358
Arbitration
358
Initialization/Application Information
361
Memory Protection Unit (MPU)
363
Introduction
363
Overview
363
Block Diagram
363
Features
364
Memory Map/Register Definition
365
Control/Error Status Register (MPU_CESR)
368
Error Address Register, Slave Port N (Mpu_Earn)
370
Error Detail Register, Slave Port N (Mpu_Edrn)
371
Region Descriptor N, Word 0 (Mpu_Rgdn_Word0)
372
Region Descriptor N, Word 1 (Mpu_Rgdn_Word1)
373
Region Descriptor N, Word 2 (Mpu_Rgdn_Word2)
373
Region Descriptor N, Word 3 (Mpu_Rgdn_Word3)
376
Region Descriptor Alternate Access Control N (Mpu_Rgdaacn)
377
Functional Description
379
Access Evaluation Macro
379
Putting It All Together and Error Terminations
380
Power Management
381
Initialization Information
381
Application Information
381
Peripheral Bridge (AIPS-Lite)
385
Introduction
385
Features
385
General Operation
385
Memory Map/Register Definition
386
Master Privilege Register a (Aipsx_Mpra)
387
Peripheral Access Control Register (Aipsx_Pacrn)
391
Peripheral Access Control Register (Aipsx_Pacrn)
396
Functional Description
401
Access Support
401
Direct Memory Access Multiplexer (DMAMUX)
403
Introduction
403
Overview
403
Features
404
Modes of Operation
404
External Signal Description
405
Memory Map/Register Definition
405
Channel Configuration Register (Dmamux_Chcfgn)
406
Functional Description
407
DMA Channels with Periodic Triggering Capability
407
DMA Channels with no Triggering Capability
410
Always Enabled" DMA Sources
410
Initialization/Application Information
411
Reset
411
Enabling and Configuring Sources
411
Direct Memory Access Controller (Edma)
415
Introduction
415
Block Diagram
415
Block Parts
416
Features
418
Modes of Operation
419
Memory Map/Register Definition
419
Control Register (DMA_CR)
434
Error Status Register (DMA_ES)
436
Enable Request Register (DMA_ERQ)
438
Enable Error Interrupt Register (DMA_EEI)
440
Clear Enable Error Interrupt Register (DMA_CEEI)
442
Set Enable Error Interrupt Register (DMA_SEEI)
443
Clear Enable Request Register (DMA_CERQ)
444
Set Enable Request Register (DMA_SERQ)
445
Clear DONE Status Bit Register (DMA_CDNE)
446
Set START Bit Register (DMA_SSRT)
447
Clear Error Register (DMA_CERR)
448
Clear Interrupt Request Register (DMA_CINT)
449
Interrupt Request Register (DMA_INT)
449
Error Register (DMA_ERR)
452
Hardware Request Status Register (DMA_HRS)
454
Channel N Priority Register (Dma_Dchprin)
456
TCD Source Address (Dma_Tcdn_Saddr)
457
TCD Signed Source Address Offset (Dma_Tcdn_Soff)
458
TCD Transfer Attributes (Dma_Tcdn_Attr)
458
TCD Minor Byte Count (Minor Loop Disabled) (Dma_Tcdn_Nbytes_Mlno)
459
TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (Dma_Tcdn_Nbytes_Mloffno)
460
TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
461
(Dma_Tcdn_Nbytes_Mloffyes)
461
TCD Last Source Address Adjustment (Dma_Tcdn_Slast)
462
TCD Destination Address (Dma_Tcdn_Daddr)
462
TCD Signed Destination Address Offset (Dma_Tcdn_Doff)
463
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (Dma_Tcdn_Citer_Elinkyes)
463
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (Dma_Tcdn_Citer_Elinkno)
464
TCD Last Destination Address Adjustment/Scatter Gather Address (Dma_Tcdn_Dlastsga)
465
TCD Control and Status (Dma_Tcdn_Csr)
466
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (Dma_Tcdn_Biter_Elinkyes)
468
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
469
(Dma_Tcdn_Biter_Elinkno)
469
Functional Description
470
Edma Basic Data Flow
470
Error Reporting and Handling
473
Channel Preemption
475
Performance
475
Initialization/Application Information
480
Edma Initialization
480
Programming Errors
482
Arbitration Mode Considerations
482
Performing DMA Transfers
483
Monitoring Transfer Descriptor Status
487
Channel Linking
489
Dynamic Programming
490
External Watchdog Monitor (EWM)
493
Introduction
493
Features
493
Modes of Operation
494
Block Diagram
495
EWM Signal Descriptions
496
Memory Map/Register Definition
496
Control Register (EWM_CTRL)
496
Service Register (EWM_SERV)
497
Compare Low Register (EWM_CMPL)
498
Compare High Register (EWM_CMPH)
498
Functional Description
499
The Ewm_Out Signal
499
The Ewm_In Signal
500
EWM Counter
500
EWM Compare Registers
500
EWM Refresh Mechanism
501
Watchdog Timer (WDOG)
503
Introduction
503
Features
503
Functional Overview
505
Unlocking and Updating the Watchdog
506
The Watchdog Configuration Time (WCT)
507
Refreshing the Watchdog
508
Windowed Mode of Operation
508
Watchdog Disabled Mode of Operation
508
Low Power Modes of Operation
509
Debug Modes of Operation
509
Testing the Watchdog
510
Quick Test
510
Byte Test
510
Backup Reset Generator
512
Generated Resets and Interrupts
512
Memory Map and Register Definition
513
Watchdog Status and Control Register High (WDOG_STCTRLH)
514
Watchdog Status and Control Register Low (WDOG_STCTRLL)
516
Watchdog Time-Out Value Register High (WDOG_TOVALH)
516
Watchdog Time-Out Value Register Low (WDOG_TOVALL)
517
Watchdog Window Register High (WDOG_WINH)
517
Watchdog Window Register Low (WDOG_WINL)
518
Watchdog Refresh Register (WDOG_REFRESH)
518
Watchdog Unlock Register (WDOG_UNLOCK)
518
Watchdog Timer Output Register High (WDOG_TMROUTH)
519
Watchdog Timer Output Register Low (WDOG_TMROUTL)
519
Watchdog Reset Count Register (WDOG_RSTCNT)
520
Watchdog Prescaler Register (WDOG_PRESC)
520
Watchdog Operation with 8-Bit Access
520
General Guideline
521
Refresh and Unlock Operations with 8-Bit Access
521
Restrictions on Watchdog Operation
522
Multipurpose Clock Generator (MCG)
525
Introduction
525
Features
525
Modes of Operation
529
External Signal Description
529
Memory Map/Register Definition
529
MCG Control 1 Register (MCG_C1)
530
MCG Control 2 Register (MCG_C2)
531
MCG Control 3 Register (MCG_C3)
532
MCG Control 4 Register (MCG_C4)
533
MCG Control 5 Register (MCG_C5)
534
MCG Control 6 Register (MCG_C6)
536
MCG Status Register (MCG_S)
537
MCG Auto Trim Control Register (MCG_ATC)
539
MCG Auto Trim Compare Value High Register (MCG_ATCVH)
539
MCG Auto Trim Compare Value Low Register (MCG_ATCVL)
540
Functional Description
540
MCG Mode State Diagram
540
Low Power Bit Usage
545
MCG Internal Reference Clocks
545
External Reference Clock
546
MCG Fixed Frequency Clock
546
MCG PLL Clock
547
MCG Auto TRIM (ATM)
547
Initialization / Application Information
548
MCG Module Initialization Sequence
548
Using a 32.768 Khz Reference
550
MCG Mode Switching
551
Oscillator (OSC)
561
Introduction
561
Features and Modes
561
Block Diagram
562
OSC Signal Descriptions
562
External Crystal / Resonator Connections
563
External Clock Connections
564
Memory Map/Register Definitions
565
OSC Memory Map/Register Definition
565
Functional Description
566
OSC Module States
567
OSC Module Modes
568
Counter
570
Reference Clock Pin Requirements
570
Reset
570
Low Power Modes Operation
571
Interrupts
571
RTC Oscillator
573
Introduction
573
Features and Modes
573
Block Diagram
573
RTC Signal Descriptions
574
EXTAL32 - Oscillator Input
574
XTAL32 - Oscillator Output
574
External Crystal Connections
575
Memory Map/Register Descriptions
575
Functional Description
575
Reset Overview
576
Interrupts
576
Flash Memory Controller (FMC)
577
Introduction
577
Overview
577
Features
578
Modes of Operation
578
External Signal Description
578
Memory Map and Register Descriptions
579
Flash Access Protection Register (FMC_PFAPR)
585
Flash Bank 0 Control Register (FMC_PFB0CR)
588
Flash Bank 1 Control Register (FMC_PFB1CR)
591
Cache Tag Storage (Fmc_Tagvdw0Sn)
593
Cache Tag Storage (Fmc_Tagvdw1Sn)
594
Cache Tag Storage (Fmc_Tagvdw2Sn)
595
Cache Tag Storage (Fmc_Tagvdw3Sn)
596
Cache Data Storage (Upper Word) (Fmc_Dataw0Snu)
597
Cache Data Storage (Lower Word) (Fmc_Dataw0Snl)
598
Cache Data Storage (Upper Word) (Fmc_Dataw1Snu)
599
Cache Data Storage (Lower Word) (Fmc_Dataw1Snl)
600
Cache Data Storage (Upper Word) (Fmc_Dataw2Snu)
601
Cache Data Storage (Lower Word) (Fmc_Dataw2Snl)
602
Cache Data Storage (Upper Word) (Fmc_Dataw3Snu)
603
Cache Data Storage (Lower Word) (Fmc_Dataw3Snl)
604
Functional Description
604
Flash Memory Module (FTFL)
607
Introduction
607
Features
608
Block Diagram
610
Glossary
611
External Signal Description
613
Memory Map and Registers
613
Flash Configuration Field Description
614
Program Flash IFR Map
614
Data Flash IFR Map
615
Register Descriptions
617
Functional Description
630
Program Flash Memory Swap
630
Flash Protection
630
Flexnvm Description
633
Interrupts
637
Flash Operation in Low-Power Modes
638
Functional Modes of Operation
638
Flash Reads and Ignored Writes
638
Read While Write (RWW)
639
Flash Program and Erase
639
FTFL Command Operations
639
Margin Read Commands
648
FTFL Command Description
649
Security
677
Reset Sequence
679
Overview
681
Introduction
681
Features
682
Modes of Operation
682
External Signal Description
683
Ezport Clock (EZP_CK)
683
Ezport Chip Select (EZP_CS)
683
Ezport Serial Data in (EZP_D)
684
Ezport Serial Data out (EZP_Q)
684
Command Definition
684
Command Descriptions
685
Flash Memory Map for Ezport Access
691
Cyclic Redundancy Check (CRC)
693
Introduction
693
Features
693
Block Diagram
694
Modes of Operation
694
Memory Map and Register Descriptions
694
CRC Data Register (CRC_CRC)
695
CRC Polynomial Register (CRC_GPOLY)
696

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NXP Semiconductors freescale MK51DX256ZCMC10 Manuals

NXP Semiconductors freescale MK51DX256ZCMC10 Reference Manual (1611 pages)

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