NXP Semiconductors LPC2888 Manuals

Manuals and User Guides for NXP Semiconductors LPC2888. We have 2 NXP Semiconductors LPC2888 manuals available for free PDF download: User Manual, Getting Started

NXP Semiconductors LPC2888 User Manual (362 pages)

Brand: NXP Semiconductors | Category: Microcontrollers | Size: 2 MB

Chapter 1: Introductory Information

3
- Introduction
  3
- Features
  3
- Applications
  4
- Architectural Overview
  4
- ARM7TDMI Processor
  4
- On-Chip Flash Memory System
  5
- On-Chip Static RAM
  5
- On-Chip ROM
  5
- Block Diagram
  6
Chapter 2: LPC2800 Memory Addressing

7
Chapter 3: Boot Process

10
Chapter 4: Processor Cache and Memory Mapping

14
- Introduction
  14
- Features
  14
- Cache Definitions
  14
- Description
  15
- Cache Enabling and Function
  18
- Cache Function Details
  18
- Register Description
  18
- Cache Reset Status Register (CACHE_RST_STAT, 0X8010 4000)
  19
- Cache Settings Register
  20
- 0X8010 4004)
  20
- Cache Page Enable Control Register (CACHE_PAGE_CTRL, 0X8010 4008)
  21
- Cache Read Misses Counter
  22
- 0X8010 400C)
  22
- Cache Flushes Counter
  22
- 0X8010 4010)
  22
- Cache Write Misses Counter
  22
- 0X8010 4014)
  22
- Page Address Pointer Registers
  22
- (PAGE_ADDRESS0:15, 0X8010 4018:4054)
  22
- CPU Clock Gate Control
  23
- 0X8010 4058)
  23
- Cache Programming Procedures
  24
- Cache Initialization
  24
- Cache Flushing
  25
- Avoiding Cache Flushing
  26
- CPU and Cache Clocking
  26
- Introduction
  28
- Features
  28
- Description
  28
- Flash Organization
  28
- Flash Buffering
  28
- Wait State Programming
  30
- In-Application Flash Programming
  30
- Introduction
  30
- Sector Protection and Un-Protection
  32
- Erasing Sectors
  32
- Presetting Data Latches
  33
- Writing and Loading
  33
- Programming
  33
- Program/Erase Timer
  34
- Register Description
  34
- Flash Control Register (F_CTRL-0X8010 2000)
  35
- Flash Status Register (F_STAT - 0X8010 2004)
  36
- Flash Program Time Register
  37
- 0X8010 2008)
  37
- Flash Wait States Register
  37
- 0X8010 2010)
  37
- Flash Clock Divider Register
  37
- 0X8010 201C)
  37
- Interrupt Registers
  38
- Flash Interrupt Status Register
  38
- 0X8010 2FE0)
  38
- 0X8010 2FEC)
  38
- 0X8010 2FE8)
  39
- 0X8010 2FE4)
  39
- Flash Interrupt Enable Set Register
  39
- Flash Interrupt Enable Clear Register
  40
- 0X8000 5030)
  40
- 0X8000 5034)
  40
Chapter 6: DC-To-DC Converter

42
Chapter 7: Clock Generation Unit (CGU) and Power Control

51
- Features
  51
- Description
  51
- Register Descriptions
  53
- CGU Configuration Registers
  53
- Main PLL
  55
- Main PLL Example
  56
- High Speed PLL Overview
  57
- Deriving Control Register Values from Multiplier and Divisor Factors
  57
- Memory Table Mapping
  58
- Manual Memory Table Lookup
  58
- Common HP PLL Applications
  58
- High Speed PLL Registers
  59
- High Speed PLL Programming and Operation
  62
- Power-Down Procedure
  62
- Handshake Procedure
  62
- Lock Time-Outs
  63
- Selection Stage Registers
  63
- Selection Stage Programming
  65
- Fractional Divider Registers
  65
- Fractional Divider Programming
  66
- Spreading Stage Registers
  66
- Power Control Registers
  67
- Power Status Registers
  68
- Enable Select Registers
  69
- Software Reset Registers
  71
- Tabular Representation of the CGU
  72
- CGU Usage Notes
  75
- Example 1: Programming the MCI and the LCD Interface Using the CGU
  75
- Code Example
  76
- Example 2: Programming the USB, SDRAM, MCI, and LCD Interfaces Using the CGU
  77
- Code Example
  79
- Low Power Operations
  81
- Clock Generation Unit and Power Control
  81
- Processor Cache and Memory Mapping
  81
- Flash Interface and Programming
  82
- External Memory Controller
  82
- Real-Time Clock
  82
- Analog-To-Digital Converter
  82
- USB Controller
  82
- Dual-Channel 16-Bit Analog-To-Digital Converter
  83
- Dual-Channel 16-Bit Digital-To-Analog Converter 83 SD/MCI Card Interface
  83
Chapter 8: External Memory Controller (EMC)

84
Chapter 9: Interrupt Controller

117
- Features
  117
- Description
  117
- Interrupt Sources
  117
- Peripherals that Supply Multiple Interrupts
  119
- Register Description
  120
- Interrupt Controller Registers
  120
- Interrupt Request Registers
  121
- 0X8030 0200)
  122
- Vector Registers (INT_VECTOR0:1, 0X8030 0100 - 0X8030 0104)
  122
- Priority Mask Registers (INT_PRIOMASK0:1, 0X8030 0000 - 0X8030 0004)
  123
- Features Register
  123
- 0X8030 0300)
  123
- Spurious Interrupts
  123
- Case Studies on Spurious Interrupts
  124
- Workaround
  125
- To Disable Irqs
  125
- Solution 2: Disable Irqs and Fiqs Using Separate Writes to the CPSR
  125
- Solution 3: Re-Enable Fiqs at the Beginning of the IRQ Handler
  126
- Interrupt Controller Usage Notes
  126
- Features
  128
- Description
  128
- Register Descriptions
  128
- Timer Register Map
  128
- Load Registers
  129
- Value Registers
  129
- Control Registers
  129
- Interrupt Clear Registers
  129
- Features
  130
- Applications
  130
- Description
  130
- Register Description
  130
- 0X8000 2800)
  131
- 0X8000 2804)
  132
- 0X8000 2808)
  132
- Watchdog Prescale Register
  132
- 0X8000 280C)
  132
- Watchdog Match Control Register
  133
- 0X8000 2814)
  133
- 0X8000 2818)
  133
- 0X8000 281C)
  133
- 0X8000 283C)
  134
- Sample Setup
  134
- Block Diagram
  135
- Features
  136
- Description
  136
- Inputs
  136
- Register Descriptions
  138
- Input Group 0 Registers
  140
- Input Group 1 Registers
  141
- Input Group 2 Registers
  142
- Input Group 3 Registers
  143
- Event Router Output Register (EVOUT - 0X8000 0D40)
  143
- Features Register (EVFEATURES - 0X8000 0E00)
  144
Chapter 13: Real-Time Clock (RTC)

145
- Features
  145
- Description
  145
- Architecture
  145
- RTC Usage Notes
  145
- RTC Interrupts
  145
- Register Description
  146
- Miscellaneous Register Group
  147
- RTC Configuration Register (RTC_CFG - 0X8000 5024)
  147
- Interrupt Location Register
  147
- 0X8000 2000
  147
- Clock Tick Counter Register (CTCR - 0X8000 2004)
  148
- Clock Control Register (CCR - 0X8000 2008)
  148
- Counter Increment Interrupt Register (CIIR - 0X8000 200C)
  148
- Alarm Mask Register (AMR - 0X8000 2010) 149 Consolidated Time Registers
  149
- Consolidated Time Register 0 (CTIME0 - 0X8000 2014)
  150
- Consolidated Time Register 1 (CTIME1 - 0X8000 2018)
  150
- Consolidated Time Register 2 (CTIME2 - 0X8000 201C)
  150
- Time Counter Group
  151
- Leap Year Calculation
  151
- Alarm Register Group
  151
Chapter 14: Universal Asynchronous Receiver-Transmitter (UART)

153
Chapter 15: General Purpose DMA Controller (GPDMA)

177
- Introduction
  177
- Features of the GPDMA
  177
- Functional Overview
  177
- GPDMA Functional Description
  178
- APB Slave Interface
  178
- Bus and Transfer Widths
  178
- Endian Behavior
  178
- Error Conditions
  178
- DMA Request Priority
  179
- Interrupt Generation
  179
- GPDMA System Connections
  179
- GPDMA Registers
  180
- Summary of GPDMA Registers
  180
- GPDMA Register Descriptions
  181
- Source Address Registers (DMA[0
  181
- Destination Address Registers (DMA[0
  182
- Transfer Length Registers (DMA[0
  182
- Channel Configuration Registers (DMA[0
  183
- Channel Enable Registers (DMA[0
  184
- Transfer Count Registers
  184
- Alternate Source Address Registers (DMA[0
  184
- Alternate Destination Address Registers (DMA[0
  184
- 0X8010 3C00)
  185
- 0X8010 3C04)
  186
- 0X8010 3C08)
  187
- 0X8010 3C10)
  188
- DMA Channel 3 External Enable Register
  188
- DMA Channel 5 External Enable Register
  188
- Interrupt Requests
  188
- Scatter/Gather
  190
- Linked List Entry Format
  190
- Starting Linked List Operation
  191
- Operation of the List-Following Channel
  191
- Operation of the Block-Handling Channel
  191
- For a Block Entry
  191
- For a Last Entry
  192
- Variations on this Theme
  192
- Flow Control
  192
Chapter 16: I 2 C Controller

193
- Features
  193
- Applications
  193
- Description
  193
- Pin Description
  194
- I 2 C Operating Modes
  194
- Master Transmit Mode
  194
- Master Receive Mode
  195
- Slave Receive Mode
  195
- Slave Transmit Mode
  195
- Register Description
  195
- I 2 C Receive Register (I2RX - 0X8002 0800)
  197
- I 2 C Transmit Register (I2TX - 0X8002 0800)
  197
- C Status Register (I2STS - 0X8002 0804)
  198
- I 2 C Control Register (I2CTL - 0X8002 0808)
  199
- I 2 C Clock Divisor High Register (I2CLKHI - 0X8002 080C)
  199
- C Clock Divisor Low Register (I2CLKLO - 0X8002 0810)
  200
- I 2 C Slave Address Register (I2ADR - 0X8002 0814)
  200
- C Rx FIFO Level Register (I2RFL - 0X8002 0818)
  200
- C Tx FIFO Level Register (I2TFL - 0X8002 081C)
  200
- C Rx Byte Count Register (I2RXB - 0X8002 0820)
  200
- C Tx Byte Count Register (I2TXB - 0X8002 0824)
  201
- C Slave Transmit Register (I2TXS - 0X8002 0828)
  201
- C Slave Tx FIFO Level Register (I2STFL - 0X8002 082C)
  201
- Cycle
  201
- Selecting the Appropriate I C Data Rate and Duty
  202
- Details of I C Operating Modes
  202
- Initialization
  202
- Interrupt Enabling
  202
- Master Transmit Mode
  203
- Master Receive Mode
  204
- Slave Mode
  205
- Slave Receive Mode
  206
- Slave Transmit Mode
  206
Chapter 17: USB Device Controller

207
Chapter 18: Analog-To-Digital Converter (ADC)

246
- Features
  246
- Description
  246
- Pin Description
  246
- Register Description
  247
- A/D Control Register
  248
- A/D Select Register (ADCSEL-0X8000 2424)
  248
- A/D Result Registers (ADCR5:0 - 0X8000 2400:2414)
  249
- A/D Interrupt Enable Register (ADCINTE - 0X8000 2428)
  249
- A/D Interrupt Status Register (ADCINTS - 0X8000 242C)
  249
- A/D Interrupt Clear Register (ADCINTC - 0X8000 2430)
  249
- A/D Power down Register (ADCPD - 0X8000 5028)
  250
- Operation
  250
- Setting up the ADC
  250
- Single Mode Conversion
  250
- Continuous Mode Conversion
  250
- Stopping Continuous Mode Conversion
  251
- Features
  252
- Description
  252
- DAI Pins
  252
- DAI Registers
  252
- Stream I/O Configuration Register (SIOCR - 6.2 0X8020 0384)
  253
- I2S Format Register (I2S_FMT - 0X8020 6.4 0380)
  253
- Streaming Analog in (SAI1) Module
  253
- SAI1 Registers
  254
- Programming the DAI and SAI1
  256
- Setting up the DAI and SAI1
  256
- Fully Interrupt-Driven Data Transfer
  256
- Data Transfer Via DMA Channel(S)
  258
- Dynamic DMA Channel Assignment
  258
- Features
  259
- Description
  259
- DAO Pins
  259
- DAO Registers
  259
- Stream I/O Configuration Register (SIOCR - 0X8020 0384)
  260
- I2S Format Register (I2S_FMT - 0X8020 0380)
  260
- Streaming Analog out (SAO1) Module
  260
- SAO1 Registers
  261
- Programming the DAO and SAO1
  263
- Setting up the DAO and SAO1
  263
- Fully Interrupt-Driven Data Transfer
  263
- Data Transfer Via DMA Channel(S)
  264
- Dynamic DMA Channel Assignment
  265
- Features
  266
- Description
  266
- Dual ADC Pins
  266
- Dual ADC Block Diagrams
  267
- Dual ADC Registers
  267
- Stream I/O Configuration Register (SIOCR - 0X8020 0384)
  268
- Dual Analog in Control Register
  268
- Dual ADC Control Register
  269
- Decimator Control Register
  270
- Decimator Status Register
  270
- Simple Analog in (SAI4) Module
  271
- SAI4 Registers
  271
- Programming the Dual ADC and SAI4
  273
- Setting up the Dual ADC and SAI4
  273
- Reading Dual ADC Data
  273
- Features
  275
- Description
  275
- Dual DAC Pins
  276
- Registers
  276
- Stream I/O Configuration Register (SIOCR - 0X8020 0384)
  277
- Dual DAC Control Register (DDACCTRL - 0X8020 0398)
  277
- Dual DAC Status Register (DDACSTAT - 0X8020 039C) Read Only
  279
- Dual DAC Settings Register (DDACSET - 0X8020 03A0)
  279
- Streaming Analog out (SAO2) Module
  280
- SAO2 Registers
  280
- Programming the Dual DAC and SAO2
  282
- Setting up the Dual DAC and SAO2
  282
- Power-Up Procedure
  282
- Power-Down Procedure
  282
- SAO Programming
  283
Chapter 23: SD/MMC Interface

284
- Introduction
  284
- Features of the SD/MCI
  284
- SD/MMC Card Interface Pin Description
  284
- Functional Overview
  284
- Multimedia Card
  284
- Secure Digital Memory Card
  285
- Secure Digital Memory Card Bus Signals
  285
- MCI Adapter
  286
- Adapter Register Block
  286
- Control Unit
  286
- Command Path
  287
- Command Path State Machine
  287
- Command Format
  288
- Data Path
  290
- Data Path State Machine
  290
- Data Counter
  291
- Bus Mode
  292
- CRC Token Status
  292
- Status Flags
  293
- CRC Generator
  293
- Data FIFO
  293
- Transmit FIFO
  294
- Receive FIFO
  294
- APB Interfaces
  295
- Interrupt Logic
  295
- Register Description
  295
- Summary of SD/MCI Registers
  295
- Power Control Register (Mcipower - 0X8010 0000)
  296
- Clock Control Register
  296
- Argument Register (Mciargument - 0X8010 0008)
  297
- Command Register (Mcicommand - 0X8010 000C)
  297
- Command Response Register (Mcirespcommand - 0X8010 0010)
  298
- Response Registers (Mciresponse0-3 - 0X8010 0014, 018, 01C, 020)
  298
- Data Timer Register (Mcidatatimer - 0X8010 0024)
  298
- Data Length Register (Mcidatalength - 0X8010 0028)
  299
- Data Control Register
  299
- Data Counter Register (Mcidatacnt - 0X8010 0030)
  300
- Status Register (Mcistatus - 0X8010 0034). 300 Clear Register (Mciclear - 0X8010 0038)
  301
- Interrupt Mask Registers (Mcimask0-1 - 0X8010 003C, 0X8010 0040)
  301
- FIFO Counter Register (Mcififocnt - 0X8010 0048)
  302
- Data FIFO Register (MCIFIFO - 0X8010 0080 to 0X8010 00BC)
  303
Chapter 24: LCD Controller

304
- Features
  304
- Description
  304
- LCD Interface Pins
  304
- Register Descriptions
  305
- LCD Interface Register Map
  305
- Control Register (LCDCTRL - 0X8010 3004)
  306
- Status Register (LCDSTAT - 0X8010 3000)
  307
- Raw Interrupt Status Register (LCDISTAT - 0X8010 0008)
  307
- Interrupt Mask Register (LCDIMASK - 0X8010 3010)
  307
- Interrupt Clear Register
  308
- 308
  308
- Read Command Register (LCDREAD - 0X8010 3014)
  308
- Instruction Byte Register (LCDIBYTE - 0X8010 3020)
  308
- Data Byte Register (LCDDBYTE - 0X8010 3030)
  309
- Instruction Word Register (LCDIWORD - 0X8010 3040)
  309
- Data Word Register (LCDDWORD - 0X8010 3080)
  309
- LCD Interface Operation
  309
- Resetting a Remote Device
  309
- Programming the LCD Interface Clock
  309
- Setting the Control Register
  310
- Writing to a Remote Device
  310
- Reading from a Remote Device
  310
- Busy Checking
  310
- Busy Checking Vs. Instruction / Data Output
  311
Chapter 25: LPC2800 Pinning

312
- Features
  312
- Pinning
  312
- Pin Descriptions by Module
  312
- Alphabetical Pin Descriptions
  317
- Pin Allocation Table
  322
- Pad Layout
  325
- Pin Structure
  326
- Standard I/O Pins
  326
- External Memory Interface Pins
  326
- External Memory Interface Clock Output
  327
- Standard I/O Pins with Pull-Down
  328
- I 2 C Pins
  328
- Input Pins with Pull-Down
  328
- Input Pins with Pull-Up
  329
- Analog Input/Ouput Functions
  329
- Introduction
  331
- Features
  331
- Interrupts
  331
- Pin Description
  331
- Register Description
  333
- I/O Configuration
  333
- Port 0 (EMC) Registers
  335
- Port 1 (EMC) Registers
  335
- Port 2 (GPIO) Registers
  336
- Port 3 (DAI/DAO) Registers
  337
- Port 4 (LCD) Registers
  337
- Port 5 (MCI/SD) Registers
  338
- Port 6 (UART) Registers
  339
- Port 7 (USB) Registers
  339
- Abbreviations
  341
- Legal Information
  342
- Definitions
  342
- Disclaimers
  342
- Trademarks
  342
- Tables
  344
- Figures
  351
- Contents
  352

NXP Semiconductors LPC2888 Getting Started (25 pages)

Brand: NXP Semiconductors | Category: Computer Hardware | Size: 0 MB

Introduction
3
Basic Startup Code
4
Port Pins
5
Code Example
5
Clock Generation Unit (Using UART)
5
Basic Configuration
5
Code Example
6
Interrupt Handling (Using the Cache and Timer0)
11
Basic Configuration
11
Multiple Interrupt Sources for a Single Peripheral
11
Cache and Interrupt Vector Table (IVT) Configuration
12
Simple Interrupt Handling
13
Code Example
14
Startup Assembly Code
14
C Code
16
Flash Programming
19
Flash Programming Flowchart
19
Signature for Valid User Code
20
C Code
21
Legal Information
24
Definitions
24
Disclaimers
24
Trademarks
24
Contents
25

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NXP Semiconductors LPC2888 Manuals

NXP Semiconductors LPC2888 User Manual (362 pages)

Table of Contents

Chapter 1: Introductory Information

Chapter 2: LPC2800 Memory Addressing

Chapter 3: Boot Process

Chapter 4: Processor Cache and Memory Mapping

Chapter 6: DC-To-DC Converter

Chapter 7: Clock Generation Unit (CGU) and Power Control

Chapter 8: External Memory Controller (EMC)

Chapter 9: Interrupt Controller

Chapter 13: Real-Time Clock (RTC)

Chapter 14: Universal Asynchronous Receiver-Transmitter (UART)

Chapter 15: General Purpose DMA Controller (GPDMA)

Chapter 16: I 2 C Controller

Chapter 17: USB Device Controller

Chapter 18: Analog-To-Digital Converter (ADC)

Chapter 23: SD/MMC Interface

Chapter 24: LCD Controller

Chapter 25: LPC2800 Pinning

NXP Semiconductors LPC2888 Getting Started (25 pages)

Table of Contents

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