Nuvoton NUC970 series Manuals

Manuals and User Guides for Nuvoton NUC970 series. We have 1 Nuvoton NUC970 series manual available for free PDF download: Technical Reference Manual

Nuvoton NUC970 series Technical Reference Manual (1251 pages)

32-bit

Brand: Nuvoton | Category: Microcontrollers | Size: 9 MB

Table of Contents
3
List of Figures
12
List of Tables
17
General Description
18
Features
19
NUC970 Series Features
19
Parts Information List and Pin Configuration
27
NUC970 Series Part Number Naming Guide
27
Figure 3.1-1 NUC970 Series Part Number Naming Guide
27
NUC970 Series Part Selection Guide
28
Pin Configuration
29
Nuc972Dfxxy Pin Diagram
29
Figure 3.3-1 Nuc972Dfxxy LQFP 216-Pin Pin Diagram
29
Nuc976Dkxxy Pin Diagram
30
Figure 3.3-2 Nuc976Dkxxy LQFP 128-Pin Pin Diagram
30
Nuc977Dkxxy Pin Diagram
31
Figure 3.3-3 Nuc977Dkxxy LQFP 128-Pin Pin Diagram
31
Pin Description
32
Block Diagram
58
NUC970 Series Block Diagram
58
Figure 4.1-1 NUC970 Series Block Diagram
58
Functional Description
59
ARM ® ARM926EJ-S CPU Core
59
Overview
59
System Control Coprocessor (CP15)
60
Memory Management Unit (MMU)
60
Figure 5.1-1 ARM926EJ-S Block Diagram
60
Caches and Write Buffer
61
Bus Interface Unit
62
Power Management
62
System Manager
63
Overview
63
System Reset
63
System Power Distribution
64
Figure 5.2-1 NUC970 Series Power Distribution Diagram
64
System Memory Map
65
Table 5.2-1 Address Space Assignments for On-Chip Controllers
68
Power-On Setting
69
Register Map
71
Register Description
73
Clock Controller (CLK_CTL)
139
Overview
139
Features
139
Block Diagram
140
Figure 5.3-1 Clock Controller Block Diagram
141
Figure 5.3-2 ADC Controller Clock Divider Block Diagram
142
Figure 5.3-3 Emmc Host Controller Clock Divider Block Diagram
142
Figure 5.3-4 Enhanced Timer Clock Divider Clock Diagram
142
Figure 5.3-5 Ethernet MAC Controller Clock Divider Block Diagram
143
Figure 5.3-6 GPIO Clock Divider Block Diagram
143
Figure 5.3-7 I S Controller Clock Divider Block Diagram
143
Figure 5.3-8 KPI Controller Clock Divider Block Diagram
144
Figure 5.3-9 LCD Display Controller Clock Divider Block Diagram
144
Figure 5.3-10 Reference Clock Output Divider Block Diagram
144
Figure 5.3-11 SD Card Host Controller Clock Divider Block Diagram
145
Figure 5.3-12 Smart Card Host Controller Clock Divider Block Diagram
145
Figure 5.3-13 CMOS Sensor Controller Divider Block Diagram
145
Figure 5.3-14 UART Clock Divider Block Diagram
146
Figure 5.3-15 USB 1.1 Host Controller 48 Mhz Clock Divider Block Diagram
146
Figure 5.3-16 Watchdog Timer Clock Divider Block Diagram
146
Figure 5.3-17 Windowed Watchdog Timer Clock Divider Block Diagram
147
Figure 5.3-18 CPU_HCLK Clock Generator Block Diagram
148
Functional Description
149
Registers Map
151
Register Description
152
Advanced Interrupt Controller (AIC)
186
Overview
186
Features
186
Block Diagram
187
Functional Description
187
Figure 5.4-1 Advanced Interrupt Controller (AIC) Block Diagram
187
Register Map
192
Register Description
194
SDRAM Interface Controller (SDIC)
217
Overview
217
Features
217
Block Diagram
218
Figure 5.5-1 SDRAM Controller Block Diagram
218
Basic Configuration
219
Functional Description
219
Register Map
223
Register Description
223
Figure 5.5-2 Clock Delay Circuit
242
MTP Controller (MTP)
246
Overview
246
Features
246
Block Diagram
247
Figure 5.6-1 MTP Controller Block Diagram
247
Basic Configuration
248
Figure 5.6-2 MTP INTERFACE PIN DESCRIPTION
248
Functional Description
249
Software Programming Flow
250
Register Map
251
Register Description
252
External Bus Interface (EBI)
261
Overview
261
Features
261
Block Diagram
261
Figure 5.7-1 EBI Block Diagram
261
Basic Configuration
262
Functional Description
262
Register Map
263
Register Description
264
Figure 5.7-2 External I/O Write Operation Timing
271
Figure 5.7-3 External I/O Read Operation Timing
271
General Purpose I/O (GPIO)
272
Overview
272
Features
272
Block Diagram
273
Basic Configuration
273
Functional Description
273
Figure 5.8-1 GPIO Block Diagram
273
Register Map
274
Register Description
279
General DMA Controller (GDMA)
299
Overview
299
Features
299
Block Diagram
299
Figure 5.9-1 GDMA Block Diagram
299
Basic Configuration
300
Functional Description
300
Register Map
304
Register Description
305
Timer Controller (TMR)
322
Overview
322
Features
322
Block Diagram
323
Basic Configuration
323
Functional Description
323
Figure 5.10-1 Timer Controller Block Diagram
323
Register Map
325
Register Description
326
Enhance Timer Controller (ETMR)
332
Overview
332
Features
332
Block Diagram
332
Figure 5.11-1 Enhance Timer Controller Block Diagram
332
Basic Configuration
333
Functional Description
333
Figure 5.11-2 Enhance Timer Clock Controller Diagram
333
Figure 5.11-3 Timer Clock Controller Diagram
335
Register Map
336
Register Description
336
Pulse Width Modulation (PWM)
347
Overview
347
Features
347
Block Diagram
348
Basic Configuration
348
Functional Description
348
Figure 5.12-1 Two Channels of PWM in One Pair
348
Figure 5.12-2 Legend of Internal Comparator Output of PWM-Timer
349
Figure 5.12-3 PWM Double Buffer Illustration
349
Figure 5.12-4 PWM Controller Output Duty Ratio
350
Figure 5.12-5 Paired PWM Output with Dead Zone Generation Operation
350
Register Map
352
Register Description
353
Watchdog Timer (WDT)
363
Overview
363
Features
363
Block Diagram
363
Basic Configuration
363
Figure 5.13-1 Watchdog Timer Block Diagram
363
Functional Description
364
Figure 5.13-2 Watchdog Timer Clock Control
364
Figure 5.13-3 Watchdog Timer Time-Out Interval and Reset Period Timing
365
Table 5.13-1 Watchdog Time-Out Interval Period Selection
365
Table 5.13-2 Watchdog Reset Period Selection
365
Register Map
367
Register Description
368
Windowed Watchdog Timer (WWDT)
372
Overview
372
Features
372
Block Diagram
372
Basic Configuration
372
Figure 5.14-1 WWDT Block Diagram
372
Figure 5.14-2 WWDT Clock Control
372
Function Description
373
Table 5.14-1 Window Watchdog Prescaler Value Selection
373
Figure 5.14-3 WWDT Reset and Reload Behavior
375
Table 5.14-2 CMPDA Setting Limitation
376
Register Map
377
Register Description
378
Real Time Clock (RTC)
384
Overview
384
Features
384
Block Diagram
385
Basic Configuration
385
Functional Description
385
Figure 5.15-1 RTC Functional Block Diagram
385
Register Map
387
Register Description
389
UART Interface Controller (UART)
411
Overview
411
Features
412
Block Diagram
413
Figure 5.16-1 UART Block Diagram
413
Basic Configuration
414
Functional Description
414
Figure 5.16-2 Auto Flow Control Block Diagram
414
Figure 5.16-3 UART Line Control of Word and Stop Length Setting
415
Figure 5.16-4 UART Line Control of Parity Bit Setting
415
Table 5.16-1 Baud Rate Equation Table
416
Table 5.16-2 Baud Rate Equation Table
416
Figure 5.16-5 UART Auto-Flow Control Block Diagram
417
Figure 5.16-6 UART Ctsn Wake-Up Case 1
417
Figure 5.16-7 UART Ctsn Wake-Up Case 2
418
Figure 5.16-8 Irda Block Diagram
418
Figure 5.16-9 Irda TX/RX Timing Diagram
421
Figure 5.16-10 RS-485 Frame Structure
425
Figure 5.16-11 LIN Frame Structure
426
Figure 5.16-12 Break Detection in LIN Mode
429
Figure 5.16-13 Relationship between Break Detection and Frame Error Detection
430
Figure 5.16-14 LIN Sync Field Measurement
438
Figure 5.16-15 UA_BAUD Update Method
439
Table 5.16-3 UART Interrupt Sources and Flag List in Software Mode
442
Register Map
443
Register Description
445
Smart Card Host Interface (SC)
474
Overview
474
Features
474
Block Diagram
475
Figure 5.17-1 SC Clock Control Diagram (4-Bit Prescale Counter in Clock Controller)
475
Figure 5.17-2 SC Controller Block Diagram
475
Basic Configuration
476
Functional Description
476
Figure 5.17-3 SC Data Character
476
Table 5.17-1 SC Host Controller Pin Description
476
Table 5.17-2 UART Pin Description
476
Figure 5.17-4 SC Activation Sequence
477
Figure 5.17-5 SC Warm Reset Sequence
479
Figure 5.17-6 SC Deactivation Sequence
480
Figure 5.17-7 Basic Operation Flow
481
Figure 5.17-8 Initial Character TS
482
Figure 5.17-9 SC Error Signal
482
Register Map
486
Register Description
488
I 2 C Synchronous Serial Interface Controller (I 2 C)
516
Overview
516
Features
516
Block Diagram
517
Basic Configuration
517
Figure 5.18-1 I 2 C Block Diagram
517
Functional Description
518
Figure 5.18-2 I 2 C Bus Timing
518
Figure 5.18-3 Data Transfer on the I C-Bus
518
Figure 5.18-4 START and STOP Conditions
520
Figure 5.18-5 Bit Transfer on the I 2 C-Bus
521
Figure 5.18-6 Acknowledge on the I 2 C-Bus
521
Figure 5.18-7 Master Transmits Data to Slave
521
Figure 5.18-8 Master Reads Data from Slave
522
Figure 5.18-9 Write 1 Byte of Data to a Slave
523
Figure 5.18-10 Read a Byte of Data
524
Figure 5.18-11 Implementation of Software I C
524
Register Map
526
Register Description
527
SPI Interface Controller (SPI)
535
Overview
535
Features
535
Block Diagram
536
Basic Configuration
536
Figure 5.19-1 SPI Block Diagram
536
Function Description
537
Figure 5.19-2 Normal SPI Timing
538
Figure 5.19-3 Alternate Phase SCLK Clock Timing
539
Figure 5.19-4 Dual-IO Output Sequence
539
Figure 5.19-5 Dual-IO Input Sequence
540
Registers Map
542
Register Description
543
I 2 S Controller (I 2 S)
550
Overview
550
Features
550
Block Diagram
551
Basic Configuration
551
Figure 5.20-1 I 2 S Controller Block Diagram
551
Functional Description
552
Figure 5.20-2 I 2 S Interface Signal of Master Mode
552
Figure 5.20-3 I 2 S Interface Signal of Slave Mode
552
Figure 5.20-4 I 2 S MSB-Justified Format
553
Figure 5.20-5 PCM Mode Signal Interface
553
Figure 5.20-6 PCM Mode Interface Waveform
554
Register Map
555
Register Description
556
Ethernet MAC Controller (EMAC)
581
Overview
581
Features
581
Block Diagram
582
Basic Configuration
582
Figure 5.21-1 Ethernet MAC Controller Block Diagram
582
Functional Description
583
Table 5.21-1 Arbiter Arbitration Results
583
Figure 5.21-2 Ethernet Frame Format
584
Figure 5.21-3 64-Bit Reference Timing Counter
585
DMA Descriptors Data Structure
586
Figure 5.21-4 RXDMA Descriptor Data Structure
586
Figure 5.21-5 TXDMA Descriptor Data Structure
592
Register Map
599
Register Description
603
Table 5.21-2 Different CAMCMR Setting and Type of Received Packet
606
Figure 5.21-6 MII Management Frame Format
621
Table 5.21-3 MII Management Function Configure Sequence
621
USB 2.0 Device Controller (USBD)
656
Overview
656
Features
656
Block Diagram
657
Basic Configuration
657
Functional Description
657
Figure 5.22-1 USB Device Controller Block Diagram
657
Registers Map
660
Register Description
665
USB Host Controller (USBH)
717
Overview
717
Features
717
Block Diagram
718
Basic Configuration
718
Functional Description
718
Figure 5.23-1 USB Host Controller Block Diagram
718
Register Map
721
Register Description
723
Controller Area Network (CAN)
771
Overview
771
Features
771
Block Diagram
772
Figure 5.24-1 CAN Peripheral Block Diagram
772
Basic Configuration
773
Functional Description
773
Test Mode
774
Figure 5.24-2 CAN Core in Silent Mode
775
Figure 5.24-3 CAN Core in Loop Back Mode
775
Figure 5.24-4 CAN Core in Loop Back Mode Combined with Silent Mode
776
CAN Communications
777
Figure 5.24-5 Data Transfer between Ifn Registers and Message
779
Table 5.24-1 Initialization of a Transmit Object
781
Table 5.24-2 Initialization of a Receive Object
782
Figure 5.24-6 Application Software Handling of a FIFO Buffer
784
Figure 5.24-7 Bit Timing
786
Table 5.24-3 CAN Bit Time Parameters
786
Figure 5.24-8 Propagation Time Segment
787
Figure 5.24-9 Synchronization on "Late" and "Early" Edges
789
Figure 5.24-10 Filtering of Short Dominant Spikes
790
Figure 5.24-11 Structure of the CAN Core's CAN Protocol Controller
791
Register Map
795
Table 5.24-4 CAN Register Map for each Bit Function
800
Register Description
801
Table 5.24-5 Error Code
805
Table 5.24-6 Source of Interrupts
808
Table 5.24-7 IF1 and IF2 Message Interface Register
811
Table 5.24-8 Structure of a Message Object in the Message Memory
825
Flash Memory Interface (FMI)
836
Overview
836
Features
836
Block Diagram
837
Basic Configuration
837
Figure 5.25-1 FMI Block Diagram
837
Functional Description
838
Table 5.25-1 Number of Parity (Byte) for each BCH Algorithm
840
Figure 5.25-2 Data Arrangement for 2 Kb Page Size NAND Flash
841
Figure 5.25-3 Data Arrangement for 4 Kb Page Size NAND Flash
841
Figure 5.25-4 Data Arrangement for 8 Kb Page Size NAND Flash
842
Register Map
843
Register Description
846
Figure 5.25-5 PAD (Physical Address Descriptor) Table Format
848
Figure 5.25-6 PAD (Physical Address Descriptor) Table Fetch Modes
849
Secure Digital Host Controller (SDH)
907
Overview
907
Features
907
Block Diagram
907
Basic Configuration
908
Functional Description
908
Registers Map
910
Register Description
910
Figure 5.26-1 PAD (Physical Address Descriptor) Table Format
912
Figure 5.26-2 PAD (Physical Address Descriptor) Table Fetch Modes
913
Cryptographic Accelerator (CRYPTO)
933
Overview
933
Features
933
Block Diagram
934
Basic Configuration
934
Figure 5.27-1 Cryptographic Accelerator Block Diagram
934
Functional Description
935
Figure 5.27-2 PRNG Function Diagram
936
Figure 5.27-3 Electronic Codebook Mode
937
Figure 5.27-4 Cipher Block Chaining Mode
938
Figure 5.27-5 Cipher Feedback Mode
939
Figure 5.27-6 Output Feedback Mode
940
Figure 5.27-7 Counter Mode
941
Figure 5.27-8 CBC-CS1 Encryption
942
Figure 5.27-9 CBC-CS1 Decryption
942
Register Map
947
Register Description
953
Graphic Engine (GE2D)
1002
Overview
1002
Features
1002
Block Diagram
1003
Basic Configuration
1003
Functional Description
1003
Figure 5.28-1 2-D GE Engine Architecture
1003
Figure 5.28-2 Bitblt Direction
1005
Figure 5.28-3 Bresenham Line Drawing Octant
1006
Figure 5.28-4 Rotation Operation Octant
1007
Register Map
1008
Register Description
1010
JPEG Codec (JPEG)
1039
Overview
1039
Features
1039
Block Diagram
1040
Figure 5.29-1 JPEG Codec Block Diagram (Encode)
1040
Basic Configuration
1041
Figure 5.29-2 JPEG Codec Block Diagram (Decode)
1041
Functional Description
1042
Figure 5.29-3 Image Starting Address and Stride
1043
Figure 5.29-4 Primary and Thumbnail Encode
1044
Figure 5.29-5 Single Mode and Continue Mode
1045
Figure 5.29-6 Specified Window Decode Mode
1046
Register Map
1047
Register Description
1051
LCD Display Interface Controller (LCM)
1105
Overview
1105
Features
1105
Block Diagram
1106
Basic Configuration
1106
Figure 5.30-1 LCD Display Interface Controller Functional Block Diagram
1106
Functional Description
1107
Figure 5.30-2 Display and Overlay Control Timing
1107
Register Map
1110
Register Description
1112
Capture Sensor Interface Controller (CAP)
1161
Overview
1161
Feature
1161
Block Diagram
1162
Basic Configuration
1162
Figure 5.31-1 Image Capture Functional Block Diagram
1162
Functional Description
1163
Register Map
1166
Register Description
1167
Analog to Digital Converter (ADC)
1198
Overview
1198
Features
1198
Block Diagram
1199
Figure 5.32-1 ADC Functional Block Diagram
1199
Basic Configuration
1200
Functional Description
1200
Figure 5.32-2 ADC Transfer Function
1200
Figure 5.32-3 Simplified Sampling Diagram
1201
Figure 5.32-4 ADC Battery Voltage Detection Diagram
1202
Figure 5.32-5 Key Pad Detection Diagram
1203
Figure 5.32-6 4-Wire Touch Screen Connection Diagram
1204
Figure 5.32-7 5-Wire Touch Screen Connection Diagram
1204
Register Map
1206
Register Description
1207
Keypad Interface (KPI)
1231
Overview
1231
Features
1231
Block Diagram
1232
Figure 5.33-1 Keypad Controller Block Diagram
1232
Basic Configuration
1233
Functional Description
1233
Figure 5.33-2 Keypad Connection
1233
Figure 5.33-3 Keypad Interface
1233
Figure 5.33-4 4X8 Keypad Scan Timing Diagram
1234
Register Map
1235
Register Description
1236
Package Dimensions
1248
LQFP 216L (24X24X1.4Mm Footprint 2.0Mm)
1248
LQFP 128L (14X14X1.4Mm Footprint 2.0Mm)
1249

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Nuvoton NUC970 series Technical Reference Manual (1251 pages)

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