National Semiconductor MacPHYTER-II DP83816 Manuals

National Semiconductor MacPHYTER-II DP83816 Manuals

Manuals and User Guides for National Semiconductor MacPHYTER-II DP83816. We have 1 National Semiconductor MacPHYTER-II DP83816 manual available for free PDF download: Manual

National Semiconductor MacPHYTER-II DP83816 Manual

National Semiconductor MacPHYTER-II DP83816 Manual (108 pages)

10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer

Brand: National Semiconductor | Category: Network Card | Size: 0.87 MB

Table of Contents

Table of Contents
3
1 Connection Diagram

5
- LQFP Package (VNG)
  5
2 Pin Description

6
3 Functional Description

12
- Figure 3-1 DP83816 Functional Block Diagram
  12
  - Mac/Biu
    13
    
    PCI Bus Interface
    13
    
    Figure 3-2 MAC/BIU Functional Block Diagram
    13
    
    Tx MAC
    14
    
    Rx MAC
    14
  - Buffer Management
    14
    
    Tx Buffer Manager
    14
    
    Rx Buffer Manager
    14
    
    Packet Recognition
    14
    
    Mib
    15
  - Interface Definitions
    15
    
    PCI System Bus
    15
    
    Boot PROM
    15
    
    Eeprom
    15
    
    Clock
    15
    
    Figure 3-3 Ethernet Packet Format
    15
    
    Figure 3-4 DSP Physical Layer Block Diagram
    16
  - Physical Layer
    17
    
    Auto-Negotiation
    17
    
    Auto-Negotiation Register Control
    17
    
    Auto-Negotiation Parallel Detection
    17
    
    Auto-Negotiation Restart
    18
    
    Enabling Auto-Negotiation Via Software
    18
    
    Auto-Negotiation Complete Time
    18
  - LED Interfaces
    18
  - Figure 3-5 LED Loading Example
    18
  - Half Duplex Vs. Full Duplex
    19
  - Phy Loopback
    19
  - Status Information
    19
  - 100Base-Tx Transmitter
    19
    
    Code-Group Encoding and Injection
    20
    
    Scrambler
    20
    
    Figure 3-6 100BASE-TX Transmit Block Diagram
    20
    
    NRZ to NRZI Encoder
    21
    
    Binary to MLT-3 Convertor / Common Driver
    21
    
    Figure 3-7 Binary to MLT-3 Conversion
    21
    
    Table 3-1 4B5B Code-Group Encoding/Decoding
    21
  - 100BASE-TX Receiver
    22
    
    Input and Base Line Wander Compensation
    22
    
    Signal Detect
    22
    
    Figure 3-8 100 M/Bs Receive Block Diagram
    23
    
    Digital Adaptive Equalization
    24
    
    Figure 3-9 100BASE-TX BLW Event Diagram
    24
    
    Line Quality Monitor
    25
    
    To NRZI Decoder
    25
    
    Figure 3-10 EIA/TIA Attenuation Vs. Frequency for 0, 50, 100, 130 & 150 Meters of CAT V Cable
    25
    
    Figure 3-11 MLT-3 Signal Measured at AII after 0 Meters of CAT V Cable
    25
    
    Figure 3-12 MLT-3 Signal Measured at AII after 50 Meters of CAT V Cable
    25
    
    Figure 3-13 MLT-3 Signal Measured at AII after 100 Meters of CAT V Cable
    25
    
    Clock Recovery Module
    26
    
    NRZI to NRZ
    26
    
    Serial to Parallel
    26
    
    Scrambler
    26
    
    Code-Group Alignment
    26
    
    5B Decoder
    26
    
    100BASE-TX Link Integrity Monitor
    26
    
    Bad SSD Detection
    26
  - 10BASE-T Transceiver Module
    27
    
    Operational Modes
    27
    
    Smart Squelch
    27
    
    Collision Detection
    27
    
    Normal Link Pulse Detection/Generation
    27
    
    Figure 3-14 10BASE-T Twisted Pair Smart Squelch Operation
    27
    
    Jabber Function
    28
    
    Automatic Link Polarity Detection
    28
    
    10BASE-T Internal Loopback
    28
    
    Transmit and Receive Filtering
    28
    
    Transmitter
    28
    
    Receiver
    28
    
    Far End Fault Indication
    28
  - MII
    28
    
    MII Access Configuration
    28
    
    MII Serial Management
    28
    
    MII Serial Management Access
    29
    
    Serial Management Access Protocol
    29
    
    Nibble-Wide MII Data Interface
    29
    
    Figure 3-15 Typical MDC/MDIO Read Operation
    29
    
    Table 3-2 Typical MDIO Frame Format
    29
    
    Collision Detection
    30
    
    Carrier Sense
    30
    
    Figure 3-16 Typical MDC/MDIO Write Operation
    30
4 Register Set

31
5 Buffer Management

78
6 Power Management and Wake-On-LAN

88
- Introduction
  88
- Definitions (for this Document Only)
  88
- Packet Filtering
  88
- Power Management
  88
  - Table 6-1 Power Management Modes
    88
  - D0 State
    89
  - D1 State
    89
  - D2 State
    89
  - D3Cold State
    89
  - D3Hot State
    89
- Wake-On-LAN (WOL) Mode
  89
  - Entering WOL Mode
    89
  - Wake Events
    90
  - Exiting WOL Mode
    90
  - Table 6-2 PM Pin Configuration
    90
- Sleep Mode
  90
  - Entering Sleep Mode
    90
  - Exiting Sleep Mode
    90
- Pin Configuration for Power Management
  90
600 DC and AC Specifications

91
- DC Specifications
  91
- AC Specifications
  92
  - PCI Clock Timing
    92
  - X1 Clock Timing
    92
  - Power on Reset (PCI Active)
    93
  - Non Power on Reset
    93
  - POR PCI Inactive
    94
  - PCI Bus Cycles
    95
  - EEPROM Auto-Load
    100
  - Boot PROM/FLASH
    101
  - 100BASE-TX Transmit
    102
  - 10BASE-T Transmit End of Packet
    103
  - Mb/S Jabber Timing
    103
  - 10BASE-T Normal Link Pulse
    104
  - Auto-Negotiation Fast Link Pulse (FLP)
    104
  - Media Independent Interface (MII)
    105

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