Summary of Contents for National Semiconductor MacPHYTER-II DP83816
- Page 1 DP83816 DP83816 10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPhyter-II) Literature Number: SNLS164D...
- Page 2 — 3.3V signalling with 5V tolerant I/O. System Diagram PCI Bus 10/100 Twisted Pair DP83816 Isolation BIOS ROM EEPROM (optional) (optional) MacPHYTER-II is a trademark of National Semiconductor Corporation. Magic Packet is a trademark of Advanced Micro Devices, Inc. © 2005 National Semiconductor Corporation www.national.com...
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Page 3: Table Of Contents
Table of Contents Connection Diagram ....4 3.12.3 MII Serial Management Access ... . . 28 3.12.4 Serial Management Access Protocol . - Page 4 6.6 Sleep Mode ..... . . 89 5.1.3 Multiple Descriptor Packets ....80 5.1.4 Descriptor Lists .
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Page 5: Connection Diagram
1.0 Connection Diagram 1.1 144 LQFP Package (VNG) MA2/LED100N MA1/LED10N MA0/LEDACTN IAUXVDD VREF Pin1 RESERVED Identification MD4/EEDO AUXVDD TPRDM TPRDP IAUXVDD MD1/CFGDISN REGEN MWRN RESERVED MRDN MCSN DP83816 EESEL TPTDM RESERVED TPTDP AUXVDD PWRGOOD AUXVDD 3VAUX PMEN/CLKRUNN PCICLK INTAN RSTN GNTN PCIVDD REQN... -
Page 6: Pin Description
2.0 Pin Description PCI Bus Interface LQFP Pin Symbol No(s) Description AD[31-0] 66, 67, 68, 70, Address and Data: Multiplexed address and data bus. As a bus master, the 71, 72, 73, 74, DP83816 will drive address during the first bus phase. During subsequent phases, 78, 79, 81, 82, the DP83816 will either read or write data expecting the target to increment its 83, 86, 87, 88,... - Page 7 2.0 Pin Description (Continued) PCI Bus Interface LQFP Pin Symbol No(s) Description SERRN System Error: This signal is asserted low by DP83816 during address parity errors and system errors if enabled. STOPN Stop: This signal is asserted low by the target device to request the master device to stop the current transaction.
- Page 8 2.0 Pin Description (Continued) Media Independent Interface (MII) LQFP Pin Symbol No(s) Description Collision Detect: The COL signal is asserted high asynchronously by the external PMD upon detection of a collision on the medium. It will remain asserted as long as the collision condition persists.
- Page 9 2.0 Pin Description (Continued) 100BASE-TX/10BASE-T Interface LQFP Pin Symbol No(s) Description TPTDP, TPTDM 54, 53 Transmit Data: Differential common output driver. This differential common output is configurable to either 10BASE-T or 100BASE-TX signaling: 10BASE-T: Transmission of Manchester encoded 10BASE-T packet data as well as Link Pulses (including Fast Link Pulses for Auto-Negotiation purposes).
- Page 10 2.0 Pin Description (Continued) Clock Interface LQFP Pin Symbol No(s) Description Crystal/Oscillator Input: This pin is the primary clock reference input for the DP83816 and must be connected to a 25 MHz 0.005% (50ppm) clock source. The DP83816 device supports either an external crystal resonator connected across pins X1 and X2, or an external CMOS-level oscillator source connected to pin X1 only.
- Page 11 2.0 Pin Description (Continued) External Reference Interface LQFP Pin Symbol No(s) Description VREF Bandgap Reference: External current reference resistor for internal Phy bandgap circuitry. The value of this resistor is 10KΩ 1% metal film (100 ppm/ C) which must be connected from the VREF pin to analog ground. No Connects and Reserved LQFP Pin Symbol...
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Page 12: Functional Description
3.0 Functional Description DP83816 consists MAC/BIU (Media Access and an 802.3 MAC. The physical layer interface used is a Controller/Bus Interface Unit), a physical layer interface, single-port version of the 3.3V DsPhyterII. Internal memory SRAM, and miscellaneous support logic. The MAC/BIU consists of one - 0.5 KB and two - 2 KB SRAM blocks. -
Page 13: Mac/Biu
3.0 Functional Description (Continued) Data FIFO Tx MAC Tx Buffer Manager Data FIFO PCI Bus Interface Rx MAC Rx Buffer Manager Rx Filter Pkt Recog Logic SRAM MAC/BIU 93C46 Boot ROM/ Serial Flash EEPROM MAC/BIU Figure 3-2 Functional Block Diagram 3.1 MAC/BIU The MAC/BIU is a derivative design from the DP83810 control, serial EEPROM access with auto configuration... -
Page 14: Tx Mac
3.0 Functional Description (Continued) Little Endian (CFG:BEM=0): The byte orientation for transmit and receive. The buffer management scheme also receive and transmit data in system memory is as follows: uses separate buffers descriptors packet information. This allows effective transfers of data from the receive buffer to the transmit buffer by simply transferring the descriptor from the receive queue to the transmit queue. -
Page 15: Mib
3.0 Functional Description (Continued) DP83816 conforms to 3.3V AC/DC specifications, but has 5V tolerant inputs. 3.3.2 Boot PROM Data The BIOS ROM interface allows the DP83816 to read from and write data to an external ROM/Flash device. 46B-1500B 3.3.3 EEPROM The DP83816 supports the attachment of an external Note: B = Bytes EEPROM. -
Page 16: Figure 3-4 Dsp Physical Layer Block Diagram
3.0 Functional Description (Continued) MAC INTERFACE POWER ON SERIAL CONFIGURATION MANAGEMENT PINS RX_DATA RXCLK RX_DATA TX_DATA RXCLK TX_DATA TXCLK TRANSMIT CHANNELS & RECEIVE CHANNELS & REGISTERS STATE MACHINES STATE MACHINES 100 MB/S 10 MB/S 100 MB/S 10 MB/S 4B/5B 4B/5B PHY ADDRESS ENCODER DECODER... -
Page 17: Physical Layer
3.0 Functional Description (Continued) 3.4 Physical Layer operation when the Auto-Negotiation Enable bit (bit 12) is set. The DP83816 has a full featured physical layer device with The Basic Mode Status Register (BMSR) indicates the set integrated PMD sub-layers to support both 10BASE-T and of available abilities for technology types, Auto-Negotiation 100BASE-TX Ethernet protocols. -
Page 18: Auto-Negotiation Restart
3.0 Functional Description (Continued) mode, and any condition other than a single good link The LED100N pin indicates a good link at 100 Mb/s data occurs, then the parallel detect fault bit will set to a one, bit rate. The standard CMOS driver goes low when this 4 of the ANER register (98h). -
Page 19: Half Duplex Vs. Full Duplex
3.0 Functional Description (Continued) 3.6 Half Duplex vs. Full Duplex looped back. Therefore, in addition to serving as a board diagnostic, this mode serves as quick functional verification The DP83816 supports both half and full duplex operation of the device. at both 10 Mb/s and 100 Mb/s speeds. -
Page 20: Code-Group Encoding And Injection
3.0 Functional Description (Continued) TXCLK TXD(3:0)/TXER FROM CGM 4B5B CODE- GROUP ENABLER BP_4B5B 5B PARALLEL TO SERIAL SCRAMBLER BP_SCR NRZ TO NRZI ENCODER 100BASE-TX LOOPBACK BINARY TO MLT-3/ COMMON DRIVER TD +/- Figure 3-6 100BASE-TX Transmit Block Diagram 3.9.1 Code-group Encoding and Injection 3.9.2 Scrambler The code-group encoder converts 4-bit (4B) nibble data The scrambler is required to control the radiated emissions... -
Page 21: Nrz To Nrzi Encoder
3.0 Functional Description (Continued) 3.9.3 NRZ to NRZI Encoder 3.9.4 Binary to MLT-3 Convertor / Common Driver After the transmit data stream has been serialized and The Binary to MLT-3 conversion is accomplished by scrambled, the data must be NRZI encoded in order to converting the serial binary data stream output from the comply with the TP-PMD standard for 100BASE-TX NRZI encoder into two binary data streams with alternately... -
Page 22: 100Base-Tx Receiver
3.0 Functional Description (Continued) Table 3-1 4B5B Code-Group Encoding/Decoding Name PCS 5B Code-group Description/4B Value INVALID CODES 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 The 100BASE-TX MLT-3 signal sourced by the TD± 3.10.1 Input and Base Line Wander Compensation common driver output pins is slew rate controlled. -
Page 23: Figure 3-8 100 M/Bs Receive Block Diagram
3.0 Functional Description (Continued) RXD(3:0)/RXER RXCLK BP_RX BP_4B5B 4B/5B DECODER LINK INTEGRITY MONITOR SERIAL TO PARALLEL RX_DATA VALID CODE GROUP SSD DETECT ALIGNMENT BP_SCR DESCRAMBLER CLOCK CLOCK NRZI TO NRZ DECODER RECOVERY MODULE MLT-3 TO BINARY DECODER DIGITAL ADAPTIVE EQUALIZATION SIGNAL DETECT INPUT BLW... -
Page 24: Digital Adaptive Equalization
3.0 Functional Description (Continued) Figure 3-9 100BASE-TX BLW Event Diagram 3.10.3 Digital Adaptive Equalization it is sensitive to transformer mismatch, resistor variation and process induced offset. The DP83223V also required When transmitting data at high speeds over copper twisted an external attenuation network to help match the incoming pair cable, frequency dependent attenuation becomes a signal amplitude to the internal reference. -
Page 25: Line Quality Monitor
3.0 Functional Description (Continued) 2ns/div Figure 3-12 MLT-3 Signal Measured at AII after 50 meters of CAT V cable Figure 3-10 EIA/TIA Attenuation vs. Frequency for 0, 50, 100, 130 & 150 meters of CAT V cable 2ns/div 2ns/div Figure 3-11 MLT-3 Signal Measured at AII after 0 meters Figure 3-13 MLT-3 Signal Measured at AII after 100 of CAT V cable meters of CAT V cable... -
Page 26: Clock Recovery Module
3.0 Functional Description (Continued) 3.10.6 Clock Recovery Module recognize sufficient unscrambled IDLE code-groups within the 722 µs period, the entire de-scrambler will be forced The Clock Recovery Module (CRM) accepts 125 Mb/s out of the current state of synchronization and reset in MLT3 data from the equalizer. -
Page 27: 10Base-T Transceiver Module
3.0 Functional Description (Continued) 3.11 10BASE-T Transceiver Module The squelch circuitry employs a combination of amplitude and timing measurements (as specified in the IEEE 802.3 The 10BASE-T Transceiver Module is IEEE 802.3 10BASE-T standard) to determine the validity of data on compliant. -
Page 28: Jabber Function
3.0 Functional Description (Continued) 3.11.5 Jabber Function clock signals and data. The differential input must be externally terminated with a differential 100Ω termination The jabber function monitors the DP83816's output and network to accommodate UTP cable. The internal disables the transmitter if it attempts to transmit a packet of impedance of RD±... -
Page 29: Mii Serial Management Access
3.0 Functional Description (Continued) 3.12.3 MII Serial Management Access 3.12.4 Serial Management Access Protocol Management access PHY(s) done The serial control interface clock (MDC) has a maximum Management Data Clock (MDC) and Management Data clock rate of 25 MHz and no minimum rate. The MDIO line Input/Output (MDIO). -
Page 30: Collision Detection
3.0 Functional Description (Continued) MDIO (STA) 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHY Address Register Address Opcode Register Data Idle Idle Start (00h = BMCR) (Write) (PHYAD = 0Ch) Figure 3-16 Typical MDC/MDIO Write Operation... -
Page 31: Register Set
This field is read-only and is set to the device ID assigned by National Semiconductor to the DP83816, which is 0020h. 15-0 VENID Vendor ID This field is read-only and is set to a value of 100Bh which is National Semiconductor's PCI Vendor ID. www.national.com... -
Page 32: Configuration Command And Status Register
4.0 Register Set (Continued) 4.1.2 Configuration Command and Status Register The CFGCS register has two parts. The upper 16-bits (31-16) are devoted to device status. A status bit is reset whenever the register is written, and the corresponding bit location is a 1. The lower 16-bits (15-0) are devoted to command and are used to configure and control the device. -
Page 33: Configuration Revision Id Register
4.0 Register Set (Continued) Bit Name Description PERRSP Parity Error Response When set, DP83816 will assert PERRN on the detection of a data parity error when acting as the target, and will sample PERRN when acting as the initiator. Also, setting PERRSP allows SERREN to enable the assertion of SERRN. -
Page 34: Configuration Latency Timer Register
4.0 Register Set (Continued) 4.1.4 Configuration Latency Timer Register This register gives status and controls such miscellaneous functions as BIST, Latency timer and Cache line size. Tag: CFGLAT Size: 32 bits Hard Reset: 00000000h Offset: 0Ch Access: Read Write Soft Reset: Unchanged Bit Name Description BISTCAP... -
Page 35: Configuration Memory Address Register
4.0 Register Set (Continued) 4.1.6 Configuration Memory Address Register This register specifies the Base Memory address which is required to build an address map during configuration. It also specifies the number of bytes required as well as an indication that it can be mapped into memory space. Tag: CFGMA Size: 32 bits Hard Reset: 00000000h... -
Page 36: Boot Rom Configuration Register
4.0 Register Set (Continued) 4.1.8 Boot ROM Configuration Register Tag: CFGROM Size: 32 bits Hard Reset: 00000000h Offset: 30h Access: Read Write Soft Reset: unchanged Bit Name Description 31-16 ROMBASE ROM Base Address Set to the base address for the boot ROM. 15-11 ROMSIZE ROM Size... -
Page 37: Configuration Interrupt Select Register
4.0 Register Set (Continued) 4.1.10 Configuration Interrupt Select Register This register stores the interrupt line number as identified by the POST software that is connected to the interrupt controller as well as DP83816 desired settings for maximum latency and minimum grant. Max latency and Min latency can be loaded from the EEPROM. -
Page 38: Power Management Control And Status Register
4.0 Register Set (Continued) Bit Name Description 24-22 AUX_CURRENT Aux_Current This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function. If PMEN generation from D3cold is not supported by the function(PMCAP[31]), this field returns a value of "000b" when read. 3.3Vaux 24 23 22 Max. -
Page 39: Operational Registers
4.0 Register Set (Continued) 4.2 Operational Registers The DP83816 provides the following set of operational registers mapped into PCI memory space or I/O space. Writes to reserved register locations are ignored. Reads to reserved register locations return undefined values. Table 4-2 Operational Register Map Offset Description Access... -
Page 40: Command Register
4.0 Register Set (Continued) 4.2.1 Command Register This register is used for issuing commands to DP83816. These commands are issued by setting the corresponding bits for the function. A global software reset along with individual reset and enable/disable for transmitter and receiver are provided here. -
Page 41: Configuration And Media Status Register
4.0 Register Set (Continued) 4.2.2 Configuration and Media Status Register This register allows configuration of a variety of device and phy options, and provides phy status information. Tag: CFG Size: 32 bits Hard Reset: 00000000h Offset: 0004h Access: Read Write Soft Reset: 00000000h Bit Name Description... - Page 42 4.0 Register Set (Continued) Bit Name Description PHY_RST Reset internal Phy Asserts reset to internal phy. Can be used to cause phy to reload options from the CFG register. This bit does not self clear when set. R/W PHY_DIS Disable internal Phy When set to a 1, this bit forces the internal phy to its low-power state.
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Page 43: Eeprom Access Register
4.0 Register Set (Continued) 4.2.3 EEPROM Access Register The EEPROM Access Register provides an interface for software access to the NMC9306 style EEPROM The default values given assume that the EEDO line has a pullup resistor to VDD. Tag: MEAR Size: 32 bits Hard Reset: 00000002h Offset: 0008h... -
Page 44: Pci Test Control Register
4.0 Register Set (Continued) PMATCH[47:0] can be accessed via the combination of the RFCR (offset 0048h) and RFDR (offset 004Ch) registers. PMATCH holds the Ethernet address info. See Section 3.3.3. The lower 8 bits of the checksum value should be 55h. For the upper 8 bits, add the top 8 data bits to the lower 8 data bits for each address. -
Page 45: Interrupt Status Register
4.0 Register Set (Continued) 4.2.6 Interrupt Status Register This register indicates the source of an interrupt when the INTA pin goes active. Enabling the corresponding bits in the Interrupt Mask Register (IMR) allows bits in this register to produce an interrupt. When an interrupt is active, one or more bits in this register are set to a “1”. -
Page 46: Interrupt Mask Register
4.0 Register Set (Continued) Bit Name Description TXDESC Tx Descriptor This event is signaled after a transmit descriptor when the INTR bit in the CMDSTS field has been updated. TXOK Tx Packet OK This event is signaled after the last transmit descriptor in a successful transmission attempt has been updated with valid status. - Page 47 4.0 Register Set (Continued) Bit Name Description RTABT Received Target Abort When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. 19-17 unused RXSOVR Rx Status FIFO Overrun When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. HIERR High Bits Error When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
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Page 48: Interrupt Enable Register
4.0 Register Set (Continued) 4.2.8 Interrupt Enable Register The Interrupt Enable Register controls the hardware INTR signal. Tag: IER Size: 32 bits Hard Reset: 00000000h Offset: 0018h Access: Read Write Soft Reset: 00000000h Bit Name Description 31-1 unused Interrupt Enable When set to 1, the hardware INTR signal is enabled. -
Page 49: Transmit Descriptor Pointer Register
4.0 Register Set (Continued) 4.2.10 Transmit Descriptor Pointer Register This register points to the current Transmit Descriptor. Tag: TXDP Size: 32 bits Hard Reset: 00000000h Offset: 0020h Access: Read Write Soft Reset: 00000000h Bit Name Description 31-2 TXDP Transmit Descriptor Pointer The current value of the transmit descriptor pointer. - Page 50 4.0 Register Set (Continued) Bit Name Description 27-26 Interframe Gap Time µ This field allows the user to adjust the interframe gap time below the standard 9.6 s @10 Mb/s and µ µ 960ns @100 Mb/s. The time can be programmed from 9.6 s to 8.4 s @10 Mb/s and 960ns to 840ns @100 Mb/s.
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Page 51: Receive Descriptor Pointer Register
4.0 Register Set (Continued) 4.2.12 Receive Descriptor Pointer Register This register points to the current Receive Descriptor. Tag: RXDP Size: 32 bits Hard Reset: 00000000h Offset: 0030h Access: Read Write Soft Reset: 00000000h Bit Name Description 31-2 RXDP Receive Descriptor Pointer The current value of the receive descriptor pointer. -
Page 52: Receive Configuration Register
4.0 Register Set (Continued) 4.2.13 Receive Configuration Register This register is used to set the receive configuration for DP83816. Receive properties such as accepting error packets, runt packets, setting the receive drain threshold etc. are controlled here. Tag: RXCFG Size: 32 bits Hard Reset: 00000002h Offset: 0034h Access: Read Write... -
Page 53: Clkrun Control/Status Register
4.0 Register Set (Continued) Bit Name Description DRTH Rx Drain Threshold Specifies the drain threshold in units of 8 bytes. When the number of bytes in the receive FIFO reaches this value (times 8), or the FIFO contains a complete packet, the receive bus master state machine will begin the transfer of data from the FIFO to host memory. - Page 54 4.0 Register Set (Continued) 4.2.14.1 CLKRUNN Function Situation 1 is a “clock continue” event and can occur if the DP83816 has not completed a pending packet transmit or CLKRUNN is a dual-function optional signal. It is used by receive. Situation 2 is a “clock start” event and can occur if the central PCI clock resource to indicate clock status (i.e.
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Page 55: Wake Command/Status Register
4.0 Register Set (Continued) 4.2.15 Wake Command/Status Register The WCSR register is used to configure/control and monitor the DP83816 Wake On LAN logic. The Wake On LAN logic is used to monitor the incoming packet stream while in a low-power state, and provide a wake event to the system if the desired packet type, contents, or Link change are detected. - Page 56 4.0 Register Set (Continued) Bit Name Description WKPAT0 Wake on Pattern 0 match Enable wake on match of pattern 0. R/W WKARP Wake on ARP Enable wake on ARP packet detection. R/W WKBCP Wake on Broadcast Enable wake on broadcast packet detection. R/W WKMCP Wake on Multicast Enable wake on multicast packet detection.
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Page 57: Pause Control/Status Register
4.0 Register Set (Continued) 4.2.16 Pause Control/Status Register The PCR register is used to control and monitor the DP83816 Pause Frame reception logic. The Pause Frame reception Logic is used to accept 802.3x Pause Frames, extract the pause length value, and initiate a TX MAC pause interval of the specified number of slot times. -
Page 58: Receive Filter/Match Control Register
4.0 Register Set (Continued) 4.2.17 Receive Filter/Match Control Register The RFCR register is used to control and configure the DP83816 Receive Filter Control logic. The Receive Filter Control Logic is used to configure destination address filtering of incoming packets. Tag: RFCR Size: 32 bits Hard Reset: 00000000h Offset: 0048h... -
Page 59: Receive Filter/Match Data Register
4.0 Register Set (Continued) Bit Name Description RFADDR Receive Filter Extended Register Address Selects which internal receive filter register is accessible via RFDR: Perfect Match Register (PMATCH) 000h - PMATCH octets 1-0 002h - PMATCH octets 3-2 004h - PMATCH octets 5-4 Pattern Count Registers (PCOUNT) 006h - PCOUNT1, PCOUNT0... -
Page 60: Receive Filter Logic
4.0 Register Set (Continued) 4.2.19 Receive Filter Logic The Receive Filter Logic supports a variety of techniques Accept on Pattern Match for qualifying incoming packets. The most basic filtering The Receive Filter Logic provides access to 4 separate options include Accept All Broadcast, Accept All Multicast internal RAM-based pattern buffers to be used as and Accept All Unicast packets. -
Page 61: Figure 4-1 Pattern Buffer Memory - 180H Words (Word = 18Bits)
4.0 Register Set (Continued) Pattern3Word7F byte1 byte0 Pattern2Word7F byte1 byte0 Pattern3Word7E byte1 byte0 Pattern2Word7E byte1 byte0 Pattern3Word1 byte1 byte0 Pattern2Word1 byte1 byte0 Pattern3Word0 byte1 byte0 Pattern2Word0 byte1 byte0 Pattern1Word3F byte1 byte0 Pattern0Word3F byte1 byte0 Pattern1Word3E byte1 byte0 Pattern0Word3E byte1 byte0 Pattern1Word1 byte1 byte0... - Page 62 4.0 Register Set (Continued) Example: Pattern match on the following destination addresses: 02-00-03-01-04-02 12-10-13-11-14-12 22-20-23-21-24-22 32-30-33-31-34-32 set $PATBUF01 = 280 set $PATBUF23 = 300 # write counts iow l $RFCR (0006) # pattern count registers 1, 0 iow l $RFDR (0406) # count 1 = 4, count 0= 6 iow l $RFCR (0008) # pattern count registers 3, 2...
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Page 63: Figure 4-2 Hash Table Memory - 40H Bytes Addressed On Word Boundaries
4.0 Register Set (Continued) Accept on Multicast or Unicast Hash Multicast and Unicast addresses may be further qualified Hash Table memory. The upper 4 bits represent the word by use of the receive filter hash functions. An internal 512 address and the lower 5 bits select the bit within the word. bit (64 byte) RAM-based hash table is used to perform If the corresponding bit is set, then the packet is accepted, imperfect filtering of multicast or unicast packets. -
Page 64: Boot Rom Address Register
4.0 Register Set (Continued) 4.2.20 Boot ROM Address Register The BRAR is used to setup the address for an access to an external ROM/FLASH device. Tag: BRAR Size: 32 bits Hard Reset: FFFFFFFFh Offset: 0050h Access: Read Write Soft Reset: unchanged Bit Name Description AUTOINC... -
Page 65: Management Information Base Control Register
4.0 Register Set (Continued) 4.2.23 Management Information Base Control Register The MIBC register is used to control access to the statistics block and the warning bits and to control the collection of management information statistics. Tag: MIBC Size: 32 bits Hard Reset: 00000002h Offset: 005ch Access: Read Write... -
Page 66: Management Information Base Registers
4.0 Register Set (Continued) 4.2.24 Management Information Base Registers The counters provide a set of statistics compliant with the "software" counters must be updated. Sizes for specific following management specifications: MIB II, Ether-like hardware statistic counters were chosen such that the MIB, and IEEE MIB. -
Page 67: Internal Phy Registers
4.0 Register Set (Continued) 4.3 Internal PHY Registers The Internal Phy Registers are only 16 bits wide. Bits [31:16] are not used. In the following register definitions under the ‘Default’ heading, the following definitions hold true: — RW=Read Write access —... -
Page 68: Basic Mode Status Register
4.0 Register Set (Continued) Bit Name Description Collision Test Collision Test: Default: 0 1 = Collision test enabled 0 = Normal operation When set, this bit will cause the COL signal to be asserted in response to the assertion of TXEN within 512-bit times. -
Page 69: Phy Identifier Register #1
A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management. National Semiconductor's IEEE assigned OUI is 080017h. Tag: PHYIDR1... -
Page 70: Auto-Negotiation Link Partner Ability Register
4.0 Register Set (Continued) Bit Name Description 100BASE-T4 Support: Default: 0/ RO 1= 100BASE-T4 is supported by the local device 0 = 100BASE-T4 not supported TX_FD 100BASE-TX Full Duplex Support: Default: dependent on setting of the ANEG_SEL in the CFG register 1 = 100BASE-TX Full Duplex is supported by the local device 0 = 100BASE-TX Full Duplex not supported 100BASE-TX Support: Default: dependent on the setting of the ANEG_SEL bits in the CFG register... -
Page 71: Auto-Negotiate Expansion Register
4.0 Register Set (Continued) Bit Name Description 10BASE-T Support: 1 = 10BASE-T is supported by the Link Partner 0 = 10BASE-T not supported by the Link Partner Selector Protocol Selection Bits: Link Partners’s binary encoded protocol selector. 4.3.7 Auto-Negotiate Expansion Register This register contains additional Local Device and Link Partner status information. -
Page 72: Phy Status Register
4.0 Register Set (Continued) Bit Name Description ACK2 Acknowledge2: Default: 0 1 = Will comply with message 0 = Cannot comply with message Acknowledge2 is used by the next page function to indicate that Local Device has the ability to comply with the message received. - Page 73 4.0 Register Set (Continued) Bit Name Description Remote Fault Remote Fault: 1 = Remote Fault condition detected (cleared on read of BMSR (address 0x84) register or by reset). Fault criteria: notification from Link Partner of Remote Fault via Auto-Negotiation 0 = No remote fault condition detected Jabber Detect Jabber Detect: This bit only has meaning in 10 Mb/s mode This bit is a duplicate of the Jabber Detect bit in the BMSR register, except that it is not cleared upon a read of the PHYSTS register.
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Page 74: Mii Interrupt Control Register
4.0 Register Set (Continued) 4.3.10 MII Interrupt Control Register This register implements the MII Interrupt PHY Specific Control register. Sources for interrupt generation include: Link State Change, Jabber Event, Remote Fault, Auto-Negotiation Complete or any of the counters becoming half-full. Note that the TINT bit operates independently of the INTEN bit. -
Page 75: False Carrier Sense Counter Register
4.0 Register Set (Continued) 4.3.12 False Carrier Sense Counter Register This counter provides information required to implement the “FalseCarriers” attribute within the MAU managed object class of Clause 30 of the IEEE 802.3u specification. Tag: FCSCR Size: 16 bits Hard Reset: 0000h Offset: 00D0h Access: Read Write Bit Name... -
Page 76: Phy Control Register
4.0 Register Set (Continued) Bit Name Description SD_OPTION Signal Detect Option: 1 = Enhanced signal detect algorithm 0 = Reduced signal detect algorithm Reserved Reserved: Read as 0 FORCE_100_OK Force 100 Mb/s Good Link: 1 = Forces 100 Mb/s Good Link 0 = Normal 100 Mb/s operation Reserved Reserved: Read as 0... -
Page 77: 10Base-T Status/Control Register
4.0 Register Set (Continued) 4.3.16 10BASE-T Status/Control Register Tag: TBTSCR Size: 16 bits Hard Reset: 0804h Offset: 00E8h Access: Read Write Bit Name Description 15:9 Unused LOOPBACK_10_DIS 10BASE-T Loopback Disable: This bit is OR’ed with bit 14 (Loopback) in the BMCR. 1 = 10 Mb/s Loopback is enabled 0 = 10 Mb/s Loopback is disabled LP_DIS... -
Page 78: Buffer Management
5.0 Buffer Management 5.1 Overview The buffer management scheme used on the DP83816 allows quick, simple and efficient use of the frame buffer The buffer management design has the following goals: memory. Frames are saved in similar formats for both —... -
Page 79: Table 5-3 Transmit Status Bit Definitions
5.0 Buffer Management (Continued) Packet OK In the last descriptor in a packet, this bit indicates that the packet was either sent or received successfully. 26-16 The usage of these bits differ in receive and transmit descriptors. See below for details. 15-12 (reserved) 11-0... -
Page 80: Single Descriptor Packets
5.0 Buffer Management (Continued) Table 5-4 Receive Status Bit Definitions Description Usage Receive Aborted Set to 1 by DP83816 when the receive was aborted, the value of this bit always equals RXO. Exists for backward compatibility. Receive Overrun Set to 1 by DP83816 to indicate that a receive overrun condition occurred. -
Page 81: Multiple Descriptor Packets
5.0 Buffer Management (Continued) 5.1.3 Multiple Descriptor Packets 5.1.4 Descriptor Lists A single packet may also cross descriptor boundaries. This Descriptors are organized in linked lists using the link field. is indicated by setting the MORE bit in all descriptors The system designer may also choose to implement a except the last one in the packet. -
Page 82: Transmit Architecture
5.0 Buffer Management (Continued) 5.2 Transmit Architecture The following figure illustrates the transmit architecture of the DP83816 10/100 Ethernet Controller. Software/Memory Hardware Current Tx Desc Ptr Transmit Descriptor TxHead link cmdsts Tx Desc Cache link cmdsts Tx Data FIFO Packet Tx DMA Figure 5-4 Transmit Architecture When the CR:TXE bit is set to 1 (regardless of the current state), and the DP83816 transmitter is idle, then DP83816 will... -
Page 83: Figure 5-5 Transmit State Diagram
5.0 Buffer Management (Continued) Table 5-5 Transmit State Tables State Event Next State Actions txIdle CR:TXE && !CTDD txDescRead Start a burst transfer at address TXDP and a length derived from TXCFG. CR:TXE && CTDD txDescRefr Start a burst transfer to refresh the link field of the current descriptor. -
Page 84: Transmit Data Flow
5.0 Buffer Management (Continued) 5.2.2 Transmit Data Flow MORE bit and the SIZE field from the cmdsts field of the current descriptor to know when packet In the DP83816 transmit architecture, packet transmission boundaries occur. involves the following steps: 8. When packet completed transmission... -
Page 85: Receive Architecture
5.0 Buffer Management (Continued) 5.3 Receive Architecture packets. When the amount of receive data in the RxDataFIFO is more than the RxDrainThreshold, or the The receive architecture is as "symmetrical" to the transmit RxDataFIFO contains a complete packet, then the state architecture as possible. -
Page 86: Table 5-6 Receive State Tables
5.0 Buffer Management (Continued) Table 5-6 Receive State Tables State Event Next State Actions rxIdle CR:RXE && !CRDD rxDescRead Start a burst transfer at address RXDP and a length derived from RXCFG. CR:RXE && CRDD rxDescRefr Start a burst transfer to refresh the link field of the current descriptor. -
Page 87: Receive Data Flow
5.0 Buffer Management (Continued) CR:RXE && CRDD rxDescRefr CR:RXE && !CRDD XferDone rxIdle XferDone && OWN link = NULL link != NULL rxAdvance rxDescRead XferDone && !OWN XferDone rxPktBytes == 0 FifoReady rxDescWrite rxFifoBlock rxFragWrite (descCnt == 0) && (rxPktBytes > 0) XferDone Figure 5-7 Receive State Diagram 5.3.2 Receive Data Flow... -
Page 88: Power Management And Wake-On-Lan
6.0 Power Management and Wake-On-LAN 6.1 Introduction • Magic Packet: “A specific packet of information sent to remotely wake up a sleeping or powered off PC on The DP83816 supports Wake-On-LAN (WOL) and the PCI a network, it is handled in the LAN controller. The Power Management Specification version 1.1. -
Page 89: D0 State
6.0 Power Management and Wake-On-LAN (Continued) 6.4.1 D0 State 6.5.1 Entering WOL Mode The D0 state is the normal operational state of the device. The following steps are required to place the DP83816 into The PME Enable bit should be set to 0 to prevent packet WOL mode: filtering based on the settings in the Wake Control/Status Disable the receiver by writing a 1 to the Receiver Dis-... -
Page 90: Wake Events
6.0 Power Management and Wake-On-LAN (Continued) 6.5.2 Wake Events 6.6 Sleep Mode If the device detects a wake event while in WOL mode, it Sleep Mode is a system-level function that allows a device will assert the PMEN pin low to signal the system that a to be placed in a lower power mode than WOL mode. -
Page 91: Dc And Ac Specifications
7.0 DC and AC Specifications Absolute Maximum Ratings Recommended Operating Conditions Supply Voltage (V -0.5 V to 3.6 V Supply voltage (V 3.3 Volts + 0.3V DC Input Voltage (V -0.5 V to 5.5 V Normal Operating Temperature (T 0 to 70 °C DC Output Voltage (V -0.5 V to V + 0.5 V... -
Page 92: Ac Specifications
7.0 DC and AC Specifications (Continued) 7.2 AC Specifications 7.2.1 PCI Clock Timing PCICLK Number Parameter Units PCICLK Low Time 7.2.1.1 PCICLK High Time 7.2.1.2 PCICLK Cycle Time ∞ 7.2.1.3 7.2.2 X1 Clock Timing Number Parameter Units X1 Low Time 7.2.2.1 X1 High Time 7.2.2.2... -
Page 93: Power On Reset (Pci Active)
7.0 DC and AC Specifications (Continued) 7.2.3 Power On Reset (PCI Active) Power Stable RSTN 1st PCI Cycle PCICLK Reset Complete Number Parameter Units RSTN Active Duration from PCICLK 7.2.3.1 stable Reset Disable to 1st PCI Cycle 7.2.3.2 EE Enabled 1500 EE Disabled Note: Minimum reset complete time is a function of the PCI, transmit, and receive clock frequencies. -
Page 94: Por Pci Inactive
7.0 DC and AC Specifications (Continued) 7.2.5 POR PCI Inactive EESEL TPRD Number Parameter Units VDD stable to EE access 7.2.5.1 VDD indicates the digital supply (AUX power plane, except PCI bus power.) Guaranteed by design. EE Configuration load duration 2000 7.2.5.2 www.national.com... -
Page 95: Pci Bus Cycles
7.0 DC and AC Specifications (Continued) 7.2.6 PCI Bus Cycles The following table parameters apply to ALL the PCI Bus Cycle Timing Diagrams contained in this section. Number Parameter Units Input Setup Time 7.2.6.1 Input Hold Time 7.2.6.2 Output Valid Delay 7.2.6.3 Output Float Delay (t time) - Page 96 7.0 DC and AC Specifications (Continued) PCI Configuration Write PCICLK FRAMEN T2 T1 AD[31:0] Addr Data C/BEN[3:0] IDSEL IRDYN TRDYN DEVSELN T1 T2 PERRN PCI Bus Master Read PCICLK FRAMEN AD[31:0] Addr Data C/BEN[3:0] IRDYN TRDYN DEVSELN PERRN www.national.com...
- Page 97 7.0 DC and AC Specifications (Continued) PCI Bus Master Write PCICLK FRAMEN AD[31:0] Addr Data C/BEN[3:0] IRDYN TRDYN DEVSELN PERRN PCI Target Read PCICLK FRAMEN T1 T2 AD[31:0] Data Addr C/BEN[3:0] IRDYN TRDYN DEVSELN T1 T2 PERRN www.national.com...
- Page 98 7.0 DC and AC Specifications (Continued) PCI Target Write PCICLK FRAMEN AD[31:0] Addr Data C/BEN[3:0] IRDYN TRDYN DEVSELN T1 T2 PERRN PCI Bus Master Burst Read PCICLK FRAMEN AD[31:0] Data Data Data Addr C/BEN[3:0] IRDYN TRDYN DEVSELN PERRN www.national.com...
- Page 99 7.0 DC and AC Specifications (Continued) PCI Bus Master Burst Write PCICLK FRAMEN AD[31:0] Data Addr Data Data C/BEN[3:0] IRDYN TRDYN DEVSELN PERRN PCI Bus Arbitration PCICLK REQN GNTN www.national.com...
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Page 100: Eeprom Auto-Load
7.0 DC and AC Specifications (Continued) 7.2.7 EEPROM Auto-Load EECLK EESEL EEDO EEDI Refer to NM93C46 data sheet Number Parameter Units EECLK Cycle Time 7.2.7.1 EECLK Delay from EESEL Valid 7.2.7.2 EECLK Low to EESEL Invalid 7.2.7.3 EECLK to EEDO Valid 7.2.7.4 EEDI Setup Time to EECLK 7.2.7.5... -
Page 101: Boot Prom/Flash
7.0 DC and AC Specifications (Continued) 7.2.8 Boot PROM/FLASH MCSN MRDN MA[15:0] MD[7:0] MWRN Number Parameter Units Data Setup Time to MRDN Invalid 7.2.8.1 Valid Address Setup Time to MRDN 7.2.8.2 Address Hold Time from MRDN Invalid 7.2.8.3 Address Invalid from MWRN Valid 7.2.8.4 MRDN Pulse Width 7.2.8.5... -
Page 102: 100Base-Tx Transmit
7.0 DC and AC Specifications (Continued) 7.2.9 100BASE-TX Transmit TPTD+/− +1 FALL +1 RISE -1 FALL -1 RISE TPTD+/− eye pattern Parameter Description Notes Units 100 Mb/s TPTD+/− Rise and see Test Conditions section 7.2.9.1 Fall Times 100 Mb/s Rise/Fall Mismatch 100 Mb/s TPTD+/−... -
Page 103: 10Base-T Transmit End Of Packet
7.0 DC and AC Specifications (Continued) 7.2.10 10BASE-T Transmit End of Packet TPTD+/- TPTD+/- Parameter Description Notes Units End of Packet High Time 10 Mb/s 7.2.10.1 (with ‘0’ ending bit) End of Packet High Time 10 Mb/s 7.2.10.2 (with ‘1’ ending bit) 7.2.11 10 Mb/s Jabber Timing TXE(Internal) +/−... -
Page 104: 10Base-T Normal Link Pulse
7.0 DC and AC Specifications (Continued) 7.2.12 10BASE-T Normal Link Pulse Parameter Description Notes Units Pulse Width 7.2.12.1 Pulse Period 7.2.12.2 Note: These specifications represent both transmit and receive timings 7.2.13 Auto-Negotiation Fast Link Pulse (FLP) Fast Link Pulse(s) clock data clock pulse... -
Page 105: Media Independent Interface (Mii)
7.0 DC and AC Specifications (Continued) 7.2.14 Media Independent Interface (MII) MDIO(output) MDIO(input) RXCLK RXD[3:0] RXDV,RXER TXCLK TXD[3:0] TXEN Number Parameter Units MDC to MDIO Valid 7.2.14.1 MDIO to MDC Setup 7.2.14.2 MDIO from MDC Hold 7.2.14.3 RXD to RXCLK Setup 7.2.14.4 RXD from RXCLK Hold 7.2.14.5... - Page 106 Notes: www.national.com...
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