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Manuals and User Guides for National Semiconductor DP83816AVNG. We have
1
National Semiconductor DP83816AVNG manual available for free PDF download: Manual
National Semiconductor DP83816AVNG Manual (108 pages)
10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer
Brand:
National Semiconductor
| Category:
Network Card
| Size: 0.87 MB
Table of Contents
Table of Contents
3
1 Connection Diagram
5
LQFP Package (VNG)
5
2 Pin Description
6
3 Functional Description
12
Figure 3-1 DP83816 Functional Block Diagram
12
Mac/Biu
13
PCI Bus Interface
13
Figure 3-2 MAC/BIU Functional Block Diagram
13
Tx MAC
14
Rx MAC
14
Buffer Management
14
Tx Buffer Manager
14
Rx Buffer Manager
14
Packet Recognition
14
Mib
15
Interface Definitions
15
PCI System Bus
15
Boot PROM
15
Eeprom
15
Clock
15
Figure 3-3 Ethernet Packet Format
15
Figure 3-4 DSP Physical Layer Block Diagram
16
Physical Layer
17
Auto-Negotiation
17
Auto-Negotiation Register Control
17
Auto-Negotiation Parallel Detection
17
Auto-Negotiation Restart
18
Enabling Auto-Negotiation Via Software
18
Auto-Negotiation Complete Time
18
LED Interfaces
18
Figure 3-5 LED Loading Example
18
Half Duplex Vs. Full Duplex
19
Phy Loopback
19
Status Information
19
100Base-Tx Transmitter
19
Code-Group Encoding and Injection
20
Scrambler
20
Figure 3-6 100BASE-TX Transmit Block Diagram
20
NRZ to NRZI Encoder
21
Binary to MLT-3 Convertor / Common Driver
21
Figure 3-7 Binary to MLT-3 Conversion
21
Table 3-1 4B5B Code-Group Encoding/Decoding
21
100BASE-TX Receiver
22
Input and Base Line Wander Compensation
22
Signal Detect
22
Figure 3-8 100 M/Bs Receive Block Diagram
23
Digital Adaptive Equalization
24
Figure 3-9 100BASE-TX BLW Event Diagram
24
Line Quality Monitor
25
To NRZI Decoder
25
Figure 3-10 EIA/TIA Attenuation Vs. Frequency for 0, 50, 100, 130 & 150 Meters of CAT V Cable
25
Figure 3-11 MLT-3 Signal Measured at AII after 0 Meters of CAT V Cable
25
Figure 3-12 MLT-3 Signal Measured at AII after 50 Meters of CAT V Cable
25
Figure 3-13 MLT-3 Signal Measured at AII after 100 Meters of CAT V Cable
25
Clock Recovery Module
26
NRZI to NRZ
26
Serial to Parallel
26
Scrambler
26
Code-Group Alignment
26
5B Decoder
26
100BASE-TX Link Integrity Monitor
26
Bad SSD Detection
26
10BASE-T Transceiver Module
27
Operational Modes
27
Smart Squelch
27
Collision Detection
27
Normal Link Pulse Detection/Generation
27
Figure 3-14 10BASE-T Twisted Pair Smart Squelch Operation
27
Jabber Function
28
Automatic Link Polarity Detection
28
10BASE-T Internal Loopback
28
Transmit and Receive Filtering
28
Transmitter
28
Receiver
28
Far End Fault Indication
28
MII
28
MII Access Configuration
28
MII Serial Management
28
MII Serial Management Access
29
Serial Management Access Protocol
29
Nibble-Wide MII Data Interface
29
Figure 3-15 Typical MDC/MDIO Read Operation
29
Table 3-2 Typical MDIO Frame Format
29
Collision Detection
30
Carrier Sense
30
Figure 3-16 Typical MDC/MDIO Write Operation
30
4 Register Set
31
Configuration Registers
31
Configuration Identification Register
31
Table 4-1 Configuration Register Map
31
Configuration Command and Status Register
32
Configuration Revision ID Register
33
Configuration Latency Timer Register
34
Configuration I/O Base Address Register
34
Configuration Memory Address Register
35
Configuration Subsystem Identification Register
35
Boot ROM Configuration Register
36
Capabilities Pointer Register
36
Configuration Interrupt Select Register
37
Power Management Capabilities Register
37
Power Management Control and Status Register
38
Operational Registers
39
Table 4-2 Operational Register Map
39
Command Register
40
Configuration and Media Status Register
41
EEPROM Access Register
43
EEPROM Map
43
PCI Test Control Register
44
Interrupt Status Register
45
Interrupt Mask Register
46
Interrupt Enable Register
48
Interrupt Holdoff Register
48
Transmit Configuration Register
49
Transmit Descriptor Pointer Register
49
Receive Descriptor Pointer Register
51
Receive Configuration Register
52
CLKRUN Control/Status Register
53
Wake Command/Status Register
55
Pause Control/Status Register
57
Receive Filter/Match Control Register
58
Receive Filter/Match Data Register
59
Receive Filter Logic
60
Figure 4-1 Pattern Buffer Memory - 180H Words (Word = 18Bits)
61
Figure 4-2 Hash Table Memory - 40H Bytes Addressed on Word Boundaries
63
Boot ROM Address Register
64
Boot ROM Data Register
64
Silicon Revision Register
64
Management Information Base Control Register
65
Management Information Base Registers
66
Table 4-3 MIB Registers
66
Internal PHY Registers
67
Basic Mode Control Register
67
Basic Mode Status Register
68
PHY Identifier Register #1
69
PHY Identifier Register #2
69
Auto-Negotiation Advertisement Register
69
Auto-Negotiation Link Partner Ability Register
70
Auto-Negotiate Expansion Register
71
Auto-Negotiation Next Page Transmit Register
71
PHY Status Register
72
MII Interrupt Control Register
74
MII Interrupt Status and Misc. Control Register
74
False Carrier Sense Counter Register
75
Receiver Error Counter Register
75
Mb/S PCS Configuration and Status Register
75
PHY Control Register
76
10BASE-T Status/Control Register
77
5 Buffer Management
78
Overview
78
Descriptor Format
78
Table 5-1 DP83816 Descriptor Format
78
Table 5-2 Cmdsts Common Bit Definitions
78
Table 5-3 Transmit Status Bit Definitions
79
Single Descriptor Packets
80
Figure 5-1 Single Descriptor Packets
80
Table 5-4 Receive Status Bit Definitions
80
Multiple Descriptor Packets
81
Descriptor Lists
81
Figure 5-2 Multiple Descriptor Packets
81
Figure 5-3 List and Ring Descriptor Organization
81
Transmit Architecture
82
Transmit State Machine
82
Figure 5-4 Transmit Architecture
82
Figure 5-5 Transmit State Diagram
83
Table 5-5 Transmit State Tables
83
Transmit Data Flow
84
Receive Architecture
85
Receive State Machine
85
Figure 5-6 Receive Architecture
85
Table 5-6 Receive State Tables
86
Receive Data Flow
87
Figure 5-7 Receive State Diagram
87
6 Power Management and Wake-On-LAN
88
Introduction
88
Definitions (for this Document Only)
88
Packet Filtering
88
Power Management
88
Table 6-1 Power Management Modes
88
D0 State
89
D1 State
89
D2 State
89
D3Cold State
89
D3Hot State
89
Wake-On-LAN (WOL) Mode
89
Entering WOL Mode
89
Wake Events
90
Exiting WOL Mode
90
Table 6-2 PM Pin Configuration
90
Sleep Mode
90
Entering Sleep Mode
90
Exiting Sleep Mode
90
Pin Configuration for Power Management
90
600 DC and AC Specifications
91
DC Specifications
91
AC Specifications
92
PCI Clock Timing
92
X1 Clock Timing
92
Power on Reset (PCI Active)
93
Non Power on Reset
93
POR PCI Inactive
94
PCI Bus Cycles
95
EEPROM Auto-Load
100
Boot PROM/FLASH
101
100BASE-TX Transmit
102
10BASE-T Transmit End of Packet
103
Mb/S Jabber Timing
103
10BASE-T Normal Link Pulse
104
Auto-Negotiation Fast Link Pulse (FLP)
104
Media Independent Interface (MII)
105
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