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National Instruments PXIe-7902 Manuals
Manuals and User Guides for National Instruments PXIe-7902. We have
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National Instruments PXIe-7902 manuals available for free PDF download: User Manual, Getting Started Manual
National Instruments
PXIe-6591R
User Manual
National Instruments PXIe-7902 User Manual (98 pages)
High-Speed Serial Instruments
Brand:
National Instruments
| Category:
Control Unit
| Size: 2 MB
Table of Contents
Table of Contents
7
About this Manual
12
Related Documentation
12
Table 1. Documentation Locations and Descriptions
12
Additional Resources
15
Table 2. Xilinx Documentation
15
Xilinx Documentation
15
Chapter 1
16
Before You Begin
16
Development Requirements
16
Table 1-1. Fundamentals Resources
16
Xilinx Licensing Information
17
Installation Instructions
17
Chapter 2
18
Pxie-6591R Hardware Architecture
18
Pxie-6591R Module Overview
19
Figure 2-1. Pxie-6591R System Architecture Elements
19
Table 2-1. Pxie-6591R Key Features
19
Clocking Architecture
20
Pxie-6591R Clocking
20
Table 2-2. Pxie-6591R Reference Clocks
20
Figure 2-2. Pxie-6591R Clocking Diagram
21
Chapter 3
22
Connecting and Interfacing with the Pxie-6591R
22
Front Panel
22
Figure 3-1. Pxie-6591R Front Panel Connectors and Pinouts
22
Recommended Mating Cables and Connectors
23
Transceiver Lane and Quad Mapping
23
Table 3-1. Pxie-6591R Front Panel Connectors
23
Table 3-2. Transceiver Lane and Quad Mapping
23
Signal Routing
24
Socketed CLIP Interface
24
Figure 3-2. Pxie-6591R Signal Routing
24
Table 3-3. Clock Signal and Quad Mapping
24
Figure 3-3. Pxie-6591R Socketed CLIP Diagram
25
Pxie-6591R Socketed CLIP
25
Table 3-4. Pxie-6591R CLIP Signals
25
Chapter 4
33
Pxie-6592R Hardware Architecture
33
Pxie-6592R Module Overview
34
Figure 4-1. Pxie-6592R System Architecture Elements
34
Table 4-1. Pxie-6592R Key Features
34
Clocking Architecture
35
Pxie-6592R Clocking
35
Table 4-3. Pxie-6592R Reference Clocks
35
Figure 4-2. Pxie-6592R Clocking Diagram
36
Chapter 5
37
Connecting and Interfacing with the Pxie-6592R
37
Front Panel
37
Recommended Mating Cables and Connectors
38
Transceiver Lane and Quad Mapping
38
Table 5-1. Pxie-6592R Front Panel Connectors
38
Table 5-2. Transceiver Lane and Quad Mapping
38
Signal Routing
39
Socketed CLIP Interface
39
Table 5-3. Clock Signal and Quad Mapping
39
Pxie-6592R Socketed CLIP
40
Table 5-4. Pxie-6592R CLIP Signals
40
Chapter 6
50
Pxie-7902 Hardware Architecture
50
Pxie-7902 Module Overview
50
Table 6-1. Pxie-7902 Key Features
50
Clocking Architecture
51
Pxie-7902 Clocking
51
Chapter 7 Connecting and Interfacing with the Pxie-7902
53
Front Panel
53
Recommended Mating Cables and Connectors
54
Transceiver Lane and Quad Mapping
54
Table 7-1. Pxie-7902 Front Panel Connectors
54
Table 7-2. Transceiver Lane and Quad Mapping
54
Signal Routing
55
Socketed CLIP Interface
55
Table 7-3. Clock Signal and Quad Mapping
55
Pxie-7902 Socketed CLIP
56
Table 7-4. Pxie-7902 Socketed CLIP Signals
56
Chapter 8
62
Developing Applications for the High-Speed Serial Device
62
Development Flow
62
Socketed CLIP Development
62
Accessing the Xilinx Vivado Tools
63
Exporting to Vivado
64
Generating an IP Core from the Xilinx Vivado IP Catalog
66
Modifying Third-Party IP Core Logic
66
Building a Netlist from the IP Core
67
Writing a VHDL Wrapper Around the Protocol IP Core
69
Constraints and Hierarchy
70
Documenting Your IP
71
Improving Performance in Larger Designs through Enable Chain Removal
71
Developing with Labview FPGA
72
Configuring the High-Speed Serial Device Labview FPGA Targets
72
Using Existing VHDL IP Inside CLIP or IPIN
76
Adding High-Speed Serial Device Target I/O
76
Using the ni Common Instrument Design Libraries
77
Using Niinstr Instruction Framework
77
Using Niinstr Streaming
79
Using Niinstr CLIP Adapters
79
Using Niinstr Data Trigger
79
Using Niinstr Basic Elements
79
Using Niinstr Eye Scan
79
Connecting AXI4-Lite and AXI4-Stream Interfaces to the Host
79
Connecting Signals to Enable Eye Scan
80
Compiling Labview FPGA Vis
82
Labview and System Integration
82
Download, Reset, and Run Side Effects in the Labview FPGA Host Interface
82
DMA Streaming
83
Peer-To-Peer Streaming
84
Maximizing Peer-To-Peer Streaming Throughput
84
PXI Triggers
84
Configuring Trigger Pulses
84
Reserving PXI Triggers
85
Reserving Trigger Lines in MAX
85
Reserving Trigger Lines in the Labview FPGA Host VI
85
Reserving Trigger Lines
85
Releasing Trigger Lines
86
Monitoring Power and Temperature
86
Soft Shutdown
87
Power/Thermal Protection and Shutdown
87
Debugging Clocks Using Frequency Counters
87
Debugging Link Connections Using Eye Scan
88
Rectangular Eye Scan
88
N Point Eye Scan
89
Eye Scan State Model
90
Appendix A
93
Appendix B
93
Table B-1. Xilinx 7-Series FPGA Documentation
93
Xilinx Documentation References
93
Appendix Cni Services
95
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National Instruments PXIe-7902 User Manual (98 pages)
High-Speed Serial Instruments
Brand:
National Instruments
| Category:
Network Hardware
| Size: 3 MB
Table of Contents
Legal Information
4
Electromagnetic Compatibility Information
6
Table of Contents
7
About this Manual
12
Related Documentation
12
Table 1. Documentation Locations and Descriptions
12
Xilinx Documentation
15
Additional Resources
15
Table 2. Xilinx Documentation
15
Before You Begin
16
Development Requirements
16
Table 1-1. Fundamentals Resources
16
Xilinx Licensing Information
17
Installation Instructions
17
Pxie-6591R Hardware Architecture
18
Pxie-6591R Module Overview
19
Figure 2-1. Pxie-6591R System Architecture Elements
19
Table 2-1. Pxie-6591R Key Features
19
Clocking Architecture
20
Pxie-6591R Clocking
20
Table 2-2. Pxie-6591R Reference Clocks
20
Figure 2-2. Pxie-6591R Clocking Diagram
21
Connecting and Interfacing with the Pxie-6591R
22
Front Panel
22
Figure 3-1. Pxie-6591R Front Panel Connectors and Pinouts
22
Recommended Mating Cables and Connectors
23
Transceiver Lane and Quad Mapping
23
Table 3-1. Pxie-6591R Front Panel Connectors
23
Table 3-2. Transceiver Lane and Quad Mapping
23
Signal Routing
24
Socketed CLIP Interface
24
Figure 3-2. Pxie-6591R Signal Routing
24
Table 3-3. Clock Signal and Quad Mapping
24
Pxie-6591R Socketed CLIP
25
Figure 3-3. Pxie-6591R Socketed CLIP Diagram
25
Table 3-4. Pxie-6591R CLIP Signals
25
Pxie-6592R Hardware Architecture
33
Pxie-6592R Module Overview
34
Figure 4-1. Pxie-6592R System Architecture Elements
34
Table 4-1. Pxie-6592R Key Features
34
Clocking Architecture
35
Pxie-6592R Clocking
35
Table 4-3. Pxie-6592R Reference Clocks
35
Figure 4-2. Pxie-6592R Clocking Diagram
36
Connecting and Interfacing with the Pxie-6592R
37
Front Panel
37
Recommended Mating Cables and Connectors
38
Transceiver Lane and Quad Mapping
38
Table 5-1. Pxie-6592R Front Panel Connectors
38
Table 5-2. Transceiver Lane and Quad Mapping
38
Signal Routing
39
Socketed CLIP Interface
39
Table 5-3. Clock Signal and Quad Mapping
39
Pxie-6592R Socketed CLIP
40
Table 5-4. Pxie-6592R CLIP Signals
40
Pxie-7902 Hardware Architecture
50
Pxie-7902 Module Overview
50
Table 6-1. Pxie-7902 Key Features
50
Clocking Architecture
51
Pxie-7902 Clocking
51
Front Panel
53
Recommended Mating Cables and Connectors
54
Transceiver Lane and Quad Mapping
54
Table 7-1. Pxie-7902 Front Panel Connectors
54
Table 7-2. Transceiver Lane and Quad Mapping
54
Signal Routing
55
Socketed CLIP Interface
55
Table 7-3. Clock Signal and Quad Mapping
55
Pxie-7902 Socketed CLIP
56
Table 7-4. Pxie-7902 Socketed CLIP Signals
56
Developing Applications for the High-Speed Serial Device
62
Development Flow
62
Socketed CLIP Development
62
Accessing the Xilinx Vivado Tools
63
Exporting to Vivado
64
Generating an IP Core from the Xilinx Vivado IP Catalog
66
Modifying Third-Party IP Core Logic
66
Building a Netlist from the IP Core
67
Writing a VHDL Wrapper Around the Protocol IP Core
69
Constraints and Hierarchy
70
Documenting Your IP
71
Improving Performance in Larger Designs through Enable Chain Removal
71
Developing with Labview FPGA
72
Configuring the High-Speed Serial Device Labview FPGA Targets
72
Using Existing VHDL IP Inside CLIP or IPIN
76
Adding High-Speed Serial Device Target I/O
76
Using the ni Common Instrument Design Libraries
77
Using Niinstr Instruction Framework
77
Using Niinstr Streaming
79
Using Niinstr CLIP Adapters
79
Using Niinstr Data Trigger
79
Using Niinstr Basic Elements
79
Using Niinstr Eye Scan
79
Connecting AXI4-Lite and AXI4-Stream Interfaces to the Host
79
Connecting Signals to Enable Eye Scan
80
Compiling Labview FPGA Vis
82
Labview and System Integration
82
Download, Reset, and Run Side Effects in the Labview FPGA Host Interface
82
DMA Streaming
83
Peer-To-Peer Streaming
84
Maximizing Peer-To-Peer Streaming Throughput
84
PXI Triggers
84
Configuring Trigger Pulses
84
Reserving PXI Triggers
85
Reserving Trigger Lines in MAX
85
Reserving Trigger Lines in the Labview FPGA Host VI
85
Reserving Trigger Lines
85
Releasing Trigger Lines
86
Monitoring Power and Temperature
86
Soft Shutdown
87
Power/Thermal Protection and Shutdown
87
Debugging Clocks Using Frequency Counters
87
Debugging Link Connections Using Eye Scan
88
Rectangular Eye Scan
88
N Point Eye Scan
89
Eye Scan State Model
90
Troubleshooting
92
Xilinx Documentation References
93
Table B-1. Xilinx 7-Series FPGA Documentation
93
Appendix Cni Services
95
National Instruments PXIe-7902 Getting Started Manual (86 pages)
mmWave Transceiver System
Brand:
National Instruments
| Category:
Transceiver
| Size: 5 MB
Table of Contents
Table of Contents
1
Verifying the System Requirements
2
Unpacking the Kit
2
System Configurations with Mmwave Radio Heads
4
Installing the Software
7
Assembling Mmwave Radio Head Tripods (Mmrh-3647/3657)
7
System Setup
10
Unidirectional System Setup
10
Bidirectional System Setup
27
Connecting Mmwave Radio Heads to the System
38
Configuring the Coding Modules of a MIMO System
50
Programming the Mmwave Transceiver System
57
NI-Mmwave Instrument Driver
57
Trigger Configuration
57
Signal Block Diagrams
59
Ghz to 33.40 Ghz Mmwave Transceiver System Block Diagram
59
37 Ghz to 43.5 Ghz Mmwave Transceiver System Block Diagram
59
71 Ghz to 76 Ghz Mmwave Transceiver System Block Diagram
60
Front Panels, Back Panels, and Connectors
60
Direct Connections to the Mmwave Transceiver System
60
Pxie-3610 Front Panel and Leds
61
Pxie-3620 Front Panel
63
Pxie-3630 Front Panel and Leds
65
Pxie-7902 Front Panel
67
Mmrh-3602 Front/Back Panel and Leds
68
Mmrh-3603 Front/Back Panel and Leds
71
Mmrh-3642 Front/Back Panel and Leds
74
Mmrh-3643 Front/Back Panel and Leds
76
Mmrh-3647 Front/Back Panel and Leds
78
Mmrh-3652 Front/Back Panel and Leds
80
Mmrh-3653 Front/Back Panel and Leds
82
Mmrh-3657 Front/Back Panel and Leds
84
Where to Go Next
85
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National Instruments PXIe-7902 Getting Started Manual (10 pages)
High-Speed Serial Module
Brand:
National Instruments
| Category:
Control Unit
| Size: 0 MB
Table of Contents
Table of Contents
1
Electromagnetic Compatibility Guidelines
1
Using Your Documentation Set
2
Verifying the System Requirements
3
Unpacking the Kit
3
Pxie-7902 Kit Contents
3
Preparing the Environment
4
Installing the Software
4
Installing the Pxie-7902 Module
5
Configuring the Pxie-7902 in MAX
5
Accessing Sample Projects
6
Pxie-7902 Front Panels
6
Troubleshooting
7
What Should I Do if the Pxie-7902 Doesn't Appear in MAX
7
What Should I Do if the Module Fails the Self-Test
8
Troubleshooting
8
Where to Go Next
8
Worldwide Support and Services
9
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