Page 1 MIPS R4000 Microprocessor User’s Manual Second Edition Joe Heinrich...
Page 2 Unpublished rights reserved under the Copyright Laws of the United States. Contractor/manufacturer is MIPS Technologies, Inc., 2011 N. Shoreline Blvd., Mountain View, CA 94039-7311. RISCompiler, RISC/os, R2000, R6000, R4000, and R4400 are trademarks of MIPS Technologies, Inc. MIPS and R3000 are registered trademarks of MIPS Technologies, Inc.
Page 3 R4000 processor synchronization support; Paul Ries, for confirming the accuracy of sections describing the memory management and the caches; John Mashey, for verifying the R4000 processor actually does employ the 64-bit architecture; Dave Ditzel, for raising the issue in the first place; and Mike Gupta, for substantiating various aspects of the errata.
Page 4 MIPS R4000 Microprocessor User's Manual...
Page 5 On the production side, thanks to Kay Maitz, Beth Fraker, Molly Castor, Lynnea Humphries, and Claudia Lohnes for their assistance at the center of the hurricane. Joe Heinrich joeh@sgi.com April 1, 1994 Mt. View, California MIPS R4000 Microprocessor User's Manual...
Page 6 MIPS R4000 Microprocessor User's Manual...
Page 7 Preface This book describes the MIPS R4000 and R4400 family of RISC microprocessors (also referred to in this book as processor). Overview of the Contents Chapter 1 is a discussion (including the historical context) of RISC development in general, and the R4000 microprocessor in particular.
Page 8 Chapter 9 describes in more detail the Initialization interface, which includes the boot modes for the processor, as well as system resets. Chapter 10 describes the clocks used in the R4000 processor, as well as the processor status reporting mechanism.
Page 9 Preface Appendix A describes the R4000 CPU instructions, in both 32- and 64- bit modes. The instruction list is given in alphabetical order. Appendix B describes the R4000 FPU instructions, listed alphabetically. Appendix C describes sub-block ordering, a nonsequential method of retrieving data.
Page 10 Preface MIPS R4000 Microprocessor User's Manual...
Page 11 Do this by typing: cd <directory_you_want_file_to_be_in> Access the MIPS document server, sgigate, through FTP by typing: ftp sgigate.sgi.com The server tells you when you are connected for FTP by responding: Connected to sgigate.sgi.com. MIPS R4000 Microprocessor User's Manual...
Page 12 You can take a look at the contents of the doc directory by listing them: ftp> ls You will find several R4000-related subdirectories, such as R4200, R4400, and R4600. When you find the subdirectory you want, cd into that subdirectory and retrieve the file you want by typing: get <filename>...
Page 13 Table of Contents Preface Overview of the Contents ................... vii A Note on Style ....................ix Preface to the Second Edition Changes From the First Edition ................. xi Getting MIPS Documents On-Line..............xi MIPS R4000 Microprocessor User's Manual xiii...
Page 14: Table Of Contents
Advanced Semiconductor Technologies ............3 Optimizing Compilers..................4 MIPS RISCompiler Language Suite ..............5 Compatibility ......................6 Processor General Features..................6 R4000 Processor Configurations ................7 R4400 Processor Enhancements ................7 R4000 Processor ......................9 64-bit Architecture ....................9 Superpipeline Architecture ................11 System Interface ....................
Page 15 Backing Up the Pipeline ................. 54 Aborting an Instruction Subsequent to an Interlock ........55 Pipelining the Exception Handling ..............56 Special Cases......................58 Performance Considerations................58 Correctness Considerations................58 R4400 Processor Uncached Store Buffer ............... 59 MIPS R4000 Microprocessor User's Manual...
Page 16 Config Register (16) ..................90 Load Linked Address (LLAddr) Register (17) ..........93 Cache Tag Registers [TagLo (28) and TagHi (29)] ........93 Virtual-to-Physical Address Translation Process..........95 TLB Misses ......................97 TLB Instructions ....................97 MIPS R4000 Microprocessor User's Manual...
Page 17 TLB Exceptions..................... 128 TLB Refill Exception..................129 TLB Invalid Exception..................130 TLB Modified Exception................. 131 Cache Error Exception..................132 Virtual Coherency Exception ................133 Bus Error Exception ..................... 134 Integer Overflow Exception ................135 MIPS R4000 Microprocessor User's Manual xvii...
Page 18 System Call Exception ..................137 Breakpoint Exception ..................138 Reserved Instruction Exception ................. 139 Coprocessor Unusable Exception ..............140 Floating-Point Exception..................141 Watch Exception ....................142 Interrupt Exception....................143 Exception Handling and Servicing Flowcharts ........... 144 xviii MIPS R4000 Microprocessor User's Manual...
Page 19 Instruction Execution ..................172 Instruction Execution Cycle Time ..............173 Scheduling FPU Instructions................175 FPU Pipeline Overlapping.................. 175 Instruction Scheduling Constraints .............. 176 Instruction Latency, Repeat Rate, and Pipeline Stage Sequences..... 181 Resource Scheduling Rules ................182 MIPS R4000 Microprocessor User's Manual...
Page 20 R4000 Processor Signal Descriptions System Interface Signals..................201 Clock/Control Interface Signals ................203 Secondary Cache Interface Signals ................ 205 Interrupt Interface Signals ..................207 JTAG Interface Signals..................... 207 Initialization Interface Signals ................208 Signal Summary ....................... 209 MIPS R4000 Microprocessor User's Manual...
Page 21 Connecting Clocks to a Phase-Locked System............. 234 Connecting Clocks to a System without Phase Locking........235 Connecting to a Gate-Array Device ..............235 Connecting to a CMOS Logic System ............... 238 Processor Status Outputs ..................241 MIPS R4000 Microprocessor User's Manual...
Page 22 An Example of Strong Ordering..............267 Testing for Strong Ordering................267 Restarting the Processor ................. 268 Maintaining Coherency on Loads and Stores ............269 Manipulation of the Cache by an External Agent ..........270 Invalidate....................... 270 Update ........................270 xxii MIPS R4000 Microprocessor User's Manual...
Page 23 Coherent Read Conflicts ................. 280 Coherent Write Conflicts ................281 Invalidate Conflicts ..................282 Sample Cycle: Coherent Read Request............. 283 R4000 Processor Synchronization Support............286 Test-and-Set (Spinlock) ..................286 Counter ........................288 LL and SC......................289 Examples Using LL and SC ................290...
Page 24 Handling Requests ....................318 Load Miss ......................318 Secondary-Cache Mode .................. 320 No-Secondary-Cache Mode ................320 Store Miss ......................321 Secondary-Cache Mode .................. 323 No-Secondary-Cache Mode ................325 Store Hit......................... 326 Secondary-Cache Mode .................. 326 xxiv MIPS R4000 Microprocessor User's Manual...
Page 25 System Interface Commands and Data Identifiers..........364 Command and Data Identifier Syntax .............. 364 System Interface Command Syntax ..............365 Read Requests ....................366 Write Requests ....................367 Null Requests ....................369 Invalidate Requests ..................370 MIPS R4000 Microprocessor User's Manual...
Page 26 4-Word Read Cycle..................383 8-Word Read Cycle..................384 Notes on a Secondary Cache Read Cycle............. 384 Write Cycles......................385 4-Word Write Cycle..................385 8-Word Write Cycle..................386 Notes on a Secondary Cache Write Cycle............ 387 xxvi MIPS R4000 Microprocessor User's Manual...
Page 27 Test Access Port (TAP) ..................395 TAP Controller ....................396 Controller Reset ....................396 Controller States....................396 Implementation-Specific Details ................400 R4000 Processor Interrupts Hardware Interrupts....................402 Nonmaskable Interrupt (NMI)................402 Asserting Interrupts....................402 MIPS R4000 Microprocessor User's Manual xxvii...
Page 28 Summary of ECC Operations................426 R4400 Master/Checker Mode................. 430 Connecting a System in Lock Step ..............431 Master-Listener Configuration ................432 Cross-Coupled Checking Configuration ............433 Fault Detection ..................... 435 Reset Operation ....................436 Fault History......................436 xxviii MIPS R4000 Microprocessor User's Manual...
Page 29 Subblock Ordering ....................C-2 Output Buffer i/ t Control Mechanism Mode Bits........................D-1 Delay Times....................... D-2 PLL Passive Components Coprocessor 0 Hazards R4000 Pinouts Pinout of R4000PC....................G-2 Pinout of R4000MC/SC Package Pinout .............. G-5 Index MIPS R4000 Microprocessor User's Manual xxix...
Page 30 Table of Contents MIPS R4000 Microprocessor User's Manual...
Page 31 And at that time it seemed self-evident to designers that architectures should continue to become more and more complex as technological advances made such VLSI designs possible. MIPS R4000 Microprocessor User's Manual...
Page 32: Benefits Of Risc Design
Some of these benefits are described below. MIPS R4000 Microprocessor User's Manual...
Page 33: Shorter Design Cycle
Since the simplicity of a RISC processor allows it to be implemented in fewer transistors than its CISC counterpart, the first computers capable of exploiting these new VLSI technologies have been using and will continue to use RISC architecture. MIPS R4000 Microprocessor User's Manual...
Page 34: Optimizing Compilers
Thus, a natural match exists between RISC architectures and efficient, optimizing compilers. This match makes it easier for compilers to generate the most effective sequences of machine instructions to accomplish tasks defined by the high-level language. MIPS R4000 Microprocessor User's Manual...
Page 35: Mips Riscompiler Language Suite
The common back-end also exports optimizing and code-generating improvements immediately throughout the language suite, thereby reducing maintenance. MIPS R4000 Microprocessor User's Manual...
Page 36: Compatibility
MIPS hardware implementation. 1.3 Processor General Features This section briefly describes the programming model, the memory management unit (MMU), and the caches in the R4000 processor. A more detailed description is given in succeeding sections. • Full 32-bit and 64-bit Operations. The R4000 processor contains 32 general purpose 64-bit registers.
Page 37: R4000 Processor Configurations
EW, added to the CacheErr register (described in Chapter 5). † Features of the R4400 processor that differ from the R4000 processor are noted throughout this book; for instance, R4400 processor enhancements are listed in the next section.
Page 38 Primary Cache States Valid Shared Clean Exclusive Dirty Exclusive Secondary Cache Interface Secondary Cache States Valid Shared Dirty Shared Clean Exclusive Dirty Exclusive Multiprocessing Cache Coherency Attributes Uncached Noncoherent Sharable Update Exclusive Packages PGA (179-pin) PGA (447-pin) MIPS R4000 Microprocessor User's Manual...
Page 39: R4000 Processor
(described in more detail in Chapters 4 and 11). The Secondary Cache interface is detailed in Chapter 13. 64-bit Architecture The natural mode of operation for the R4000 processor is as a 64-bit microprocessor; however, 32-bit applications maintain compatibility even when the processor operates as a 64-bit processor.
Page 40 Pipeline Bypass Memory Management Registers Load Aligner/Store Driver FP Multiplier Integer Multiplier/Divider FP Divider Translation Lookaside Buffers Address Unit FP Add, Convert Square Root PC Incrementer Pipeline Control Figure 1-1 R4000 Processor Internal Block Diagram MIPS R4000 Microprocessor User's Manual...
Page 41: Superpipeline Architecture
Under normal circumstances, two instructions are issued each cycle. The internal pipeline of the R4000 processor operates at twice the frequency of the master clock, as discussed in Chapter 3. The processor...
Page 42: Cpu Register Overview
2 registers that hold the results of integer multiply and divide operations (HI and LO). Floating-point unit (FPU) registers are described in Chapter 6. CPU registers can be either 32 bits or 64 bits wide, depending on the R4000 processor mode of operation. Figure 1-2 shows the CPU registers.
Page 43 (in LO) and remainder (in HI) of integer divide operations The R4000 processor has no Program Status Word (PSW) register as such; this is covered by the Status and Cause registers incorporated within the System Control Coprocessor (CP0). CP0 registers are described later in this chapter.
Page 44: Cpu Instruction Set Overview
Instruction decoding is greatly simplified by limiting the number of formats to these three. This limitation means that the more complicated (and less frequently used) operations and addressing modes can be synthesized by the compiler, using sequences of these same simple instructions. MIPS R4000 Microprocessor User's Manual...
Page 45 R-type (both the operands and the result are registers) and I-type (one operand is a 16-bit immediate value) formats. Chapter 2 provides a more detailed summary and Appendix A gives a complete description of each instruction. MIPS R4000 Microprocessor User's Manual...
Page 46 Table 1-3 CPU Instruction Set: Arithmetic Instructions (ALU Immediate) OpCode Description ADDI Add Immediate ADDIU Add Immediate Unsigned SLTI Set on Less Than Immediate SLTIU Set on Less Than Immediate Unsigned ANDI AND Immediate OR Immediate XORI Exclusive OR Immediate Load Upper Immediate MIPS R4000 Microprocessor User's Manual...
Page 47 Table 1-5 CPU Instruction Set: Multiply and Divide Instructions OpCode Description MULT Multiply MULTU Multiply Unsigned Divide DIVU Divide Unsigned MFHI Move From HI MTHI Move To HI MFLO Move From LO MTLO Move To LO MIPS R4000 Microprocessor User's Manual...
Page 48 Branch on Greater Than or Equal to Zero And Link Table 1-7 CPU Instruction Set: Shift Instructions OpCode Description Shift Left Logical Shift Right Logical Shift Right Arithmetic SLLV Shift Left Logical Variable SRLV Shift Right Logical Variable SRAV Shift Right Arithmetic Variable MIPS R4000 Microprocessor User's Manual...
Page 49 Move Control From Coprocessor z COPz Coprocessor Operation z BCzT Branch on Coprocessor z True BCzF Branch on Coprocessor z False Table 1-9 CPU Instruction Set: Special Instructions OpCode Description SYSCALL System Call BREAK Break MIPS R4000 Microprocessor User's Manual...
Page 50 DADDI Doubleword Add Immediate DADDIU Doubleword Add Immediate Unsigned Table 1-12 Extensions to the ISA: Multiply and Divide Instructions OpCode Description DMULT Doubleword Multiply DMULTU Doubleword Multiply Unsigned DDIV Doubleword Divide DDIVU Doubleword Divide Unsigned MIPS R4000 Microprocessor User's Manual...
Page 51 Branch on Coprocessor z True Likely BCzFL Branch on Coprocessor z False Likely Table 1-14 Extensions to the ISA: Arithmetic Instructions (3-operand, R-type) OpCode Description DADD Doubleword Add DADDU Doubleword Add Unsigned DSUB Doubleword Subtract DSUBU Doubleword Subtract Unsigned MIPS R4000 Microprocessor User's Manual...
Page 52 Trap if Greater Than or Equal Immediate Trap if Greater Than or Equal Immediate TGEIU Unsigned TLTI Trap if Less Than Immediate TLTIU Trap if Less Than Immediate Unsigned TEQI Trap if Equal Immediate TNEI Trap if Not Equal Immediate MIPS R4000 Microprocessor User's Manual...
Page 53 MTC0 Move to CP0 MFC0 Move from CP0 TLBR Read Indexed TLB Entry TLBWI Write Indexed TLB Entry TLBWR Write Random TLB Entry TLBP Probe TLB for Matching Entry CACHE Cache Operation ERET Exception Return MIPS R4000 Microprocessor User's Manual...
Page 54: Data Formats And Addressing
When the R4000 processor is configured as a big-endian system, byte 0 is the most-significant (leftmost) byte, thereby providing compatibility with MC 68000 and IBM 370 conventions. Figure 1-4 shows this configuration.
Page 55 56 55 48 47 40 39 24 23 16 15 Bit # Byte # Byte Halfword 7 6 5 4 3 2 1 Bit # Bits in a Byte Figure 1-7 Big-Endian Data in a Doubleword MIPS R4000 Microprocessor User's Manual...
Page 56 Figures 1-8 and 1-9 show the access of a misaligned word that has byte address 3. Higher Address Bit # 24 23 16 15 Lower Address Figure 1-8 Big-Endian Misaligned Word Addressing Higher Bit # Address 24 23 16 15 Lower Address Figure 1-9 Little-Endian Misaligned Word Addressing MIPS R4000 Microprocessor User's Manual...
Page 57: Coprocessors (Cp0-Cp2)
CP0 also controls the cache subsystem, as well as providing diagnostic control and error recovery facilities. The CP0 registers shown in Figure 1-10 and described in Table 1-19 manipulate the memory management and exception handling capabilities of the CPU. MIPS R4000 Microprocessor User's Manual...
Page 58 Register Name Reg. # Index Config Random LLAddr EntryLo0 WatchLo EntryLo1 WatchHi XContext Context PageMask Wired BadVAddr Count EntryHi Compare CacheErr TagLo Cause TagHi ErrorEPC PRId Exception Processing Memory Management Reserved Figure 1-10 R4000 CP0 Registers MIPS R4000 Microprocessor User's Manual...
Page 59 Pointer to kernel virtual PTE table in 64-bit addressing mode 21–25 — Reserved Secondary-cache error checking and correcting (ECC) and Primary parity CacheErr Cache Error and Status register TagLo Cache Tag register TagHi Cache Tag register ErrorEPC Error Exception Program Counter — Reserved MIPS R4000 Microprocessor User's Manual...
Page 60: Floating-Point Unit (Fpu), Cp1
FPU form a tightly-coupled unit with a seamless integration of ﬂoating-point and ﬁxed-point instruction sets. Since each unit receives and executes instructions in parallel, some ﬂoating- point instructions can execute at the same rate (two instructions per cycle) as ﬁxed-point instructions. MIPS R4000 Microprocessor User's Manual...
Page 61: Memory Management System (Mmu)
Introduction Memory Management System (MMU) The R4000 processor has a 36-bit physical addressing range of 64 Gbytes. However, since it is rare for systems to implement a physical memory space this large, the CPU provides a logical expansion of memory space by translating addresses composed in the large virtual address space into available physical memory addresses.
Page 62: Operating Modes
Cache Memory Hierarchy To achieve a high performance in uniprocessor and multiprocessor systems, the R4000 processor supports a two-level cache memory hierarchy that increases memory access bandwidth and reduces the latency of load and store instructions. This hierarchy consists of on-chip instruction and data caches, together with an optional external secondary cache that varies in size from 128 Kbytes to 4 Mbytes.
Page 63: Primary Caches
Each cache has its own 64-bit data path, and each can be accessed in parallel. The R4000 processor primary caches hold from 8 Kbytes to 32 Kbytes; the R4400 processor primary caches are ﬁxed at 16 Kbytes.
Page 64 Chapter 1 MIPS R4000 Microprocessor User's Manual...
Page 65: Cpu Instruction Set Summary
Appendix A for detailed descriptions of individual CPU instructions. An overview of the floating-point unit (FPU) instruction set is in Chapter 6; refer to Appendix B for detailed descriptions of individual FPU instructions. MIPS R4000 Microprocessor User's Manual...
Page 66: Cpu Instruction Formats
5-bit destination register specifier 5-bit shift amount funct 6-bit function field Figure 2-1 CPU Instruction Formats In the MIPS architecture, coprocessor instructions are implementation- dependent; see Appendix A for details of individual Coprocessor 0 instructions. MIPS R4000 Microprocessor User's Manual...
Page 67: Load And Store Instructions
R-Series processor compatibility. However, the scheduling of load delay slots is not absolutely required. Defining Access Types Access type indicates the size of an R4000 processor data item to be loaded or stored, set by the load or store instruction opcode. Access types are defined in Appendix A.
Page 68 4 5 6 7 7 6 5 4 0 1 2 2 1 0 1 2 3 3 2 1 Triplebyte (2) 4 5 6 6 5 4 5 6 7 7 6 5 Halfword (1) 6 7 7 6 Byte (0) MIPS R4000 Microprocessor User's Manual...
Page 69: Computational Instructions
Register-Type instructions • shift instructions • multiply and divide instructions 64-bit Operations When operating in 64-bit mode, 32-bit operands must be sign extended. The result of operations that use incorrect sign-extended 32-bit values is unpredictable. MIPS R4000 Microprocessor User's Manual...
Page 70: Cycle Timing For Multiply And Divide Instructions
CPU operation. Table 2-2 Multiply/Divide Instruction Cycle Timing Instruction Total Cycles Overlap MULT MULTU DIVU DMULT DMULTU DDIV DDIVU For more information about computational instructions, refer to the individual instruction as described in Appendix A. MIPS R4000 Microprocessor User's Manual...
Page 71: Jump And Branch Instructions
For more information about branch instructions, refer to the individual instruction as described in Appendix A. † Taken branches have a 3 cycle penalty in this implementation. See Chapter 3 for more information. MIPS R4000 Microprocessor User's Manual...
Page 72: Special Instructions
CP0) and B (for the FPU, CP1). CP0 instructions perform operations specifically on the System Control Coprocessor registers to manipulate the memory management and exception handling facilities of the processor. Appendix A details CP0 instructions. MIPS R4000 Microprocessor User's Manual...
Page 73: The Cpu Pipeline
(instructions that follow a branch or load instruction in the pipeline), interruptions to the pipeline flow caused by interlocks and exceptions, and R4400 implementation of an uncached store buffer. The FPU pipeline is described in Chapter 6. MIPS R4000 Microprocessor User's Manual...
Page 74: Cpu Pipeline Operation
Once the pipeline has been filled, eight instructions are executed simultaneously. Figure 3-1 shows the eight stages of the instruction pipeline; the next section describes the pipeline stages. PCycle (8-Deep) MasterClock Cycle TC WB Current Cycle Figure 3-1 Instruction Pipeline Stages MIPS R4000 Microprocessor User's Manual...
Page 75: Cpu Pipeline Stages
The instruction decoder (IDEC) decodes the instruction and checks for interlock conditions. • The instruction cache tag is checked against the page frame number obtained from the ITLB. • Any required operands are fetched from the register ﬁle. MIPS R4000 Microprocessor User's Manual...
Page 76 For load and store instructions, the cache performs the tag check during the TC stage. The physical address from the TLB is checked against the cache tag to determine if there is a hit or a miss. † The TLB is described in Chapter 4. MIPS R4000 Microprocessor User's Manual...
Page 77 Data cache access stage 2 Data load or store align JTLB1 Data/Instruction address translation stage 1 JTLB2 Data/Instruction address translation stage 2 Data tag check Instruction virtual address calculation Write back to register file Figure 3-2 CPU Pipeline Activities MIPS R4000 Microprocessor User's Manual...
Page 78: Branch Delay
Figure 3-4 shows the load delay of two pipeline stages. load DF DS TC WB two load EX DF DS TC WB delay instructions RF EX DF DS TC WB DS TC WB f(load) Load Delay Figure 3-4 CPU Pipeline Load Delay MIPS R4000 Microprocessor User's Manual...
Page 79: Interlock And Exception Handling
Figure 3-6. For instance, an Illegal Instruction (II) exception is raised in the execution (EX) stage. Tables 3-1 and 3-2 describe the pipeline interlocks and exceptions listed in Figure 3-6. MIPS R4000 Microprocessor User's Manual...
Page 80 *MP stalls can occur at any stage; they are not associated with any instruction or pipe stage MultB DivB Slip MDOne ShSlip FCBsy ITLB Intr DTLB TLBMod Watch IVACoh ExTrap DVACoh DECCErr Exceptions Reset IECCErr Figure 3-6 Correspondence of Pipeline Stage to Interlock Condition MIPS R4000 Microprocessor User's Manual...
Page 81 Integer Overflow FP Interrupt ExTrap EX Stage Traps DTLB Data Translation or Address Exception TLBMod TLB Modified Data Bus Error Watch Memory Reference Address Compare DVACoh DVA Coherent DECCErr Data ECC Error Non-maskable Interrupt Reset Reset MIPS R4000 Microprocessor User's Manual...
Page 82: Exception Conditions
After instruction cancellation, a new instruction stream begins, starting execution at a predefined exception vector. System Control Coprocessor registers are loaded with information that identifies the type of exception and auxiliary information such as the virtual address at which translation exceptions occur. MIPS R4000 Microprocessor User's Manual...
Page 83: Stall Conditions
Interlock and Exception Timing To prevent interlock and exception handling from adversely affecting the processor cycle time, the R4000 processor uses both logic and circuit pipeline techniques to reduce critical timing paths. Interlock and exception handling have the following effects on the pipeline: •...
Page 84: Backing Up The Pipeline
Run Run Run Run Run Run Run Stl Stl Run Run Run Run Run Rst2 Rst1 Restart DS TC TC WB Load DF DS TC WB TC WB RF EX- RF EX+ DF TC WB TC WB Figure 3-7 Pipeline Overrun MIPS R4000 Microprocessor User's Manual...
Page 85: Aborting An Instruction Subsequent To An Interlock
Handling of the exception is done in this fashion because the frequency of an exception occurring is, by definition, relatively low. MIPS R4000 Microprocessor User's Manual...
Page 86: Pipelining The Exception Handling
Figure 3-9 shows this process for a sequence of loads. Clock Phase Load1: TagCk Resolve Buffer Load2: TagCk Resolve Buffer Load3: TagCk Resolve Buffer Figure 3-9 Pipelining of Interlock and Exception Handling MIPS R4000 Microprocessor User's Manual...
Page 87 • Pipeline advance control signals are buffered and distributed. Figure 3-10 illustrates this process. Clock Phase Cycle Evaluate Resolve Buffer Evaluate Resolve Buffer Evaluate Resolve Buffer Figure 3-10 Pipeline Advance Decision MIPS R4000 Microprocessor User's Manual...
Page 88: Special Cases
Cycle Cache Index Address Restart Rst3 Rst2 Rst1 Load EX DF DS TC WB Figure 3-11 Load Address Bypassing Correctness Considerations An example in which bypassing is necessary to guarantee correctness is a cache write. MIPS R4000 Microprocessor User's Manual...
Page 89: R4400 Processor Uncached Store Buffer
3.6 R4400 Processor Uncached Store Buffer The R4400 processor contains an uncached store buffer to improve the performance of uncached stores over that available from an R4000 processor. When an uncached store reaches the write-back (WB) stage in the CPU pipeline, the CPU must stall until the store is sent off-chip. In the R4400 processor, a single-entry buffer stores this uncached WB-stage data on the chip without stalling the pipeline.
Page 90 10), an uncached store can occur every eight pipeline cycles. If a larger clock divisor is used, more pipeline cycles are required for each store. CAUTION: The R4000 processor always had a strongly-ordered execution; however, with the addition of the uncached store buffer in...
Page 91: Memory Management
Memory Management The MIPS R4000 processor provides a full-featured memory management unit (MMU) which uses an on-chip translation lookaside buffer (TLB) to translate virtual addresses into physical addresses. This chapter describes the processor virtual and physical address spaces, the virtual-to-physical address translation, the operation of the TLB in making these translations, and those System Control Coprocessor (CP0) registers that provide the software interface to the TLB.
Page 92: Translation Lookaside Buffer (Tlb)
† There are virtual-to-physical address translations that occur outside of the TLB. For example, addresses in the kseg0 and kseg1 spaces are unmapped translations. In these spaces the physical address is derived by subtracting the base address of the space from the virtual address. MIPS R4000 Microprocessor User's Manual...
Page 93: Address Spaces
3. The Offset, which does not pass through the TLB, is then concatenated to the PFN. Offset Physical address Figure 4-1 Overview of a Virtual-to-Physical Address Translation † Figure 4-8 shows the 32-bit and 64-bit versions of the processor TLB entry. MIPS R4000 Microprocessor User's Manual...
Page 94: Physical Address Space
Virtual-to-physical translation is described in greater detail throughout the remainder of this chapter; Figure 4-20 is a flow diagram of the process shown at the end of this chapter. The next two sections describe the 32-bit and 64-bit address translations. MIPS R4000 Microprocessor User's Manual...
Page 95: 32-Bit Mode Address Translation
Offset Virtual-to-physical Offset passed translation in TLB unchanged to physical memory Offset ASID 8 bits = 256 pages Virtual Address with 256 (2 )16-Mbyte pages Figure 4-2 32-bit Mode Virtual Address Translation MIPS R4000 Microprocessor User's Manual...
Page 96: 64-Bit Mode Address Translation
Offset Offset passed Virtual-to-physical unchanged to translation in TLB physical memory 0 or -1 ASID Offset 16 bits = 64K pages Virtual Address with 64K (2 )16-Mbyte pages Figure 4-3 64-bit Mode Virtual Address Translation MIPS R4000 Microprocessor User's Manual...
Page 97: Operating Modes
0x 0000 0000 0000 0000 Figure 4-4 User Mode Virtual Address Space *NOTE: The R4000 uses 64-bit addresses internally. When the kernel is running in Kernel mode, it initializes registers before switching modes, and saves (or restores, whichever is appropriate) register values on context switches.
Page 98 0x0000 0000 0000 0000 64-bit 1 Tbyte xuseg through A(63:40) = 0 bytes) 0x0000 00FF FFFF FFFF † The cached (C) ﬁeld in a TLB entry determines whether the reference is cached; see Figure 4-8. MIPS R4000 Microprocessor User's Manual...
Page 99: Supervisor Mode Operations
Supervisor Mode Operations Supervisor mode is designed for layered operating systems in which a true kernel runs in R4000 Kernel mode, and the rest of the operating system runs in Supervisor mode. The processor operates in Supervisor mode when the Status register contains the following bit-values: •...
Page 100 0x 0000 0000 0000 0000 Figure 4-5 Supervisor Mode Address Space *NOTE: The R4000 uses 64-bit addresses internally. In 32-bit mode, a valid address must be a 32-bit signed number, where bits 63:32 = bit 31. In normal operation it is not possible for a 32-bit Supervisor-mode program to create an invalid address through arithmetic operations.
Page 101 The virtual address is extended with the contents of the 8-bit ASID field to form a unique virtual address. This mapped space begins at virtual address 0xC000 0000 and runs through 0xDFFF FFFF. MIPS R4000 Microprocessor User's Manual...
Page 102 32-bit mode. The virtual address is extended with the contents of the 8-bit ASID field to form a unique virtual address. This mapped space begins at virtual address 0xFFFF FFFF C000 0000 and runs through 0xFFFF FFFF DFFF FFFF. MIPS R4000 Microprocessor User's Manual...
Page 103: Kernel Mode Operations
Figure 4-6. Table 4-3 lists the characteristics of the 32-bit kernel mode segments, and Table 4-4 lists the characteristics of the 64-bit kernel mode segments. MIPS R4000 Microprocessor User's Manual...
Page 104 0x 0000 0000 0000 0000 Figure 4-6 Kernel Mode Address Space *NOTE: The R4000 uses 64-bit addresses internally. In 32-bit mode, a valid address must be a 32-bit signed number, where bits 63:32 = bit 31; an invalid address produces an undefined result. In 32-bit mode,...
Page 105 References to kseg0 are not mapped through the TLB; the physical address selected is defined by subtracting 0x8000 0000 from the virtual address. The K0 field of the Config register, described in this chapter, controls cacheability and coherency. MIPS R4000 Microprocessor User's Manual...
Page 106 , the kseg3 virtual address space is selected; it is the current 2 -byte (512-Mbyte) kernel virtual space. The virtual address is extended with the contents of the 8-bit ASID field to form a unique virtual address. MIPS R4000 Microprocessor User's Manual...
Page 107 When ERL = 1 in the Status register, the user address region becomes a 2 byte unmapped (that is, mapped directly to physical addresses) uncached address space. See the Cache Error exception in Chapter 5 for more information. MIPS R4000 Microprocessor User's Manual...
Page 108 Cacheable, noncoherent 0x9800 0000 0000 0000 Cacheable, coherent exclusive 0xA000 0000 0000 0000 Cacheable, coherent exclusive on write 0xA800 0000 0000 0000 Cacheable, coherent update on write 0xB000 0000 0000 0000 Reserved 0xB800 0000 0000 0000 MIPS R4000 Microprocessor User's Manual...
Page 109 This 64-bit virtual address space is the current supervisor virtual space, compatible with the 32-bit address model ksseg. • ckseg3. This 64-bit virtual address space is kernel virtual space, compatible with the 32-bit address model kseg3. MIPS R4000 Microprocessor User's Manual...
Page 110: System Control Coprocessor
Used with exception Used with memory processing. See management system. Chapter 5 for details. *Register number Figure 4-7 CP0 Registers and the TLB † For a description of CP0 data dependencies and hazards, please see Appendix F. MIPS R4000 Microprocessor User's Manual...
Page 111: Format Of A Tlb Entry
R4000 processor 30 29 64-bit Mode MASK 190 189 139 136 135 256-bit TLB VPN2 ASID entry in 64- bit mode of R4000 94 93 processor 30 29 Figure 4-8 Format of a TLB Entry MIPS R4000 Microprocessor User's Manual...
Page 112 63...62 Fill ..Reserved. 0 on read; ignored on write. 0 ... Reserved. Must be written as zeroes, and returns zeroes when read. Figure 4-9 Fields of the PageMask and EntryHi Registers MIPS R4000 Microprocessor User's Manual...
Page 113 G ..Global. If this bit is set in both Lo0 and Lo1, then the processor ignores the ASID during TLB lookup. 0 ... Reserved. Must be written as zeroes, and returns zeroes when read. Figure 4-10 Fields of the EntryLo0 and EntryLo1 Registers MIPS R4000 Microprocessor User's Manual...
Page 114: Cp0 Registers
EntryLo0 (2) and EntryLo1 (3) registers • PageMask register (5) • Wired register (6) • EntryHi register (10) • PRId register (15) • Conﬁg register (16) • LLAddr register (17) • TagLo (28) and TagHi (29) registers MIPS R4000 Microprocessor User's Manual...
Page 115: Index Register (0)
Probe failure. Set to 1 when the previous TLBProbe (TLBP) instruction was unsuccessful. Index to the TLB entry affected by the TLBRead and Index TLBWrite instructions Reserved. Must be written as zeroes, and returns zeroes when read. MIPS R4000 Microprocessor User's Manual...
Page 116: Random Register (1)
Figure 4-12 shows the format of the Random register; Table 4-8 describes the Random register fields. Random Register Random Figure 4-12 Random Register Table 4-8 Random Register Field Descriptions Field Description Random TLB Random index Reserved. Must be written as zeroes, and returns zeroes when read. MIPS R4000 Microprocessor User's Manual...
Page 117: Entrylo0 (2), And Entrylo1 (3) Registers
Table 4-9, the operation of the TLB is undefined. Table 4-9 Mask Field Values for Page Sizes Page Size 4 Kbytes 16 Kbytes 64 Kbytes 256 Kbytes 1 Mbyte 4 Mbytes 16 Mbytes MIPS R4000 Microprocessor User's Manual...
Page 118: Wired Register (6)
4-10 describes the register fields. Wired Register Wired Figure 4-14 Wired Register Table 4-10 Wired Register Field Descriptions Field Description Wired TLB Wired boundary Reserved. Must be written as zeroes, and returns zeroes when read. MIPS R4000 Microprocessor User's Manual...
Page 119: Entryhi Register (Cp0 Register 10)
PRId register fields. PRId Register 16 15 Figure 4-15 Processor Revision Identifier Register Format Table 4-11 PRId Register Fields Field Description Implementation number Revision number Reserved. Must be written as zeroes, and returns zeroes when read. MIPS R4000 Microprocessor User's Manual...
Page 120: Config Register (16)
The low-order byte (bits 7:0) of the PRId register is interpreted as a revision number, and the high-order byte (bits 15:8) is interpreted as an implementation number. The implementation number of the R4000 processor is 0x04. The content of the high-order halfword (bits 31:16) of the register are reserved.
Page 121 (joint cache) instruction and data separated by SCAddr(17) Secondary Cache port width 128-bit data path to S-cache Reserved System Port width 64-bit 1, 2, 3 Reserved Secondary Cache present S-cache present no S-cache present MIPS R4000 Microprocessor User's Manual...
Page 122 Reserved. Must be written as zeroes, returns zeroes when read. 12+IC Primary I-cache Size (I-cache size = 2 bytes). In the R4000 processor, this is set to 8 Kbytes; in the R4400 processor, this is set to 16 Kbytes. 12+DC Primary D-cache Size (D-cache size = 2 bytes).
Page 123: Load Linked Address (Lladdr) Register (17)
Figure 4-18 shows the format of these registers for primary cache operations. Figure 4-19 shows the format of these registers for secondary cache operations. Table 4-13 lists the field definitions of the TagLo and TagHi registers. MIPS R4000 Microprocessor User's Manual...
Page 124 Specifies the virtual index of the associated Primary cache line, VIndex vAddr(14:12) ECC for the STag, SState, and VIndex fields Reserved. Must be written as zeroes, and returns zeroes when read. Undefined The TagHi register should not be used. MIPS R4000 Microprocessor User's Manual...
Page 125: Virtual-To-Physical Address Translation Process
V) are retrieved from the matching TLB entry. While the V bit of the entry must be set for a valid translation to take place, it is not involved in the determination of a matching TLB entry. Figure 4-20 illustrates the TLB address translation process. MIPS R4000 Microprocessor User's Manual...
Page 126 ASID Match? = 1? 32-bit Valid address? = 1? Dirty Write? = 1? Non- cacheable XTLB Invalid Refill Refill 010? Exception Exception Access Access Main Cache Memory Physical Address (Output) Figure 4-20 TLB Address Translation MIPS R4000 Microprocessor User's Manual...
Page 127: Tlb Misses
Op Code Description of Instruction TLBP Translation Lookaside Buffer Probe TLBR Translation Lookaside Buffer Read TLBWI Translation Lookaside Buffer Write Index TLBWR Translation Lookaside Buffer Write Random † TLB miss exceptions are described in Chapter 5. MIPS R4000 Microprocessor User's Manual...
Page 128 Chapter 4 MIPS R4000 Microprocessor User's Manual...
Page 129 CPU exception register. The chapter concludes with a description of each exception’s cause, together with the manner in which the CPU processes and services these exceptions. For information about Floating-Point Unit exceptions, see Chapter 7. MIPS R4000 Microprocessor User's Manual...
Page 130: How Exception Processing Works
For a description of the exception handling process, see the description of the individual exception contained in this chapter, or the flowcharts at the end of this chapter. MIPS R4000 Microprocessor User's Manual...
Page 131: Exception Processing Registers
CP0 registers and the TLB are not interlocked, however; there may be some delay before a value written by one instruction is available to following instructions. For more information please see Appendix F. MIPS R4000 Microprocessor User's Manual...
Page 132: Context Register (4)
For a 4-Kbyte page size, this format can directly address the pair-table of 8-byte PTEs. For other page and PTE sizes, shifting and masking this value produces the appropriate address. MIPS R4000 Microprocessor User's Manual...
Page 133: Bad Virtual Address Register (Badvaddr) (8)
This register can be read or written. It can be written for diagnostic purposes or system initialization; for example, to synchronize processors. Figure 5-3 shows the format of the Count register. Count Register Count Figure 5-3 Count Register Format MIPS R4000 Microprocessor User's Manual...
Page 134: Compare Register (11)
For diagnostic purposes, the Compare register is a read/write register. In normal use however, the Compare register is write-only. Figure 5-4 shows the format of the Compare register. Compare Register Compare Figure 5-4 Compare Register Format MIPS R4000 Microprocessor User's Manual...
Page 135: Status Register (12)
Diagnostic Status (DS) field. All bits in the DS field except TS are readable and writable. Status Register 28 27 25 24 RP FR IM7 - IM0 KSU ERL EXL IE (Cu3:.Cu0) Figure 5-5 Status Register MIPS R4000 Microprocessor User's Manual...
Page 136 TLB refill exception is used for TLB misses on kernel addresses. 32 bit 64 bit Enables 64-bit addressing and operations in Supervisor mode. The extended-addressing TLB refill exception is used for TLB misses on supervisor addresses. 32 bit 64 bit MIPS R4000 Microprocessor User's Manual...
Page 137: Mode Bits
NMI, or Cache Error exception are taken. normal error Exception Level; set by the processor when any exception other than Reset, Soft Reset, NMI, or Cache Error exception are taken. normal exception Interrupt Enable disable interrupts enables interrupts MIPS R4000 Microprocessor User's Manual...
Page 138 CE = 1; see description of the ECC register. Specifies that cache parity or ECC errors cannot cause exceptions. parity/ECC remain enabled disables parity/ECC Reserved. Must be written as zeroes, and returns zeroes when read. MIPS R4000 Microprocessor User's Manual...
Page 139: Status Register Modes And Access States
Kernel mode. Supervisor Address Space Accesses: Access to the supervisor address space is allowed when the processor is in Kernel or Supervisor mode, as described above in the section above titled, Operating Modes. MIPS R4000 Microprocessor User's Manual...
Page 140: Status Register Reset
Coprocessor unit number referenced when a Coprocessor Unusable exception is taken. Indicates an interrupt is pending. interrupt pending no interrupt ExcCode Exception code field (see Table 5-6) Reserved. Must be written as zeroes, and returns zeroes when read. MIPS R4000 Microprocessor User's Manual...
Page 141 Breakpoint exception Reserved instruction exception Coprocessor Unusable exception Arithmetic Overflow exception Trap exception VCEI Virtual Coherency Exception instruction Floating-Point exception 16–22 – Reserved WATCH Reference to WatchHi/WatchLo address 24–30 – Reserved VCED Virtual Coherency Exception data MIPS R4000 Microprocessor User's Manual...
Page 142: Exception Program Counter (Epc) Register (14)
The processor does not write to the EPC register when the EXL bit in the Status register is set to a 1. Figure 5-8 shows the format of the EPC register. EPC Register 32-bit Mode 64-bit Mode Figure 5-8 EPC Register Format MIPS R4000 Microprocessor User's Manual...
Page 143: Watchlo (18) And Watchhi (19) Registers
CPU Exception Processing WatchLo (18) and WatchHi (19) Registers R4000 processors provide a debugging feature to detect references to a selected physical address; load and store operations to the location specified by the WatchLo and WatchHi registers cause a Watch exception (described later in this chapter).
Page 144: Xcontext Register (20)
The Page Table Entry Base read/write field is normally written with a value PTEBase that allows the operating system to use the Context register as a pointer into the current PTE array in memory. MIPS R4000 Microprocessor User's Manual...
Page 145: Error Checking And Correcting (Ecc) Register (26)
An 8-bit field specifying the ECC bits read from or written to a secondary cache, or the even byte parity bits to be read from or written to a primary cache. Reserved. Must be written as zeroes, and returns zeroes when read. MIPS R4000 Microprocessor User's Manual...
Page 146: Cache Error (Cacheerr) Register (27)
Table 5-10 CacheErr Register Fields Field Description Type of reference instruction data Cache level of the error primary secondary Indicates if a data field error occurred no error error Indicates if a tag field error occurred no error error MIPS R4000 Microprocessor User's Manual...
Page 147 Bits vAddr(14:12) of the doubleword in error (used with SIdx to construct PIdx a virtual index for the primary caches). Reserved. Must be written as zeroes, and returns zeroes when read. MIPS R4000 Microprocessor User's Manual...
Page 148: Error Exception Program Counter (Error Epc) Register (30)
There is no branch delay slot indication for the ErrorEPC register. Figure 5-13 shows the format of the ErrorEPC register. ErrorEPC Register 32-bit ErrorEPC Mode 64-bit ErrorEPC Mode Figure 5-13 ErrorEPC Register Format MIPS R4000 Microprocessor User's Manual...
Page 149: Processor Exceptions
Returning from an exception, also resets the EXL bit to 0 (see the ERET instruction in Appendix A). In the following sections, sample hardware processes for various exceptions are shown, together with the servicing required by the handler (software). MIPS R4000 Microprocessor User's Manual...
Page 150: Reset Exception Process
ER || EC || ED || ET || ES || EE || EB || EI || EW || 0 || SIdx || PIdx endif || 1 ||SR 31:3 if SR = 1 then 0xFFFF FFFF BFC0 0200 + 0x100 else 0xFFFF FFFF A000 0000 + 0x100 endif Figure 5-15 Cache Error Exception Processing MIPS R4000 Microprocessor User's Manual...
Page 151: Soft Reset And Nmi Exception Process
/* EXL */ 31:2 if SR = 1 then 0xFFFF FFFF BFC0 0200 + vector else 0xFFFF FFFF 8000 0000 + vector endif Figure 5-17 General Exception Processing (Except Reset, Soft Reset, NMI, and Cache Error) MIPS R4000 Microprocessor User's Manual...
Page 152: Exception Vector Locations
Table 5-12 Exception Vector Offsets Exception R4000 Processor Vector Offset TLB refill, EXL = 0 0x000 XTLB refill, EXL = 0 (X = 64-bit TLB) 0x080 Cache Error 0x100 Others 0x180 Reset, Soft Reset, NMI none MIPS R4000 Microprocessor User's Manual...
Page 153: Priority Of Exceptions
Watch Virtual Coherency –– Data access Bus error –– Data access Interrupt (lowest priority) Generally speaking, the exceptions described in the following sections are handled (“processed”) by hardware; these exceptions are then serviced by software. MIPS R4000 Microprocessor User's Manual...
Page 154: Reset Exception
• performing diagnostic tests • bootstrapping the operating system † In the following sections—indeed, throughout this book—a signal followed by an asterisk, such as Reset*, is low active. MIPS R4000 Microprocessor User's Manual...
Page 155: Soft Reset Exception
† In this book, a Soft Reset exception caused by assertion of the Reset* signal is referred to as a “soft reset” or “warm reset.” A Soft Reset exception caused by a nonmaskable interrupt (NMI) is referred to as a “nonmaskable interrupt exception.” MIPS R4000 Microprocessor User's Manual...
Page 156 It is not normally possible to continue program execution after returning from this exception, since a Reset* signal can be accepted anytime and an NMI can occur in the midst of another error exception. MIPS R4000 Microprocessor User's Manual...
Page 157: Address Error Exception
Address Error exception processing is shown in Figure 5-17. Servicing The process executing at the time is handed a UNIX SIGSEGV (segmentation violation) signal. This error is usually fatal to the process incurring the exception. MIPS R4000 Microprocessor User's Manual...
Page 158: Tlb Exceptions
TLB Modiﬁed occurs when a store operation virtual address reference to memory matches a TLB entry which is marked valid but is not dirty (the entry is not writable). The following three sections describe these TLB exceptions. MIPS R4000 Microprocessor User's Manual...
Page 159: Tlb Refill Exception
TLB. This condition is processed by allowing a TLB refill exception in the TLB refill handler. This second exception goes to the common exception vector because the EXL bit of the Status register is set. MIPS R4000 Microprocessor User's Manual...
Page 160: Tlb Invalid Exception
(for example, to maintain a reference bit) After servicing the cause of a TLB Invalid exception, the TLB entry is located with TLBP (TLB Probe), and replaced by an entry with that entry’s Valid bit set. MIPS R4000 Microprocessor User's Manual...
Page 161: Tlb Modified Exception
TLB entry that must be altered into the Index register. The EntryLo register is loaded with a word containing the physical page frame and access control bits (with the D bit set), and the EntryHi and EntryLo registers are written into the TLB. MIPS R4000 Microprocessor User's Manual...
Page 162: Cache Error Exception
Cache Error exception because error detection is disabled while ERL = 1, so the handler should avoid actions which might cause an unnoticed cache error. The R4400 (but not R4000) implements the EW bit in the CacheErr register to record a nonrecoverable error occurring while ERL = 1.
Page 163: Virtual Coherency Exception
Software can avoid the cost of this exception by using consistent virtual primary cache indexes to access the same physical data. † When a cache miss occurs, the processor reﬁlls the primary cache line at the present virtual index before taking an exception. MIPS R4000 Microprocessor User's Manual...
Page 164: Bus Error Exception
The virtual address of the load and store reference can then be obtained by interpreting the instruction. The physical address can be obtained by using the TLBP instruction and reading the EntryLo register to compute MIPS R4000 Microprocessor User's Manual...
Page 165: Integer Overflow Exception
The process executing at the time of the exception is handed a UNIX SIGFPE/FPE_INTOVF_TRAP (floating-point exception/integer overflow) signal. This error is usually fatal to the current process. † See Appendix A for a description of these instructions. MIPS R4000 Microprocessor User's Manual...
Page 166: Trap Exception
Servicing The process executing at the time of a Trap exception is handed a UNIX SIGFPE/FPE_INTOVF_TRAP (floating-point exception/integer overflow) signal. This error is usually fatal. † See Appendix A for a description of these instructions. MIPS R4000 Microprocessor User's Manual...
Page 167: System Call Exception
4 to the EPC register (EPC register + 4) before returning. If a SYSCALL instruction is in a branch delay slot, a more complicated algorithm, beyond the scope of this description, may be required. MIPS R4000 Microprocessor User's Manual...
Page 168: Breakpoint Exception
4 to the EPC register (EPC register + 4) before returning. If a BREAK instruction is in a branch delay slot, interpretation of the branch instruction is required to resume execution. MIPS R4000 Microprocessor User's Manual...
Page 169: Reserved Instruction Exception
Servicing No instructions in the MIPS ISA are currently interpreted. The process executing at the time of this exception is handed a UNIX SIGILL/ ILL_RESOP_FAULT (illegal instruction/reserved operand fault) signal. This error is usually fatal. MIPS R4000 Microprocessor User's Manual...
Page 170: Coprocessor Unusable Exception
• If the process is not entitled access to the coprocessor, the process executing at the time is handed a UNIX SIGILL/ ILL_PRIVIN_FAULT (illegal instruction/privileged instruction fault) signal. This error is usually fatal. MIPS R4000 Microprocessor User's Manual...
Page 171: Floating-Point Exception
This exception is cleared by clearing the appropriate bit in the Floating- Point Control/Status register. For an unimplemented instruction exception, the kernel should emulate the instruction; for other exceptions, the kernel should pass the exception to the user program that caused the exception. MIPS R4000 Microprocessor User's Manual...
Page 172: Watch Exception
To continue, the Watch exception must be disabled to execute the faulting instruction. The Watch exception must then be reenabled. The faulting instruction can be executed either by interpretation or by setting breakpoints. MIPS R4000 Microprocessor User's Manual...
Page 173: Interrupt Exception
(SW1 or SW0), the interrupt condition is cleared by setting the corresponding Cause register bit to 0. If the interrupt is hardware-generated, the interrupt condition is cleared by correcting the condition causing the interrupt pin to be asserted. MIPS R4000 Microprocessor User's Manual...
Page 174: Exception Handling And Servicing Flowcharts
• reset, soft reset and NMI exceptions, and a guideline to their handler. Generally speaking, the exceptions are handled by hardware (HW); the exceptions are then serviced by software (SW). MIPS R4000 Microprocessor User's Manual...
Page 175 & interrupt disabled (normal) =1 (bootstrap) PC <- 0xFFFF FFFF 8000 0000 + 180 PC <- 0xFFFF FFFF BFC0 0200 + 180 (unmapped, cached) (unmapped, uncached) To General Exception Servicing Guidelines Figure 5-18 General Exception Handler (HW) MIPS R4000 Microprocessor User's Manual...
Page 176 Jump Instruction * Processor does not execute the instruction which is ERET in the ERET’s branch delay slot * PC <- EPC; EXL <- 0 * LLbit <- 0 Figure 5-19 General Exception Servicing Guidelines (SW) MIPS R4000 Microprocessor User's Manual...
Page 177 (SR bit 22) PC <- 0xFFFF FFFF 8000 0000 + Vec.Off. PC <- 0xFFFF FFFF BFC0 0200 + Vec.Off. (unmapped, cached) (unmapped, uncached) To TLB/XTLB Exception Servicing Guidelines Figure 5-20 TLB/XTLB Miss Exception Handler (HW) MIPS R4000 Microprocessor User's Manual...
Page 178 Jump Instruction * Processor does not execute the instruction which is ERET in the ERET’s branch delay slot * PC <- EPC; EXL <- 0 * LLbit <- 0 Figure 5-21 TLB/XTLB Exception Servicing Guidelines (SW) MIPS R4000 Microprocessor User's Manual...
Page 179 * Processor does not execute the instruction which is in the ERET’s branch delay slot ERET * PC <- ErrorEPC; ERL <- 0 * LLbit <- 0 Figure 5-22 Cache Error Exception Handling (HW) and Servicing Guidelines (SW) MIPS R4000 Microprocessor User's Manual...
Page 180 Status bit 20 NMI Service Code (SR) Soft Reset Service Code Reset Service Code (Optional) ERET Figure 5-23 Reset, Soft Reset & NMI Exception Handling (HW) and Servicing Guidelines (SW) MIPS R4000 Microprocessor User's Manual...
Page 181 The FPU, with associated system software, fully conforms to the requirements of ANSI/IEEE Standard 754–1985, IEEE Standard for Binary Floating-Point Arithmetic. In addition, the MIPS architecture fully supports the recommendations of the standard and precise exceptions. MIPS R4000 Microprocessor User's Manual...
Page 182: Overview
Figure 6-1 illustrates the functional organization of the FPU. Data Cache Control FP Bypass Pipeline Chain FAdd FP Div FP Mul FP Sqrt FP Reg File Figure 6-1 FPU Functional Block Diagram MIPS R4000 Microprocessor User's Manual...
Page 183: Fpu Features
ﬂoating-point and ﬁxed-point instruction sets. Since each unit receives and executes instructions in parallel, some ﬂoating-point instructions can execute at the same single-cycle- per-instruction rate as ﬁxed-point instructions. MIPS R4000 Microprocessor User's Manual...
Page 184: Fpu Programming Model
FPRs), each of which is 64-bits wide, when the FR bit in the CPU Status register equals 1. The FPRs hold values in either single- or double-precision ﬂoating-point format. Each FPR corresponds to an FGR as shown in Figure 6-2. MIPS R4000 Microprocessor User's Manual...
Page 185 • • • FGR28 FPR28 FGR28 (least) FPR28 FGR29 FGR29 FPR29 (most) FGR30 FPR30 FGR30 (least) FPR30 (most) FPR31 FGR31 FGR31 Floating-Point Control Registers (FCR) Control/Status Register Implementation/Revision Register FCR31 FCR0 Figure 6-2 FPU Registers MIPS R4000 Microprocessor User's Manual...
Page 186: Floating-Point Registers
If the FR bit equals 0 during a double-precision floating-point operation, the general registers are accessed in double pairs. Thus, in a double- precision operation, selecting Floating-Point Register 0 (FPR0) actually addresses adjacent Floating-Point General Purpose registers FGR0 and FGR1. MIPS R4000 Microprocessor User's Manual...
Page 187: Floating-Point Control Registers
FCR1 to FCR30 are reserved. Table 6-1 lists the assignments of the FCRs. Table 6-1 Floating-Point Control Register Assignments FCR Number FCR0 Coprocessor implementation and revision register FCR1 to FCR30 Reserved FCR31 Rounding mode, cause, trap enables, and flags MIPS R4000 Microprocessor User's Manual...
Page 188: Implementation And Revision Register, (Fcr0)
For this reason revision number values are not listed, and software should not rely on the revision number to characterize the chip. MIPS R4000 Microprocessor User's Manual...
Page 189: Control/Status Register (Fcr31)
Cause, Flag, and Enable bits. Flag bits. See Figure 6-5 and the description of Control/Status register Flags Cause, Flag, and Enable bits. Rounding mode bits. See Table 6-4 and the description of Control/Status register Rounding Mode Control bits. MIPS R4000 Microprocessor User's Manual...
Page 190: Accessing The Control/Status Register
Move Control To Coprocessor 1 (CTC1) instruction. FCR31 must only be written to when the FPU is not actively executing floating-point operations; this can be ensured by reading the contents of the register to empty the pipeline. MIPS R4000 Microprocessor User's Manual...
Page 191: Ieee Standard 754
The Unimplemented Operation (E) bit is set to a 1 if software emulation is required, otherwise it remains 0. The other bits are set to 0 or 1 to indicate the occurrence or non-occurrence (respectively) of an IEEE 754 exception. MIPS R4000 Microprocessor User's Manual...
Page 192 Status register, using a Move To Coprocessor Control instruction. When a floating-point exception is taken, the flag bits are not set by the hardware; floating-point exception software is responsible for setting these bits before invoking a user handler. MIPS R4000 Microprocessor User's Manual...
Page 193: Control/Status Register Rounding Mode Control Bits
Round toward + : round to value closest to and not less than the infinitely precise result. Round toward – : round to value closest to and not greater than the infinitely precise result. MIPS R4000 Microprocessor User's Manual...
Page 194: Floating-Point Formats
• -1 (to encode 0 and denormalized numbers) • +1 (to encode and NaNs [Not a Number]) For single- and double-precision formats, each representable nonzero numerical value has just one encoding. MIPS R4000 Microprocessor User's Manual...
Page 195 Table 6-6 Floating-Point Format Parameter Values Format Parameter Single Double +127 +1023 –126 –1022 Exponent bias +127 +1023 Exponent width in bits Integer bit hidden hidden f (Fraction width in bits) Format width in bits MIPS R4000 Microprocessor User's Manual...
Page 196: Binary Fixed-Point Format
Sign Integer Figure 6-8 Binary Fixed-Point Format Field assignments of the binary fixed-point format are: Table 6-8 Binary Fixed-Point Format Fields Field Description sign sign bit integer integer value MIPS R4000 Microprocessor User's Manual...
Page 197: Floating-Point Instruction Set Overview
Store Doubleword From FPU MTC1 Move Word To FPU MFC1 Move Word From FPU CTC1 Move Control Word To FPU CFC1 Move Control Word From FPU DMTC1 Doubleword Move To FPU DMFC1 Doubleword Move From FPU MIPS R4000 Microprocessor User's Manual...
Page 198 Table 6-12 FPU Instruction Summary: Compare and Branch Instructions OpCode Description C.cond.fmt Floating-point Compare BC1T Branch on FPU True BC1F Branch on FPU False BC1TL Branch on FPU True Likely BC1FL Branch on FPU False Likely MIPS R4000 Microprocessor User's Manual...
Page 199: Floating-Point Load, Store, And Move Instructions
The instruction immediately following a load can use the contents of the loaded register. In such cases the hardware interlocks, requiring additional real cycles; for this reason, scheduling load delay slots is desirable, although it is not required for functional code. MIPS R4000 Microprocessor User's Manual...
Page 200: Data Alignment
Branch on FPU Condition Instructions Table 6-12 lists the Branch on FPU (coprocessor unit 1) condition instructions that can test the result of the FPU compare (C.cond) instructions. Appendix B gives a detailed description of each instruction. MIPS R4000 Microprocessor User's Manual...
Page 201: Floating-Point Compare Operations
Not Greater Than or Less Greater Than or Less Than Than Not Less Than Less Than Greater Than or Equal Not Greater Than or Equal Not Less Than or Equal Less Than or Equal Greater Than Not Greater Than MIPS R4000 Microprocessor User's Manual...
Page 202: Fpu Instruction Pipeline Overview
FPU instructions, however, require more than one cycle in the EX stage. This means the FPU must stall the pipeline if an instruction execution cannot proceed because of register or resource conflicts. Figure 6-10 illustrates the effect of a three-cycle stall on the FPU pipeline. MIPS R4000 Microprocessor User's Manual...
Page 203: Instruction Execution Cycle Time
Table 6-14 gives the minimum latency, in processor pipeline cycles, of each floating-point operation for the currently implemented configurations. These latency calculations assume the result of the operation is immediately used in a succeeding operation. MIPS R4000 Microprocessor User's Manual...
Page 204 BC1T DIV.fmt BC1F SQRT.fmt BC1TL ABS.fmt BC1FL MOV.fmt LWC1 NEG.fmt SWC1 ROUND.[W,L].fmt LDC1 TRUNC.[W,L].fmt SDC1 CEIL.[W,L].fmt MTC1 FLOOR.[W,L].fmt MFC1 CVT.S.fmt CTC1 CVT.D.fmt CFC1 (a) ..These operations are illegal. (b) ..These operations are undeﬁned. MIPS R4000 Microprocessor User's Manual...
Page 205: Scheduling Fpu Instructions
Description FPU Adder Mantissa Add stage FPU Adder Exception Test stage CPU EX stage FPU Multiplier 1st stage FPU Multiplier 2nd stage FPU Adder Result Round stage FPU Adder Operand Shift stage FPU Unpack stage MIPS R4000 Microprocessor User's Manual...
Page 206: Instruction Scheduling Constraints
– – – – – – – – – – – MUL.[S.D] – – – – – – – – – MUL.[S.D] – – – – – – MUL.[S.D] – – – MUL.[S.D] MUL.[S.D] Figure 6-11 MUL.S Instruction Scheduling in the FPU Multiplier MIPS R4000 Microprocessor User's Manual...
Page 207 Figure 6-13. NEG.[S,D] ADD.[S,D] S+A A+R R+S C.COND.[S,D] SQRT.[S,D] E A+R . . . A+R R ..ADD.[S,D] Figure 6-13 Instruction Cycle Overlap in FPU Adder MIPS R4000 Microprocessor User's Manual...
Page 208 – – – – – – – – – – – S+A A+R R+S Indicates a resource conflict – – – – – – – – – S+A A+R R+S Figure 6-15 MUL.S and ADD.[S,D] Cycle Conflict in FPU Adder MIPS R4000 Microprocessor User's Manual...
Page 209 – – – – – – – – – † While there is no resource conﬂict in issuing this CMP.[S,D] instruction, the hardware does not allow it. Figure 6-17 MUL.S and CMP.[S,D] Cleanup Cycle Conflict in FPU Adder MIPS R4000 Microprocessor User's Manual...
Page 210 . . . DIV.D S+R S+D D A+D R+D A+D R+D A ..ADD.[S,D] S+A A+R R+S ..CMP.[S,D] Figure 6-18 Adder Prep and Cleanup Cycle Overlap MIPS R4000 Microprocessor User's Manual...
Page 211: Instruction Latency, Repeat Rate, And Pipeline Stage Sequences
ABS.[S,D] CVT.S.W CVT.D.W CVT.S.L CVT.D.L CVT.D.S CVT.S.D CVT.[W,L].[S,D] or ROUND.[W,L].[S,D] or TRUNC.[W,L].[S,D] or CEIL.[W,L].[S,D] or FLOOR.[W,L].[S,D] MUL.S MUL.D D...D DIV.S D/R A R D...D DIV.D SQRT.S 2–54 2–53 A+R ... SQRT.D 2–112 2–111 A+R ... MIPS R4000 Microprocessor User's Manual...
Page 212: Resource Scheduling Rules
The multiplier is either idle, or in its second-to-last execution cycle. Idle means an operation unit—adder, multiplier or divider—is either not processing any instruction, or is currently in its last execution cycle completing an instruction. MIPS R4000 Microprocessor User's Manual...
Page 213 - idle, or in its second-to-last execution cycle. - in the ﬁrst 8 execution cycles (EX...EX+7) of a DIV.S - in the ﬁrst 21 execution cycles, except for the second execution cycle, (cycles EX, EX+2...EX+20) of a DIV.D) MIPS R4000 Microprocessor User's Manual...
Page 214 The divider is one of the following: - idle, or in its second-to-last execution cycle. - in the third through eighth execution cycle (EX+2...EX+7) of a DIV.S - in the third through twenty-ﬁrst execution cycle (EX+2...EX+20) of a DIV.D MIPS R4000 Microprocessor User's Manual...
Page 215 The divider is one of the following: - idle, or in its second-to-last execution cycle. - in the third through eighth execution cycle (EX+2...EX+7) of a DIV.S - in the third through twenty-ﬁrst execution cycle (EX+2...EX+20) of a DIV.D MIPS R4000 Microprocessor User's Manual...
Page 216 Chapter 6 MIPS R4000 Microprocessor User's Manual...
Page 217: Floating-Point Exceptions
A ﬂoating-point exception occurs whenever the FPU cannot handle either the operands or the results of a ﬂoating-point operation in its normal way. The FPU responds by generating an exception to initiate a software trap or by setting a status ﬂag. MIPS R4000 Microprocessor User's Manual...
Page 218: Exception Types
The Unimplemented Operation exception has no Enable or Flag bit; whenever this exception occurs, an unimplemented exception trap is taken (if the FPU interrupt input to the CPU is enabled). Figure 7-1 illustrates the Control/Status register bits that support exceptions. MIPS R4000 Microprocessor User's Manual...
Page 219: Exception Trap Processing
Floating-Point Exception (FPE) code is used, and the Cause bits of the ﬂoating-point Control/Status register indicate the reason for the ﬂoating- point exception. These bits are, in effect, an extension of the system coprocessor Cause register. MIPS R4000 Microprocessor User's Manual...
Page 220: Flags
+ Modify positive overflows to the format’s largest finite number; modify negative overflows to – Division by Supply a properly signed zero Invalid Supply a quiet Not a Number (NaN) operation MIPS R4000 Microprocessor User's Manual...
Page 221 ‡ Exponent underﬂow sets the U and I Cause bits if both the U and I Enable bits are not set and the FS bit is set; otherwise exponent underﬂow sets the E Cause bit. MIPS R4000 Microprocessor User's Manual...
Page 222: Fpu Exceptions
Trap Enabled Results: If Inexact exception traps are enabled, the result register is not modiﬁed and the source registers are preserved. Trap Disabled Results: The rounded or overﬂowed result is delivered to the destination register if no other software trap occurs. MIPS R4000 Microprocessor User's Manual...
Page 223: Invalid Operation Exception (V)
(–5) or cos–1(3). Refer to Appendix B for examples or for routines to handle these cases. Trap Enabled Results: The original operand values are undisturbed. Trap Disabled Results: A quiet NaN is delivered to the destination register if no other software trap occurs. MIPS R4000 Microprocessor User's Manual...
Page 224: Division-By-Zero Exception (Z)
Trap Enabled Results: The result register is not modiﬁed, and the source registers are preserved. Trap Disabled Results: The result, when no trap occurs, is determined by the rounding mode and the sign of the intermediate result (as listed in Table 7-1). MIPS R4000 Microprocessor User's Manual...
Page 225: Underflow Exception (U)
Trap Disabled Results: If Underﬂow and Inexact traps are not enabled and the FS bit is set, the result is determined by the rounding mode and the sign of the intermediate result (as listed in Table 7-1). MIPS R4000 Microprocessor User's Manual...
Page 226: Unimplemented Instruction Exception (E)
IEEE Standard 754. Trap Enabled Results: The original operand values are undisturbed. Trap Disabled Results: This trap cannot be disabled. MIPS R4000 Microprocessor User's Manual...
Page 227: Saving And Restoring State
If an exception is possible, the FPU executes the instruction in stall mode to ensure that no more than one instruction (that might cause an exception) is executed at a time. MIPS R4000 Microprocessor User's Manual...
Page 228: Trap Handlers For Ieee Standard 754 Exceptions
The IEEE Standard 754 recommends that, if enabled, the overﬂow and underﬂow traps take precedence over a separate inexact trap. This prioritization is accomplished in software; hardware sets the bits for both the Inexact exception and the Overﬂow or Underﬂow exception. MIPS R4000 Microprocessor User's Manual...
Page 229: R4000 Processor Signal Descriptions
R4000 Processor Signal Descriptions This chapter describes the signals used by and in conjunction with the R4000 processor. The signals include the System interface, the Clock/ Control interface, the Secondary Cache interface, the Interrupt interface, the Joint Test Action Group (JTAG) interface, and the Initialization interface.
Page 230 ColdReset* Fault* Reset* VccP VssP Status(7:0) JTDI VccSense JTDO VssSense JTMS JTCK (1) = R4000SC and R4000MC only (2) = R4000PC only (3) = R4000MC only (4) = R4400 only Figure 8-1 R4000 Processor Signals MIPS R4000 Microprocessor User's Manual...
Page 231: System Interface Signals
R4000 Processor Signal Descriptions 8.1 System Interface Signals System interface signals provide the connection between the R4000 processor and the other components in the system. IvdAck* and IvdErr* signals are applicable only on R4000MC; on the R4000SC they must be tied to Vcc.
Page 232 WrRdy* when it can accept WrRdy* a processor write request. †. The SysADC(7:0) bits map to the SysAD bus in this manner: SysADC(7) covers SysAD(63:56), SysADC(6) covers SysAD(55:48), and so on down to SysADC(0), which covers SysAD(7:0). MIPS R4000 Microprocessor User's Manual...
Page 233: Clock/Control Interface Signals
TClock(1:0) Transmit clocks Output that establish the System interface frequency. The processor asserts Fault* to indicate a mismatch output of Fault* Fault Output boundary comparators, and indication of System interface input parity or ECC errors. MIPS R4000 Microprocessor User's Manual...
Page 234 Vss node to a package pin Input/ without having to connect to the VssSense Vss sense Output in-package ground planes. VssSense should be connected to Vss in functional system designs. MIPS R4000 Microprocessor User's Manual...
Page 235: Secondary Cache Interface Signals
R4000 Processor Signal Descriptions 8.3 Secondary Cache Interface Signals Secondary Cache interface signals constitute the interface between the R4000 processor and secondary cache. These signals are available only on the R4000MC and R4000SC. Table 8-3 lists the Secondary Cache interface signals.
Page 236 RAM. Secondary cache Write enable for the secondary SCWrY* Output write enable cache data and tag RAM. Secondary cache Write enable for the secondary SCWrZ* Output write enable cache data and tag RAM. MIPS R4000 Microprocessor User's Manual...
Page 237: Interrupt Interface Signals
8.4 Interrupt Interface Signals The Interrupt interface signals make up the interface used by external agents to interrupt the R4000 processor. Int*(5:1) are available only on the R4000PC; Int*(0) and NMI* are available on all three conﬁgurations. Table 8-4 lists the Interrupt interface signals.
Page 238: Initialization Interface Signals
The assertion of VCCOk initiates the initialization sequence. †. A warm reset restarts processor, but does not affect clocks; it preserves the processor in- ternal state. A description of warm reset is given in Chapter 9. MIPS R4000 Microprocessor User's Manual...
Page 239: Signal Summary
System command/data identifier bus SysCmd(8:0) High System command/data identifier bus parity SysCmdP High Valid input ValidIn* Valid output ValidOut* External request ExtRqst* Release interface Release* Read ready RdRdy* Write ready WrRdy* Invalidate acknowledge IvdAck* Invalidate error IvdErr* MIPS R4000 Microprocessor User's Manual...
Page 240 IOIn High Vcc is OK VCCOk High Cold reset ColdReset* Reset Reset* Fault Fault* Quiet Vcc for PLL VccP High Quiet Vss for PLL VssP High Status Status(7:0) High Vcc sense VccSense Vss sense VssSense MIPS R4000 Microprocessor User's Manual...
Page 241 Receive clocks RClock(1:0) High Master clock MasterClock High Master clock out MasterOut High Synchronization clock out SyncOut High Synchronization clock in SyncIn High I/O output IOOut High I/O input IOIn High Vcc is OK VCCOk High MIPS R4000 Microprocessor User's Manual...
Page 242 Chapter 8 Table 8-8 (cont.) R4000PC Processor Signal Summary Asserted Description Name 3-State State Cold reset ColdReset* Reset Reset* Fault Fault* Quiet Vcc for PLL VccP High Quiet Vss for PLL VssP High MIPS R4000 Microprocessor User's Manual...
Page 243: Initialization Interface
Initialization Interface This chapter describes the R4000 Initialization interface. This includes the reset signal description and types, initialization sequence, with signals and timing dependencies, and boot modes, which are set at initialization time. Signal names are listed in bold letters—for instance the signal VCCOk indicates +5 voltage is stable.
Page 244: Functional Overview
Chapter 9 9.1 Functional Overview The R4000 processor has the following three types of resets; they use the VCCOk, ColdReset*, and Reset* input signals. • Power-on reset: starts when the power supply is turned on and completely reinitializes the internal state machine of the processor without saving any state information.
Page 245: Reset Signal Description
† Asserted means the signal is true, or in its valid state. For example, the low-active Reset* signal is said to be asserted when it is in a low (true) state; the high-active VCCOk signal is true when it is asserted high. MIPS R4000 Microprocessor User's Manual...
Page 246: Power-On Reset
64 MasterClock cycles after the deassertion of ColdReset*.) Reset* must be deasserted synchronously with MasterClock. NOTE: ColdReset* must be asserted when VCCOk asserts. The behavior of the processor is undefined if VCCOk asserts while ColdReset* is deasserted. MIPS R4000 Microprocessor User's Manual...
Page 247: Cold Reset
† Since MasterOut is undeﬁned until after the serial PROM is read, reset logic must not depend on MasterOut before the boot PROM is read. MIPS R4000 Microprocessor User's Manual...
Page 248: Initialization Sequence
ModeClock. The processor samples 256 initialization bits from the ModeIn input. Figures 9-1, 9-2, and 9-3 on the next three pages show the timing diagrams for the power-on, warm, and cold resets. MIPS R4000 Microprocessor User's Manual...
Page 249 Power-on Reset (POR) 5.25V 4.75V Wavy lines indicate one or more identical cycles, not shown due to space constraints MasterClock (MClk) > 100ms VCCOK MClk 256 MClk cycles cycles ModeClock TMDS TMDH Bit 0 Bit 1 ModeIn > 64K MClk cycles* ColdReset* >...
Page 250 Cold Reset Wavy lines indicate one or more identical cycles, not shown due to space constraints MasterClock (MClk) > 64 MClk cycles VCCOK MClk MClk 256 MClk cycles 256 MClk cycles cycles cycles ModeClock TMDS TMDH Bit 1 Bit 0 ModeIn >...
Page 251: Warm Reset
Warm Reset Wavy lines indicate one or more identical cycles, not shown due to space constraints MasterClock (MClk) VCCOK 256 MClk cycles ModeClock ModeIn ColdReset* > 64 MClk cycles Reset* Undefined MasterOut Undefined SyncOut Undefined TClock Undefined RClock...
Page 252: Sequential Ordering
No secondary cache present SysPort: System Interface port width, bit 6 most significant 64 bits Reserved SC64BitMd: Secondary cache interface port width 128 bits Reserved EISpltMd: Specifies secondary cache organization Secondary cache unified Secondary cache split MIPS R4000 Microprocessor User's Manual...
Page 253 Otherwise, only compulsory updates are issued Potential updates enabled Potential updates disabled TWrSUp: Secondary cache write deassertion delay, T in PCycles, bit WrSup 24 most significant 21:24 Undefined 3-15 Number of PClock cycles: Min 3, Max 15 MIPS R4000 Microprocessor User's Manual...
Page 254 NoMPmode off: after a secondary cache miss, the existing valid cache line is invalidated (following writeback if necessary) NoMPmode on: after a secondary cache miss, the existing valid cache line is not invalidated. Available on the R4000SC and R4400SC, to improve performance. MIPS R4000 Microprocessor User's Manual...
Page 255 Secondary Cache Master (SCMaster, paired with SIMaster) 43:45 Reserved Pkg179: R4000 Processor Package type Large (447 pin) Small (179 pin) CycDivisor: This mode determines the clock divisor for the reduced power mode. When the RP bit in the Status register is set to 1, the pipeline clock is divided by one of the following values.
Page 256 RClock, TClock, SClock, and the internal clocks. Enable PLLs Disable PLLs SRTristate: Controls when output-only pins are tristated Only when ColdReset* is asserted When Reset* or ColdReset* are asserted 65:255 Reserved. Scan in zeros. MIPS R4000 Microprocessor User's Manual...
Page 257: Clock Interface
Clock Interface This chapter describes the clock signals (“clocks”) used in the R4000 processor and the processor status reporting mechanism. The subject matter includes basic system clocks, system timing parameters, connecting clocks to a phase-locked system, connecting clocks to a system without phase locking, and processor status outputs.
Page 258: Signal Terminology
(clock) to the output of the device (Q). Figures 10-1 and 10-2 illustrate these terms. single clock cycle high-to-low transition low-to-high transition Figure 10-1 Signal Transitions data out data in clock input Clock-to-Q delay Figure 10-2 Clock-to-Q Delay MIPS R4000 Microprocessor User's Manual...
Page 259: Basic System Clocks
Clock Interface 10.2 Basic System Clocks The various clock signals used in the R4000 processor are described below, starting with MasterClock, upon which the processor bases all internal and external clocking. MasterClock The processor bases all internal and external clocking on the single MasterClock input signal.
Page 260: Sclock
Chapter 10 SClock The R4000 processor divides PClock by 2, 3, or 4 (as programmed at boot- mode initialization) to generate the internal clock signal, SClock. The R4400 processor divides PClock by 2, 3, 4, 6 or 8 (as programmed at boot- mode initialization) to generate SClock.
Page 261 Clock Interface Cycle MasterClock MCkHigh MCkLow MCkP MasterOut PClock SClock TClock RClock SysAD Driven SysAD Received Figure 10-3 Processor Clocks, PClock-to-SClock Division by 2 MIPS R4000 Microprocessor User's Manual...
Page 262 Chapter 10 cycle MasterClock SyncOut PClock SClock TClock RClock SysAD Driven t DM t DO SysAD Received t DS t DH Figure 10-4 Processor Clocks, PClock-to-SClock Division by 4 MIPS R4000 Microprocessor User's Manual...
Page 263: System Timing Parameters
Clocks generated using PLL circuits contain some inherent inaccuracy, or jitter; a clock aligned with MasterClock by the PLL can lead or trail MasterClock by as much as the related maximum jitter allowed by the individual vendor. MIPS R4000 Microprocessor User's Manual...
Page 264: Connecting Clocks To A Phase-Locked System
(Clock Jitter for A Max) – (Clock Jitter for B Max) Figure 10-5 shows a block-level diagram of a phase-locked system using the R4000 processor. MasterClock External Agent R4000 MasterClock MasterClock SysCmd SysCmd SysAD SysAD SyncOut SyncIn RClock TClock Figure 10-5 R4000 Processor Phase-Locked System MIPS R4000 Microprocessor User's Manual...
Page 265: Connecting Clocks To A System Without Phase Locking
Clock Interface 10.5 Connecting Clocks to a System without Phase Locking When the R4000 processor is used in a system in which the external agent cannot lock its phase to a common MasterClock, the output clocks RClock and TClock can clock the remainder of the system. Two clocking methodologies are described in this section: connecting to a gate-array device or connecting to discrete CMOS logic devices.
Page 266 Chapter 10 Sampling Staging Register Register Gate Array MasterClock R4000 MasterClock SysCmd SysAD SyncOut SyncIn RClock TClock Sampling Staging Register Register Figure 10-6 Gate-Array System without Phase Lock, using the R4000 Processor MIPS R4000 Microprocessor User's Manual...
Page 267 R4000) + (Minimum External Clock Buffer Delay) – (External Sample Register Setup Time) – (Maximum Clock Jitter for R4000 Internal Clocks) – (Maximum Clock Jitter for RClock) The transmission time for a signal from an external agent composed of gate...
Page 268: Connecting To A Cmos Logic System
– (Maximum Clock Jitter for TClock) Figure 10-7 is a block diagram of a system without phase lock, employing the R4000 processor and an external agent composed of both a gate array and discrete CMOS logic devices. MIPS R4000 Microprocessor User's Manual...
Page 269 Clock Interface MasterClock R4000 MasterClock SysCmd Control SysAD Gate Array SyncOut SyncIn RClock TClock Sample Registers Memory Memory Figure 10-7 Gate Array and CMOS System without Phase Lock, using the R4000 Processor MIPS R4000 Microprocessor User's Manual...
Page 270 – (Maximum External Output Register Clock-to-Q Delay) – (Maximum External Clock Buffer Delay Mismatch) – (Maximum Clock Jitter for R4000 Internal Clocks) – (Maximum Clock Jitter for TClock) In this clocking methodology, the hold time of data driven from the processor to an external sampling register is a critical parameter.
Page 271: Processor Status Outputs
The Status(7:0) bits are treated as two fields, as follows: • The Status(7:4) ﬁeld indicates the internal status of the processor during PCycle T-3. • The Status(3:0) bits indicate the internal status of the processor during the PCycle T-2. MIPS R4000 Microprocessor User's Manual...
Page 272 Secondary cache stall Other floating-point instruction (not load, store, or Run cycle conditional branch) Run cycle Instruction killed by branch, jump, or ERET Run cycle Instruction killed by exception Run cycle Floating-point instruction killed by slip MIPS R4000 Microprocessor User's Manual...
Page 273 Cache Organization, Operation, and Coherency This chapter describes in detail the cache memory: its place in the R4000 memory organization, individual operations of the primary and secondary caches, cache interactions, and an example of a cache coherency request cycle. The chapter concludes with a description of R4000 processor synchronization in a multiprocessor environment.
Page 274: Memory Organization
Chapter 11 11.1 Memory Organization Figure 11-1 shows the R4000 system memory hierarchy. In the logical memory hierarchy, caches lie between the CPU and main memory. They are designed to make the speedup of memory accesses transparent to the user. Each functional block in Figure 11-1 has the capacity to hold more data than the block above it.
Page 275: Overview Of Cache Operations
The R4000 processor has two on-chip primary caches: one holds instructions (the instruction cache), the other holds data (the data cache). Off-chip, the R4000 processor supports a secondary cache on the R4000SC and MC models. 11.2 Overview of Cache Operations As described earlier, caches provide fast temporary data storage, and they make the speedup of memory accesses transparent to the user.
Page 276: R4000 Cache Description
11.3 R4000 Cache Description As Figure 11-1 shows, the R4000 contains separate primary instruction and data caches. Figure 11-1 also shows that the R4000 supports a secondary cache that can be split into separate portions, one portion containing data and the other portion containing instructions, or it can be a joint cache, holding combined instructions and data.
Page 277 Caches D-cache Primary and Secondary Cache R4000SC/MC Main Memory Cache Controller I-cache Primary Caches D-cache I-cache primary instruction cache Secondary Cache D-cache primary data cache Figure 11-2 Cache Support in the R4000PC, R4000SC, and R4000MC MIPS R4000 Microprocessor User's Manual...
Page 278: Secondary Cache Size
The primary instruction and data caches are indexed with a virtual address (VA), while the secondary cache is indexed with a physical address (PA). † Primary and secondary cache tags are described in the following sections. MIPS R4000 Microprocessor User's Manual...
Page 279: Organization Of The Primary Instruction Cache (I-Cache)
26-bit tag that contains a 24-bit physical address, a single valid bit, and a single parity bit. Byte parity is used on I-cache data. The R4000 processor primary I-cache has the following characteristics: • direct-mapped •...
Page 280: Organization Of The Primary Data Cache (D-Cache)
24-bit physical address, 2-bit cache line state, a write-back bit, a parity bit for the physical address and cache state fields, and a parity bit for the write-back bit. Byte parity is used on D-cache data. The R4000 processor primary D-cache has the following characteristics: • write-back •...
Page 281: Accessing The Primary Caches
Cache Organization, Operation, and Coherency In all R4000 processors, the W (write-back) bit, not the cache state, indicates whether or not the primary cache contains modified data that must be written back to memory or to the secondary cache. Accessing the Primary Caches Figure 11-5 shows the virtual address (VA) index into the primary caches.
Page 282: Organization Of The Secondary Cache
I- and D-caches. Figure 11-6 shows the format of the R4000 processor secondary-cache line. The size of the secondary cache line is set in the SB field of the Config register.
Page 283 Cache Organization, Operation, and Coherency The R4000 processor secondary cache has the following characteristics: • write-back • direct-mapped • indexed with a physical address • checked with a physical tag • organized with either a 4-word (16-byte), 8-word (32-byte), 16-word (64-byte), or 32-word (128-byte) cache line.
Page 284: Accessing The Secondary Cache
PA(21:n*) PIdx *n = 4 for 4-word lines n = 5 for 8-word lines n = 6 for 16-word lines n = 7 for 32-word lines Data Figure 11-7 Secondary Cache Data and Tag Organization MIPS R4000 Microprocessor User's Manual...
Page 285: Cache States
Shared: a cache line that is present in more than one cache in the system. Each primary and secondary cache line in the R4000 system is in one of the states described in Table 11-3. Table 11-3 also lists with the types of cache and the R4000 models in which the various states may be found.
Page 286: Primary Cache States
Each primary instruction cache line is in one of the following states: • invalid • valid Secondary Cache States Each secondary cache line is in one of the following states: • invalid • shared • dirty shared • clean exclusive • dirty exclusive MIPS R4000 Microprocessor User's Manual...
Page 287: Mapping States Between Caches
R4000PC Invalid State Invalid State Invalid State Dirty Exclusive State Clean Exclusive State Clean Exclusive State Dirty Exclusive State Dirty Exclusive State Shared State Figure 11-8 Primary Cache States Available to Each Type of Processor MIPS R4000 Microprocessor User's Manual...
Page 288: Cache Line Ownership
(Chapter 12 deﬁnes external agent). • Memory always owns clean cache lines. • The processor gives up ownership of a cache line when the state of the cache line changes to invalid, shared, or clean exclusive. MIPS R4000 Microprocessor User's Manual...
Page 289: Cache Write Policy
(see the section titled Cache Coherency Overview later in this chapter). In the R4000 system, when the content of a cache line is inconsistent with memory, it is classified as dirty and is written back to memory according to the rules of the cache write-back policy.
Page 290: Cache State Transition Diagrams
• A store to a dirty exclusive line remains in a dirty exclusive state. These state diagrams do not cover the initial state of the system since the initial state is system dependent. MIPS R4000 Microprocessor User's Manual...
Page 291 Bus read [intervention] Figure 11-9 Primary Data Cache State Diagram If the system is in no-secondary-cache mode, the cache state provided by the system is ignored, and the primary data cache state is set to dirty exclusive. MIPS R4000 Microprocessor User's Manual...
Page 292 Update received Write hit Write hit [invalidate] Bus read [intervention] Write hit [update], Read hit Dirty Write hit [invalidate] Dirty Read hit, Write hit Exclusive Shared Bus read [intervention] Figure 11-10 Secondary Cache State Diagram MIPS R4000 Microprocessor User's Manual...
Page 293 For case 1, if the refill occurs on a store miss, the processor changes the cache line state to dirty exclusive. For each of the remaining cases listed above, the R4000 processor passes the state received from the external agent to the secondary cache.
Page 294: Cache Coherency Overview
Noncoherent read Noncoherent read Invalidate † Exclusive Coherent read exclusive Coherent read exclusive Invalidate Sharable Coherent read Coherent read exclusive Invalidate Update Coherent read Coherent read Update † These should not occur under normal circumstances. MIPS R4000 Microprocessor User's Manual...
Page 295: Uncached
† A coherent read that requests exclusivity implies that the processor functions most efﬁciently if the requested cache line is returned to it in an exclusive state, but the processor still performs correctly if the cache line is returned in a shared state. MIPS R4000 Microprocessor User's Manual...
Page 296: Exclusive
Cache Operation Modes The R4000 processor supports the following two cache modes: • secondary-cache mode (R4000MC and R4000SC models; for R4000MC all ﬁve cache coherency attributes described above...
Page 297: Strong Ordering
X precedes the store to location Y, or vice versa. If this global ordering is enforced, the test algorithm for strong ordering succeeds. MIPS R4000 Microprocessor User's Manual...
Page 298: Restarting The Processor
If either IvdAck* or IvdErr* is asserted during or after the ﬁrst cycle that the external agent asserts ExtRqst*, the processor accepts the external request and completes any cache state changes associated with the external request before restarting. † That is, present but not yet executed. MIPS R4000 Microprocessor User's Manual...
Page 299: Maintaining Coherency On Loads And Stores
Set the primary data cache state to Dirty Exclusive None Dirty Exclusive. † Dirty Exclusive Dirty Exclusive None None † The dirty exclusive primary state allows the primary cache to be written without a secondary access. MIPS R4000 Microprocessor User's Manual...
Page 300: Manipulation Of The Cache By An External Agent
ﬁrst process by setting the state of the remaining cache line. MIPS R4000 Microprocessor User's Manual...
Page 301: Intervention
R4000MC • coherent read • invalidate • update External Agent • invalidate • update external coherency request • snoop • intervention Figure 11-11 Coherency Requests: Processor and External MIPS R4000 Microprocessor User's Manual...
Page 302: How Coherency Conflicts Arise
In such a case, the processor simply discards any external coherency requests that conflict with a pending processor coherent read request. MIPS R4000 Microprocessor User's Manual...
Page 303: Processor Invalidate Or Update Requests
Processor potential update requests cannot be cancelled. Potential updates are always issued with processor read requests and become compulsory only after the response to the processor read request is returned in one of the shared states. MIPS R4000 Microprocessor User's Manual...
Page 304: External Coherency Requests
Invalidate or Update Unacknowledged: a processor invalidate or update request has been issued but has not yet been acknowl- edged. By definition, no coherent read request is pending. MIPS R4000 Microprocessor User's Manual...
Page 305: System Implications Of Coherency Conflicts
The constraints that the processor must place on the handling of coherency conflicts have certain implications on the design of a multiprocessor system using the R4000MC model. These constraints and their implications are described in this section. MIPS R4000 Microprocessor User's Manual...
Page 306: System Model
• The secondary cache states used are invalid, shared, clean exclusive, and dirty exclusive; the dirty shared secondary cache state is not allowed. MIPS R4000 Microprocessor User's Manual...
Page 307 S-cache Figure 11-12 4-Processor System Illustrating Coherency Transactions Given this system model, the following operations are described: • loads and stores • processor coherent read request and read response • processor invalidate • processor write MIPS R4000 Microprocessor User's Manual...
Page 308: Load
These are described in the following sections. † The shared indication is the result of an intervention request to another processor, and is supplied by an external agent that is a part of the other three processor subsystems. MIPS R4000 Microprocessor User's Manual...
Page 309: Processor Invalidate
Processor Write In this system model, an external agent takes no action in response to a write request on the bus. MIPS R4000 Microprocessor User's Manual...
Page 310: Handling Coherency Conflicts
(since the targeted cache line is not present in the cache), conflict detection for processor coherent read requests is not necessary. MIPS R4000 Microprocessor User's Manual...
Page 311: Coherent Write Conflicts
It is not possible for an invalidate request, or a write request that conflicts with a waiting processor write request, to appear on the system bus; before a processor write request can be issued, the state of the processor cache line must be set to dirty exclusive. MIPS R4000 Microprocessor User's Manual...
Page 312: Invalidate Conflicts
It is not possible for a write request that conflicts with a waiting processor invalidate request to appear on the system bus. To issue an invalidate request, the state of the cache line must be shared with every cache in the system that contains the line. MIPS R4000 Microprocessor User's Manual...
Page 313: Sample Cycle: Coherent Read Request
Agent A (E Agent B (E Processor Processor A (P B (P Secondary Secondary Cache A (S Cache B (S Figure 11-13 Cache Load Miss Cycle: Coherent Read Request † Request Cycles are described in Chapter 12. MIPS R4000 Microprocessor User's Manual...
Page 314 In Figure 11-14 the retrieved data is in the dirty exclusive state (DE), servicing a load miss, when the state of cache line S goes from dirty † exclusive to dirty shared (DS), indicating P is owner of the line. † Assuming DS mode is enabled. MIPS R4000 Microprocessor User's Manual...
Page 315 Figure 11-15 shows the cache state and cache data returned from P through E to the bus. This cache state and data are returned to E 10. E issues a read response to P 11. P remains owner of the cache line. MIPS R4000 Microprocessor User's Manual...
Page 316: R4000 Processor Synchronization Support
Chapter 11 11.12 R4000 Processor Synchronization Support In a multiprocessor system, it is essential that two or more processors working on a common task execute without corrupting each other’s subtasks. Synchronization, an operation that guarantees an orderly access to shared memory, must be implemented for a properly functioning multiprocessor system.
Page 317 If the processor is successful at setting the semaphore (step 4), it executes the critical section of code (step 5) and gains access to the shared data, completes its task, unlocks the semaphore (step 6), and continues processing. MIPS R4000 Microprocessor User's Manual...
Page 318: Counter
Figure 11-17 shows this process. Load counter Execute critical section Counter > 0? Load counter Try decrementing counter Try incrementing counter Successful? Successful? Continue processing Figure 11-17 Synchronization Using a Counter MIPS R4000 Microprocessor User's Manual...
Page 319: Ll And Sc
† The most obvious case where the link is broken occurs when an invalidate to the cache line is the subject of the load. In this case, some other processor has successfully completed a store to that line. MIPS R4000 Microprocessor User's Manual...
Page 320: Examples Using Ll And Sc
Loop: LL r2,(r1) Load semaphore ORI r3,r2,1 BEQ r3,r2,Loop Unlocked? (=0?) Try locking SC r3,(r1) semaphore Successful? BEQ r3,0,Loop (r3=0?) Execute critical section (Access shared data) SW r2,(r1) Unlock semaphore Figure 11-18 Test-and-Set using LL and SC MIPS R4000 Microprocessor User's Manual...
Page 321 Try decrementing counter SC r3,(r1) Successful? BEQ r3,0,Loop1 (r3=0?) Execute critical section Loop2: LL r2,(r1) Load counter Try incrementing ADDr3,r2,1 counter SC r3,(r1) Successful? BEQ r3,0,Loop2 Continue processing Figure 11-19 Counter Using LL and SC MIPS R4000 Microprocessor User's Manual...
Page 322 Chapter 11 MIPS R4000 Microprocessor User's Manual...
Page 323: System Interface
This chapter describes the System interface from the point of view of both the processor and the external agent. MIPS R4000 Microprocessor User's Manual...
Page 324: Terminology
12.2 System Interface Description The R4000 processor supports a 64-bit address/data interface that can construct systems ranging from a simple uniprocessor with main memory to a multiprocessor system with caches and complete cache coherency.
Page 325: Interface Buses
System interface command that speciﬁes the precise nature of the request • a series of data elements if the request is for a write, read response, or update. R4000 External Agent SysAD(63:0) SysCmd(8:0) Figure 12-1 System Interface Buses MIPS R4000 Microprocessor User's Manual...
Page 326: Address And Data Cycles
As shown in Figure 12-2, RdRdy* must be asserted two cycles prior to the address cycle of the processor read/invalidate/update request to define the address cycle as the issue cycle. SCycle SClock Addr SysAD Bus RdRdy* Figure 12-2 State of RdRdy* Signal for Read, Invalidate, or Update Requests MIPS R4000 Microprocessor User's Manual...
Page 327 In the latter case, the processor issues the processor request (provided the processor request is still necessary) after the external request is complete. The rules governing an issue cycle again apply to the processor request. MIPS R4000 Microprocessor User's Manual...
Page 328: Handshake Signals
Release* is asserted by the processor when it transfers the mastership of the System interface to the external agent. • The R4000 processor uses ValidOut* and the external agent uses ValidIn* to indicate valid command/data on the SysCmd/SysAD buses. •...
Page 329: System Interface Protocols
Figure 12-4 System Interface Register-to-Register Operation Master and Slave States When the R4000 processor is driving the SysAD and SysCmd buses, the System interface is in master state. When the external agent is driving the SysAD and SysCmd buses, the System interface is in slave state.
Page 330: Moving From Master To Slave State
System interface from master to slave state by asserting Release* for one cycle. The System interface returns to master state as soon as the issue of the external request is complete. This process is described in External Arbitration Protocol, later in this chapter. MIPS R4000 Microprocessor User's Manual...
Page 331: Uncompelled Change To Slave State
System interface to slave state, even though the external agent is not arbitrating to issue an external request. This transition to slave state allows the external agent to return read response data. MIPS R4000 Microprocessor User's Manual...
Page 332: Processor And External Requests
• Update • Null • Invalidate • Update • Snoop • Intervention System Events • Load Miss • Store Miss • Store Hit • Uncached Load/Store • CACHE operations Figure 12-5 Requests and System Events MIPS R4000 Microprocessor User's Manual...
Page 333: Rules For Processor Requests
Figure 12-6. SCycle SClock Cycles Addr SysAD Bus Data Unused Unused Addr Data Write #2 Write #1 WrRdy* Figure 12-6 Back-to-Back Write Cycle Timing MIPS R4000 Microprocessor User's Manual...
Page 334: Processor Requests
Update request provides a block, doubleword, partial doubleword, word, or partial word of data that must be transferred to every other cache in the system. Table 12-1 lists the processor requests that each type of R4000 can issue. Table 12-1 Supported Processor Requests Request...
Page 335 WrRdy*. The processor request cycle sequence is shown in Figure 12-8. External Agent R4000 1. Processor issues read, write, invalidate, or update request 2. External system controls acceptance of requests by asserting RdRdy* or WrRdy* Figure 12-8 Processor Request MIPS R4000 Microprocessor User's Manual...
Page 336: Processor Read Request
In no-secondary-cache mode, the external agent must be capable of accepting a processor read request any time the following two conditions are met: • There is no processor read request pending. • The signal RdRdy* has been asserted for two or more cycles. MIPS R4000 Microprocessor User's Manual...
Page 337: Processor Write Request
In no-secondary-cache mode, the external agent must be capable of accepting a processor write request any time the following two conditions are met: • No processor read request is pending. • The signal WrRdy* has been asserted for two or more cycles. MIPS R4000 Microprocessor User's Manual...
Page 338: Processor Invalidate Request
Figure 12-9 shows this cancellation cycle. MIPS R4000 Microprocessor User's Manual...
Page 339 The processor re-examines the state of the cache line and discovers the cache line which was target of the store is now invalid. The processor issues a processor read request to service the store miss. MIPS R4000 Microprocessor User's Manual...
Page 340: Processor Update Request
IvdErr* signals a processor update request has failed. Since a completion acknowledge for processor update requests is signaled through the System interface on dedicated pins, this acknowledgment can occur in parallel with processor and external requests. MIPS R4000 Microprocessor User's Manual...
Page 341: Clusters
Once the processor issues a read request, a potential update request follows, regardless of the state of RdRdy*. Potential update requests do not obey the RdRdy* flow control rules for issuance, but rather issue with a single address cycle regardless of the state of RdRdy*. MIPS R4000 Microprocessor User's Manual...
Page 342 WrRdy*. Any external request that changes the state of a cache line from dirty exclusive or dirty shared to clean exclusive, shared, or invalid obviates the need for a write back of that cache line. MIPS R4000 Microprocessor User's Manual...
Page 343: External Requests
The state of the line can also be modified by this request. MIPS R4000 Microprocessor User's Manual...
Page 344 System interface to the master state without affecting the processor. Table 12-2 lists the external requests that each type of R4000 can receive (an X indicates the request is supported on that model). Table 12-2 Supported External Requests...
Page 345 If waiting for the response to a read request after the processor has made an uncompelled change to a slave state, the external agent can issue an external request before providing the read response data. MIPS R4000 Microprocessor User's Manual...
Page 346: External Read Request
External Update Request When an external agent issues an update request, the specified resource is accessed and the line is replaced. An external update request is considered complete after the request has been transmitted. MIPS R4000 Microprocessor User's Manual...
Page 347: External Snoop Request
System interface arbitration. For this reason, read responses are handled separately from all other external requests, and are simply called read responses. R4000 External Agent 1. Read request 2. Read response Figure 12-13 Read Response MIPS R4000 Microprocessor User's Manual...
Page 348: Handling Requests
If the coherency attribute is sharable or update, the processor issues a coherent read request. • If the coherency attribute is noncoherent, the processor issues a noncoherent read request. Table 12-3 shows the actions taken on a load miss to primary and secondary caches. MIPS R4000 Microprocessor User's Manual...
Page 349 R-W ....Cluster: Processor coherent block read request with write forthcoming followed by processor block write request ..... Processor coherent block read request with exclusivity -W....Cluster: Processor coherent block read request with exclusivity and write forthcoming followed by processor block write request MIPS R4000 Microprocessor User's Manual...
Page 350: Secondary-Cache Mode
If the current cache line must be written back, the processor issues a write request to save the dirty cache line in memory. † Only noncoherent and uncached attributes are supported in no-secondary-cache mode. MIPS R4000 Microprocessor User's Manual...
Page 351: Store Miss
• If the coherency attribute is noncoherent, a noncoherent block read request is issued. Table 12-4 shows the actions taken on a store miss to primary and secondary caches. MIPS R4000 Microprocessor User's Manual...
Page 352 R-W/U ....Cluster: Processor coherent block read request with write forthcoming followed by processor block write request, followed by processor update request (if read response data is shared or dirty shared) ....Potential update disable [Modebit(20): PotUpdDis = 1] ....Potential update enable [Modebit(20): PotUpdDis = 0] MIPS R4000 Microprocessor User's Manual...
Page 353: Secondary-Cache Mode
MIPS R4000 Microprocessor User's Manual...
Page 354 The external agent must forward the update to the system, then signal the acknowledge to the processor when the update is complete. The processor will not complete the store until it has received an acknowledge for the update request. MIPS R4000 Microprocessor User's Manual...
Page 355: No-Secondary-Cache Mode
In no-secondary-cache mode, if the new cache line replaces a current cache line whose Write back (W) bit is set, the current cache line moves to an internal write buffer before the new cache line is loaded in the primary cache. MIPS R4000 Microprocessor User's Manual...
Page 356: Store Hit
R4400 processor, it is possible for the external agent to receive cached and uncached stores out of program order, as the example below illustrates. Figure 12-14 shows a cached and uncached store instruction sequence: MIPS R4000 Microprocessor User's Manual...
Page 357: Cache Operations
Load Linked Store Conditional instruction sequence maps to the same cache line to which the instruction area containing the Load Linked Store Conditional code sequence is mapped. In this case, immediately after executing the Load Linked instruction, the cache line that contains the link MIPS R4000 Microprocessor User's Manual...
Page 358 For more information, refer to Chapter 11, or see the specific Load Linked and Store Conditional instructions described in Appendix A. MIPS R4000 Microprocessor User's Manual...
Page 359: Processor And External Request Protocols
A noncoherent data identifier for the last data NEOD element A coherent data identifier for a data element other CData than the last data element CEOD A coherent data identifier for the last data element MIPS R4000 Microprocessor User's Manual...
Page 360: Processor Request Protocols
The processor makes an uncompelled change to slave state either at the issue cycle of the read request, or sometime after the issue cycle of the read request by asserting the Release* signal for one cycle. MIPS R4000 Microprocessor User's Manual...
Page 361 NOTE: Timings for the SysADC and SysCmdP buses are the same as those of the SysAD and SysCmd buses, respectively. Master Slave SCycle SClock Addr SysAD Bus Read SysCmd Bus ValidOut* ValidIn* RdRdy* WrRdy* Release* Figure 12-17 Processor Read Request Protocol MIPS R4000 Microprocessor User's Manual...
Page 362 ExtRqst*, whereupon the processor accepts either a read response, or any other external request. If any external request other than a read response is issued, the processor performs another uncompelled change to slave state, asserting Release*, after processing the external request. MIPS R4000 Microprocessor User's Manual...
Page 363: Processor Write Request Protocol
ValidIn* RdRdy* WrRdy* Release* Figure 12-19 Processor Noncoherent Single Word Write Request Protocol † Called word to distinguish it from block request protocol. Data transferred can actually be doubleword, partial doubleword, word, or partial word. MIPS R4000 Microprocessor User's Manual...
Page 364 Figures 12-20 and 12-21 illustrate a processor coherent block request for eight words of data. Master SCycle SClock Addr Data0 Data1 Data2 Data3 SysAD Bus Write CData CData CData CEOD SysCmd Bus ValidOut* ValidIn* RdRdy* WrRdy* Release* Figure 12-20 Processor Coherent Block Write Request Protocol MIPS R4000 Microprocessor User's Manual...
Page 365: Processor Invalidate And Update Request Protocol
IvdAck* occurs in parallel with requests on the SysAD and SysCmd buses. IvdAck* or IvdErr* can be driven at any time after a processor update or invalidate request is issued, provided the update request is compulsory. MIPS R4000 Microprocessor User's Manual...
Page 366: Processor Null Write Request Protocol
RdRdy* or WrRdy* signals. Figure 12-22 illustrates a processor null write request. Master SCycle SClock Unsd SysAD Bus Null SysCmd Bus ValidOut* ValidIn* RdRdy* WrRdy* Release* Figure 12-22 Processor Null Write Request Protocol MIPS R4000 Microprocessor User's Manual...
Page 367: Processor Cluster Request Protocol
Master Slave SCycle SClock Addr Addr Data0 Addr Data0 Data1 Data2 Data3 SysAD Bus RwWF Upd CEOD Write CData CData CData CEOD SysCmd Bus ValidOut* ValidIn* RdRdy* WrRdy* Release* Figure 12-23 Processor Cluster Request Protocol MIPS R4000 Microprocessor User's Manual...
Page 368: Processor Request And Cluster Flow Control
Figure 12-27 illustrates the issue of a processor write request delayed for the assertion of WrRdy* and the completion of an external invalidate request. NOTE: Timings for the SysADC and SysCmdP buses are the same as those of the SysAD and SysCmd buses, respectively. MIPS R4000 Microprocessor User's Manual...
Page 369 Addr Data0 Addr Data0 Data1 Data2 Data3 SysAD Bus Read CEOD Write CData CData CData CEOD SysCmd Bus ValidOut* ValidIn* RdRdy* WrRdy* Release* Figure 12-25 Processor Read Request within a Cluster Delayed for the Assertion of RdRdy* MIPS R4000 Microprocessor User's Manual...
Page 370 Addr Data0 SysAD Bus Write CEOD Write NEOD SysCmd Bus ValidOut* ValidIn* RdRdy* WrRdy* ExtRqst* Release* Figure 12-27 Processor Write Request Delayed for the Assertion of WrRdy* and the Completion of an External Invalidate Request MIPS R4000 Microprocessor User's Manual...
Page 371: External Request Protocols
As long as ExtRqst* is asserted, the string of external requests is not interrupted by a processor request. This section describes the following external request protocols: • read • null • write • invalidate and update • intervention • snoop • read response MIPS R4000 Microprocessor User's Manual...
Page 372: External Arbitration Protocol
NOTE: Timings for the SysADC and SysCmdP buses are the same as those of the SysAD and SysCmd buses, respectively. Master Master Slave SCycle SClock Addr Data0 SysAD Bus Cmd NEOD SysCmd Bus ValidIn* ExtRqst* Release* Figure 12-28 Arbitration Protocol for External Requests MIPS R4000 Microprocessor User's Manual...
Page 373: External Read Request Protocol
SysAD and SysCmd buses, respectively. External read requests are only allowed to read a word of data from the processor. The processor response to external read requests for any data element other than a word is undefined. MIPS R4000 Microprocessor User's Manual...
Page 374: External Null Request Protocol
• A System interface release external null request returns the System interface to master state from slave state without otherwise affecting the processor. MIPS R4000 Microprocessor User's Manual...
Page 375 For a secondary cache release external null request, the System interface remains in slave state. For a System interface release external null request, the external agent releases the SysCmd and SysAD buses, and expects the System interface to return to master state. MIPS R4000 Microprocessor User's Manual...
Page 376 SysCmd Bus ValidOut* ValidIn* ExtRqst* Release* Figure 12-30 Secondary Cache Release External Null Request Master Slave SCycle SClock Unsd SysAD Bus SINull SysCmd Bus ValidOut* ValidIn* ExtRqst* Release* Figure 12-31 System Interface Release External Null Request MIPS R4000 Microprocessor User's Manual...
Page 377: External Write Request Protocol
Master Master Slave SCycle SClock Addr Data0 SysAD Bus Write NEOD SysCmd Bus ValidOut* ValidIn* ExtRqst* Release* Figure 12-32 External Write Request, with System Interface initially a Bus Master MIPS R4000 Microprocessor User's Manual...
Page 378: External Invalidate And Update Request Protocols
SysAD and SysCmd buses, respectively. Slave Master Master Slave SCycle SClock Addr Unsd SysAD Bus CEOD SysCmd Bus ValidOut* ValidIn* ExtRqst* Release* Figure 12-33 External Invalidate Request following an Uncompelled Change to Slave State MIPS R4000 Microprocessor User's Manual...
Page 379: External Intervention Request Protocol
† If the cache line that is the target of the intervention request is not present in the cache— that is, the tag comparison for the cache line at the target cache address fails—the cache line that is the target of the intervention request is considered to be in the invalid state. MIPS R4000 Microprocessor User's Manual...
Page 380 SysAD and SysCmd buses, respectively. Master Slave Master SCycle SClock Addr Unsd SysAD Bus Ivtn SysCmd Bus CEOD ValidOut* ValidIn* ExtRqst* Release* Figure 12-34 External Intervention Request, Shared Line, System Interface in Master State MIPS R4000 Microprocessor User's Manual...
Page 381 Note, however, that if the intervention address targets the doubleword at the beginning of the block, subblock ordering is equivalent to sequential ordering. MIPS R4000 Microprocessor User's Manual...
Page 382: External Snoop Request Protocol
Figure 12-37 shows an external snoop request submitted with the System interface in slave state. NOTE: Timings for the SysADC and SysCmdP buses are the same as those of the SysAD and SysCmd buses, respectively. MIPS R4000 Microprocessor User's Manual...
Page 383 Figure 12-36 External Snoop Request, System Interface in Master State Master Slave Slave SCycle SClock Addr Unsd SysAD Bus Snoop SysCmd Bus CEOD ValidOut* ValidIn* ExtRqst* Release* Figure 12-37 External Snoop Request, System Interface in Slave State MIPS R4000 Microprocessor User's Manual...
Page 384: Read Response Protocol
The behavior of the processor is undefined if the read response is returned before a processor write request is accepted. MIPS R4000 Microprocessor User's Manual...
Page 385 Figure 12-38 Processor Word Read Request, followed by a Word Read Response Slave Master SCycle SClock Data0 Data1 Data2 Data3 SysAD Bus CData CData CData CEOD SysCmd Bus ValidOut* ValidIn* ExtRqst* Release* Figure 12-39 Block Read Response, System Interface already in Slave State MIPS R4000 Microprocessor User's Manual...
Page 386: Data Rate Control
2 Doubles/5 SClock Cycles DDxxx 10 PCycles 1 Double/3 SClock Cycles DDxxxx 12 PCycles 1 Double/3 SClock Cycles DxxDxx 12 PCycles 1 Double/4 SClock Cycles DDxxxxxx 16 PCycles 1 Double/4 SClock Cycles DxxxDxxx 16 PCycles MIPS R4000 Microprocessor User's Manual...
Page 387: Secondary Cache Transfers
Doublewords in the transfer pattern are numbered beginning at 0: the odd-numbered doublewords are the second, fourth, sixth, and so on. MIPS R4000 Microprocessor User's Manual...
Page 388: Secondary Cache Write Cycle Time
DDxx. SCycle SClock Addr Data0 Data1 Data2 Data3 SysAD Bus Write CData CData CData CEOD SysCmd Bus ValidOut* ValidIn* ExtRqst* Release* Figure 12-41 Processor Write Request, Transmit Data Rate Reduced MIPS R4000 Microprocessor User's Manual...
Page 389: Independent Transmissions On The Sysad Bus
These are called independent transmissions. To effect an independent transmission, the external agent must coordinate control of the SysAD bus by using arbitration handshake signals and external null requests. MIPS R4000 Microprocessor User's Manual...
Page 390: System Interface Endianness
Software cannot change the endianness of the System interface and the external system; software can set the reverse endian bit to reverse the interpretation of endianness inside the processor, but the endianness of the System interface remains unchanged. MIPS R4000 Microprocessor User's Manual...
Page 391: System Interface Cycle Time
Table 12-8 Unused Cycles Separating Requests within a Cluster From Processor To Processor Minimum Unused Maximum Unused Request Request SClock Cycles SClock Cycles Read Update Read Write Update Write MIPS R4000 Microprocessor User's Manual...
Page 392: Release Latency
(depending upon Primary cache size) (3a) Read = + 4-word Secondary cache write cycle time + Secondary cache line size + 16 PCycles (3b) Read 4-word Secondary cache Write cycle time With Write + 4 PCycles Forthcoming MIPS R4000 Microprocessor User's Manual...
Page 393: External Request Response Latency
Latency Cache Latency Access 1-4 PCycles 5-6 PCycles 7-8 PCycles 9-10 PCycles 11-12 PCycles External read response latency is a function of processor internal activity. Minimum and maximum external read response latency is 4 PCycles. MIPS R4000 Microprocessor User's Manual...
Page 394: System Interface Commands And Data Identifiers
For System interface commands, SysCmd(8) must be set to 0. For System interface data identifiers, SysCmd(8) must be set to 1. MIPS R4000 Microprocessor User's Manual...
Page 395: System Interface Command Syntax
SysCmd(7:5) Command Read Request Read-With-Write-Forthcoming Request Write Request Null Request Invalidate Request Update Request Intervention Request Snoop Request SysCmd(4:0) are specific to each type of request and are defined in each of the following sections. MIPS R4000 Microprocessor User's Manual...
Page 396: Read Requests
Table 12-13 Encoding of SysCmd(2:0) for Coherent and Noncoherent Block Read Request SysCmd(2) Link Address Retained Indication Link address not retained Link address retained SysCmd(1:0) Read Block Size 4 words 8 words 16 words 32 words MIPS R4000 Microprocessor User's Manual...
Page 397: Write Requests
SysCmd(2:0). Write Request Specific (see tables) Figure 12-44 Write Request SysCmd Bus Bit Definition Table 12-15 Write Request Encoding of SysCmd(4:3) SysCmd(4:3) Write Attributes Reserved Reserved Block write Doubleword, partial doubleword, word, or partial word MIPS R4000 Microprocessor User's Manual...
Page 398 Write Data Size 1 byte valid (Byte) 2 bytes valid (Halfword) 3 bytes valid (Tribyte) 4 bytes valid (Word) 5 bytes valid (Quintibyte) 6 bytes valid (Sextibyte) 7 bytes valid (Septibyte) 8 bytes valid (Doubleword) MIPS R4000 Microprocessor User's Manual...
Page 399: Null Requests
Table 12-18 Processor Null Write Request Encoding of SysCmd(4:3) SysCmd(4:3) Null Write Attributes Null write Reserved Reserved Reserved Table 12-19 External Null Request Encoding of SysCmd(4:3) SysCmd(4:3) Null Attributes System Interface release Secondary cache release Reserved Reserved MIPS R4000 Microprocessor User's Manual...
Page 400: Invalidate Requests
Table 12-21 lists the encodings of SysCmd(4:0) for external update requests. Table 12-22 lists the encodings of SysCmd(4:0) for processor update requests. The remaining upper bits are the same for both processor and external update requests. MIPS R4000 Microprocessor User's Manual...
Page 401 Update Data Size 1 byte valid (Byte) 2 bytes valid (Halfword) 3 bytes valid (Tribyte). 4 bytes valid (Word) 5 bytes valid (Quintibyte) 6 bytes valid (Sextibyte) 7 bytes valid (Septibyte) 8 bytes valid (Doubleword) MIPS R4000 Microprocessor User's Manual...
Page 402: Intervention And Snoop Requests
If cache state is clean exclusive, dirty exclusive, or dirty shared, change to shared; otherwise make no change to cache state Change to invalid regardless of current cache state Reserved Reserved MIPS R4000 Microprocessor User's Manual...
Page 403 If cache state is clean exclusive, dirty exclusive, or dirty shared, change to shared; otherwise make no change to cache state Change to invalid regardless of current cache state Reserved Reserved MIPS R4000 Microprocessor User's Manual...
Page 404: System Interface Data Identifier Syntax
• data that is associated with external write requests • data that is returned in response to an external read request • data that is associated with processor update requests. MIPS R4000 Microprocessor User's Manual...
Page 405: Data Identifier Bit Definitions
SysCmd(2:0) are reserved for noncoherent data identifiers. Table 12-25 lists the encodings of SysCmd(7:3) for processor data identifiers. Table 12-26 lists the encodings of SysCmd(7:3) for external data identifiers. Table 12-27 lists the encodings of SysCmd(2:0) for coherent data identifiers. MIPS R4000 Microprocessor User's Manual...
Page 406 Data is not response data SysCmd(5) Good Data Indication Data is error free Data is erroneous SysCmd(4) Data Checking Enable Check the data and check bits Do not check the data and check bits Reserved SysCmd(3) MIPS R4000 Microprocessor User's Manual...
Page 407: System Interface Addresses
• Word requests set the low-order 2 bits of address to 0. • Halfword requests set the low-order bit of address to 0. • Byte, tribyte, quintibyte, sextibyte, and septibyte requests use the byte address. MIPS R4000 Microprocessor User's Manual...
Page 408: Sequential And Subblock Ordering
Erroneous Data bit, SysCmd(5), set. The Interrupt register is the only processor internal resource available for write access by an external request. The Interrupt register is accessed by an external write request with an address of 000 on bits 6:4 of the SysAD bus. MIPS R4000 Microprocessor User's Manual...
Page 409: Secondary Cache Interface
Secondary Cache Interface The R4000SC and R4000MC versions of the R4000 processor contain interface signals for an optional external secondary cache. This interface consists of: • a 128-bit data bus • a 25-bit tag bus • an 18-bit address bus •...
Page 410: Data Transfer Rates
† Other cache designs within this constraint are also acceptable. For example, a smaller cache design can use 22 8-Kbyte-by-8-bit static RAMs; this design presents less load on the address pins and control signals, and reduces the overall parts count. MIPS R4000 Microprocessor User's Manual...
Page 411: Accessing A Split Secondary Cache
These signals are useful for saving power on snoop and invalidate requests since access to the data array is not necessary. These signals also write data from the primary data cache to the secondary cache. MIPS R4000 Microprocessor User's Manual...
Page 412: Operation Of The Secondary Cache Interface
Table 13-1 Secondary Cache Timing Parameters Symbol Number of Cycles 4-15 PCycles Rd1Cyc 2-15 PCycles Rd2Cyc 2-7 PCycles 1-3 PCycles Wr1Dly 1-3 PCycles Wr2Dly 0-1 PCycles WrRC 3-15 PCycles WrSUp MIPS R4000 Microprocessor User's Manual...
Page 413: Read Cycles
Figure 13-2 illustrates the 4-word read cycle, including the two user- accessible timing parameters. PCycle SCAddr(17:0) Address Rd1Cyc SCData(127:0) SCTag(24:0) Data SCDChk(15:0) SCTChk(6:0) SCOE* SCAPar(2:0) SCDCS*: SCTCS*: Figure 13-2 Timing Diagram of a 4-Word Read Cycle MIPS R4000 Microprocessor User's Manual...
Page 414: 8-Word Read Cycle
If a read cycle is aborted by a write cycle, SCOE* must be deasserted for the period before the write cycle can begin. Read cycles can also be extended indefinitely. There is no requirement to change the address at the end of a read cycle. MIPS R4000 Microprocessor User's Manual...
Page 415: Write Cycles
Figure 13-4 illustrates the 4-word write cycle. Either the upper or lower data doubleword can be driven ﬁrst. MIPS R4000 Microprocessor User's Manual...
Page 416: 8-Word Write Cycle
SCAddr(0) changes and ends when SCWR* is asserted for the second time. The lower half of SCData is driven on the same edge as the change in SCAddr(0). Figure 13-5 illustrates the 8-word write cycle. MIPS R4000 Microprocessor User's Manual...
Page 417: Notes On A Secondary Cache Write Cycle
When receiving data from the System interface, the first data doubleword can arrive several cycles before the second data doubleword. In this case, the cache state machine enters a wait-state that extends SCWR* until period after the second data item is transmitted. WrSUp MIPS R4000 Microprocessor User's Manual...
Page 418 Chapter 13 MIPS R4000 Microprocessor User's Manual...
Page 419: Jtag Interface
JTAG Interface The R4000 processor provides a boundary-scan interface that is compatible with Joint Test Action Group (JTAG) speciﬁcations, using the industry-standard JTAG protocol. This chapter describes that interface, including descriptions of boundary scanning, the pins and signals used by the interface, and the Test Access Port (TAP).
Page 420: What Boundary Scanning Is
To accomplish this, the tests use the four signals described in the next section: JTDI, JTDO, JTMS, and JTCK. Integrated Circuit IC package pin Boundary-scan cells Figure 14-1 JTAG Boundary-scan Cells MIPS R4000 Microprocessor User's Manual...
Page 421: Signal Summary
In addition, the JTAG mechanism provides rudimentary capability for low-speed logical testing of the secondary cache RAM. The JTAG mechanism does not provide any capability for testing the processor itself. MIPS R4000 Microprocessor User's Manual...
Page 422: Jtag Controller And Registers
Boundary-scan register (external test only) Bypass register Bypass register Bypass register The Instruction register has two stages: • shift register • parallel output latch Figure 14-3 shows the format of the Instruction register. Figure 14-3 Instruction Register MIPS R4000 Microprocessor User's Manual...
Page 423: Bypass Register
ICs that remain active in the board-level test datapath. JTDI Bypass Board register input JTDO JTDI JTDO Board JTDI JTDO output JTDO JTDI JTDI JTDO Boundary-scan IC package register pad cell Board Figure 14-4 Bypass Register Operation MIPS R4000 Microprocessor User's Manual...
Page 424: Boundary-Scan Register
Boundary-Scan Register The Boundary-scan register is a single, 319-bit-wide, shift register-based path containing cells connected to all input and output pads on the R4000 processor. Figure 14-5 shows the three most-significant bits of the Boundary-scan register; these three bits control the output enables on the various bidirectional buses.
Page 425: Test Access Port (Tap)
Figure 14-6 JTAG Test Access Port Data on the JTDI and JTMS pins is sampled on the rising edge of the JTCK input clock signal. Data on the JTDO pin changes on the falling edge of the JTCK clock signal. MIPS R4000 Microprocessor User's Manual...
Page 426: Tap Controller
When the TAP controller is in the Shift-IR state, data is loaded serially into the shift register stage of the Instruction register from the JTDI input pin, and the MSB of the Instruction register’s shift register stage is shifted onto the JTDO pin. MIPS R4000 Microprocessor User's Manual...
Page 427 I/O pins whose outputs are enabled (by the three MSBs of the Boundary-scan register), are loaded onto the processor pins. Table 14-2 shows the boundary scan order of the processor signals. Table 14-2 JTAG Scan Order of R4000 Processor Pins Pin # Signal Name Pin #...
Page 428 Chapter 14 Table 14-2 (cont.) JTAG Scan Order of R4000 Processor Pins Pin # Signal Name Pin # Signal Name Pin # Signal Name Pin # Signal Name 97. SysAD(55) 98. SCData(23) 99. SysAD(23) 100. SCData(119) 101. Release* 102. SCTChk(2) 103.
Page 429 JTAG Interface Table 14-2 (cont.) JTAG Scan Order of R4000 Processor Pins Pin # Signal Name Pin # Signal Name Pin # Signal Name Pin # Signal Name 225. SysAD(37) 226. SCData(37) 227. SCData(70) 228. WrRdy* 229. ModeClock 230. SCData(102) 231.
Page 430: Implementation-Specific Details
Processor Clock-based register before they actually enable the data onto the pads. Therefore, the delay from the rising edge of JTCK in the Update-DR (Boundary-scan) state to data valid at the output pins of the chip is greater than two MasterClock periods. MIPS R4000 Microprocessor User's Manual...
Page 431: R4000 Processor Interrupts
R4000 Processor Interrupts The R4000 processor supports the following interrupts: six hardware interrupts, one internal “timer interrupt,” two software interrupts, and one nonmaskable interrupt. The processor takes an exception on any interrupt. This chapter describes the six hardware and single nonmaskable interrupts.
Page 432: Hardware Interrupts
15.2 Nonmaskable Interrupt (NMI) The nonmaskable interrupt is caused either by an external write request to the R4000 or by a dedicated pin in the R4000. This pin is latched into an internal register by the rising edge of SClock.
Page 433 The select line for the Timer Interrupt multiplexer is enabled by boot- mode bit 19, TimerIntDis, as described in Chapter 9. The Timer Interrupt input to the multiplexer is asserted when the Count register equals the Compare register. MIPS R4000 Microprocessor User's Manual...
Page 434 14:10 of the Cause register. Interrupt register (5:0) Figure 15-5. Cause Timer register Interrupt OR gate (Internal SClock register) multiplexer Int*(3) Int*(1) Int*(5) Int*(4) Int*(2) Int*(0) Figure 15-3 R4000PC Interrupt Signals MIPS R4000 Microprocessor User's Manual...
Page 435 Bit 6 of the Interrupt register is then ORed with the inverted value of NMI* to form the nonmaskable interrupt. Interrupt register (6) (Internal register) (Internal) NMI* Edge- SClock triggered Inverter OR gate Flip-ﬂop Figure 15-4 R4000 Nonmaskable Interrupt Signal MIPS R4000 Microprocessor User's Manual...
Page 436 Chapter 15 Figure 15-5 shows the masking of the R4000 interrupt signal. • Cause register bits 15:8 (IP7-IP0) are AND-ORed with Status register interrupt mask bits 15:8 (IM7-IM0) to mask individual interrupts. • Status register bit 0 is a global Interrupt Enable (IE). It is ANDed with the output of the AND-OR logic to produce the R4000 interrupt signal.
Page 437 Error Checking and Correcting This chapter describes the Error Checking and Correcting (ECC) mechanism used in both the R4000 and R4400 processors. This chapter also contains a description of the Master/Checker mode used in the R4400 processor. MIPS R4000 Microprocessor User's Manual...
Page 438: Error Checking In The Processor
Even Parity adds 1 to any odd number of 1s in the data, making the total number of 1s even (including the parity bit). Odd and even parity are shown in the example below: Data(3:0) Odd Parity Bit Even Parity Bit 0 0 1 0 MIPS R4000 Microprocessor User's Manual...
Page 439: Secded Ecc Code
† The 64-bit data code is a modiﬁcation of one of the 64-bit codes proposed by M. Y. Hsiao, to include the ability to detect 3- and 4-bit errors within a nibble. The 25-bit tag code was created using the patterns observed in the 64-bit data code. MIPS R4000 Microprocessor User's Manual...
Page 440 ‡ This makes it possible to decode the syndrome to ﬁnd which data bit is in error, using 4- input NAND gates, provided a pre-decode AND of bits 0-3 and bits 4-7 of the syndrome is available. For the check bits, a full 8-bit decode of the syndrome is required. MIPS R4000 Microprocessor User's Manual...
Page 441 ﬁve 1s or seven 1s. • 4-bit errors within a nibble are indicated by syndromes that contain either four 1s or six 1s. Because these are even numbers of 1s, 4-bit errors within a nibble look like double-bit errors. MIPS R4000 Microprocessor User's Manual...
Page 442: Error Checking Operation
SECDED code that also detects any 3- or 4-bit error in a nibble. The 8 check bits for each half of the secondary cache data bus are always generated in accordance with the SECDED code. MIPS R4000 Microprocessor User's Manual...
Page 443: Secondary Cache Tag Bus
System Interface Command Bus In the R4000 processor, the System interface command bus has a single parity bit, SysCmdP, that provides even parity over the 9 bits of this bus. The SysCmdP parity bit is generated when the System interface is in master state, but it is not checked when the System interface is in slave state.
Page 444: Secded Ecc Matrices For Data And Tag Buses
25 bits. ECC Check Bits The R4000 processor provides the following check bits: 16 check bits, SCDChk(15:0), are used for the secondary cache data bus; 7 check bits, SCTChk(6:0), are used for the secondary cache tag bus; 8 check bits, SysADC(7:0), are used for the System interface address and data bus;...
Page 445: Data Ecc Generation
3333 5511 3333 5511 3333 3333 3333 3333 3333 3333 3333 3333 3333 3333 5511 3333 5511 3333 syndrome* Figure 16-1 Check Matrix for Data ECC Code NOTE: * This row indicates the number of 1s in the generated syndrome for each data bit in error. MIPS R4000 Microprocessor User's Manual...
Page 446 They are 0001 0011 Take even parity of check bits 0001 0011 Parity (even) MSB (7) LSB (0) This even parity value, 0001 0011 , is sent out over the bus as ECC check bits, ECC(7:0). MIPS R4000 Microprocessor User's Manual...
Page 447 Using Figure 16-1, generate even parity for the ECC check codes in columns 0, 1, and 6: Column 0 ECC Column 1 ECC Column 6 ECC Parity (even) This parity value, 0011 1100 , is sent out over the ECC(7:0) check bus. MIPS R4000 Microprocessor User's Manual...
Page 448: Detecting Data Transmission Errors
System A. If the syndrome is any other value than 0000 0000 , it is assumed either the received word or the received check bits are in error. MIPS R4000 Microprocessor User's Manual...
Page 449 • multiple data bit errors (2 consecutive bits in a nibble) • multiple data bit errors (3 consecutive bits in a nibble) • multiple data bit errors (4 consecutive bits in a nibble) MIPS R4000 Microprocessor User's Manual...
Page 450: Single Data Bit Ecc Error
, corresponds to data bit 0. This means the state of received data bit 0 is incorrect. To correct the error, the system inverts the state of the received data bit 0 from a value of 1 to 0. MIPS R4000 Microprocessor User's Manual...
Page 451: Single Check Bit Ecc Error
0. This indicates that the state of the received check bit 0 is incorrect. To correct the error, the system inverts the state of the received check bit 0 from a value of 1 to 0. MIPS R4000 Microprocessor User's Manual...
Page 452: Double Data Bit Ecc Errors
, and the System B regenerated check bits, 0011 0000 The resulting syndrome is 0011 0000 The syndrome of two 1s (or an even number of 1s) indicates that a double-bit error has been detected. Double-bit errors cannot be corrected. MIPS R4000 Microprocessor User's Manual...
Page 453: Three Data Bit Ecc Errors
The resulting syndrome has five 1s. Since no four of the 1s are contained in check bits (7:4) or check bits (3:0), three errors have occurred within a nibble. Triple-bit errors within a nibble cannot be corrected. MIPS R4000 Microprocessor User's Manual...
Page 454: Four Data Bit Ecc Errors
The resulting syndrome is 1111 0000 Since the resulting syndrome has four 1s (or an even number of 1s), this error is recognized as some variation of a double-bit error. A 4-bit error within a nibble cannot be corrected. MIPS R4000 Microprocessor User's Manual...
Page 455: Tag Ecc Generation
3331 3311 3311 3311 3333 3333 3333 3333 syndrome* Figure 16-4 Check Matrix for the Tag ECC Code NOTE: * This row indicates the number of 1s in the generated syndrome for each data bit in error. MIPS R4000 Microprocessor User's Manual...
Page 456: Summary Of Ecc Operations
Trap on Processor † error System Interface Data Checked; Generated Check Bits Trap on † Error † If error level (ERL bit of the Status register) is 1, the error is reported to the Fault* pin. MIPS R4000 Microprocessor User's Manual...
Page 457 ‡ If error level (ERL bit of the Status register) is 1, the error is reported to the Fault* pin. * Only if the current CACHE op needs to modify and write back the tag. MIPS R4000 Microprocessor User's Manual...
Page 458 Not Checked; System Interface Data Generated Trap on Not Checked reported to the Check Bits Error Fault* pin † Read-Modify-Write cycle ‡ Only the pair of doublewords accessed on the read portion of RMW is checked. MIPS R4000 Microprocessor User's Manual...
Page 459 Fault* reported to the and Check Bits: Fault* pin Fault* pin Receive From Secondary System Interface Data Cache System Interface Data From Secondary Check Bits Cache † Read-Modify-Write cycle MIPS R4000 Microprocessor User's Manual...
Page 460: R4400 Master/Checker Mode
Complete Master mode. In a fault tolerant system, there are two possible configurations using the Master-Listener and Cross-Coupled modes described in Table 16-5. These are referred to as lock-step configurations, and are described later in this section. MIPS R4000 Microprocessor User's Manual...
Page 461: Connecting A System In Lock Step
The remaining processor signals can be connected either in parallel or independently. † Fault* is a non-persistent signal which is synchronous with the System interface. Fault* signal timing is determined by the PClock-to-SClock divisor from boot-time mode bit settings. MIPS R4000 Microprocessor User's Manual...
Page 462: Master-Listener Configuration
SCData/ SysCmd Agent SCTag SysADC/ Data Chk/ SCAddr SysCmdP Tag Chk R4400 Fault* Complete Listener SysAD SysCmd SCData/ SCTag SysADC/ SysCmdP Data Chk/ Tag Chk Maintenance Processor Fault* Figure 16-5 Master-Listener Configuration of Master/Checker Mode MIPS R4000 Microprocessor User's Manual...
Page 463: Cross-Coupled Checking Configuration
SC Master SCAddress SysAD/ SysCmd SCData/ SCTag SysADC/ SysCmdP Data Chk/ Tag Chk Maintenance Fault* Processor Figure 16-6 Cross-Coupled Configuration of Master/Checker Mode † This includes such errors as an input parity error at SysCmd. MIPS R4000 Microprocessor User's Manual...
Page 464 It should be noted that the fault detection mechanism associated with the Fault* pin does not cause any exceptions; the processor continues to run normally regardless of the state of the Fault* signal. It is up to external logic to handle an asserted Fault* signal. MIPS R4000 Microprocessor User's Manual...
Page 465: Fault Detection
System interface cycle is reported in the current cycle. In Complete Master mode, output fault reporting is disabled for the Secondary Cache interface, but enabled for the following System interface signals: SysCmd, SysCmdP, SysAD, SysADC, ValidOut*, and Release*. MIPS R4000 Microprocessor User's Manual...
Page 466: Reset Operation
The fault history bits can be reset (cleared) while the R4400 processor is running by asserting 1 to the ModeIn pin. Consequently, ModeIn must be held to 0 to maintain the status of the fault history bits. Table 16-6 presents this information in tabular form. MIPS R4000 Microprocessor User's Manual...
Page 467 Forced Complete Master Output Fault Reset* just asserted History bit is (R4400 is reset) connected to the Fault* pin Input Fault Reset just asserted History bit is (R4400 is reset) connected to Fault* pin MIPS R4000 Microprocessor User's Manual...
Page 468 Chapter 16 MIPS R4000 Microprocessor User's Manual...
Page 469 CPU Instruction Set Details This appendix provides a detailed description of the operation of each R4000 instruction in both 32- and 64-bit modes. The instructions are listed in alphabetical order. Exceptions that may occur due to the execution of each instruction are listed after the description of each instruction.
Page 470 Coprocessor zero (CP0) instructions manipulate the memory management and exception handling facilities of the processor. • Special instructions perform a variety of tasks, including movement of data between special and general registers, trap, and breakpoint. They are always R-type. MIPS R4000 Microprocessor User's Manual...
Page 471 5-bit target (source/destination) or branch condition 16-bit immediate, branch displacement or address immediate displacement target 26-bit jump target address 5-bit destination register specifier shamt 5-bit shift amount funct 6-bit function field Figure A-1 CPU Instruction Formats MIPS R4000 Microprocessor User's Manual...
Page 472 In the instruction descriptions that follow, the Operation section describes the operation performed by each instruction using a high-level language notation. The R4000 can operate as either a 32- or 64-bit microprocessor and the operation for both modes is included with the instruction description.
Page 473 T+ i at time i + j . The interpretation of the order of execution between two instructions or two operations which execute at the same time should be pessimistic; the or- der is not defined. MIPS R4000 Microprocessor User's Manual...
Page 474 Bit 15 (the sign bit) of an immediate value is extended for 16 bit positions, and the result is concatenated with bits 15 through 0 of the immediate value to form a 32-bit sign extended value. MIPS R4000 Microprocessor User's Manual...
Page 475 Two special instructions are provided in the R4000 implementation of the MIPS ISA, Load Linked and Store Conditional. These instructions are...
Page 476 HALFWORD 2 bytes (16 bits) BYTE 1 byte (8 bits) The bytes within the addressed doubleword which are used can be determined directly from the access type and the three low-order bits of the address. MIPS R4000 Microprocessor User's Manual...
Page 477 Since instructions must be word-aligned, a Jump Register or Jump and Link Register instruction must use a register whose two low-order bits are zero. If these low-order bits are not zero, an address exception will occur when the jump target instruction is subsequently fetched. MIPS R4000 Microprocessor User's Manual...
Page 478 CP0 registers. Several CP0 instructions are defined to directly read, write, and probe TLB entries and to modify the operating modes in preparation for returning to User mode or interrupt-enabled states. A-10 MIPS R4000 Microprocessor User's Manual...
Page 479 An overflow exception occurs if the carries out of bits 30 and 31 differ (2’s complement overflow). The destination register rd is not modified when an integer overflow exception occurs. Operation: GPR[rd] GPR[rs] + GPR[rt] temp GPR[rs] + GPR[rt] GPR[rd] (temp || temp 31...0 Exceptions: Integer overflow exception MIPS R4000 Microprocessor User's Manual A-11...
Page 480 The destination register rt is not modified when an integer overflow exception occurs. Operation: GPR [rt] GPR[rs] +(immediate || immediate 15...0 temp GPR[rs] + (immediate || immediate 15...0 GPR[rt] (temp || temp 31...0 Exceptions: Integer overflow exception A-12 MIPS R4000 Microprocessor User's Manual...
Page 481 The only difference between this instruction and the ADDI instruction is that ADDIU never causes an overflow exception. Operation: GPR [rt] GPR[rs] + (immediate || immediate 15...0 temp GPR[rs] + (immediate || immediate 15...0 GPR[rt] (temp || temp 31...0 Exceptions: None MIPS R4000 Microprocessor User's Manual A-13...
Page 482 The only difference between this instruction and the ADD instruction is that ADDU never causes an overflow exception. Operation: GPR[rd] GPR[rs] + GPR[rt] temp GPR[rs] + GPR[rt] GPR[rd] (temp || temp 31...0 Exceptions: None A-14 MIPS R4000 Microprocessor User's Manual...
Page 483 The contents of general register rs are combined with the contents of general register rt in a bit-wise logical AND operation. The result is placed into general register rd. Operation: GPR[rd] GPR[rs] and GPR[rt] GPR[rd] GPR[rs] and GPR[rt] Exceptions: None MIPS R4000 Microprocessor User's Manual A-15...
Page 484 The 16-bit immediate is zero-extended and combined with the contents of general register rs in a bit-wise logical AND operation. The result is placed into general register rt. Operation: GPR[rt] || (immediate and GPR[rs] 15...0 GPR[rt] || (immediate and GPR[rs] 15...0 Exceptions: None A-16 MIPS R4000 Microprocessor User's Manual...
Page 485 (offset || offset || 0 T+1: if condition then PC + target endif *See the table “Opcode Bit Encoding” on next page, or “CPU Instruction Opcode Bit Encoding” at the end of Appendix A. MIPS R4000 Microprocessor User's Manual A-17...
Page 486 Bit # 0 0 0 BC1F 31 30 29 28 27 26 24 23 22 21 20 19 18 17 16 Bit # 0 0 0 BC2F Opcode BC sub-opcode Branch condition Coprocessor Unit Number A-18 MIPS R4000 Microprocessor User's Manual...
Page 487 *See the table “Opcode Bit Encoding” on next page, or “CPU Instruction Opcode Bit Encoding” at the end of Appendix A. MIPS R4000 Microprocessor User's Manual A-19...
Page 488 24 23 22 21 20 19 18 17 16 Bit # BC1FL 31 30 29 28 27 26 24 23 22 21 20 19 18 17 16 Bit # BC2FL Opcode BC sub-opcode Branch condition Coprocessor Unit Number A-20 MIPS R4000 Microprocessor User's Manual...
Page 489 (offset || offset || 0 T+1: if condition then PC + target endif *See the table “Opcode Bit Encoding” on next page, or “CPU Instruction Opcode Bit Encoding” at the end of Appendix A. MIPS R4000 Microprocessor User's Manual A-21...
Page 490 24 23 22 21 20 19 18 17 16 Bit # 0 0 1 BC1T 31 30 29 28 27 26 24 23 22 21 20 19 18 17 16 Bit # BC2T Opcode BC sub-opcode Branch condition Coprocessor Unit Number A-22 MIPS R4000 Microprocessor User's Manual...
Page 491 || offset || 0 T+1: if condition then PC + target else NullifyCurrentInstruction endif *See the table “Opcode Bit Encoding” on next page, or “CPU Instruction Opcode Bit Encoding” at the end of Appendix A. MIPS R4000 Microprocessor User's Manual A-23...
Page 492 Bit # 0 1 1 BC1TL 31 30 29 28 27 26 24 23 22 21 20 19 18 17 16 Bit # 0 1 1 BC2TL Opcode BC sub-opcode Branch condition Coprocessor Unit Number A-24 MIPS R4000 Microprocessor User's Manual...
Page 493 || offset || 0 condition (GPR[rs] = GPR[rt]) T+1: if condition then PC + target endif target (offset || offset || 0 condition (GPR[rs] = GPR[rt]) T+1: if condition then PC + target endif Exceptions: None MIPS R4000 Microprocessor User's Manual A-25...
Page 494 (GPR[rs] = GPR[rt]) T+1: if condition then PC + target else NullifyCurrentInstruction endif target (offset || offset || 0 condition (GPR[rs] = GPR[rt]) T+1: if condition then PC + target else NullifyCurrentInstruction endif Exceptions: None A-26 MIPS R4000 Microprocessor User's Manual...
Page 495 || offset || 0 condition (GPR[rs] = 0) T+1: if condition then PC + target endif target (offset || offset || 0 condition (GPR[rs] = 0) T+1: if condition then PC + target endif Exceptions: None MIPS R4000 Microprocessor User's Manual A-27...
Page 496 PC + 8 T+1: if condition then PC + target endif target (offset || offset || 0 condition (GPR[rs] = 0) GPR[31] PC + 8 T+1: if condition then PC + target endif Exceptions: None A-28 MIPS R4000 Microprocessor User's Manual...
Page 497 T+1: if condition then PC + target else NullifyCurrentInstruction endif target (offset || offset || 0 condition (GPR[rs] = 0) GPR[31] PC + 8 T+1: if condition then PC + target else NullifyCurrentInstruction endif Exceptions: None MIPS R4000 Microprocessor User's Manual A-29...
Page 498 = 0) T+1: if condition then PC + target else NullifyCurrentInstruction endif target (offset || offset || 0 condition (GPR[rs] = 0) T+1: if condition then PC + target else NullifyCurrentInstruction endif Exceptions: None A-30 MIPS R4000 Microprocessor User's Manual...
Page 499 = 0) and (GPR[rs] T+1: if condition then PC + target endif target (offset || offset || 0 condition (GPR[rs] = 0) and (GPR[rs] T+1: if condition then PC + target endif Exceptions: None MIPS R4000 Microprocessor User's Manual A-31...
Page 500 T+1: if condition then PC + target else NullifyCurrentInstruction endif target (offset || offset || 0 condition (GPR[rs] = 0) and (GPR[rs] T+1: if condition then PC + target else NullifyCurrentInstruction endif Exceptions: None A-32 MIPS R4000 Microprocessor User's Manual...
Page 501 = 1) or (GPR[rs] = 0 T+1: if condition then PC + target endif target (offset || offset || 0 condition (GPR[rs] = 1) or (GPR[rs] T+1: if condition then PC + target endif Exceptions: None MIPS R4000 Microprocessor User's Manual A-33...
Page 502 T+1: if condition then PC + target else NullifyCurrentInstruction endif target (offset || offset || 0 condition (GPR[rs] = 1) or (GPR[rs] T+1: if condition then PC + target else NullifyCurrentInstruction endif Exceptions: None A-34 MIPS R4000 Microprocessor User's Manual...
Page 503 || offset || 0 condition (GPR[rs] = 1) T+1: if condition then PC + target endif target (offset || offset || 0 condition (GPR[rs] = 1) T+1: if condition then PC + target endif Exceptions: None MIPS R4000 Microprocessor User's Manual A-35...
Page 504 PC + 8 T+1: if condition then PC + target endif target (offset || offset || 0 condition (GPR[rs] = 1) GPR[31] PC + 8 T+1: if condition then PC + target endif Exceptions: None A-36 MIPS R4000 Microprocessor User's Manual...
Page 505 T+1: if condition then PC + target else NullifyCurrentInstruction endif target (offset || offset || 0 condition (GPR[rs] = 1) GPR[31] PC + 8 T+1: if condition then PC + target else NullifyCurrentInstruction endif Exceptions: None MIPS R4000 Microprocessor User's Manual A-37...
Page 506 = 1) T+1: if condition then PC + target else NullifyCurrentInstruction endif target (offset || offset || 0 condition (GPR[rs] = 1) T+1: if condition then PC + target else NullifyCurrentInstruction endif Exceptions: None A-38 MIPS R4000 Microprocessor User's Manual...
Page 507 || offset || 0 condition (GPR[rs] GPR[rt]) T+1: if condition then PC + target endif target (offset || offset || 0 condition (GPR[rs] GPR[rt]) T+1: if condition then PC + target endif Exceptions: None MIPS R4000 Microprocessor User's Manual A-39...
Page 508 (GPR[rs] GPR[rt]) T+1: if condition then PC + target else NullifyCurrentInstruction endif target (offset || offset || 0 condition (GPR[rs] GPR[rt]) T+1: if condition then PC + target else NullifyCurrentInstruction endif Exceptions: None A-40 MIPS R4000 Microprocessor User's Manual...
Page 509 The code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction. Operation: 32, 64 BreakpointException Exceptions: Breakpoint exception MIPS R4000 Microprocessor User's Manual A-41...
Page 510 (a hit). If the cache block is invalid or contains a different address (a miss), no operation is performed. A-42 MIPS R4000 Microprocessor User's Manual...
Page 511 TLB exceptions. This operation never causes TLB Modified or Virtual Coherency exceptions. Bits 17...16 of the instruction specify the cache as follows: Code Name Cache primary instruction primary data secondary instruction secondary data (or combined instruction/data) MIPS R4000 Microprocessor User's Manual A-43...
Page 512 Write the tag for the cache block at the specified index from the TagLo and TagHi CP0 registers. The processor uses computed parity for the Index Store primary caches and the TagLo register in the case of the secondary cache. A-44 MIPS R4000 Microprocessor User's Manual...
Page 513 CE bit of the Status register is set, the contents of the Invalidate ECC register is XOR’d into the computed check bits during the write to the secondary cache for the addressed doubleword. MIPS R4000 Microprocessor User's Manual A-45...
Page 514 When a secondary cache is present, and the CE bit of Hit Writeback the Status register is set, the contents of the ECC register is XOR’d into the computed check bits during the write to the secondary cache for the addressed doubleword. A-46 MIPS R4000 Microprocessor User's Manual...
Page 515 The CH bit in the Status register is set or cleared to indicate a hit or miss. Operation: 32, 64 vAddr ((offset || offset ) + GPR[base] 15...0 (pAddr, uncached) AddressTranslation (vAddr, DATA) CacheOp (op, vAddr, pAddr) Exceptions: Coprocessor unusable exception MIPS R4000 Microprocessor User's Manual A-47...
Page 516 (CCR[z,rd] || CCR[z,rd] T+1: GPR[rt] data Exceptions: Coprocessor unusable exception *Opcode Bit Encoding: 22 21 31 30 Bit # CFCz CFC1 22 21 31 30 Bit # CFC2 Opcode Coprocessor Suboperation Coprocessor Unit Number A-48 MIPS R4000 Microprocessor User's Manual...
Page 517 Appendix B. Operation: 32, 64 CoprocessorOperation (z, cofun) Exceptions: Coprocessor unusable exception Coprocessor interrupt or Floating-Point Exception (R4000 CP1 only) *Opcode Bit Encoding: COPz 31 30 29 28 27 26 Bit # C0P0 31 30 29 28 27 26...
Page 518 This instruction is not valid for CP0. Operation: 32,64 data GPR[rt] T + 1: CCR[z,rd] data Exceptions: Coprocessor unusable *See “CPU Instruction Opcode Bit Encoding” at the end of Appendix A. A-50 MIPS R4000 Microprocessor User's Manual...
Page 519 An overflow exception occurs if the carries out of bits 62 and 63 differ (2’s complement overflow). The destination register rd is not modified when an integer overflow exception occurs. This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception.
Page 520 An overflow exception occurs if carries out of bits 62 and 63 differ (2’s complement overflow). The destination register rt is not modified when an integer overflow exception occurs. This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception.
Page 521 The only difference between this instruction and the DADDI instruction is that DADDIU never causes an overflow exception. This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception.
Page 522 The only difference between this instruction and the DADD instruction is that DADDU never causes an overflow exception. This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception.
Page 523 Correct operation requires separating reads of HI or LO from writes by two or more instructions. This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception.
Page 524 Correct operation requires separating reads of HI or LO from writes by two or more instructions. This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception.
Page 525 If either of the two preceding instructions is MFHI or MFLO, the results of those instructions are undefined. Correct operation requires separating reads of HI or LO from writes by two or more instructions. MIPS R4000 Microprocessor User's Manual A-57...
Page 526 T–1: undefined undefined GPR[rs] div GPR[rt] GPR[rs] mod GPR[rt] T–2: undefined undefined T–1: undefined undefined GPR[rs] div GPR[rt] 31...0 31...0 GPR[rs] mod GPR[rt] 31...0 31...0 || q 31...0 || r 31...0 Exceptions: None A-58 MIPS R4000 Microprocessor User's Manual...
Page 527 If either of the two preceding instructions is MFHI or MFLO, the results of those instructions are undefined. Correct operation requires separating reads of HI or LO from writes by two or more instructions. MIPS R4000 Microprocessor User's Manual A-59...
Page 528 T–2: undefined undefined T–1: undefined undefined (0 || GPR[rs] ) div (0 || GPR[rt] 31...0 31...0 (0 || GPR[rs] ) mod (0 || GPR[rt] 31...0 31...0 || q 31...0 || r 31...0 Exceptions: None A-60 MIPS R4000 Microprocessor User's Manual...
Page 529 The contents of coprocessor register rd of the CP0 are loaded into general register rt. This operation is deﬁned for the R4000 operating in 64-bit mode and in 32- bit kernel mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception.
Page 530 The contents of general register rt are loaded into coprocessor register rd of the CP0. This operation is deﬁned for the R4000 operating in 64-bit mode or in 32- bit kernel mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception.
Page 531 Correct operation requires separating reads of HI or LO from writes by a minimum of two other instructions. This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception.
Page 532 Correct operation requires separating reads of HI or LO from writes by a minimum of two instructions. This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception.
Page 533 The contents of general register rt are shifted left by sa bits, inserting zeros into the low-order bits. The result is placed in register rd. Operation: 0 || sa GPR[rd] GPR[rt] || 0 (63–s)...0 Exceptions: Reserved instruction exception (R4000 in 32-bit mode) MIPS R4000 Microprocessor User's Manual A-65...
Page 534 The result is placed in register rd. This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception.
Page 535 The contents of general register rt are shifted left by 32+sa bits, inserting zeros into the low-order bits. The result is placed in register rd. This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception.
Page 536 The contents of general register rt are shifted right by sa bits, sign- extending the high-order bits. The result is placed in register rd. This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception.
Page 537 The result is placed in register rd. This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception.
Page 538 The contents of general register rt are shifted right by 32+sa bits, sign- extending the high-order bits. The result is placed in register rd. This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception.
Page 539 The contents of general register rt are shifted right by sa bits, inserting zeros into the high-order bits. The result is placed in register rd. This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception.
Page 540 The result is placed in register rd. This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception.
Page 541 The contents of general register rt are shifted right by 32+sa bits, inserting zeros into the high-order bits. The result is placed in register rd. This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception.
Page 542 63 differ (2’s complement overflow). The destination register rd is not modified when an integer overflow exception occurs. This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception.
Page 543 The only difference between this instruction and the DSUB instruction is that DSUBU never traps on overflow. No integer overflow exception occurs under any circumstances. This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception.
Page 544 Format: ERET Description: ERET is the R4000 instruction for returning from an interrupt, exception, or error trap. Unlike a branch or jump instruction, ERET does not execute the next instruction. ERET must not itself be placed in a branch delay slot.
Page 545 The program unconditionally jumps to this calculated address with a delay of one instruction. Operation: temp target T+1: PC || temp || 0 31...28 temp target T+1: PC || temp || 0 63...28 Exceptions: None MIPS R4000 Microprocessor User's Manual A-77...
Page 546 The address of the instruction after the delay slot is placed in the link register, r31. Operation: temp target GPR[31] PC + 8 T+1: PC || temp || 0 31...28 temp target GPR[31] PC + 8 T+1: PC || temp || 0 63...28 Exceptions: None A-78 MIPS R4000 Microprocessor User's Manual...
Page 547 If these low-order bits are not zero, an address exception will occur when the jump target instruction is subsequently fetched. Operation: 32, 64 temp GPR [rs] GPR[rd] PC + 8 T+1: temp Exceptions: None MIPS R4000 Microprocessor User's Manual A-79...
Page 548 (rs) whose two low-order bits are zero. If these low-order bits are not zero, an address exception will occur when the jump target instruction is subsequently fetched. Operation: 32, 64 temp GPR[rs] T+1: temp Exceptions: None A-80 MIPS R4000 Microprocessor User's Manual...
Page 549 PSIZE – 1 ... 3 2...0 LoadMemory (uncached, BYTE, pAddr, vAddr, DATA) byte vAddr xor BigEndianCPU 2...0 GPR[rt] (mem || mem 7+8*byte 7+8*byte...8*byte Exceptions: TLB refill exception TLB invalid exception Bus error exception Address error exception MIPS R4000 Microprocessor User's Manual A-81...
Page 550 PSIZE – 1...3 2...0 LoadMemory (uncached, BYTE, pAddr, vAddr, DATA) byte vAddr xor BigEndianCPU 2...0 GPR[rt] || mem 7+8* byte...8* byte Exceptions: TLB refill exception TLB invalid exception Bus error exception Address error exception A-82 MIPS R4000 Microprocessor User's Manual...
Page 551 If any of the three least-significant bits of the effective address are non- zero, an address error exception occurs. This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception.
Page 552 This instruction is undefined when the least-significant bit of the rt field is non-zero. *See the table “Opcode Bit Encoding” on next page, or “CPU Instruction Opcode Bit Encoding” at the end of Appendix A. A-84 MIPS R4000 Microprocessor User's Manual...
Page 553 Exceptions: TLB refill exception TLB invalid exception Bus error exception Address error exception Coprocessor unusable exception Opcode Bit Encoding: LDCz 31 30 Bit # LDC1 31 30 Bit # LDC2 Coprocessor Unit Number Opcode MIPS R4000 Microprocessor User's Manual A-85...
Page 554 (big-endian) register 10 11 12 13 14 15 address 8 A B C D E F G H before address 0 LDL $24,3($0) 3 4 5 6 7 F G H after A-86 MIPS R4000 Microprocessor User's Manual...
Page 555 LDL (or LDR) instruction which also specifies register rt. No address exceptions due to alignment are possible. This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception.
Page 556 Type AccessType (see Table 2-1) sent to memory Offset pAddr sent to memory 2...0 Exceptions: TLB refill exception TLB invalid exception Bus error exception Address error exception Reserved instruction exception (R4000 in 32-bit mode) A-88 MIPS R4000 Microprocessor User's Manual...
Page 557 (big-endian) register 10 11 12 13 14 15 address 8 B C D E F G H before address 0 LDR $24,4($0) register after B C 0 1 2 3 4 MIPS R4000 Microprocessor User's Manual A-89...
Page 558 LDR (or LDL) instruction which also specifies register rt. No address exceptions due to alignment are possible. This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception.
Page 559 Type AccessType (see Table 2-1) sent to memory Offset pAddr sent to memory 2...0 Exceptions: TLB refill exception TLB invalid exception Bus error exception Address error exception Reserved instruction exception (R4000 in 32-bit mode) MIPS R4000 Microprocessor User's Manual A-91...
Page 560 2...0 LoadMemory (uncached, HALFWORD, pAddr, vAddr, DATA) byte vAddr xor (BigEndianCPU || 0) 2...0 GPR[rt] (mem || mem 15+8*byte 15+8*byte...8* byte Exceptions: TLB refill exception TLB invalid exception Bus error exception Address error exception A-92 MIPS R4000 Microprocessor User's Manual...
Page 561 PSIZE – 1...3 2...0 LoadMemory (uncached, HALFWORD, pAddr, vAddr, DATA) byte vAddr xor (BigEndianCPU || 0) 2...0 GPR[rt] || mem 15+8*byte...8*byte Exceptions: TLB refill exception TLB invalid exception Bus Error exception Address error exception MIPS R4000 Microprocessor User's Manual A-93...
Page 562 LL and SC, otherwise the SC may never be successful. Exceptions also cause SC to fail, so persistent exceptions must be avoided. If either of the two least-significant bits of the effective address are non-zero, an address error exception takes place. A-94 MIPS R4000 Microprocessor User's Manual...
Page 563 2...0 LoadMemory (uncached, WORD, pAddr, vAddr, DATA) byte vAddr xor (BigEndianCPU || 0 2...0 GPR[rt] (mem || mem 31+8*byte 31+8*byte...8*byte LLbit Exceptions: TLB refill exception TLB invalid exception Bus error exception Address error exception MIPS R4000 Microprocessor User's Manual A-95...
Page 564 T1, (T0) T2, T1, 1 T2, (T0) T2, 0, L1 This atomically increments the word addressed by T0. Changing the ADD to an OR changes this to an atomic bit set. A-96 MIPS R4000 Microprocessor User's Manual...
Page 565 If any of the three least-significant bits of the effective address are non- zero, an address error exception takes place. This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception.
Page 566 The 16-bit immediate is shifted left 16 bits and concatenated to 16 bits of zeros. The result is placed into general register rt. In 64-bit mode, the loaded word is sign-extended. Operation: GPR[rt] immediate || 0 GPR[rt] (immediate || immediate || 0 Exceptions: None A-98 MIPS R4000 Microprocessor User's Manual...
Page 567 PSIZE-1...3 2...0 LoadMemory (uncached, WORD, pAddr, vAddr, DATA) byte vAddr xor (BigEndianCPU || 0 2...0 GPR[rt] (mem || mem 31+8*byte 31+8*byte...8*byte Exceptions: TLB refill exception TLB invalid exception Bus error exception Address error exception MIPS R4000 Microprocessor User's Manual A-99...
Page 568 This instruction is not valid for use with CP0. *See the table “Opcode Bit Encoding” on next page, or “CPU Instruction Opcode Bit Encoding” at the end of Appendix A. A-100 MIPS R4000 Microprocessor User's Manual...
Page 569 COPzLW (byte, rt, mem) Exceptions: TLB refill exception TLB invalid exception Bus error exception Address error exception Coprocessor unusable exception Opcode Bit Encoding: LWCz Bit # LWC1 Bit # LWC2 Coprocessor Unit Number Opcode MIPS R4000 Microprocessor User's Manual A-101...
Page 570 The least-significant (right-most) byte(s) of the register will not be changed. memory (big-endian) register address 4 before address 0 LWL $24,1($0) after A-102 MIPS R4000 Microprocessor User's Manual...
Page 571 BigEndianMem = 0 then pAddr pAddr || 0 PSIZE–1...2 endif byte vAddr xor BigEndianCPU 1...0 word vAddr xor BigEndianCPU LoadMemory (uncached, 0 || byte, pAddr, vAddr, DATA) temp || GPR[rt] 32*word+8*byte+7...32*word 23-8*byte...0 GPR[rt] (temp || temp MIPS R4000 Microprocessor User's Manual A-103...
Page 572 Little-endian memory (BigEndianMem = 0) BigEndianMem = 1 Type AccessType (see Table 2-1) sent to memory Offset pAddr sent to memory 2...0 sign-extend of destination Exceptions: TLB refill exception TLB invalid exception Bus error exception Address error exception A-104 MIPS R4000 Microprocessor User's Manual...
Page 573 The most significant (left-most) byte(s) of the register will not be changed. memory (big-endian) register address 4 before address 0 LWR $24,4($0) after MIPS R4000 Microprocessor User's Manual A-105...
Page 574 BigEndianMem = 1 then pAddr pAddr || 0 PSIZE–31...3 endif byte vAddr xor BigEndianCPU 1...0 word vAddr xor BigEndianCPU LoadMemory (uncached, 0 || byte, pAddr, vAddr, DATA) temp GPR[rt] || mem 31...32-8*byte 31+32*word...32*word+8*byte GPR[rt] (temp || temp A-106 MIPS R4000 Microprocessor User's Manual...
Page 575 AccessType (see Table 2-1) sent to memory Offset pAddr sent to memory 2...0 sign-extend of destination either unchanged or sign-extend of destination Exceptions: TLB refill exception TLB invalid exception Bus error exception Address error exception MIPS R4000 Microprocessor User's Manual A-107...
Page 576 If either of the two least-significant bits of the effective address is non-zero, an address error exception occurs. This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception.
Page 577 Description: The contents of coprocessor register rd of the CP0 are loaded into general register rt. Operation: data CPR[0,rd] T+1: GPR[rt] data data CPR[0,rd] T+1: GPR[rt] (data || data 31...0 Exceptions: Coprocessor unusable exception MIPS R4000 Microprocessor User's Manual A-109...
Page 578 || 0] 4...1 63...32 endif T+1: GPR[rt] (data || data Exceptions: Coprocessor unusable exception *See the table “Opcode Bit Encoding” on next page, or “CPU Instruction Opcode Bit Encoding” at the end of Appendix A. A-110 MIPS R4000 Microprocessor User's Manual...
Page 579 MFCz MFCz (continued) Opcode Bit Encoding: MFCz 22 21 31 30 Bit # MFC0 22 21 31 30 Bit # MFC1 22 21 31 30 Bit # MFC2 Coprocessor Suboperation Opcode Coprocessor Unit Number MIPS R4000 Microprocessor User's Manual A-111...
Page 580 To ensure proper operation in the event of interruptions, the two instructions which follow a MFHI instruction may not be any of the instructions which modify the HI register: MULT, MULTU, DIV, DIVU, MTHI, DMULT, DMULTU, DDIV, DDIVU. Operation: 32, 64 GPR[rd] Exceptions: None A-112 MIPS R4000 Microprocessor User's Manual...
Page 581 To ensure proper operation in the event of interruptions, the two instructions which follow a MFLO instruction may not be any of the instructions which modify the LO register: MULT, MULTU, DIV, DIVU, MTLO, DMULT, DMULTU, DDIV, DDIVU. Operation: 32, 64 GPR[rd] Exceptions: None MIPS R4000 Microprocessor User's Manual A-113...
Page 582 TLB operations immediately prior to and after this instruction are undefined. Operation: 32, 64 data GPR[rt] T+1: CPR[0,rd] data Exceptions: Coprocessor unusable exception A-114 MIPS R4000 Microprocessor User's Manual...
Page 583 Coprocessor unusable exception *Opcode Bit Encoding: 22 21 31 30 Bit # MTCz C0P0 22 21 31 30 Bit # C0P1 22 21 31 30 Bit # C0P2 Opcode Coprocessor Unit Number Coprocessor Suboperation MIPS R4000 Microprocessor User's Manual A-115...
Page 584 If a MTHI operation is executed following a MULT, MULTU, DIV, or DIVU instruction, but before any MFLO, MFHI, MTLO, or MTHI instructions, the contents of special register LO are undefined. Operation: 32,64 T–2: HI undefined T–1: HI undefined GPR[rs] Exceptions: None A-116 MIPS R4000 Microprocessor User's Manual...
Page 585 If a MTLO operation is executed following a MULT, MULTU, DIV, or DIVU instruction, but before any MFLO, MFHI, MTLO, or MTHI instructions, the contents of special register HI are undefined. Operation: 32,64 T–2: LO undefined T–1: LO undefined GPR[rs] Exceptions: None MIPS R4000 Microprocessor User's Manual A-117...
Page 586 If either of the two preceding instructions is MFHI or MFLO, the results of these instructions are undefined. Correct operation requires separating reads of HI or LO from writes by a minimum of two other instructions. A-118 MIPS R4000 Microprocessor User's Manual...
Page 587 T–2: LO undefined undefined T–1: LO undefined undefined GPR[rs] * GPR[rt] 31...0 63...32 T–2: LO undefined undefined T–1: LO undefined undefined GPR[rs] * GPR[rt] 31...0 31...0 || t 31...0 || t 63...32 Exceptions: None MIPS R4000 Microprocessor User's Manual A-119...
Page 588 If either of the two preceding instructions is MFHI or MFLO, the results of these instructions are undefined. Correct operation requires separating reads of HI or LO from writes by a minimum of two instructions. A-120 MIPS R4000 Microprocessor User's Manual...
Page 589 (0 || GPR[rs]) * (0 || GPR[rt]) 31...0 63...32 T–2: LO undefined undefined T–1: LO undefined undefined (0 || GPR[rs] ) * (0 || GPR[rt] 31...0 31...0 || t 31...0 || t 63...32 Exceptions: None MIPS R4000 Microprocessor User's Manual A-121...
Page 590 The contents of general register rs are combined with the contents of general register rt in a bit-wise logical NOR operation. The result is placed into general register rd. Operation: 32, 64 GPR[rd] GPR[rs] nor GPR[rt] Exceptions: None A-122 MIPS R4000 Microprocessor User's Manual...
Page 591 The contents of general register rs are combined with the contents of general register rt in a bit-wise logical OR operation. The result is placed into general register rd. Operation: 32, 64 GPR[rd] GPR[rs] or GPR[rt] Exceptions: None MIPS R4000 Microprocessor User's Manual A-123...
Page 592 OR operation. The result is placed into general register rt. Operation: GPR[rt] GPR[rs] || (immediate or GPR[rs] 31...16 15...0 GPR[rt] GPR[rs] || (immediate or GPR[rs] 63...16 15...0 Exceptions: None A-124 MIPS R4000 Microprocessor User's Manual...
Page 593 BigEndianCPU 2...0 8*byte data GPR[rt] || 0 63–8*byte...0 StoreMemory (uncached, BYTE, data, pAddr, vAddr, DATA) Exceptions: TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception MIPS R4000 Microprocessor User's Manual A-125...
Page 594 If either of the two least-significant bits of the effective address is non-zero, an address error exception takes place. If this instruction should both fail and take an exception, the exception takes precedence. A-126 MIPS R4000 Microprocessor User's Manual...
Page 595 GPR[rt] || 0 63-8*byte...0 if LLbit then StoreMemory (uncached, WORD, data, pAddr, vAddr, DATA) endif GPR[rt] LLbit Exceptions: TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception MIPS R4000 Microprocessor User's Manual A-127...
Page 596 This instruction is available in User mode; it is not necessary for CP0 to be enabled. If either of the three least-significant bits of the effective address is non- zero, an address error exception takes place. A-128 MIPS R4000 Microprocessor User's Manual...
Page 597 (continued) If this instruction should both fail and take an exception, the exception takes precedence. This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception. Operation:...
Page 598 If either of the three least-significant bits of the effective address are non- zero, an address error exception occurs. This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception.
Page 599 (pAddr, uncached) AddressTranslation (vAddr, DATA) data COPzSD(rt), StoreMemory (uncached, DOUBLEWORD, data, pAddr, vAddr, DATA) *See the table, “Opcode Bit Encoding” on next page, or “CPU Instruction Opcode Bit Encoding” at the end of Appendix A. MIPS R4000 Microprocessor User's Manual A-131...
Page 600 TLB invalid exception TLB modification exception Bus error exception Address error exception Coprocessor unusable exception Opcode Bit Encoding: SDCz 31 30 Bit # SDC1 31 30 Bit # SDC2 SD opcode Coprocessor Unit Number A-132 MIPS R4000 Microprocessor User's Manual...
Page 601 No address exceptions due to alignment are possible. memory (big-endian) register 10 11 12 13 14 15 address 8 before A B C D E F G H address 0 SDL $24,1($0) address 8 10 11 12 13 after address 0 MIPS R4000 Microprocessor User's Manual A-133...
Page 602 Appendix A Store Doubleword Left (continued) This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception. Operation: vAddr ((offset || offset ) + GPR[base] 15...0 (pAddr, uncached)
Page 603 AccessType (see Table 2-1) sent to memory Offset pAddr sent to memory 2...0 Exceptions: TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception Reserved instruction exception (R4000 in 32-bit mode) MIPS R4000 Microprocessor User's Manual A-135...
Page 604 8 10 11 12 13 14 15 before B C D E F G H address 0 memory SDR $24,4($0) (big-endian) address 8 10 11 12 13 14 15 after address 0 A-136 MIPS R4000 Microprocessor User's Manual...
Page 605 CPU Instruction Set Details Store Doubleword Right (continued) This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception. Operation: T: vAddr ((offset || offset ) + GPR[base] 15...0...
Page 606 AccessType (see Table 2-1) sent to memory Offset pAddr sent to memory 2...0 Exceptions: TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception Reserved instruction exception (R4000 in 32-bit mode) A-138 MIPS R4000 Microprocessor User's Manual...
Page 607 (BigEndianCPU || 0) 2...0 8*byte data GPR[rt] || 0 63–8*byte...0 StoreMemory (uncached, HALFWORD, data, pAddr, vAddr, DATA) Exceptions: TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception MIPS R4000 Microprocessor User's Manual A-139...
Page 608 If using SLL with a zero shift to truncate 64-bit values, check the assembler you are using. Operation: GPR[rd] GPR[rt] || 0 31– sa...0 0 || sa temp GPR[rt] || 0 31-s...0 GPR[rd] (temp || temp Exceptions: None A-140 MIPS R4000 Microprocessor User's Manual...
Page 609 64-bit values, check the assembler you are using. Operation: GP[rs] 4...0 GPR[rd] GPR[rt] || 0 (31–s)...0 0 || GP[rs] 4...0 temp GPR[rt] || 0 (31-s)...0 GPR[rd] (temp || temp Exceptions: None MIPS R4000 Microprocessor User's Manual A-141...
Page 610 Operation: if GPR[rs] < GPR[rt] then GPR[rd] || 1 else GPR[rd] endif if GPR[rs] < GPR[rt] then GPR[rd] || 1 else GPR[rd] endif Exceptions: None A-142 MIPS R4000 Microprocessor User's Manual...
Page 611 Operation: if GPR[rs] < (immediate || immediate then 15...0 GPR[rd] || 1 else GPR[rd] endif if GPR[rs] < (immediate || immediate then 15...0 GPR[rd] || 1 else GPR[rd] endif Exceptions: None MIPS R4000 Microprocessor User's Manual A-143...
Page 612 (0 || GPR[rs]) < (immediate || immediate then 15...0 GPR[rd] || 1 else GPR[rd] endif if (0 || GPR[rs]) < (immediate || immediate then 15...0 GPR[rd] || 1 else GPR[rd] endif Exceptions: None A-144 MIPS R4000 Microprocessor User's Manual...
Page 613 Operation: if (0 || GPR[rs]) < 0 || GPR[rt] then GPR[rd] || 1 else GPR[rd] endif if (0 || GPR[rs]) < 0 || GPR[rt] then GPR[rd] || 1 else GPR[rd] endif Exceptions: None MIPS R4000 Microprocessor User's Manual A-145...
Page 614: Sra Shift Right Arithmetic
The result is placed in register rd. In 64-bit mode, the operand must be a valid sign-extended, 32-bit value. Operation: GPR[rd] (GPR[rt] || GPR[rt] 31...sa 0 || sa temp (GPR[rt] || GPR[rt] 31...s GPR[rd] (temp || temp Exceptions: None A-146 MIPS R4000 Microprocessor User's Manual...
Page 615 The result is placed in register rd. In 64-bit mode, the operand must be a valid sign-extended, 32-bit value. Operation: GPR[rs] 4...0 GPR[rd] (GPR[rt] || GPR[rt] 31...s GPR[rs] 4...0 temp (GPR[rt] || GPR[rt] 31...s GPR[rd] (temp || temp Exceptions: None MIPS R4000 Microprocessor User's Manual A-147...
Page 616 The result is placed in register rd. In 64-bit mode, the operand must be a valid sign-extended, 32-bit value. Operation: GPR[rd] || GPR[rt] 31...sa 0 || sa temp || GPR[rt] 31...s GPR[rd] (temp || temp Exceptions: None A-148 MIPS R4000 Microprocessor User's Manual...
Page 617 The result is placed in register rd. In 64-bit mode, the operand must be a valid sign-extended, 32-bit value. Operation: GPR[rs] 4...0 GPR[rd] || GPR[rt] 31...s GPR[rs] 4...0 temp || GPR[rt] 31...s GPR[rd] (temp || temp Exceptions: None MIPS R4000 Microprocessor User's Manual A-149...
Page 618 31 differ (2’s complement overflow). The destination register rd is not modified when an integer overflow exception occurs. Operation: GPR[rd] GPR[rs] – GPR[rt] temp GPR[rs] - GPR[rt] GPR[rd] (temp || temp 31...0 Exceptions: Integer overflow exception A-150 MIPS R4000 Microprocessor User's Manual...
Page 619 The only difference between this instruction and the SUB instruction is that SUBU never traps on overflow. No integer overflow exception occurs under any circumstances. Operation: GPR[rd] GPR[rs] – GPR[rt] temp GPR[rs] - GPR[rt] GPR[rd] (temp || temp 31...0 Exceptions: None MIPS R4000 Microprocessor User's Manual A-151...
Page 620 (BigEndianCPU || 0 2...0 8*byte data GPR[rt] || 0 63-8*byte StoreMemory (uncached, WORD, data, pAddr, vAddr, DATA) Exceptions: TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception A-152 MIPS R4000 Microprocessor User's Manual...
Page 621 (BigEndianCPU || 0 2...0 data COPzSW (byte,rt) StoreMemory (uncached, WORD, data, pAddr, vAddr DATA) *See the table “Opcode Bit Encoding” on next page, or “CPU Instruction Opcode Bit Encoding” at the end of Appendix A. MIPS R4000 Microprocessor User's Manual A-153...
Page 622 TLB invalid exception TLB modification exception Bus error exception Address error exception Coprocessor unusable exception Opcode Bit Encoding: SWCz 31 30 Bit # SWC1 31 30 Bit # SWC2 SW opcode Coprocessor Unit Number A-154 MIPS R4000 Microprocessor User's Manual...
Page 623 No address exceptions due to alignment are possible. memory (big-endian) register address 4 before address 0 SWL $24,1($0) address 4 after address 0 MIPS R4000 Microprocessor User's Manual A-155...
Page 624 BigEndianCPU 1...0 if (vAddr xor BigEndianCPU) = 0 then 24-8*byte data || 0 || GPR[rt] 31...24-8*byte else 24-8*byte data || GPR[rt] || 0 31...24-8*byte endif StoreMemory(uncached, byte, data, pAddr, vAddr, DATA) A-156 MIPS R4000 Microprocessor User's Manual...
Page 625 Little-endian memory (BigEndianMem = 0) BigEndianMem = 1 Type AccessType (see Table 2-1) sent to memory Offset pAddr sent to memory 2...0 Exceptions: TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception MIPS R4000 Microprocessor User's Manual A-157...
Page 626 No address exceptions due to alignment are possible. memory (big-endian) register address 4 before address 0 SWR $24,1($0) address 4 after address 0 A-158 MIPS R4000 Microprocessor User's Manual...
Page 627 BigEndianCPU 1...0 if (vAddr xor BigEndianCPU) = 0 then 8*byte data || GPR[rt] || 0 31-8*byte...0 else 8*byte data GPR[rt] || 0 || 0 31-8*byte...0 endif StoreMemory(uncached, WORD-byte, data, pAddr, vAddr, DATA) MIPS R4000 Microprocessor User's Manual A-159...
Page 628 Little-endian memory (BigEndianMem = 0) BigEndianMem = 1 Type AccessType (see Table 2-1) sent to memory Offset pAddr sent to memory 2...0 Exceptions: TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception A-160 MIPS R4000 Microprocessor User's Manual...
Page 629 NOP. LL and SC instructions implicitly perform a SYNC. This instruction is allowed in User mode. Operation: 32, 64 SyncOperation() Exceptions: None MIPS R4000 Microprocessor User's Manual A-161...
Page 630 The code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction. Operation: 32, 64 T: SystemCallException Exceptions: System Call exception A-162 MIPS R4000 Microprocessor User's Manual...
Page 631 The code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction. Operation: 32, 64 if GPR[rs] = GPR[rt] then TrapException endif Exceptions: Trap exception MIPS R4000 Microprocessor User's Manual A-163...
Page 632 If the contents of general register rs are equal to the sign-extended immediate, a trap exception occurs. Operation: if GPR[rs] = (immediate || immediate then 15...0 TrapException endif if GPR[rs] = (immediate || immediate then 15...0 TrapException endif Exceptions: Trap exception A-164 MIPS R4000 Microprocessor User's Manual...
Page 633 The code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction. Operation: 32, 64 T: if GPR[rs] GPR[rt] then TrapException endif Exceptions: Trap exception MIPS R4000 Microprocessor User's Manual A-165...
Page 634 Operation: T: if GPR[rs] (immediate || immediate then 15...0 TrapException endif T: if GPR[rs] (immediate || immediate then 15...0 TrapException endif Exceptions: Trap exception A-166 MIPS R4000 Microprocessor User's Manual...
Page 635 Operation: T: if (0 || GPR[rs]) (0 || (immediate || immediate ) then 15...0 TrapException endif T: if (0 || GPR[rs]) (0 || (immediate || immediate ) then 15...0 TrapException endif Exceptions: Trap exception MIPS R4000 Microprocessor User's Manual A-167...
Page 636 The code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction. Operation: if (0 || GPR[rs]) (0 || GPR[rt]) then TrapException endif Exceptions: Trap exception A-168 MIPS R4000 Microprocessor User's Manual...
Page 637 || TLB[i] 167...141 216...205 = EntryHi ) and not (0 || TLB[i] )) and 39...13 216...205 (TLB[i] or (TLB[i] = EntryHi )) then 135...128 7...0 Index || i 5...0 endif endfor Exceptions: Coprocessor unusable exception MIPS R4000 Microprocessor User's Manual A-169...
Page 638 5...0 31...0 T: PageMask TLB[Index 5...0 255...192 EntryHi TLB[Index and not TLB[Index 5...0 191...128 5...0 255...192 EntryLo1 TLB[Index || TLB[Index 5...0 127...65 5...0 EntryLo0 TLB[Index || TLB[Index 5...0 63...1 5...0 Exceptions: Coprocessor unusable exception A-170 MIPS R4000 Microprocessor User's Manual...
Page 639 TLB Index register are greater than the number of TLB entries in the processor. Operation: 32, 64T: TLB[Index 5...0 PageMask || (EntryHi and not PageMask) || EntryLo1 || EntryLo0 Exceptions: Coprocessor unusable exception MIPS R4000 Microprocessor User's Manual A-171...
Page 640 The TLB entry pointed at by the contents of the TLB Random register is loaded with the contents of the EntryHi and EntryLo registers. Operation: 32, 64T: TLB[Random 5...0 PageMask || (EntryHi and not PageMask) || EntryLo1 || EntryLo0 Exceptions: Coprocessor unusable exception A-172 MIPS R4000 Microprocessor User's Manual...
Page 641 The code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction. Operation: 32, 64 T: if GPR[rs] < GPR[rt] then TrapException endif Exceptions: Trap exception MIPS R4000 Microprocessor User's Manual A-173...
Page 642 Operation: T: if GPR[rs] < (immediate || immediate then 15...0 TrapException endif T: if GPR[rs] < (immediate || immediate then 15...0 TrapException endif Exceptions: Trap exception A-174 MIPS R4000 Microprocessor User's Manual...
Page 643 Operation: if (0 || GPR[rs]) < (0 || (immediate || immediate ) then 15...0 TrapException endif if (0 || GPR[rs]) < (0 || (immediate || immediate ) then 15...0 TrapException endif Exceptions: Trap exception MIPS R4000 Microprocessor User's Manual A-175...
Page 644 The code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction. Operation: 32, 64T: if (0 || GPR[rs]) < (0 || GPR[rt]) then TrapException endif Exceptions: Trap exception A-176 MIPS R4000 Microprocessor User's Manual...
Page 645 The code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction. Operation: 32, 64T: if GPR[rs] GPR[rt] then TrapException endif Exceptions: Trap exception MIPS R4000 Microprocessor User's Manual A-177...
Page 646 If the contents of general register rs are not equal to the sign-extended immediate, a trap exception occurs. Operation: if GPR[rs] (immediate || immediate then 15...0 TrapException endif if GPR[rs] (immediate || immediate then 15...0 TrapException endif Exceptions: Trap exception A-178 MIPS R4000 Microprocessor User's Manual...
Page 647 The contents of general register rs are combined with the contents of general register rt in a bit-wise logical exclusive OR operation. The result is placed into general register rd. Operation: 32, 64 GPR[rd] GPR[rs] xor GPR[rt] Exceptions: None MIPS R4000 Microprocessor User's Manual A-179...
Page 648 The 16-bit immediate is zero-extended and combined with the contents of general register rs in a bit-wise logical exclusive OR operation. The result is placed into general register rt. Operation: GPR[rt] GPR[rs] xor (0 || immediate) GPR[rt] GPR[rs] xor (0 || immediate) Exceptions: None A-180 MIPS R4000 Microprocessor User's Manual...
Page 649 CPU Instruction Set Details CPU Instruction Opcode Bit Encoding The remainder of this Appendix presents the opcode bit encoding for the CPU instruction set (ISA and extensions), as implemented by the R4000. Figure A-2 lists the R4000 Opcode Bit Encoding. 28...26 Opcode 31...29...
Page 650 Operation codes marked with a gamma cause a reserved instruction exception. They are reserved for future versions of the architecture. Operation codes marked with a delta are valid only for R4000 processors with CP0 enabled, and cause a reserved instruction exception on other processors.
Page 651 Figure B-3 at the end of this appendix lists the entire bit encoding for the constant fields of the floating-point instruction set; the bit encoding for each instruction is included with that individual instruction. MIPS R4000 Microprocessor User's Manual...
Page 652 (marked V in Table B-1). Combinations marked R in Table B-1 are not currently specified by this architecture, and cause an unimplemented operation trap. They will be available for future extensions to the architecture. MIPS R4000 Microprocessor User's Manual...
Page 653 FPU Instruction Set Details Table B-1 Valid FPU Instruction Formats Source Format Operation Single Double Word Longword SQRT TRUNC.L ROUND.L CEIL.L FLOOR.L TRUNC.W ROUND.W CEIL.W FLOOR.W CVT.S CVT.D CVT.W CVT.L MIPS R4000 Microprocessor User's Manual...
Page 654 16 distinct comparisons, as shown in Table B-2 below. Table B-2 Logical Negation of Predicates by Condition True/False Condition Relations Invalid Operation Mnemonic Greater Less Exception If Code Equal Unordered Than Than True False Unordered NGLE MIPS R4000 Microprocessor User's Manual...
Page 655 Specifically, these operations obtain a result which is identical to an infinite-precision result rounded to the specified format, using the current rounding mode. Instructions must specify the format of their operands. Except for conversion functions, mixed-format operations are not provided. MIPS R4000 Microprocessor User's Manual...
Page 656 Bit 15 (the sign bit) of an immediate value is extended for 16 bit positions, and the result is concatenated with bits 15 through 0 of the immediate value to form a 32-bit sign extended value. MIPS R4000 Microprocessor User's Manual...
Page 657 FPU Instruction Set Details B.3 Load and Store Instructions In the R4000 implementation, the instruction immediately following a load may use the contents of the register being loaded. In such cases, the hardware interlocks, requiring additional real cycles, so scheduling load delay slots is still desirable, although not required for functional code.
Page 658 Regardless of byte-numbering order (endianness), the address specifies that byte which has the smallest byte-address in the addressed field. For a big-endian machine, this is the leftmost byte; for a little-endian machine, this is the rightmost byte. MIPS R4000 Microprocessor User's Manual...
Page 659 Table B-4. Table B-4 Format Field Decoding Code Mnemonic Size Format single Binary floating-point double Binary floating-point Reserved Reserved single 32-bit binary fixed-point longword 64-bit binary fixed-point 22–31 Reserved Table B-5 lists all floating-point instructions. MIPS R4000 Microprocessor User's Manual...
Page 660 Reserved CVT.S Convert to single floating-point CVT.D Convert to double floating-point – Reserved – Reserved CVT.W Convert to 32-bit binary fixed-point CVT.L Convert to 64-bit (long) binary fixed-point 38–47 – Reserved 48–63 Floating-point compare B-10 MIPS R4000 Microprocessor User's Manual...
Page 661 = 0 then /* valid specifier, 32-bit wide FGRs */ case fmt of S, W: value FGR[fpr] return D, L: value FGR[fpr+1] || FGR[fpr] return endcase else /* undefined result for odd 32-bit reg #s */ value undefined endif MIPS R4000 Microprocessor User's Manual B-11...
Page 662 = 0 then /* valid specifier, 32-bit wide FGRs */ case fmt of S, W: FGR[fpr+1] undefined FGR[fpr] value return D, L: FGR[fpr+1] value 63...32 FGR[fpr] value 31...0 return endcase else /* undefined result for odd 32-bit reg #s */ undefined_result endif B-12 MIPS R4000 Microprocessor User's Manual...
Page 663 When the FR bit in the Status register equals one, both even and odd register numbers are valid. Operation: StoreFPR(fd, fmt, AbsoluteValue(ValueFPR(fs, fmt))) Exceptions: Coprocessor unusable exception Coprocessor exception trap Coprocessor Exceptions: Unimplemented operation exception Invalid operation exception MIPS R4000 Microprocessor User's Manual B-13...
Page 664 Operation: StoreFPR (fd, fmt, ValueFPR(fs, fmt) + ValueFPR(ft, fmt)) Exceptions: Coprocessor unusable exception Floating-Point exception Coprocessor Exceptions: Unimplemented operation exception Invalid operation exception Inexact exception Overflow exception Underflow exception B-14 MIPS R4000 Microprocessor User's Manual...
Page 665 || offset || 0 T+1: if condition then PC + target endif T–1: condition not COC[1] target (offset || offset || 0 T+1: if condition then PC + target endif Exceptions: Coprocessor unusable exception MIPS R4000 Microprocessor User's Manual B-15...
Page 666 T+1: if condition then PC + target else NullifyCurrentInstruction endif T–1: condition not COC[1] target (offset || offset || 0 T+1: if condition then PC + target else NullifyCurrentInstruction endif Exceptions: Coprocessor unusable exception B-16 MIPS R4000 Microprocessor User's Manual...
Page 667 (offset || offset || 0 T+1: if condition then PC + target endif T–1: condition COC[1] target (offset || offset || 0 T+1: if condition then PC + target endif Exceptions: Coprocessor unusable exception MIPS R4000 Microprocessor User's Manual B-17...
Page 668 || offset || 0 T+1: if condition then PC + target else NullifyCurrentInstruction endif T–1: condition COC[1] target (offset || offset || 0 T+1: if condition then PC + target else NullifyCurrentInstruction endif Exceptions: Coprocessor unusable exception B-18 MIPS R4000 Microprocessor User's Manual...
Page 669 When the FR bit in the Status register equals one, both even and odd register numbers are valid. *See “FPU Instruction Opcode Bit Encoding” at the end of Appendix B. MIPS R4000 Microprocessor User's Manual B-19...
Page 670 ValueFPR(fs, fmt) = ValueFPR(ft, fmt) unordered false endif and equal) or condition (cond and less) or (cond (cond and unordered) FCR[31] condition COC[1] condition Exceptions: Coprocessor unusable Floating-Point exception Coprocessor Exceptions: Unimplemented operation exception Invalid operation exception B-20 MIPS R4000 Microprocessor User's Manual...
Page 671 When the source operand is an Infinity, NaN, or the correctly rounded integer result is outside of –2 to 2 – 1, the Invalid operation exception is raised. If the Invalid operation is not enabled then no exception is taken and 2 –1 is returned. MIPS R4000 Microprocessor User's Manual B-21...
Page 672 Floating-Point CEIL.L.fmt CEIL.L.fmt Ceiling to Long Fixed-Point Format (continued) Operation: StoreFPR(fd, L, ConvertFmt(ValueFPR(fs, fmt), fmt, L)) Exceptions: Coprocessor unusable exception Floating-Point exception Coprocessor Exceptions: Invalid operation exception Unimplemented operation exception Inexact exception Overflow exception B-22 MIPS R4000 Microprocessor User's Manual...
Page 673 When the source operand is an Infinity or NaN, or the correctly rounded integer result is outside of –2 to 2 – 1, the Invalid operation exception is raised. If the Invalid operation is not enabled then no exception is taken and 2 –1 is returned. MIPS R4000 Microprocessor User's Manual B-23...
Page 674 Floating-Point CEIL.W.fmt CEIL.W.fmt Ceiling to Single Fixed-Point Format (continued) Operation: StoreFPR(fd, W, ConvertFmt(ValueFPR(fs, fmt), fmt, W)) Exceptions: Coprocessor unusable exception Floating-Point exception Coprocessor Exceptions: Invalid operation exception Unimplemented operation exception Inexact exception Overflow exception B-24 MIPS R4000 Microprocessor User's Manual...
Page 675 This operation is only defined when fs equals 0 or 31. The contents of general register rt are undefined for the instruction immediately following CFC1. Operation: temp FCR[fs] T+1: GPR[rt] temp temp FCR[fs] T+1: GPR[rt] (temp || temp Exceptions: Coprocessor unusable exception MIPS R4000 Microprocessor User's Manual B-25...
Page 676 COC[1] FCR[31] temp GPR[rt] 31...0 T+1: FCR[fs] temp COC[1] FCR[31] Exceptions: Coprocessor unusable exception Floating-Point exception Coprocessor Exceptions: Unimplemented operation exception Invalid operation exception Division by zero exception Inexact exception Overflow exception Underflow exception B-26 MIPS R4000 Microprocessor User's Manual...
Page 677 Operation: StoreFPR (fd, D, ConvertFmt(ValueFPR(fs, fmt), fmt, D)) Exceptions: Coprocessor unusable exception Floating-Point exception Coprocessor Exceptions: Invalid operation exception Unimplemented operation exception Inexact exception Overflow exception Underflow exception MIPS R4000 Microprocessor User's Manual B-27...
Page 678 If the Invalid operation is not enabled then no exception is taken and 2 –1 is returned. Operation: StoreFPR (fd, L, ConvertFmt(ValueFPR(fs, fmt), fmt, L)) Exceptions: Coprocessor unusable exception Floating-Point exception Coprocessor Exceptions: Invalid operation exception Unimplemented operation exception Inexact exception Overflow exception B-28 MIPS R4000 Microprocessor User's Manual...
Page 679 Operation: StoreFPR(fd, S, ConvertFmt(ValueFPR(fs, fmt), fmt, S)) Exceptions: Coprocessor unusable exception Floating-Point exception Coprocessor Exceptions: Invalid operation exception Unimplemented operation exception Inexact exception Overflow exception Underflow exception MIPS R4000 Microprocessor User's Manual B-29...
Page 680 If Invalid operation is not enabled, then no exception is taken and –1 is returned. Operation: StoreFPR(fd, W, ConvertFmt(ValueFPR(fs, fmt), fmt, W)) Exceptions: Coprocessor unusable exception Floating-Point exception Coprocessor Exceptions: Invalid operation exception Unimplemented operation exception Inexact exception Overflow exception B-30 MIPS R4000 Microprocessor User's Manual...
Page 681 FR bit in the Status register equals one, both even and odd register numbers are valid. Operation: StoreFPR (fd, fmt, ValueFPR(fs, fmt)/ValueFPR(ft, fmt)) Exceptions: Coprocessor unusable exception Floating-Point exception Coprocessor Exceptions: Unimplemented operation exception Invalid operation exception Division-by-zero exception Inexact exception Overflow exception Underflow exception MIPS R4000 Microprocessor User's Manual B-31...
Page 682 The FR bit in the Status register specifies whether all 32 registers of the R4000 are addressable. When FR equals zero, this instruction is not defined when the least significant bit of fs is non-zero. When FR is set, fs may specify either odd or even registers.
Page 683 DMTC1. The FR bit in the Status register specifies whether all 32 registers of the R4000 are addressable. When FR equals zero, this instruction is not defined when the least significant bit of fs is non-zero. When FR equals one, fs may specify either odd or even registers.
Page 684 When the source operand is an Infinity, NaN, or the correctly rounded integer result is outside of –2 to 2 – 1, the Invalid operation exception is raised. If the Invalid operation is not enabled then no exception is taken and 2 –1 is returned. B-34 MIPS R4000 Microprocessor User's Manual...
Page 685 Floating-Point FLOOR.L.fmt FLOOR.L.fmt Floor to Long Fixed-Point Format (continued) Operation: StoreFPR(fd, L, ConvertFmt(ValueFPR(fs, fmt), fmt, L)) Exceptions: Coprocessor unusable exception Floating-Point exception Coprocessor Exceptions: Invalid operation exception Unimplemented operation exception Inexact exception Overflow exception MIPS R4000 Microprocessor User's Manual B-35...
Page 686 When the source operand is an Infinity or NaN, or the correctly rounded integer result is outside of –2 to 2 –1, an Invalid operation exception is raised. If Invalid operation is not enabled, then no exception is taken and –1 is returned. B-36 MIPS R4000 Microprocessor User's Manual...
Page 687 Floating-Point FLOOR.W.fmt FLOOR.W.fmt Floor to Single Fixed-Point Format (continued) Operation: StoreFPR(fd, W, ConvertFmt(ValueFPR(fs, fmt), fmt, W)) Exceptions: Coprocessor unusable exception Floating-Point exception Coprocessor Exceptions: Invalid operation exception Unimplemented operation exception Inexact exception Overflow exception MIPS R4000 Microprocessor User's Manual B-37...
Page 688 The FR bit of the Status register (SR ) speciﬁes whether all 32 registers of the R4000 are addressable. If FR equals zero, this instruction is not deﬁned when the least signiﬁcant bit of ft is non-zero. If FR equals one, ft may specify either odd or even registers.
Page 689 = 0 then /* valid specifier, 32-bit wide FGRs */ FGR[ft+1] data 63...32 FGR[ft] data 31...0 else /* undefined result if odd */ undefined_result endif Exceptions: Coprocessor unusable TLB refill exception TLB invalid exception Bus error exception Address error exception MIPS R4000 Microprocessor User's Manual B-39...
Page 690 16 even Floating-Point registers. If FR equals one, LWC1 loads the low 32-bits of both even and odd Floating-Point registers. If either of the two least-significant bits of the effective address is non-zero, an address error exception occurs. B-40 MIPS R4000 Microprocessor User's Manual...
Page 691 = 1 then /* 64-bit wide FGRs */ FGR[ft] undefined || mem 31+8*byte...8*byte else /* 32-bit wide FGRs */ FGR[ft] 31+8*byte...8*byte endif Exceptions: Coprocessor unusable TLB refill exception TLB invalid exception Bus error exception Address error exception MIPS R4000 Microprocessor User's Manual B-41...
Page 692 The FR bit of the Status register specifies whether all 32 registers of the R4000 are addressable. If FR equals zero, MFC1 stores either the high or low half of the 16 even Floating-Point registers. If FR equals one, MFC1 stores the low 32-bits of both even and odd Floating-Point registers.
Page 693 When the FR bit in the Status register equals one, both even and odd register numbers are valid. Operation: StoreFPR(fd, fmt, ValueFPR(fs, fmt)) Exceptions: Coprocessor unusable exception Floating-Point exception Coprocessor Exceptions: Unimplemented operation exception MIPS R4000 Microprocessor User's Manual B-43...
Page 694 The FR bit of the Status register specifies whether all 32 registers of the R4000 are addressable. If FR equals zero, MTC1 loads either the high or low half of the 16 even Floating-Point registers. If FR equals one, MTC1 loads the low 32-bits of both even and odd Floating-Point registers.
Page 695 FR bit in the Status register equals one, both even and odd register numbers are valid. Operation: StoreFPR (fd, fmt, ValueFPR(fs, fmt) * ValueFPR(ft, fmt)) Exceptions: Coprocessor unusable exception Floating-Point exception Coprocessor Exceptions: Unimplemented operation exception Invalid operation exception Inexact exception Overflow exception Underflow exception MIPS R4000 Microprocessor User's Manual B-45...
Page 696 When the FR bit in the Status register equals one, both even and odd register numbers are valid. Operation: StoreFPR(fd, fmt, Negate(ValueFPR(fs, fmt))) Exceptions: Coprocessor unusable exception Floating-Point exception Coprocessor Exceptions: Unimplemented operation exception Invalid operation exception B-46 MIPS R4000 Microprocessor User's Manual...
Page 697 When the source operand is an Infinity, NaN, or the correctly rounded integer result is outside of –2 to 2 – 1, the Invalid operation exception is raised. If the Invalid operation is not enabled then no exception is taken and 2 –1 is returned. MIPS R4000 Microprocessor User's Manual B-47...
Page 698 Floating-Point ROUND.L.fmt ROUND.L.fmt Round to Long Fixed-Point Format (continued) Operation: StoreFPR(fd, L, ConvertFmt(ValueFPR(fs, fmt), fmt, L)) Exceptions: Coprocessor unusable exception Floating-Point exception Coprocessor Exceptions: Invalid operation exception Unimplemented operation exception Inexact exception Overflow exception B-48 MIPS R4000 Microprocessor User's Manual...
Page 699 When the source operand is an Infinity or NaN, or the correctly rounded integer result is outside of –2 to 2 –1, an Invalid operation exception is raised. If Invalid operation is not enabled, then no exception is taken and –1 is returned. MIPS R4000 Microprocessor User's Manual B-49...
Page 700 ROUND.W.fmt ROUND.W.fmt Floating-Point Round to Single Fixed-Point Format (continued) Operation: StoreFPR(fd, W, ConvertFmt(ValueFPR(fs, fmt), fmt, W)) Exceptions: Coprocessor unusable exception Floating-Point exception Coprocessor Exceptions: Invalid operation exception Unimplemented operation exception Inexact exception Overflow exception B-50 MIPS R4000 Microprocessor User's Manual...
Page 701 The FR bit of the Status register (SR ) specifies whether all 32 registers of the R4000 are addressable. When FR equals zero, this instruction is not defined if the least significant bit of ft is non-zero. If FR equals one, ft may specify either odd or even registers.
Page 702 /* undefined for odd 32-bit reg #s */ data undefined endif StoreMemory(uncached, DOUBLEWORD, data, pAddr, vAddr, DATA) Exceptions: Coprocessor unusable TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception B-52 MIPS R4000 Microprocessor User's Manual...
Page 703 FR bit in the Status register equals one, both even and odd register numbers are valid. Operation: StoreFPR(fd, fmt, SquareRoot(ValueFPR(fs, fmt))) Exceptions: Coprocessor unusable exception Floating-Point exception Coprocessor Exceptions: Unimplemented operation exception Invalid operation exception Inexact exception MIPS R4000 Microprocessor User's Manual B-53...
Page 704 FR bit in the Status register equals one, both even and odd register numbers are valid. Operation: StoreFPR (fd, fmt, ValueFPR(fs, fmt) – ValueFPR(ft, fmt)) Exceptions: Coprocessor unusable exception Floating-Point exception Coprocessor Exceptions: Unimplemented operation exception Invalid operation exception Inexact exception Overflow exception Underflow exception B-54 MIPS R4000 Microprocessor User's Manual...
Page 705 If FR equals one, SWC1 stores the low 32-bits of both even and odd floating-point registers. If either of the two least-significant bits of the effective address are non- zero, an address error exception occurs. MIPS R4000 Microprocessor User's Manual B-55...
Page 706 /* 32-bit wide FGRs */ 32-8*byte 8*byte data || FGR[ft] || 0 endif StoreMemory (uncached, WORD, data, pAddr, vAddr, DATA) Exceptions: Coprocessor unusable TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception B-56 MIPS R4000 Microprocessor User's Manual...
Page 707 When the source operand is an Infinity, NaN, or the correctly rounded integer result is outside of –2 to 2 –1, the Invalid operation exception is raised. If the Invalid operation is not enabled then no exception is taken and 2 –1 is returned. MIPS R4000 Microprocessor User's Manual B-57...
Page 708 Floating-Point TRUNC.L.fmt TRUNC.L.fmt Truncate to Long Fixed-Point Format (continued) Operation: StoreFPR(fd, L, ConvertFmt(ValueFPR(fs, fmt), fmt, L)) Exceptions: Coprocessor unusable exception Floating-Point exception Coprocessor Exceptions: Invalid operation exception Unimplemented operation exception Inexact exception Overflow exception B-58 MIPS R4000 Microprocessor User's Manual...
Page 709 When the source operand is an Infinity or NaN, or the correctly rounded 31–1 integer result is outside of –2 to 2 , an Invalid operation exception is raised. If Invalid operation is not enabled, then no exception is taken and –2 is returned. MIPS R4000 Microprocessor User's Manual B-59...
Page 710 TRUNC.W.fmt TRUNC.W.fmt Floating-Point Truncate to Single Fixed-Point Format (continued) Operation: StoreFPR(fd, W, ConvertFmt(ValueFPR(fs, fmt), fmt, W)) Exceptions: Coprocessor unusable exception Floating-Point exception Coprocessor Exceptions: Invalid operation exception Unimplemented operation exception Inexact exception Overflow exception B-60 MIPS R4000 Microprocessor User's Manual...
Page 711 FPU Instruction Set Details FPU Instruction Opcode Bit Encoding Opcode 28...26 31...29 COP1 LDC1 LWC1 SDC1 SWC1 23...21 25...24 18...16 20...19 BCFL BCTL Figure B-3 Bit Encoding for FPU Instructions MIPS R4000 Microprocessor User's Manual B-61...
Page 712 Operation codes marked with an eta are valid only when MIPS III instructions are enabled. Any attempt to execute these without MIPS III instructions enabled causes an unimplemented operation exception. B-62 MIPS R4000 Microprocessor User's Manual...
Page 713: Subblock Ordering
A block of data elements (whether bytes, halfwords, words, or doublewords) can be retrieved from storage in two ways: in sequential order, or using a subblock order. This chapter describes these retrieval methods, with an emphasis on subblock ordering. MIPS R4000 Microprocessor User's Manual...
Page 714 8 doublewords, in which DW2 is taken first. hexword (block) octalword quadword Order of retrieval DW 3 taken third taken eighth taken second taken fourth taken seventh taken fifth taken first taken sixth Figure C-2 Retrieving Data in a Subblock Order MIPS R4000 Microprocessor User's Manual...
Page 715 XOR of address 0010 with the binary count of DW8, 0111 . The result is 0101 , or DW5 (shown in Table C-1). The remaining tables illustrate this method of subblock ordering, using various address permutations. MIPS R4000 Microprocessor User's Manual...
Page 716 0100 0110 0010 0101 0111 0010 0110 0100 0010 0111 0101 0010 1000 1010 0010 1001 1011 0010 1010 1000 0010 1011 1001 0010 1100 1110 0010 1101 1111 0010 1110 1100 0010 1111 1101 MIPS R4000 Microprocessor User's Manual...
Page 717 0100 1111 1011 0101 1110 1011 0110 1101 1011 0111 1100 1011 1000 0011 1011 1001 0010 1011 1010 0001 1011 1011 0000 1011 1100 0111 1011 1101 0110 1011 1110 0101 1011 1111 0100 MIPS R4000 Microprocessor User's Manual...
Page 718 0100 0001 0101 0101 0000 0101 0110 0011 0101 0111 0010 0101 1000 1101 0101 1001 1100 0101 1010 1111 0101 1011 1110 0101 1100 1001 0101 1101 1000 0101 1110 1011 0101 1111 1010 MIPS R4000 Microprocessor User's Manual...
Page 719 Output Buffer i/ t Control Mechanism The speed of the R4000 output drivers is controlled by a negative feedback loop that insures the drive-off times are only as fast as necessary to meet the system requirement for single cycle transfers. This guarantees the minimum ground bounce from L* i/ t) of the switching buffers, consistent with the system timing requirements.
Page 720: Delay Times
All output drivers on the R4000, with the exception of the clock drivers, are controlled by the i/ t control mechanism. The delay due to the output...
Page 721: Cpu Board
• connecting an incident-wave trace of length L with a capacitive loading of C between the IO_In and IO_Out pins of the R4000 • connecting a reﬂected wave trace of length L/2 to the IO_In pin of the R4000.
Page 722 Appendix D MIPS R4000 Microprocessor User's Manual...
Page 723 VssP (as shown), VccP, or one to VssP and one to VccP. Note that C2 and the Cp capacitors are incorporated into both the 179PGA and 447PGA package designs as surface-mounted chip capacitors. MIPS R4000 Microprocessor User's Manual...
Page 724 Appendix E PLLCap1 VccP R4000 C1, C3, Rs and Ls are Board Caps VssP PLLCap0 Figure E-1 PLL Passive Components MIPS R4000 Microprocessor User's Manual...
Page 725 In addition, the chokes (inductors: L) can be considered for use as an alternative to the resistors (R) for use in filtering the power supply. MIPS R4000 Microprocessor User's Manual...
Page 726 Appendix E MIPS R4000 Microprocessor User's Manual...
Page 727 In addition to instructions, events can be writers and users of CP0 information. For instance, an exception writes information to CP0 registers and events that occur for every instruction, like an instruction MIPS R4000 Microprocessor User's Manual...
Page 728 1. This means 1 instruction must be inserted between the MTC0 and TLBWR. If the result of the computation is less than or equal to zero, there is no hazard and no instructions are required between the pair. MIPS R4000 Microprocessor User's Manual...
Page 729 Coprocessor 0 Hazards Table F-1 R4000 Coprocessor 0 Data Writer and User Timing Instruction or Event CP0 Data Used, Stage Used CP0 Data Written, Stage Available MTC0 / DMTC0 CPR[0,rd] MFC0 / DMFC0 CPR[0,rd] PageMask, EntryHi, TLBR Index, TLB EntryLo0, EntryLo1...
Page 730 †. You cannot depend on a delay in effect if the instruction execution order is changed by exceptions. In this case, for example, the minimum delay for IE to be effective is the maximum delay before a pending, enabled interrupt can occur. MIPS R4000 Microprocessor User's Manual...
Page 731 R4000 Pinouts This Appendix shows the pinouts for the three microprocessor configurations: R4000PC, R4000SC, and R4000MC. NOTE: This entire Appendix, Appendix G, is new for the second edition. MIPS R4000 Microprocessor User's Manual...
Page 732: Pinout Of R4000Pc
• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • Figure G-1 R4000PC Physical Pinout MIPS R4000 Microprocessor User's Manual...
Page 733 SysAD42 SysAD43 SysAD44 SysAD45 SysAD46 SysAD47 SysAD48 SysAD49 SysAD50 SysAD51 SysAD52 SysAD53 SysAD54 SysAD55 SysAD56 SysAD57 SysAD58 SysAD59 SysAD60 SysAD61 SysAD62 SysAD63 SysADC0 †. This node has capacitors for the PLL premounted to the package. MIPS R4000 Microprocessor User's Manual...
Page 734 PC Pkg R4000 PC Pkg R4000 PC Pkg Function Function Function SysADC1 SysADC2 SysADC3 SysADC4 SysADC5 SysADC6 SysADC7 SysCmd0 SysCmd1 SysCmd2 SysCmd3 SysCmd4 SysCmd5 SysCmd6 SysCmd7 SysCmd8 SysCmdP TClock0 TClock1 VCCOk ValidIn* ValidOut* WrRdy* VccP VssP MIPS R4000 Microprocessor User's Manual...
Page 735: Pinout Of R4000Mc/Sc Package Pinout
• • • • • • • • • • • • • • • • AW AU AR AN AG AE AC AA AP AM AK AH AD AB Figure G-2 R4000MC/SC Physical Pinout MIPS R4000 Microprocessor User's Manual...
Page 736 AN13 SCData22 AT14 SCData23 AR17 SCData24 AT22 †. Used only in the MC part. Must be tied to Vcc for the SC part. ‡. This node has capacitors for the PLL premounted to the package. MIPS R4000 Microprocessor User's Manual...
Page 737 AR33 SCData94 AL35 SCData95 AH34 SCData96 SCData97 SCData98 SCData99 SCData100 SCData101 SCData102 SCData103 SCData104 SCData105 SCData106 SCData107 SCData108 SCData109 SCData110 SCData111 SCData112 SCData113 SCData114 SCData115 SCData116 AN11 SCData117 AU11 SCData118 AU13 SCData119 AN17 SCData120 AR21 MIPS R4000 Microprocessor User's Manual...
Page 738 SysAD15 SysAD16 SysAD17 SysAD18 SysAD19 SysAD20 SysAD21 SysAD22 SysAD23 AW13 SysAD24 AW21 SysAD25 AW25 SysAD26 AW29 SysAD27 AW33 SysAD28 AV38 SysAD29 AR37 SysAD30 AM38 SysAD31 AH38 SysAD32 SysAD33 SysAD34 SysAD35 SysAD36 SysAD37 SysAD38 SysAD39 SysAD40 MIPS R4000 Microprocessor User's Manual...
Page 739 SysCmd1 SysCmd2 SysCmd3 SysCmd4 SysCmd5 SysCmd6 SysCmd7 SysCmd8 SysCmdP TClock0 TClock1 VCCOk AE39 ValidIn* ValidOut* WrRdy* VccSense VssSense VccP AA33 VssP AB34 AD36 AF38 AK34 AM36 AP10 AP18 AP26 AP38 AT16 AT24 AT32 AT36 AV14 MIPS R4000 Microprocessor User's Manual...
Page 740 PC Pkg R4000 PC Pkg R4000 PC Pkg Function Function Function AV22 AV30 AV34 AW39 AB36 AB38 AF34 AH36 AK38 AP14 AP22 AP30 AP34 AP36 AT12 AT20 AT28 AT34 AT38 AV10 AV18 AV26 AV36 G-10 MIPS R4000 Microprocessor User's Manual...
Page 741 MIPS R2000, R3000, and R6000 data format processors double-precision FP format architecture floating-point registers 64-bit superpipeline internal data path widths array, page table entry (PTE) 6, 39, 67 operations ASID. See address space identifier System interface virtual-to-physical-address translation MIPS R4000 Microprocessor User's Manual...
Page 742 Cache Error (CacheErr) register line size Cache Error exception secondary cache Cache Error exception process accessing caches line size attributes organization clean states clean exclusive dirty dirty exclusive MIPS R4000 Microprocessor User's Manual...
Page 743 See also System Control historical context Coprocessor computational instructions, CPU System interface 64-bit operations See also System interface cycle timing for multiply and divide transfers between FPU and CPU instructions CISC. See complex instruction set formats computer MIPS R4000 Microprocessor User's Manual...
Page 744 Bus Error dirty exclusive, cache attribute Cache Error dirty shared, cache attribute Cache Error exception process dirty, cache attribute Coprocessor Unusable divide registers, CPU Floating-Point Division-by-Zero exception general exception process doublewords, byte ordering in Integer Overflow MIPS R4000 Microprocessor User's Manual...
Page 745 See yellow_slugs Exception Program Counter (EPC) register general exception 100, 112 handler exclusive, cache attribute process Execution (EX) servicing guidelines 68, 69, 73, 109, 112, 119 EXL bit extensions, to instruction set architecture external stalls, conditions MIPS R4000 Microprocessor User's Manual...
Page 746 (ISA) instructions, FPU extensions to branch overview compare instruction set, CPU computational extensions conversion 14, 35 overview latency types of instructions load See also instructions, CPU move instruction set, FPU pipeline stage sequences MIPS R4000 Microprocessor User's Manual...
Page 747 Joint Test Action Group (JTAG) interface language suite approach, benefits of boundary scanning, explanation of latency determining operation external read response registers 361, 363 external response Boundary-scan fault detection Bypass FPU instruction Instruction FPU operation MIPS R4000 Microprocessor User's Manual...
Page 748 System Control Coprocessor (CP0) exception conditions memory organization, hierarchy external stalls MIPS RISCompilers, language suite load delay MIPS R-Series processors, instructions operation 16–23 common to overrun move instructions, FPU performance considerations multiply registers, CPU slip conditions MIPS R4000 Microprocessor User's Manual...
Page 749 EC bit ECC Fault* signal Load Linked Address (LLAddr) enhancements over R4000 EW bit Processor Revision Identifier fault detection latency (PRId) IC bit, setting primary I-cache size register numbers Master/Checker boot-mode bits Status 223, 225 TagHi MIPS R4000 Microprocessor User's Manual...
Page 750 JTAG interface Instruction request cycle control signals Request Secondary Cache interface requests. See System interface summary Reserved Instruction exception system clocks Reset exception System interface handling slips, conditions overview slugs, banana. See UCSC process I-10 MIPS R4000 Microprocessor User's Manual...
Page 751 SysAD bus xsseg secondary cache transfers xsuseg secondary cache write cycle time suseg 69, 109 293–294 SX bit description System Call exception endianness System Control Coprocessor (CP0) hazards instructions register numbers MIPS R4000 Microprocessor User's Manual I-11...
Page 752 TLB/XTLB refill exception servicing cluster flow control guidelines invalidate request translation lookaside buffer (TLB) null write request and memory management overview and virtual memory read request coherency attributes update request entry formats write request I-12 MIPS R4000 Microprocessor User's Manual...
Page 753 Virtual Coherency exception virtual memory and the TLB hits and misses mapping multiple matches virtual address translation 208, 214, 217 warm reset Watch exception WatchHi register WatchLo register 86, 88 Wired register Write Back (WB) MIPS R4000 Microprocessor User's Manual I-13...
Page 754 Index I-14 MIPS R4000 Microprocessor User's Manual...

Mips Technologies R4000 User Manual

Introduction

CPU Instruction Set Summary

The CPU Pipeline

Memory Management

CPU Exception Processing

Output Buffer ∆I/∆T Control Mechanism

Floating-Point Unit

Floating-Point Exceptions

R4000 Processor Signal Descriptions

Initialization Interface

Subblock Ordering

Clock Interface

Cache Organization, Operation, and Coherency

System Interface

Quick Links

Related Manuals for Mips Technologies R4000

Summary of Contents for Mips Technologies R4000