Microchip Technology Microsemi UG0936 Manuals

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Microchip Technology Microsemi UG0936 User Manual (130 pages)

RT PolarFire FPGA Transceiver

Brand: Microchip Technology | Category: Transceiver | Size: 4 MB

Table of Contents
3
Revision History
8
Revision 1.0
8
Overview
9
Table 1 Supported Serial Protocols
9
Figure 1 Transceiver Lane Overview
10
Features
11
Functional Description
12
Pma
12
Receiver
12
Figure 2 Transceiver Receiver
13
Figure 3 Receiver Input Buffer
13
Figure 4 Input Signal Path
14
Figure 5 CDR Lock Mode Options
16
Table 2 CDR Lock Mode Values
16
Table 3 Mode of Operations
18
Transmitter
19
Figure 6 Transceiver Transmitter
19
Figure 7 Transmit Output Driver
20
Enhanced Receiver Management
21
Table 4 ERM Ports
21
Figure 8 Enhanced Receiver Management in XCVR Configurator
22
Figure 9 Calibration Options for Enhanced Receiver Management Operations
22
Figure 10 Exposing RX_READY_CDR and RX_VAL_CDR Pins
23
Table 5 DFE Options
23
Figure 11 DFE Options
24
Figure 12 First Lock Calibration Waveform
24
Figure 13 Disruption of Serial Rx Data Stream
25
Figure 14 Restart after Initialization
25
Transceiver PCS Interface Modes
26
Figure 15 On-Demand Calibration Waveform
26
8B10B
27
Figure 16 8B10B Data Path
29
Table 6 System Registers Affecting 8B10B Data Path
30
Table 7 8B10B Port List
31
64B66B/64B67B
34
Table 8 64B6Xb Transmit Data Path Blocks, Fabric to PMA Order
34
Figure 17 64B6Xb Data Path
35
Table 9 64B6Xb Receive Data Path Blocks, PMA to Fabric Order
35
Table 10 System Registers Affecting 64B6Xb Data Path
36
Figure 18 64B66B Receive Sequence for 32-Bit Interface
37
Figure 19 64B66B Receive Sequence for 64-Bit Interface
37
Figure 20 64B66B Transmit Sequence for 64-Bit Interface
38
Figure 21 64B66B Transmit Sequence for 32-Bit Interface
38
Figure 22 64B67B Transmit Sequence for 32-Bit Interface
39
Figure 23 64B67B Receive Sequence for 32-Bit Interface
40
Table 11 64B66B/64B67B Port List
40
Pipe
42
Table 12 PIPE Port List
44
PIPE Interface Compliance Exceptions
47
Figure 24 Initial Receiver Detection Response for Receiver-Not-Present
47
PMA Only
48
Figure 25 Initial Receiver Detection for Receiver-Present
48
Figure 26 Subsequent Receiver Detection Where Prior Status was Receiver-Not-Present
48
Figure 27 PMA-Bus Waveform
49
Figure 28 PMA Only Data Path - 80-Bits
49
Figure 29 PMA Only Data Path - Less than or Equal to 40-Bits
50
Table 13 PMA Port List
50
PCS/FPGA Fabric Interface
52
Non-Deterministic Interface
53
Figure 30 Global-Shared Clocking Example
53
Figure 31 Non-Deterministic Interface with FWF
54
Figure 32 Non-Deterministic Interface Transmit Timing Waveform
54
Figure 33 Non-Deterministic Transceiver Receive Timing Waveform
54
Deterministic Interface
55
Figure 34 Deterministic Timing Interface
55
Figure 35 Deterministic Transceiver Transmit Timing Waveform
55
Transceiver Clock Regions
56
Figure 36 Deterministic Transceiver Receive Timing Waveform
56
Figure 37 Transceiver Clock Regions
56
Transceiver Data Path Latency
57
Transceiver Clocking Use Cases
57
Table 14 Clock Region Connectivity
57
Table 15 Transceiver Data Path Latency
57
Transceiver Clocking
58
Table 16 Transceiver Interface Clocking Use Cases
58
Transmit PLL
59
Figure 38 Transmit PLL
59
Table 17 Transmit PLL
60
Spread Spectrum Clocking
61
Figure 39 Spread Spectrum Clocking Modulation Mode
61
Transmit Lane Alignment
62
Figure 40 Using TXPLL_SSC for Upto Four Lanes
62
Figure 41 Using Txplls for Upto Four Lanes
63
Figure 42 FPGA Logic for TX Alignment (5 to 8 Lanes)
64
Transceiver Clocks
65
Figure 43 Reference Clock (REFCLK) Interface to Transmit PLL
66
Table 18 Transmit PLL Pin List
66
Figure 44 Typical Jitter Attenuator Application Scheme
67
Figure 45 Jitter Attenuation TXPLL
68
Table 19 Jitter Attenuation PLL Presets
68
Figure 46 JAPLL Custom Protocol Setting
69
Figure 47 Reference Clock Source Options
69
Figure 48 Rx JA Clock Frequency (XCVR Configurator)
69
Figure 49 Dedicated Transceiver Reference Clock Inputs
70
Table 20 XCVR REFCLK Defaults
71
Figure 50 REFCLK Input Pin Diagram
72
Table 21 Reference Clock Input Buffer Standards
72
Table 22 RT Polarfire Transceiver Resources
73
Figure 51 RTPF500T Transceiver and Transmit PLL Layout
74
PMA and PCS Resets
75
PCS Rate Switch between 8B10B and 64B66B Mode for CPRI
76
Figure 52 PCS Rate Switch between 8B10B and 64B66B Mode
76
Table 23 Port Crossover between the 8B10B and 64B66B Modes
76
Table 24 System Registers Affecting 8B10B and 64B6Xb Data Paths
79
Implementation
82
Libero Configurators
82
Table 25 Transceiver Configurator Component List
82
Transceiver Reference Clock Configurator
83
Figure 53 Transceiver Reference Clock Selection from Catalog
83
Figure 54 Transceiver Reference Clock Configurator GUI
84
Table 26 Transceiver Reference Clock Configurator GUI Options
84
Figure 55 Transceiver Reference Clock Mode Type
85
Figure 56 PF_XCVR_REF_CLK with One Single-Ended Input and Single Output Clock
85
Figure 57 PF_XCVR_REF_CLK with Two Single-Ended Input and Two Output Clock
85
Figure 58 PF_XCVR_REF_CLK with Differential Input and Single Output Clock
86
Figure 59 PF_XCVR_REF_CLK with Fabric Output Clock
86
Transmit PLL Configurator
87
Figure 60 Transceiver Transmit PLL Selection from Catalog
87
Figure 61 Transmit PLL Configurator GUI
88
Table 27 Transmit PLL Configurator GUI Options
88
Figure 62 Clock Inputs
89
Figure 63 Fabric Clock Input
89
Figure 64 Clock Options
90
Figure 65 Spread Spectrum Clock Generation Enable
90
Figure 66 Spread Spectrum Modulation Options
90
Figure 67 Enable Dynamic Reconfiguration Interface
91
Table 28 Spread Spectrum
91
Transceiver Interface Configurator
92
Figure 68 CLK_125 GUI
92
Figure 69 Transceiver Interface Selection from Catalog
92
Figure 70 Transceiver Interface Configuration GUI
93
Table 29 Transceiver Interface General Settings
93
Table 30 Transceiver Interface PMA Settings
93
Table 31 Transceiver Interface PCS Settings
95
Table 32 Clocks and Resets
95
Figure 71 PMA Mode-Enable CDR Bit-Slip Port
96
Figure 72 XCVR Component with CDR Bit-Slip Port Enabled
96
Figure 73 XCVR Component with BMR Port Enabled
96
Figure 74 XCVR Component with DRI Port Enabled
97
Figure 75 Transceiver with ERM Example Smartdesign Component
97
Figure 76 PMA Only PCS Example Smartdesign Component
98
Figure 77 8B10B PCS Example Smartdesign Component
98
Figure 78 64B66B PCS Example Smartdesign Component
98
Figure 79 Soft PIPE PCS Example Smartdesign Component
99
Figure 80 Completed Transceiver Subsystem
99
Transceiver Modes
100
Figure 81 Completed Transceiver Subsystem with ERM
100
Figure 82 Transceiver Modes Shown in Transceiver GUI
100
Full-Duplex Mode
101
Half-Duplex Mode
101
Table 33 PCS Modes Supported
101
Libero Generated Files
102
Design Constraints
102
Timing Constraints
102
Figure 83 Derive Constraints Using Constraints Editor
103
Physical Constraints
104
Table 34 Physical Constraint Instances for XCVR
104
Adding Physical Constraints Using Libero
105
Invoking the Pin Planner
106
Figure 84 IO Editor GUI
106
Figure 85 XCVR Placement Tab
107
Figure 86 XCVR Signal Integrity Tab
107
Transceiver Initialization
108
Transceiver Initialization Data
108
Signal Integrity Conditioning
109
Figure 87 Signal Integrity Conditioning Flow
109
Transmitter
110
Transmit Emphasis and DC Amplitude
110
Impedance (Differential)
110
Tx Insertion Loss
110
Transmit Common Mode Level
110
Table 35 Amplitude and Emphasis
110
Receiver
111
Rx Insertion Loss
111
Rx CTLE
111
Rx Termination
111
AC/DC Coupled Connection
111
Loss-Of-Signal Detector
112
Polarity Invert
112
IO Editor for Signal Integrity
112
Table 36 LOS Range
112
IO Editor-Signal Integrity
113
PDC Constraint File Commands for XCVR Signal Integrity
113
Figure 88 IO Editor-XCVR View
113
Figure 89 IO Editor-Signal Integrity View
113
Table 37 TX Attributes and Values
114
Table 38 RX Attributes and Values
115
Smartdebug Signal Integrity
117
Figure 90 Smartdebug Signal Integrity GUI Panel
117
Loopback Modes
118
Smartbert
118
Figure 91 Loopback Modes-Far-End Example
118
Eye Monitoring
119
Figure 92 PRBS Self Test Near-End Loopback Example
119
Figure 93 Test Status Indicators
119
Figure 94 Eye Monitor Plot
120
Figure 95 Example of Optimize DFE
121
Simulation
122
RTL Simulation Mode
122
Figure 96 RTL Simulation Block Diagram
122
Debug and Testing
123
PRBS Generator/Checker
123
Loopback
123
EQ Far-End Loopback
123
EQ Near-End Loopback
123
CDR Far-End Loopback
123
Figure 97 Transceiver Loopbacks
124
Dynamic Reconfiguration Interface
125
Figure 98 PF_DRI Example
125
Board Design Recommendations
126
Transceiver Top-Level Pin out
126
Table 39 Transceiver Device Level Pin List
126
Design for Protocols
128
PCI Express
128
Figure 99 Connectivity between XCVR Interface and Pcie Edge Connector
128
Jesd204B
129
Interface
129
Figure 100 Connectivity between RT Polarfire Device and JESD204B Interface
129
Figure 101 Connectivity between RT Polarfire Device to SFP+ Interface
129
Unused Transceiver Pins
130
Transceivers Insertion Loss
130
Table 40 Transceivers Insertion Loss
130

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Microchip Technology Microsemi UG0936 User Manual (130 pages)

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