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KSZ8862-32MQL
Micrel KSZ8862-32MQL Manuals
Manuals and User Guides for Micrel KSZ8862-32MQL. We have
1
Micrel KSZ8862-32MQL manual available for free PDF download: Manual
Micrel KSZ8862-32MQL Manual (125 pages)
2-Port Ethernet Switch with Non-PCI Interface and Fiber Support
Brand:
Micrel
| Category:
Switch
| Size: 0 MB
Table of Contents
General Description
1
Functional Diagram
1
Figure 1. KSZ8862M Functional Diagram
1
Features
2
Applications
2
Markets
2
Ordering Information
3
Revision History
3
Table of Contents
4
Content
4
List of Figures
9
List of Tables
10
Pin Configuration for KSZ8862-16MQL (8/16-Bit)
11
Figure 2. Standard - KSZ8862-16 MQL 128-Pin PQFP (Top View)
11
Pin Description for KSZ8862-16MQL (8/16-Bit)
12
Pin Configuration for KSZ8862-32MQL (32-Bit)
17
Figure 3. Standard - KSZ8862-32 MQL 128-Pin PQFP (Top View)
17
Pin Description for KSZ8862-32 MQL (32-Bit)
18
Functional Description
23
Functional Overview: Physical Layer Transceiver
23
100BASE-TX Transmit
23
100BASE-TX Receive
23
Scrambler/De-Scrambler (100BASE-TX Only)
23
100BASE-FX Operation
23
100BASE-FX Signal Detection
23
100BASE-FX Far-End-Fault (FEF)
24
100BASE-SX Operation
24
Physical Interface
24
Enabling 100BASE-SX Mode
24
Enabling Fiber Forced Mode
24
10BASE-FL Operation
24
Enabling 10BASE-FL Mode
24
10BASE-T Transmit
25
10BASE-T Receive
25
LED Driver
25
Post Amplifier
25
Power Management
25
MDI/MDI-X Auto Crossover
25
Table 1. MDI/MDI-X Pin Definitions
25
Crossover Cable
26
Figure 4. Typical Straight Cable Connection
26
Figure 5. Typical Crossover Cable Connection
26
Straight Cable
26
Auto Negotiation
27
Figure 6. Auto Negotiation and Parallel Operation
27
Linkmd ® Cable Diagnostics
28
Access
28
Usage
28
Functional Overview: MAC and Switch
29
Address Lookup
29
Learning
29
Migration
29
Aging
29
Forwarding
30
Figure 7. Destination Address Lookup Flow Chart in Stage One
30
Figure 8. Destination Address Resolution Flow Chart in Stage Two
31
Switching Engine
32
MAC Operation
32
Inter Packet Gap (IPG)
32
Back-Off Algorithm
32
Late Collision
32
Legal Packet Size
32
Flow Control
32
Half-Duplex Backpressure
32
Broadcast Storm Protection
33
Clock Generator
33
Bus Interface Unit (BIU)
33
Asynchronous Interface
35
Table 2. Bus Interface Unit Signal Grouping
35
Synchronous Interface
36
Summary
36
Figure 9. Mapping from ISA-Like, EISA-Like, and Vlbus-Like Transactions to the KSZ8862M Bus
36
BIU Implementation Principles
37
Figure 10. KSZ8862M 8-Bit, 16-Bit, and 32-Bit Data Bus Connections
37
Queue Management Unit (QMU)
38
Transmit Queue (TXQ) Frame Format
38
Table 3. Transmit Queue Frame Format
38
Table 4. Transmit Control Word Bit Fields
38
Receive Queue (RXQ) Frame Format
39
Table 5. Transmit Byte Count Format
39
Table 6. Receive Queue Frame Format
39
Table 7. FRXQ Packet Receive Status
40
Table 8. FRXQ RX Byte Count Field
40
Advanced Switch Functions
41
Spanning Tree Support
41
Table 9. Spanning Tree States
41
IGMP Support
42
IGMP" Snooping
42
Multicast Address Insertion" in the Static MAC Table
42
Ipv6 MLD Snooping
42
Port Mirroring Support
42
IEEE 802.1Q VLAN Support
43
Qos Priority Support
43
Port-Based Priority
43
802.1P-Based Priority
43
Table 10. FID+DA Lookup in VLAN Mode
43
Table 11. FID+SA Lookup in VLAN Mode
43
Diffserv-Based Priority
44
Rate Limiting Support
44
Figure 11. 802.1P Priority Field Format
44
MAC Filtering Function
45
Configuration Interface
45
EEPROM Interface
45
Table 12. EEPROM Format
45
Loopback Support
46
Far-End Loopback
46
Near-End (Remote) Loopback
46
Table 13. Configparam Word in EEPROM Format
46
Figure 12. Port 2 Far-End Loopback Path
47
Figure 13. Port 1 and Port 2 Near-End (Remote) Loopback Path
47
CPU Interface I/O Registers
48
I/O Registers
48
Internal I/O Space Mapping
49
Register Map: Switch and MAC/PHY
57
Bit Type Definition
57
Bank 0-63 Bank Select Register (0X0E): BSR (same Location in All Banks)
57
Bank 0 Base Address Register (0X00): BAR
57
Bank 0 QMU RX Flow Control High Watermark Configuration Register (0X04): QRFCR
57
Bank 0 Bus Error Status Register (0X06): BESR
58
Bank 0 Bus Burst Length Register (0X08): BBLR
58
Bank 1 Reserved
58
Bank 2 Host MAC Address Register Low (0X00): MARL
58
Bank 2 Host MAC Address Register Middle (0X02): MARM
59
Bank 2 Host MAC Address Register High (0X04): MARH
59
Bank 3 On-Chip Bus Control Register (0X00): OBCR
59
Bank 3 EEPROM Control Register (0X02): EEPCR
60
Bank 3 Memory bist INFO Register (0X04): MBIR
60
Bank 3 Global Reset Register (0X06): GRR
60
Bank 3 Bus Configuration Register (0X08): BCFG
61
Banks 4 - 15: Reserved
61
Bank 16 Transmit Control Register (0X00): TXCR
61
Bank 16 Transmit Status Register (0X02): TXSR
61
Bank 16 Receive Control Register (0X04): RXCR
62
Bank 16 TXQ Memory Information Register (0X08): TXMIR
62
Bank 16 RXQ Memory Information Register (0X0A): RXMIR
63
Bank 17 TXQ Command Register (0X00): TXQCR
63
Bank 17 RXQ Command Register (0X02): RXQCR
63
Bank 17 TX Frame Data Pointer Register (0X04): TXFDPR
63
Bank 17 RX Frame Data Pointer Register (0X06): RXFDPR
64
Bank 17 QMU Data Register Low (0X08): QDRL
64
Bank 17 QMU Data Register High (0X0A): QDRH
64
Bank 18 Interrupt Enable Register (0X00): IER
65
Bank 18 Interrupt Status Register (0X02): ISR
66
Bank 18 Receive Status Register (0X04): RXSR
67
Bank 18 Receive Byte Counter Register (0X06): RXBC
67
Bank 19 Multicast Table Register 0 (0X00): MTR0
68
Bank 19 Multicast Table Register 1 (0X02): MTR1
68
Bank 19 Multicast Table Register 2 (0X04): MTR2
68
Bank 19 Multicast Table Register 3 (0X06): MTR3
68
Banks 20 - 31: Reserved
68
Bank 32 Switch ID and Enable Register (0X00): SIDER
69
Bank 32 Switch Global Control Register 1 (0X02): SGCR1
69
Bank 32 Switch Global Control Register 2 (0X04): SGCR2
70
Bank 32 Switch Global Control Register 3 (0X06): SGCR3
71
Bank 32 Switch Global Control Register 4 (0X08): SGCR4
71
Bank 32 Switch Global Control Register 5 (0X0A): SGCR5
72
Bank 33 Switch Global Control Register 6 (0X00): SGCR6
73
Bank 33 Switch Global Control Register 7 (0X02): SGCR7
73
Banks 34 - 38: Reserved
73
Bank 39 MAC Address Register 1 (0X00): MACAR1
74
Bank 39 MAC Address Register 2 (0X02): MACAR2
74
Bank 39 MAC Address Register 3 (0X04): MACAR3
74
Bank 40 TOS Priority Control Register 1 (0X00): TOSR1
74
Bank 40 TOS Priority Control Register 2 (0X02): TOSR2
75
Bank 40 TOS Priority Control Register 3 (0X04): TOSR3
75
Bank 40 TOS Priority Control Register 4 (0X06): TOSR4
76
Bank 40 TOS Priority Control Register 5 (0X08): TOSR5
76
Bank 40 TOS Priority Control Register 6 (0X0A): TOSR6
77
Bank 41 TOS Priority Control Register 7 (0X00): TOSR7
77
Bank 41 TOS Priority Control Register 8 (0X02): TOSR8
78
Bank 42 Indirect Access Control Register (0X00): IACR
78
Bank 42 Indirect Access Data Register 1 (0X02): IADR1
79
Bank 42 Indirect Access Data Register 2 (0X04): IADR2
79
Bank 42 Indirect Access Data Register 3 (0X06): IADR3
79
Bank 42 Indirect Access Data Register 4 (0X08): IADR4
79
Bank 42 Indirect Access Data Register 5 (0X0A): IADR5
79
Bank 43: Reserved
79
Bank 44 Digital Testing Status Register (0X00): DTSR
80
Bank 44 Analog Testing Status Register (0X02): ATSR
80
Bank 44 Digital Testing Control Register (0X04): DTCR
80
Bank 44 Analog Testing Control Register 0 (0X06): ATCR0
80
Bank 44 Analog Testing Control Register 1 (0X08): ATCR1
80
Bank 44 Analog Testing Control Register 2 (0X0A): ATCR2
80
Bank 45 PHY 1 MII-Register Basic Control Register (0X00): P1MBCR
80
Bank 45 PHY 1 MII-Register Basic Status Register (0X02): P1MBSR
82
Bank 45 PHY 1 PHYID Low Register (0X04): PHY1ILR
82
Bank 45 PHY 1 PHYID High Register (0X06): PHY1IHR
82
Bank 45 PHY 1 Auto-Negotiation Advertisement Register (0X08): P1ANAR
83
Bank 45 PHY 1 Auto-Negotiation Link Partner Ability Register (0X0A): P1ANLPR
83
Bank 46 PHY 2 MII-Register Basic Control Register (0X00): P2MBCR
84
Bank 46 PHY 2 MII-Register Basic Status Register (0X02): P2MBSR
85
Bank 46 PHY 2 PHYID Low Register (0X04): PHY2ILR
85
Bank 46 PHY 2 PHYID High Register (0X06): PHY2IHR
85
Bank 46 PHY 2 Auto-Negotiation Advertisement Register (0X08): P2ANAR
86
Bank 46 PHY 2 Auto-Negotiation Link Partner Ability Register (0X0A): P2ANLPR
86
Bank 47 PHY1 Special Control/Status Register (0X02): P1PHYCTRL
87
Bank 47 PHY2 Linkmd ® Control/Status (0X04): P2VCT
87
Bank 47 PHY2 Special Control/Status Register (0X06): P2PHYCTRL
88
Bank 48 Port 1 Control Register 1 (0X00): P1CR1
88
Bank 48 Port 1 Control Register 2 (0X02): P1CR2
89
Bank 48 Port 1 VID Control Register (0X04): P1VIDCR
90
Bank 48 Port 1 Control Register 3 (0X06): P1CR3
90
Bank 48 Port 1 Ingress Rate Control Register (0X08): P1IRCR
91
Bank 48 Port 1 Egress Rate Control Register (0X0A): P1ERCR
93
Bank 49 Port 1 PHY Special Control/Status, Linkmd
95
(0X00): P1SCSLMD
95
Bank 49 Port 1 Control Register 4 (0X02): P1CR4
95
Bank 49 Port 1 Status Register (0X04): P1SR
96
Bank 50 Port 2 Control Register 1 (0X00): P2CR1
97
Bank 50 Port 2 Control Register 2 (0X02): P2CR2
97
Bank 50 Port 2 VID Control Register (0X04): P2VIDCR
97
Bank 50 Port 2 Control Register 3 (0X06): P2CR3
97
Bank 50 Port 2 Ingress Rate Control Register (0X08): P2IRCR
97
Bank 50 Port 2 Egress Rate Control Register (0X0A): P2ERCR
97
Bank 51 Port 2 PHY Special Control/Status, Linkmd
98
(0X00): P2SCSLMD
98
Bank 51 Port 2 Control Register 4 (0X02): P2CR4
99
Bank 51 Port 2 Status Register (0X04): P2SR
100
Bank 52 Host Port Control Register 1 (0X00): P3CR1
101
Bank 52 Host Port Control Register 2 (0X02): P3CR2
101
Bank 52 Host Port VID Control Register (0X04): P3VIDCR
102
Bank 52 Host Port Control Register 3 (0X06): P3CR3
102
Bank 52 Host Port Ingress Rate Control Register (0X08): P3IRCR
102
Bank 52 Host Port Egress Rate Control Register (0X0A): P3ERCR
102
Banks 53 - 63: Reserved
102
MIB (Management Information Base) Counters
103
Table 14. Format of Per Port MIB Counters
103
Format of "All Ports Dropped Packet" MIB Counters
104
Table 15. Port 1 MIB Counters Indirect Memory Offset
104
Table 16. "All Ports Dropped Packet" MIB Counters Format
104
Table 17. "All Ports Dropped Packet" MIB Counters Indirect Memory Offsets
104
Additional MIB Information
105
Static MAC Address Table
106
Static MAC Table Lookup Examples
106
Table 18. Static MAC Table Format (8 Entries)
106
Dynamic MAC Address Table
107
Dynamic MAC Address Lookup Example
107
Table 19. Dynamic MAC Address Table Format (1024 Entries)
107
VLAN Table
108
VLAN Table Lookup Examples
108
Table 20. VLAN Table Format (16 Entries)
108
Absolute Maximum Ratings
109
Operating Ratings
109
Table 21. Maximum Ratings
109
Table 22. Operating Ratings
109
Electrical Characteristics
110
Table 23. Electrical Characteristics
110
Timing Specifications
111
Asynchronous Timing Without Using Address Strobe (ADSN = 0)
111
Figure 14. Asynchronous Cycle - ADSN = 0
111
Table 24. Asynchronous Cycle (ADSN = 0) Timing Parameters
111
Asynchronous Timing Using Address Strobe (ADSN)
112
Figure 15. Asynchronous Cycle - Using ADSN
112
Table 25. Asynchronous Cycle Using ADSN Timing Parameters
112
Asynchronous Timing Using DATACSN
113
Figure 16. Asynchronous Cycle - Using DATACSN
113
Table 26. Asynchronous Cycle Using DATACSN Timing Parameters
113
Address Latching Timing for All Modes
114
Figure 17. Address Latching Cycle for All Modes
114
Table 27. Address Latching Timing Parameters
114
Synchronous Timing in Burst Write (VLBUSN = 1)
115
Figure 18. Synchronous Burst Write Cycles - VLBUSN = 1
115
Table 28. Synchronous Burst Write Timing Parameters
115
Synchronous Timing in Burst Read (VLBUSN = 1)
116
Figure 19. Synchronous Burst Read Cycles - VLBUSN = 1
116
Table 29. Synchronous Burst Read Timing Parameters
116
Synchronous Write Timing (VLBUSN = 0)
117
Figure 20. Synchronous Write Cycle - VLBUSN = 0
117
Table 30. Synchronous Write (VLBUSN = 0) Timing Parameters
117
Synchronous Read Timing (VLBUSN = 0)
118
Figure 21. Synchronous Read Cycle - VLBUSN = 0
118
Table 31. Synchronous Read (VLBUSN = 0) Timing Parameters
118
EEPROM Timing
119
Figure 22. EEPROM Read Cycle Timing Diagram
119
Table 32. EEPROM Timing Parameters
119
Auto Negotiation Timing
120
Figure 23. Auto-Negotiation Timing
120
Table 33. Auto Negotiation Timing Parameters
120
Reset Timing
121
Figure 24. Reset Timing
121
Table 34. Reset Timing Parameters
121
Selection of Isolation Transformers
122
Selection of Reference Crystal
122
Table 35. Transformer Selection Criteria
122
Table 36. Qualified Single Port Magnetic
122
Table 37. Typical Reference Crystal Characteristics
122
Package Information
123
Figure 25. 128-Pin PQFP Package
123
Acronyms and Glossary
124
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