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Micrel KSZ8862-16MQL Manual

2-port ethernet switch with non-pci interface and fiber support
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General Description

The KSZ8862M is 2-port switch with non-PCI CPU
interface and fiber support, and is available in 8/16-bit
and 32-bit bus designs (see Ordering Information). This
datasheet describes the KSZ8862M non-PCI CPU
interface chip.
The KSZ8862M is the industry's first fully managed, 2-
port switch with a non-PCI CPU interface and fiber
support. It is based on a proven, 4
integrated Layer-2 switch, compliant with IEEE 802.3u
standards.
For industrial applications, the KSZ8862M can run in
half-duplex mode regardless of the application.
In fiber mode, port 1 can be configurable to either
100BASE-FX or 100BASE-SX/10BASE-FL.
The LED driver and post amplifier are also included for
10Base-FL and 100Base-SX applications.

Functional Diagram

8 , 1 6 , o r 3 2 - b i t
G e n e r i c H o s t
P 1 L E D [ 3 : 0 ]
P 2 L E D [ 3 : 0 ]
E E P R O M I / F
LinkMD is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
August 2010
th
generation,
T X
L E D
D r i v e r
P o r t 1
F i b e r
P o s t
A m p
R X
1 0 / 1 0 0 B a s e -
P o r t 2
T / T X
C o p p e r
P H Y 2
N o n - P C I
C P U
B u s
I n t e r f a c e
U n i t
I n t e r f a c e
L E D
D r i v e r s

Figure 1. KSZ8862M Functional Diagram

2-Port Ethernet Switch with Non-PCI Interface
In copper mode, port 2 supports 10/100BASE-T/TX with
HP Auto MDI/MDI-X for reliable detection of and
correction for straight-through and crossover cables.
Micrel's
Reflectometry (TDR)-based function is also available for
determining the cable length, as well as cable
diagnostics for identifying faulty cabling.
The KSZ8862M offers an extensive feature set that
includes tag/port-based VLAN, quality of service (QoS)
priority management, management information base
(MIB) counters, and CPU control/data interfaces to
effectively address Fast Ethernet applications.
The KSZ8862M contains: Two 10/100 transceivers with
patented, mixed-signal, low-power technology, two
media access control (MAC) units, a direct memory
access (DMA) channel, a high-speed, non-blocking,
switch fabric, a dedicated 1K entry forwarding table, and
an on-chip frame buffer memory.
1 0 / 1 0 0 B a s e -
1 0 / 1 0 0
F L / F X / S X
M A C 1
P H Y 1
1 0 / 1 0 0
M A C 2
R X Q
Q M U
S w i t c h
4 K B
D M A
H o s t
C h a n n e l
T X Q
M A C
4 K B
C o n t r o l
R e g i s t e r s
KSZ8862-16/32MQL
and Fiber Support
Rev 3.1
proprietary
LinkMD
1 K l o o k - u p
E n g i n e
S c h e d u l i n g
M a n a g e m e n t
B u f f e r
M a n a g e m e n t
F r a m e
B u f f e r s
M I B
C o u n t e r s
E E P R O M
I n t e r f a c e
®
LinkMD
®
Time
Domain
M9999-081310-3.1

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Summary of Contents for Micrel KSZ8862-16MQL

  • Page 1: General Description

    Figure 1. KSZ8862M Functional Diagram LinkMD is a registered trademark of Micrel, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com August 2010...

  • Page 2: Features

    • 2-port switch with a flexible 8, 16, or 32-bit generic • IEEE 802.1d spanning tree protocol support host processor interfaces • MAC filtering function to filter or forward unknown • Micrel LinkMD ® cable diagnostics to determine cable unicast packets length, diagnose faulty cables, and determine •...

  • Page 3: Ordering Information

    KSZ8862-32MQL C to 70 128-Pin PQFP Port 1 operates on 10BASE-FL or 100BASE-SX mode only KSZ8862-100FX-EVAL Evaluation Board for the KSZ8862-16MQL at 100FX Mode KSZ8862-10FL-EVAL Evaluation Board for the KSZ8862-16MQL at 100SX_10FL Mode Revision History Revision Date Summary of Changes...

  • Page 4: Table Of Contents

    Ordering Information ..............................3 Revision History ................................3 Content.....................................4 List of Figures..................................9 List of Tables .................................10 Pin Configuration for KSZ8862-16MQL (8/16-Bit) ......................11 Pin Description for KSZ8862-16MQL (8/16-Bit) ......................12 Pin Configuration for KSZ8862-32MQL (32-Bit) ......................17 Pin Description for KSZ8862-32 MQL (32-Bit) ......................18 Functional Description ..............................23 Functional Overview: Physical Layer Transceiver ....................23...
  • Page 5 Micrel, Inc. KSZ8862-16/32MQL Inter Packet Gap (IPG) ................................32 Back-Off Algorithm................................... 32 Late Collision ................................... 32 Legal Packet Size ..................................32 Flow Control..................................... 32 Half-Duplex Backpressure ............................... 32 Broadcast Storm Protection ..............................33 Clock Generator..................................33 Bus Interface Unit (BIU)..............................33 Asynchronous Interface ................................
  • Page 6 Micrel, Inc. KSZ8862-16/32MQL Bank 3 Global Reset Register (0x06): GRR..........................60 Bank 3 Bus Configuration Register (0x08): BCFG ........................61 Banks 4 – 15: Reserved................................61 Bank 16 Transmit Control Register (0x00): TXCR ........................61 Bank 16 Transmit Status Register (0x02): TXSR........................61 Bank 16 Receive Control Register (0x04): RXCR........................
  • Page 7 Micrel, Inc. KSZ8862-16/32MQL Bank 44 Digital Testing Control Register (0x04): DTCR ......................80 Bank 44 Analog Testing Control Register 0 (0x06): ATCR0 ....................80 Bank 44 Analog Testing Control Register 1 (0x08): ATCR1 ....................80 Bank 44 Analog Testing Control Register 2 (0x0A): ATCR2 ....................80 Bank 45 PHY 1 MII-Register Basic Control Register (0x00): P1MBCR ...................
  • Page 8 Micrel, Inc. KSZ8862-16/32MQL VLAN Table ..................................108 VLAN Table Lookup Examples: ............................. 108 Absolute Maximum Ratings ............................109 Operating Ratings ..............................109 Electrical Characteristics ............................110 Timing Specifications ..............................111 Asynchronous Timing without using Address Strobe (ADSN = 0)..................111 Asynchronous Timing Using Address Strobe (ADSN) ......................112 Asynchronous Timing Using DATACSN ..........................

  • Page 9: List Of Figures

    Micrel, Inc. KSZ8862-16/32MQL List of Figures Figure 1. KSZ8862M Functional Diagram ............................ 1 Figure 2. Standard – KSZ8862-16 MQL 128-Pin PQFP (Top View) ..................11 Figure 3. Standard – KSZ8862-32 MQL 128-Pin PQFP (Top View) ..................17 Figure 4. Typical Straight Cable Connection ..........................

  • Page 10: List Of Tables

    Micrel, Inc. KSZ8862-16/32MQL List of Tables Table 1. MDI/MDI-X Pin Definitions..............................25 Table 2. Bus Interface Unit Signal Grouping ............................ 35 Table 3. Transmit Queue Frame Format ............................38 Table 4. Transmit Control Word Bit Fields............................38 Table 5. Transmit Byte Count Format .............................. 39 Table 6.

  • Page 11: Pin Configuration For Ksz8862-16Mql (8/16-Bit)

    Micrel, Inc. KSZ8862-16/32MQL Pin Configuration for KSZ8862-16MQL (8/16-Bit) Figure 2. 128-Pin PQFP (Top View) August 2010 M9999-081310-3.1...

  • Page 12: Pin Description For Ksz8862-16Mql (8/16-Bit)

    Micrel, Inc. KSZ8862-16/32MQL Pin Description for KSZ8862-16MQL (8/16-Bit) Pin Name Type Pin Function Number TEST_EN Test Enable For normal operation, 1K ohm pull-down this pin to ground. SCAN_EN Scan Test Scan MUX Enable For normal operation, 1K ohm pull-down this pin to ground.
  • Page 13 Micrel, Inc. KSZ8862-16/32MQL Pin Name Type Pin Function Number INTRN Interrupt Active Low signal to host CPU to indicate an interrupt status bit is set, this pin need an external 4.7K pull-up resistor. LDEVN Local Device Not Active Low output signal, asserted when AEN is Low and A15-A4 decode to the KSZ8862M address programmed into the high byte of the base address register.
  • Page 14 Micrel, Inc. KSZ8862-16/32MQL Pin Name Type Pin Function Number Write Strobe Not Asynchronous write strobe, active Low. DGND Digital IO ground ADSN Address Strobe Not For systems that require address latching, the rising edge of ADSN indicates the latching moment of A15-A1 and AEN.
  • Page 15 Micrel, Inc. KSZ8862-16/32MQL Pin Name Type Pin Function Number 25MHz crystal or oscillator clock connection. Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V tolerant oscillator and X2 is a no connect.
  • Page 16 Micrel, Inc. KSZ8862-16/32MQL Pin Name Type Pin Function Number No Connect No Connect No Connect DGND Digital IO ground VDDIO 3.3V digital V input power supply for IO with well decoupling capacitors. DDIO No Connect Data 15 Data 14 Data 13...

  • Page 17: Pin Configuration For Ksz8862-32Mql (32-Bit)

    Micrel, Inc. KSZ8862-16/32MQL Pin Configuration for KSZ8862-32MQL (32-Bit) Figure 3. 128-Pin PQFP (Top View) August 2010 M9999-081310-3.1...

  • Page 18: Pin Description For Ksz8862-32 Mql (32-Bit)

    Micrel, Inc. KSZ8862-16/32MQL Pin Description for KSZ8862-32 MQL (32-Bit) Pin Name Type Pin Function Number TEST_EN Test Enable For normal operation, 1K ohm pull-down this pin-to-ground. SCAN_EN Scan Test Scan Mux Enable For normal operation, 1K ohm pull-down this pin-to-ground.
  • Page 19 Micrel, Inc. KSZ8862-16/32MQL Pin Name Type Pin Function Number Interrupt INTRN Active Low signal to host CPU to indicate an interrupt status bit is set, this pin need an external 4.7K pull-up resistor. Local Device Not LDEVN Active Low output signal, asserted when AEN is Low and A15-A4 decode to the KSZ8862M address programmed into the high byte of the base address register.
  • Page 20 Micrel, Inc. KSZ8862-16/32MQL Pin Name Type Pin Function Number DGND Digital IO ground ADSN Address Strobe Not For systems that require address latching, the rising edge of ADSN indicates the latching moment of A15-A1 and AEN. PWRDN Full-chip power-down. Low = Power down; High or floating = Normal operation.
  • Page 21 Micrel, Inc. KSZ8862-16/32MQL Pin Name Type Pin Function Number Address 15 Address 14 Address 13 Address 12 Address 11 Address 10 Address 9 Address 8 Address 7 Address 6 DGND Digital IO ground VDDIO 3.3V digital V input power supply for IO with well decoupling capacitors.
  • Page 22 Micrel, Inc. KSZ8862-16/32MQL Pin Name Type Pin Function Number Data 16 Data 15 Data 14 Data 13 Data 12 Data 11 Data 10 Data 9 Data 8 Data 7 Data 6 Data 5 Data 4 Data 3 DGND Digital IO ground...

  • Page 23: Functional Description

    Micrel, Inc. KSZ8862-16/32MQL Functional Description The KSZ8862M contains two 10/100 physical layer transceivers (PHYs), two MAC units, and a DMA channel integrated with a Layer-2 switch. The KSZ8862M contains a bus interface unit (BIU), which controls the KSZ8862M via an 8, 16, or 32-bit host interface.

  • Page 24: 100Base-Fx Far-End-Fault (Fef)

    300m. The interface connections between the KSZ8862M and fiber module are single-ended (common mode). 100BASE-SX signal transmission and reception are done on TXM1 (pin 49) and RXM1 (pin 46), respectively. Refer to Micrel reference schematic for recommended interface circuit and termination. Enabling 100BASE-SX Mode To enable 100BASE-SX mode, tie FXSD1 (pin 44) to high (+3.3V) and 100FX/10FL (pin 41)-to-ground.

  • Page 25: 10Base-T Transmit

    Micrel, Inc. KSZ8862-16/32MQL Forced mode and auto-negotiation disabled mode settings for 10BASE-FL fiber use the same registers (P1MBCR, P1CR4). These registers are summarized in the Register Map section. 10BASE-T Transmit The 10BASE-T driver (port 2 only) is incorporated with the 100BASE-TX driver to allow for transmission using the same magnetic.

  • Page 26: Straight Cable

    Micrel, Inc. KSZ8862-16/32MQL Straight Cable A straight cable connects an MDI device to an MDI-X device or an MDI-X device to an MDI device. The following diagram shows a typical straight cable connection between a network interface card (NIC) (MDI) and a switch, or hub (MDI-X).

  • Page 27: Auto Negotiation

    Micrel, Inc. KSZ8862-16/32MQL Auto Negotiation The KSZ8862M conforms to the auto negotiation protocol as described by the 802.3 committee to allow the channel to operate at 10Base-T or 100Base-TX on port 2 only. Auto negotiation allows unshielded twisted pair (UTP) link partners to select the best common mode of operation. In auto negotiation, the link partners advertise capabilities across the link to each other.

  • Page 28: Linkmd ® Cable Diagnostics

    Micrel, Inc. KSZ8862-16/32MQL ® LinkMD Cable Diagnostics ® The KSZ8862M LinkMD uses Time Domain Reflectometry (TDR) to analyze the port 2 cabling plant for common cabling problems such as open circuits, short circuits, and impedance mismatches. ® LinkMD works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs and then analyzes the shape of the reflected signal.

  • Page 29: Functional Overview: Mac And Switch

    Micrel, Inc. KSZ8862-16/32MQL Functional Overview: MAC and Switch Address Lookup The internal lookup table stores MAC addresses and their associated information. It contains a 1K entry unicast address learning table plus switching information. The KSZ8862M is guaranteed to learn 1K addresses and distinguishes itself from hash-based look-up tables, which depending upon the operating environment and probabilities, may not guarantee the absolute number of addresses it can learn.

  • Page 30: Forwarding

    Micrel, Inc. KSZ8862-16/32MQL Forwarding The KSZ8862M forwards packets using the algorithm that is depicted in the following flowcharts. Figure 7 shows stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table for the destination address, and comes up with “port to forward 1”...

  • Page 31: Figure 8. Destination Address Resolution Flow Chart In Stage Two

    Micrel, Inc. KSZ8862-16/32MQL PTF1 - Check receiving port's receive enable bit - Check destination port's transmit enable bit Spanning Tree - Check whether packets are special (BPDU) Process or specified - Applied to MAC #1 and MAC #2 IGMP Process...

  • Page 32: Switching Engine

    Micrel, Inc. KSZ8862-16/32MQL Switching Engine The KSZ8862M features a high-performance switching engine to move data to and from the MAC’s packet buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency. The switching engine has a 32KB internal frame buffer. This resource is shared between all the ports. There are a total of 256 buffers available.

  • Page 33: Broadcast Storm Protection

    For example, for a 32-bit system/host data bus, it allows 8, 16, and 32-bit data transfers (KSZ8862- 32MQL); for a 16-bit system/host data bus, it allows 8 and 16-bit data transfers (KSZ8862-16MQL); and for 8-bit system/host data bus, it only allows 8-bit data transfers (KSZ8862-16MQL).
  • Page 34 Micrel, Inc. KSZ8862-16/32MQL Table 2 describes the BIU signal grouping. Signal Type Function Common Signals A[15:1] Address Address Enable Address Enable asserted indicates memory address on the bus for DMA access and since the device is an I/O device, address decoding is only enabled when AEN is low.

  • Page 35: Asynchronous Interface

    Micrel, Inc. KSZ8862-16/32MQL Signal Type Function Synchronous Ready SRDYN For VLBus-like access: exactly the same signal definition of nSRDY in VLBus. For burst access: insert wait state by the KSZ8862M whenever necessary during the Data Register access. Ready Return RDYRTNN For VLBus-like access: exactly like RDYRTNN signal in VLBus to end the cycle.

  • Page 36: Synchronous Interface

    Micrel, Inc. KSZ8862-16/32MQL wait state, the BIU will assert ARDY to prolong the cycle. Synchronous Interface For synchronous transfers, the synchronous dedicated signals CYCLEN, SWR, and RDYRTNN will toggle but the asynchronous dedicated signals RDN and WRN are de-asserted and stay at the same logic level throughout the entire synchronous transfer.

  • Page 37: Biu Implementation Principles

    Micrel, Inc. KSZ8862-16/32MQL KSZ8862-16 KSZ8862-16 KSZ8862-32 HA[1] HA[1] A[1] A[1] A[1] HA[15:2] A[15:2] HA[15:2] A[15:2] HA[15:2] A[15:2] D[7:0] HD[7:0] HD[7:0] D[7:0] HD[7:0] D[7:0] D[15:8] HD[15:8] HD[15:8] D[15:8] D[15:8] D[23:16] HD[23:16] D[31:24] HD[31:24] HA[0] BE0N HA[0] BE0N BE0N nHBE[0] BE1N BE1N...

  • Page 38: Queue Management Unit (Qmu)

    Micrel, Inc. KSZ8862-16/32MQL Queue Management Unit (QMU) The Queue Management Unit (QMU) manages packet traffic between the MAC/PHY interface and the system host. It has built-in packet memory for receive and transmit functions called TXQ (Transmit Queue) and RXQ (Receive Queue). Each queue contains 4KB of memory for back-to-back, non-blocking frame transfer performance.

  • Page 39: Receive Queue (Rxq) Frame Format

    Micrel, Inc. KSZ8862-16/32MQL The transmit Byte Count specifies the total number of bytes to be transmitted from the TXQ. Its format is given in Table 5. Description 15-11 Reserved TXBC Transmit Byte Count 10-0 Transmit Byte Count. Hardware uses the byte count information to conserve the TX buffer memory for better utilization of the packet memory.

  • Page 40: Table 7. Frxq Packet Receive Status

    Micrel, Inc. KSZ8862-16/32MQL For receive, the packet receive status always reflects the receive status of the packet received in the current RX packet memory (see Table 7). The RXSR register indicates the status of the current received frame. Description RXFV Receive Frame Valid When bit is set, indicates that the present frame in the receive packet memory is valid and received from MAC/PHY.

  • Page 41: Advanced Switch Functions

    Micrel, Inc. KSZ8862-16/32MQL Advanced Switch Functions Spanning Tree Support To support spanning tree, the host port is the designated port for the processor. The other ports can be configured in one of the five spanning tree states via “transmit enable”, “receive enable” and “learning disable”...

  • Page 42: Igmp Support

    Micrel, Inc. KSZ8862-16/32MQL IGMP Support For Internet Group Management Protocol (IGMP) support in Layer 2, the KSZ8862M provides two components: “IGMP” Snooping The KSZ8862M traps IGMP packets and forwards them only to the processor (host port). The IGMP packets are identified as IP packets (either Ethernet IP packets, or IEEE 802.3 SNAP IP packets) with IP version = 0x4 and...

  • Page 43: Ieee 802.1Q Vlan Support

    Micrel, Inc. KSZ8862-16/32MQL IEEE 802.1Q VLAN Support The KSZ8862M supports 16 active VLANs out of the 4096 possible VLANs specified in the IEEE 802.1Q specification. KSZ8862M provides a 16-entry VLAN table, which converts the 12-bits VLAN ID (VID) to the 4-bits Filter ID (FID) for address lookup.

  • Page 44: Diffserv-Based Priority

    Micrel, Inc. KSZ8862-16/32MQL Figure 11 illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag. Bytes 46-1500 Preamble VPID length Data Bits Tagged Packet Type 802.1q VLAN Tag 802.1p VLAN ID (8100 for Ethernet) Figure 11. 802.1p Priority Field Format 802.1p-based priority is enabled by bit 5 of registers P1CR1, P2CR1, and P3CR1 for ports 1, 2, and the host port,...

  • Page 45: Mac Filtering Function

    Micrel, Inc. KSZ8862-16/32MQL Preamble byte, in addition to the data field (from packet DA to FCS). For ingress rate limiting, KSZ8862M provides options to selectively choose frames from all types, multicast, broadcast, and flooded unicast frames. The KSZ8862M counts the data rate from those selected type of frames. Packets are dropped at the ingress port when the data rate exceeds the specified rate limit.

  • Page 46: Loopback Support

    Micrel, Inc. KSZ8862-16/32MQL The format for ConfigParam is shown in Table 13. Bit Name Description 15 -2 Reserved Reserved Internal clock rate selection Clock_Rate 0: 125 MHz 1: 25 MHz Note: At power up, this chip operates on 125 MHz clock. The internal frequency can be dropped to 25 MHz via the external EEPROM.

  • Page 47: Figure 12. Port 2 Far-End Loopback Path

    Micrel, Inc. KSZ8862-16/32MQL O r i g i n a t i n g R X P 1 / T X P 1 / P H Y P o r t 1 R X M 1 T X M 1...

  • Page 48: Cpu Interface I/O Registers

    Micrel, Inc. KSZ8862-16/32MQL CPU Interface I/O Registers The KSZ8862M provides an EISA-like, ISA-like, or VLBUS-like bus interface for the CPU to access its internal I/O registers. I/O registers serve as the address that the microprocessor uses when communicating with the device. This is used for configuring operational settings, reading or writing control, status information, and transferring packets by reading and writing through the packet data registers.

  • Page 49: Internal I/O Space Mapping

    Micrel, Inc. KSZ8862-16/32MQL Internal I/O Space Mapping I/O Register Location Bank Location 32-Bit 16-Bit 8-Bit Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Base Host On-Chip Bus Address Low Control Address [7:0]...
  • Page 50 Micrel, Inc. KSZ8862-16/32MQL Internal I/O Space Mapping (continued) I/O Register Location Bank Location 32-Bit 16-Bit 8-Bit Bank 8 Bank 9 Bank 10 Bank 11 Bank 12 Bank 13 Bank 14 Bank 15 Reserved - 0x1 Reserved - 0x3 Reserved - 0x5...
  • Page 51 Micrel, Inc. KSZ8862-16/32MQL Internal I/O Space Mapping (continued) I/O Register Location Bank Location 32-Bit 16-Bit 8-Bit Bank 16 Bank 17 Bank 18 Bank 19 Bank 20 Bank 21 Bank 22 Bank 23 Transmit Interrupt Multicast Control Command Enable Table 0...
  • Page 52 Micrel, Inc. KSZ8862-16/32MQL Internal I/O Space Mapping (continued) I/O Register Location Bank Location 32-Bit 16-Bit 8-Bit Bank 24 Bank 25 Bank 26 Bank 27 Bank 28 Bank 29 Bank 30 Bank 31 Reserved - 0x1 Reserved - 0x3 Reserved - 0x5...
  • Page 53 Micrel, Inc. KSZ8862-16/32MQL Internal I/O Space Mapping (continued) I/O Register Location Bank Location 32-Bit 16-Bit 8-Bit Bank 32 Bank 33 Bank 34 Bank 35 Bank 36 Bank 37 Bank 38 Bank 39 Switch ID and Switch Global Enable Control 6...
  • Page 54 Micrel, Inc. KSZ8862-16/32MQL Internal I/O Space Mapping (continued) I/O Register Location Bank Location 32-Bit 16-Bit 8-Bit Bank 40 Bank 41 Bank 42 Bank 43 Bank 44 Bank 45 Bank 46 Bank 47 TOS Priority TOS Priority Indirect Digital Test PHY1 MII-...
  • Page 55 Micrel, Inc. KSZ8862-16/32MQL Internal I/O Space Mapping (continued) I/O Register Location Bank Location 32-Bit 16-Bit 8-Bit Bank 48 Bank 49 Bank 50 Bank 51 Bank 52 Bank 53 Bank 54 Bank 55 Port 1 Port 1 PHY Port 2 Port 2 PHY...
  • Page 56 Micrel, Inc. KSZ8862-16/32MQL Internal I/O Space Mapping (continued) I/O Register Location Bank Location 32-Bit 16-Bit 8-Bit Bank 56 Bank 57 Bank 58 Bank 59 Bank 60 Bank 61 Bank 62 Bank 63 Reserved - 0x1 Reserved - 0x3 Reserved - 0x5...

  • Page 57: Register Map: Switch And Mac/Phy

    Micrel, Inc. KSZ8862-16/32MQL Register Map: Switch and MAC/PHY Do not write to bit values or to registers defined as Reserved. Manipulating reserved bits or registers causes unpredictable and often fatal results. If the user wants to write to these reserved bits, the user has to read back these reserved bits (RO or RW) first, then “OR”...

  • Page 58: Bank 0 Bus Error Status Register (0X06): Besr

    Micrel, Inc. KSZ8862-16/32MQL Bank 0 Bus Error Status Register (0x06): BESR This register flags the different kinds of errors on the host bus. Default Value Description IBEC Illegal Byte Enable Combination 1: illegal byte enable combination occurs. The illegal combination value can be found from bit 14 to bit 11.

  • Page 59: Bank 2 Host Mac Address Register Middle (0X02): Marm

    Micrel, Inc. KSZ8862-16/32MQL MARH[15:0] = 0x0123 The following table shows the register bit fields: Default Value Description 15-0 MARL MAC Address Low The least significant word of the MAC address. Bank 2 Host MAC Address Register Middle (0x02): MARM The middle word of Host MAC address.

  • Page 60: Bank 3 Eeprom Control Register (0X02): Eepcr

    Micrel, Inc. KSZ8862-16/32MQL Bank 3 EEPROM Control Register (0x02): EEPCR To support an external EEPROM, tie the EEPROM Enable (EEEN) pin to High; otherwise, tie it to Low. If an external EEPROM is not used, the default chip Base Address (0x300), and the software programs the host MAC address. If an EEPROM is used in the design (EEPROM Enable pin to High), the chip Base Address and host MAC address are loaded from the EEPROM immediately after reset.

  • Page 61: Bank 3 Bus Configuration Register (0X08): Bcfg

    Micrel, Inc. KSZ8862-16/32MQL Bank 3 Bus Configuration Register (0x08): BCFG This register is a read-only register. The bit 0 is automatically downloaded from bit 0 Configparm word of EEPROM, if pin EEEN is high (enabled EEPROM) Default Value Description 15-1...

  • Page 62: Bank 16 Receive Control Register (0X04): Rxcr

    Micrel, Inc. KSZ8862-16/32MQL Bank 16 Receive Control Register (0x04): RXCR This register holds control information programmed by the CPU to control the receive function. Default Value Description 15-11 Reserved RXFCE Receive Flow Control Enable When this bit is set, the KSZ8862M will acknowledge a PAUSE frame from the receive interface;...

  • Page 63: Bank 16 Rxq Memory Information Register (0X0A): Rxmir

    Micrel, Inc. KSZ8862-16/32MQL Bank 16 RXQ Memory Information Register (0x0A): RXMIR This register indicates the amount of receive data available in the RXQ of the QMU module. Default Value Description 15-13 Reserved 12-0 RXMA Receive Packet Data Available The amount of Receive packet data available is represented in units of byte. The RXQ memory is used for both frame payload, status word.

  • Page 64: Bank 17 Rx Frame Data Pointer Register (0X06): Rxfdpr

    Micrel, Inc. KSZ8862-16/32MQL Bank 17 RX Frame Data Pointer Register (0x06): RXFDPR The value of this register determines the address to be accessed within the RXQ frame buffer. When the Auto Increment is set, it will automatically increment the RXQ Pointer on read accesses to the data register.

  • Page 65: Bank 18 Interrupt Enable Register (0X00): Ier

    Micrel, Inc. KSZ8862-16/32MQL Bank 18 Interrupt Enable Register (0x00): IER This register enables the interrupts from the QMU and other sources. Default Value Description LCIE Link Change Interrupt Enable When this bit is set, the link change interrupt is enabled.

  • Page 66: Bank 18 Interrupt Status Register (0X02): Isr

    Micrel, Inc. KSZ8862-16/32MQL Bank 18 Interrupt Status Register (0x02): ISR This register contains the status bits for all QMU and other interrupt sources. When the corresponding enable bit is set, it causes the interrupt pin to be asserted. This register is usually read by the host CPU and device drivers during interrupt service routine or polling. The register bits are not cleared when read.

  • Page 67: Bank 18 Receive Status Register (0X04): Rxsr

    Micrel, Inc. KSZ8862-16/32MQL Bank 18 Receive Status Register (0x04): RXSR This register indicates the status of the current received frame and mirrors the Receive Status word of the Receive Frame in the RXQ. Default Value Description RXFV Receive Frame Valid When set, it indicates that the present frame in the receive packet memory is valid.

  • Page 68: Bank 19 Multicast Table Register 0 (0X00): Mtr0

    Micrel, Inc. KSZ8862-16/32MQL Bank 19 Multicast Table Register 0 (0x00): MTR0 The 64-bit multicast table is used for group address filtering. This value is defined as the six most significant bits from CRC circuit calculation result that is based on 48-bit of DA input. The two most significant bits select one of the four registers to be used, while the others determine which bit within the register.

  • Page 69: Bank 32 Switch Id And Enable Register (0X00): Sider

    Micrel, Inc. KSZ8862-16/32MQL Bank 32 Switch ID and Enable Register (0x00): SIDER This register contains the switch ID and the switch enable control. Default Description 15-8 0x88 Family ID Chip family ID Chip ID 0x8 is assigned to KSZ8862M Revision ID Start Switch 1 = start the chip.

  • Page 70: Bank 32 Switch Global Control Register 2 (0X04): Sgcr2

    Micrel, Inc. KSZ8862-16/32MQL Bank 32 Switch Global Control Register 2 (0x04): SGCR2 This register contains the global control for the switch function. Default Description 802.1Q VLAN Enable 1 = 802.1Q VLAN mode is turned on. VLAN table must be set up before the operation.

  • Page 71: Bank 32 Switch Global Control Register 3 (0X06): Sgcr3

    Micrel, Inc. KSZ8862-16/32MQL Default Description Legal Maximum Packet Size Check Enable 0 = accepts packet sizes up to 1536 bytes (inclusive). 1 = 1522 bytes for tagged packets, 1518 bytes for untagged packets. Any packets larger than the specified value are dropped.

  • Page 72: Bank 32 Switch Global Control Register 5 (0X0A): Sgcr5

    Micrel, Inc. KSZ8862-16/32MQL Bank 32 Switch Global Control Register 5 (0x0A): SGCR5 This register contains the global control for the switch function. Default Description LEDSEL1 See the description in bit 9. 14-12 Reserved 11-10 Reserved LEDSEL0 These two bits, LEDSEL1 and LEDSEL0, are used to select LED mode.

  • Page 73: Bank 33 Switch Global Control Register 6 (0X00): Sgcr6

    Micrel, Inc. KSZ8862-16/32MQL Bank 33 Switch Global Control Register 6 (0x00): SGCR6 Default Description 15-14 Tag_0x7 IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its IEEE Tag has a value of 0x7. Tag_0x6 13-12 IEEE 802.1p mapping.

  • Page 74: Bank 39 Mac Address Register 1 (0X00): Macar1

    Micrel, Inc. KSZ8862-16/32MQL Bank 39 MAC Address Register 1 (0x00): MACAR1 This register contains the MAC address for the switch function. This MAC address is used for sending PAUSE frame. Default Description 15-0 0x0010 MACA[47:32] Specifies MAC address 1. This value has to be same as MARH in Bank2.

  • Page 75: Bank 40 Tos Priority Control Register 2 (0X02): Tosr2

    Micrel, Inc. KSZ8862-16/32MQL Bank 40 TOS Priority Control Register 2 (0x02): TOSR2 This register contains the TOS priority control for the switch function. Default Description 15-14 DSCP[31:30] The value in this field is used as the frame’s priority when bits [7:2] of it IP TOS/DiffServ/Traffic Class value is 0x3c.

  • Page 76: Bank 40 Tos Priority Control Register 4 (0X06): Tosr4

    Micrel, Inc. KSZ8862-16/32MQL Bank 40 TOS Priority Control Register 4 (0x06): TOSR4 This register contains the TOS priority control for the switch function. Default Description 15-14 DSCP[63:62] The value in this field is used as the frame’s priority when bits [7:2] of it IP TOS/DiffServ/Traffic Class value is 0x7c.

  • Page 77: Bank 40 Tos Priority Control Register 6 (0X0A): Tosr6

    Micrel, Inc. KSZ8862-16/32MQL Default Description DSCP[65:64] The value in this field is used as the frame’s priority when bits [7:2] of it IP TOS/DiffServ/Traffic Class value is 0x80. Bank 40 TOS Priority Control Register 6 (0x0A): TOSR6 This register contains the TOS priority control for the switch function.

  • Page 78: Bank 41 Tos Priority Control Register 8 (0X02): Tosr8

    Micrel, Inc. KSZ8862-16/32MQL Default Description DSCP[101:100] The value in this field is used as the frame’s priority when bits [7:2] of it IP TOS/DiffServ/Traffic Class value is 0xc8. DSCP[99:98] The value in this field is used as the frame’s priority when bits [7:2] of it IP TOS/DiffServ/Traffic Class value is 0xc4.

  • Page 79: Bank 42 Indirect Access Data Register 1 (0X02): Iadr1

    Micrel, Inc. KSZ8862-16/32MQL Default Description Indirect Address 0x000 Bit 9-0 of indirect address. Note: Write IACR triggers a command. Read or write access is determined by Register bit 12. Bank 42 Indirect Access Data Register 1 (0x02): IADR1 This register contains the indirect data for the switch function.

  • Page 80: Bank 44 Digital Testing Status Register (0X00): Dtsr

    Micrel, Inc. KSZ8862-16/32MQL Bank 44 Digital Testing Status Register (0x00): DTSR This register contains the user defined register for the switch function. Default Description 15-3 0x0000 Reserved Reserved Bank 44 Analog Testing Status Register (0x02): ATSR This register contains the user defined register for the switch function.
  • Page 81 Collision test Not supported. Reserved. HP_mdix Bank 49 0x04 bit 15 1 = HP Auto MDI-X mode. 0 = Micrel Auto MDI-X mode. Force MDI-X Bank 49 0x02 bit 9 1 = force MDI-X. 0 = normal operation. Disable MDI-X Bank 49 0x02 bit 10 1 = disable auto MDI-X.

  • Page 82: Bank 45 Phy 1 Mii-Register Basic Status Register (0X02): P1Mbsr

    Micrel, Inc. KSZ8862-16/32MQL Bank 45 PHY 1 MII-Register Basic Status Register (0x02): P1MBSR This register contains the MII register status for the switch port 1 function. Default Description Bit is same as: T4 Capable 1 = 100 BASE-T4 capable. 0 = not 100 BASE-T4 capable.

  • Page 83: Bank 45 Phy 1 Auto-Negotiation Advertisement Register (0X08): P1Anar

    Micrel, Inc. KSZ8862-16/32MQL Bank 45 PHY 1 Auto-Negotiation Advertisement Register (0x08): P1ANAR This register contains the auto-negotiation advertisement for the switch port 1 function. Default Description Bit is same as: Next page Not supported. Reserved Remote fault Not supported. 12-11...

  • Page 84: Bank 46 Phy 2 Mii-Register Basic Control Register (0X00): P2Mbcr

    Collision test Not supported. Reserved HP_mdix Bank 51 0x04 bit 15 1 = HP Auto MDI-X mode. 0 = Micrel Auto MDI-X mode. Force MDI-X Bank 51 0x02 bit 9 1 = force MDI-X. 0 = normal operation. Disable MDI-X Bank 51 0x02 bit 10 1 = disable auto MDI-X.

  • Page 85: Bank 46 Phy 2 Mii-Register Basic Status Register (0X02): P2Mbsr

    Micrel, Inc. KSZ8862-16/32MQL Bank 46 PHY 2 MII-Register Basic Status Register (0x02): P2MBSR This register contains the MII register for the switch port 2 function. Default Description Bit is same as: T4 Capable 0 = not 100 BASE-T4 capable. 100 Full Capable 1 = 100BASE-TX full-duplex capable.

  • Page 86: Bank 46 Phy 2 Auto-Negotiation Advertisement Register (0X08): P2Anar

    Micrel, Inc. KSZ8862-16/32MQL Bank 46 PHY 2 Auto-Negotiation Advertisement Register (0x08): P2ANAR This register contains the auto-negotiation advertisement for the switch port 2 function. Default Description Bit is same as: Next page Not supported. Reserved Remote fault Not supported. 12-11...

  • Page 87: Bank 47 Phy1 Special Control/Status Register (0X02): P1Phyctrl

    Micrel, Inc. KSZ8862-16/32MQL Bank 47 PHY1 Special Control/Status Register (0x02): P1PHYCTRL This register contains the control and status information of PHY1. Default Description Bit is same as: 15-6 0x000 Reserved Polarity Reverse (polrvs) Bank 49 0x04 bit 13 1 = polarity is reversed.

  • Page 88: Bank 47 Phy2 Special Control/Status Register (0X06): P2Phyctrl

    Micrel, Inc. KSZ8862-16/32MQL Bank 47 PHY2 Special Control/Status Register (0x06): P2PHYCTRL This register contains the control and status information of PHY2. Default Description Bit is same as: 15-6 0x000 Reserved Polarity reverse (polrvs) Bank 51 0x04 bit 13 1 = polarity is reversed.

  • Page 89: Bank 48 Port 1 Control Register 2 (0X02): P1Cr2

    Micrel, Inc. KSZ8862-16/32MQL Default Description Tag Removal 1 = when packets are output on the port, the switch removes 802.1p/q tags from packets with 802.1p/q tags when received. The switch will not modify packets received without tags. 0 = disable tag removal.

  • Page 90: Bank 48 Port 1 Vid Control Register (0X04): P1Vidcr

    Micrel, Inc. KSZ8862-16/32MQL Default Description User Priority Ceiling 1 = if the packet’s “priority field” is greater than the “user priority field” in the port VID control register bit[15:13], replace the packet’s “priority field” with the “user priority field” in the port VID control register bit[15:13].

  • Page 91: Bank 48 Port 1 Ingress Rate Control Register (0X08): P1Ircr

    Micrel, Inc. KSZ8862-16/32MQL Bank 48 Port 1 Ingress Rate Control Register (0x08): P1IRCR Default Description 15-12 Ingress Pri3 Rate Priority 3 frames will be discarded after the ingress rate selected as shown below is reached or exceeded. 0000 = Not limited (default)
  • Page 92 Micrel, Inc. KSZ8862-16/32MQL Default Description 0110 = 2Mbps 0111 = 4Mbps 1000 = 8Mbps 1001 = 16Mbps 1010 = 32Mbps 1011 = 48Mbps 1100 = 64 Mbps 1101 = 72Mbps 1110 = 80Mbps 1111 = 88Mbps Note: For 10BT, rate settings above 10Mbps are set to the default value 0000 (not limited).

  • Page 93: Bank 48 Port 1 Egress Rate Control Register (0X0A): P1Ercr

    Micrel, Inc. KSZ8862-16/32MQL Bank 48 Port 1 Egress Rate Control Register (0x0A): P1ERCR Default Description 15-12 Egress Pri3 Rate Egress data rate limit for priority 3 frames. Output traffic from this priority queue is shaped according to the egress rate selected below:...
  • Page 94 Micrel, Inc. KSZ8862-16/32MQL Default Description 0110 = 2Mbps 0111 = 4Mbps 1000 = 8Mbps 1001 = 16Mbps 1010 = 32Mbps 1011 = 48Mbps 1100 = 64 Mbps 1101 = 72Mbps 1110 = 80Mbps 1111 = 88Mbps Notes: For 10BT, rate settings above 10Mbps are set to the default value 0000 (not limited).

  • Page 95: Bank 49 Port 1 Phy Special Control/Status, Linkmd

    Micrel, Inc. KSZ8862-16/32MQL ® Bank 49 Port 1 PHY Special Control/Status, LinkMD (0x00): P1SCSLMD Default Description Bit is same as: Reserved 14-13 Reserved Reserved Force_lnk Bank 47 0x02 bit 3 Force link. 1 = force link pass. 0 = normal operation.

  • Page 96: Bank 49 Port 1 Status Register (0X04): P1Sr

    Description Bit is same as: Bank 45 0x00 bit 5 HP_mdix 1 = HP Auto MDI-X mode. 0 = Micrel Auto MDI-X mode. Reserved Bank 47 0x02 bit 5 Polarity Reverse 1 = polarity is reversed. 0 = polarity is not reversed.

  • Page 97: Bank 50 Port 2 Control Register 1 (0X00): P2Cr1

    Micrel, Inc. KSZ8862-16/32MQL Default Description Bit is same as: Operation Duplex 1 = link duplex is full. 0 = link duplex is half. Far-End-Fault Bank 45 0x02 bit 4 1 = far-end-fault status detected. 0 = no Far-end-fault status detected.

  • Page 98: Bank 51 Port 2 Phy Special Control/Status, Linkmd

    Micrel, Inc. KSZ8862-16/32MQL ® Bank 51 Port 2 PHY Special Control/Status, LinkMD (0x00): P2SCSLMD Default Description Bit is same as: Vct_10m_short Bank 47 0x04 bit 12 1 = Less than 10 meter short. 14-13 Vct_result Bank 47 0x04 bit 14-13 VCT result.

  • Page 99: Bank 51 Port 2 Control Register 4 (0X02): P2Cr4

    Micrel, Inc. KSZ8862-16/32MQL Bank 51 Port 2 Control Register 4 (0x02): P2CR4 This register contains the global per port control for the switch function. Default Description Bit is same as: LED Off Bank 46 0x00 bit 0 1 = turn off all of the port 2 LEDs (P2LED3, P2LED2, P2LED1, P2LED0).

  • Page 100: Bank 51 Port 2 Status Register (0X04): P2Sr

    Description Bit is same as: HP_mdix Bank 46 0x00 bit 5 1 = HP Auto MDI-X mode. 0 = Micrel Auto MDI-X mode. Reserved Polarity Reverse Bank 47 0x06 bit 5 1 = polarity is reversed. 0 = polarity is not reversed.

  • Page 101: Bank 52 Host Port Control Register 1 (0X00): P3Cr1

    Micrel, Inc. KSZ8862-16/32MQL Default Description Bit is same as: Partner 100BT half duplex capability. Bank 46 0x0A bit 7 1 = link partner 100BT half-duplex capable. 0 = link partner not 100BT half-duplex capable. Partner 10BT full-duplex capability. Bank 46 0x0A bit 6 1 = link partner 10BT full-duplex capable.

  • Page 102: Bank 52 Host Port Vid Control Register (0X04): P3Vidcr

    Micrel, Inc. KSZ8862-16/32MQL Default Description User Priority Ceiling 1 = if the packet’s “user priority field” is greater than the “user priority field” in the port default tag register, replace the packet’s “user priority field” with the “user priority field” in the port default tag register.

  • Page 103: Mib (Management Information Base) Counters

    Micrel, Inc. KSZ8862-16/32MQL MIB (Management Information Base) Counters The KSZ8862M provides 34 MIB counters for each port. These counters are used to monitor the port activity for network management. The MIB counters are formatted “per port” as shown in Table 14 and “all ports dropped packet” as shown in Table 16.

  • Page 104: Format Of "All Ports Dropped Packet" Mib Counters

    Micrel, Inc. KSZ8862-16/32MQL Offset Counter Name Description 0x13 Rx1024to1522Octets Total Rx packets (bad packets included) that are between 1024 and 1522 octets in length (upper limit depends on max packet size setting) 0x14 TxLoPriorityByte Tx lo-priority good octet count, including PAUSE packets...

  • Page 105: Additional Mib Information

    Micrel, Inc. KSZ8862-16/32MQL Examples: 1. MIB Counter Read (read port 1 “Rx64Octets” counter at indirect address offset 0x0E) Write to reg. IACR with 0x1c0e (set indirect address and trigger a read MIB counters operation) Then Read reg. IADR5 (MIB counter value 31-16) // If bit 31 = 1, there was a counter overflow // If bit 30 = 0, restart (reread) from this register Read reg.

  • Page 106: Static Mac Address Table

    Micrel, Inc. KSZ8862-16/32MQL Static MAC Address Table The KSZ8862M supports both a static and a dynamic MAC address table. In response to a Destination Address (DA) look up, The KSZ8862M searches both tables to make a packet forwarding decision. In response to a Source Address (SA) look up, only the dynamic table is searched for aging, migration and learning purposes.

  • Page 107: Dynamic Mac Address Table

    Micrel, Inc. KSZ8862-16/32MQL Dynamic MAC Address Table The Dynamic MAC address is a read only table. Default Value Description Data not ready 1: specifies that the entry is not ready, continue retrying until bit is set to 0 0: specifies that the entry is ready...

  • Page 108: Vlan Table

    Micrel, Inc. KSZ8862-16/32MQL VLAN Table The KSZ8862M uses the VLAN table to perform look-ups. If 802.1Q VLAN mode is enabled (SGCR2[15]), this table will be used to retrieve the VLAN information that is associated with the ingress packet. This information includes FID (filter...

  • Page 109: Absolute Maximum Ratings

    Micrel, Inc. KSZ8862-16/32MQL Absolute Maximum Ratings Description Pins Value Supply Voltage VDDATX, VDDARX, VDDIO –0.5V to 4.0V Input Voltage All Inputs –0.5V to 5V Output Voltage All Outputs –0.5V to 4.0V Lead Temperature (soldering, 10 sec) 270°C –55°C to 150°C Storage Temperature (T Table 21.

  • Page 110: Electrical Characteristics

    Micrel, Inc. KSZ8862-16/32MQL Electrical Characteristics Parameter Symbol Condition Supply Current for 100BASE-SX/FX and 100BASE-TX Operation (All Ports@ Full Duplex and 100% Utilization) 100BASE-TX /SX/FX VDDATX, VDDARX, VDDIO = 3.3V 153mA (analog core + PLL + digital core + ddxio transceiver + digital I/O)

  • Page 111: Timing Specifications

    Micrel, Inc. KSZ8862-16/32MQL Timing Specifications Asynchronous Timing without using Address Strobe (ADSN = 0) Addr, AEN, BExN valid ADSN Read Data valid RDN, WRN Write Data valid ARDY (Read Cycle) ARDY ( Write Cycle) Figure 14. Asynchronous Cycle – ADSN = 0...

  • Page 112: Asynchronous Timing Using Address Strobe (Adsn)

    Micrel, Inc. KSZ8862-16/32MQL Asynchronous Timing Using Address Strobe (ADSN) Addr, AEN, BExN valid ADSN Read Data valid RDN, WRN Write Data valid ARDY (Read Cycle) ARDY ( Write Cycle) Figure 15. Asynchronous Cycle – Using ADSN Symbol Parameter Unit A1-A15, AEN, BExN[3:0] valid to RDN, WRN active...

  • Page 113: Asynchronous Timing Using Datacsn

    Micrel, Inc. KSZ8862-16/32MQL Asynchronous Timing Using DATACSN DATACSN Read Data valid RDN, WRN valid Write Data ARDY (Read Cycle) ARDY ( Write Cycle) Figure 16. Asynchronous Cycle – Using DATACSN Symbol Parameter Unit DATACSN setup to RDN, WRN active DATACSN hold after RDN, WRN inactive (assume...

  • Page 114: Address Latching Timing For All Modes

    Micrel, Inc. KSZ8862-16/32MQL Address Latching Timing for All Modes ADSN Address, AEN, BExN LDEVN Figure 17. Address Latching Cycle for All Modes Symbol Parameter Unit A1-A15, AEN, BExN[3:0] setup to ADSN A1-A15, AEN, BExN[3:0] hold after ADSN rising A4-A15, AEN to LDEVN delay Table 27.

  • Page 115: Synchronous Timing In Burst Write (Vlbusn = 1)

    Micrel, Inc. KSZ8862-16/32MQL Synchronous Timing in Burst Write (VLBUSN = 1) Figure 18. Synchronous Burst Write Cycles – VLBUSN = 1 Symbol Parameter Unit SWR setup to BCLK falling DATDCSN setup to BCLK rising CYCLEN setup to BCLK rising Write data setup to BCLK rising...

  • Page 116: Synchronous Timing In Burst Read (Vlbusn = 1)

    Micrel, Inc. KSZ8862-16/32MQL Synchronous Timing in Burst Read (VLBUSN = 1) BCLK DATACSN CYCLEN Read Data data0 data1 data2 data3 RDYRTNN SRDYN Figure 19. Synchronous Burst Read Cycles – VLBUSN = 1 Symbol Parameter Unit SWR setup to BCLK falling...

  • Page 117: Synchronous Write Timing (Vlbusn = 0)

    Micrel, Inc. KSZ8862-16/32MQL Synchronous Write Timing (VLBUSN = 0) BCLK Address, AEN, BExN valid ADSN CYCLEN Write Data valid SRDYN RDYRTNN Figure 20. Synchronous Write Cycle – VLBUSN = 0 Symbol Parameter Unit A1-A15, AEN, BExN[3:0] setup to ADSN rising...

  • Page 118: Synchronous Read Timing (Vlbusn = 0)

    Micrel, Inc. KSZ8862-16/32MQL Synchronous Read Timing (VLBUSN = 0) BCLK Address, AEN, BExN valid ADSN CYCLEN Read Data valid SRDYN RDYRTNN Figure 21. Synchronous Read Cycle – VLBUSN = 0 Symbol Parameter Unit A1-A15, AEN, BExN[3:0] setup to ADSN rising...

  • Page 119: Eeprom Timing

    Micrel, Inc. KSZ8862-16/32MQL EEPROM Timing EECS EESK tcyc EEDO High-Z EEDI *1 Start bit Figure 22. EEPROM Read Cycle Timing Diagram Timing Description Unit Parameter μs tcyc Clock cycle 4 (OBCR[1:0]=11 on-chip bus speed @ 25 MHz) 0.8 (OBCR[1:0]=00 on-chip...

  • Page 120: Auto Negotiation Timing

    Micrel, Inc. KSZ8862-16/32MQL Auto Negotiation Timing Figure 23. Auto-Negotiation Timing Timing Description Unit Parameter FLP burst to FLP burst FLP burst width FLPW Clock/Data pulse width Clock pulse to 55.5 69.5 µs data pulse Clock pulse to µs clock pulse...

  • Page 121: Reset Timing

    Micrel, Inc. KSZ8862-16/32MQL Reset Timing As long as the stable supply voltages to reset High timing (minimum of 10ms) are met, there is no power-sequencing requirement for the KSZ8862M supply voltage (3.3V). The reset timing requirement is summarized in the Figure 26 and Table 34.

  • Page 122: Selection Of Isolation Transformers

    Micrel, Inc. KSZ8862-16/32MQL Selection of Isolation Transformers A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode choke is recommended to exceed FCC requirements. Table 35 gives recommended transformer characteristics. Parameter Value Test Condition...

  • Page 123: Package Information

    Micrel, Inc. KSZ8862-16/32MQL Package Information Figure 25. 128-Pin PQFP Package August 2010 M9999-081310-3.1...

  • Page 124: Acronyms And Glossary

    Micrel, Inc. KSZ8862-16/32MQL Acronyms and Glossary Bus Interface Unit The host interface function that performs code conversion, buffering, and the like required for communications to and from a network. BPDU Bridge Protocol Data Unit A packet containing ports, addresses, etc. to make sure data being passed through a bridged network arrives at its proper destination.
  • Page 125 TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

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