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KS8852HLE
Micrel KS8852HLE Manuals
Manuals and User Guides for Micrel KS8852HLE. We have
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Micrel KS8852HLE manual available for free PDF download: Manual
Micrel KS8852HLE Manual (193 pages)
Two-Port 10/100 Mb/s Ethernet Switch with 8 or 16-Bit Host Interface
Brand:
Micrel
| Category:
Switch
| Size: 2 MB
Table of Contents
General Description
1
Functional Diagram
2
Features
3
Management Capabilities
3
Robust PHY Ports
3
MAC Ports
3
Advanced Switch Capabilities
3
Comprehensive Configuration Registers Access
3
Host Interface
3
Power and Power Management
4
Additional Features
4
Packaging
4
Target Applications
4
Ordering Information
5
Revision History
5
Table of Contents
6
Contents
6
List of Figures
13
List of Tables
14
Acronyms
15
Pin Configuration
17
Pin Description
18
Strapping Options
23
Functional Description
24
Direction Terminology
24
Physical (PHY) Block
25
100BASE-TX Transmit
25
100BASE-TX Receive
25
Scrambler/De-Scrambler (100BASE-TX Only)
25
PLL Clock Synthesizer (Recovery)
25
10BASE-T Receive
25
MDI/MDI−X Auto Crossover
26
Straight Cable
26
Figure 1. Typical Straight Cable Connection
26
Table 1. MDI/MDI-X Pin Definitions
26
Crossover Cable
27
Figure 2. Typical Crossover Cable Connection
27
Auto Negotiation
28
Figure 3. Auto-Negotiation and Parallel Operation
28
Linkmd ® Cable Diagnostics
29
Access
29
Usage
29
On-Chip Termination Resistors
29
Loopback Support
30
Far-End Loopback
30
Near−End (Remote) Loopback
30
Figure 4. Near-End and Far-End Loopback
30
Media Access Controller (MAC) Block
31
Mac Operation
31
Address Lookup
31
Learning
31
Migration
31
Aging
31
Forwarding
31
Figure 5. Destination Address Lookup Flow Chart in Stage One
32
Figure 6. Destination Address Resolution Flow Chart in Stage Two
33
Inter Packet Gap (IPG)
34
Back-Off Algorithm
34
Late Collision
34
Legal Packet Size
34
Flow Control
34
Half-Duplex Backpressure
34
Broadcast Storm Protection
35
Port Individual MAC Address and Source Port Filtering
35
Address Filtering Function
35
Table 2. MAC Address Filtering Scheme
36
Switch Block
37
Switching Engine
37
Spanning Tree Support
37
Table 3. Spanning Tree States
37
Rapid Spanning Tree Support
38
Discarding State
38
Learning State
38
Forwarding State
38
Tail Tagging Mode
38
Figure 7. Tail Tag Frame Format
38
IGMP Support
39
IGMP" Snooping
39
Multicast Address Insertion" in the Static MAC Table
39
Ipv6 MLD Snooping
39
Table 4. Tail Tag Rules
39
Port Mirroring Support
40
Receive Only" Mirror-On-A-Port
40
Transmit Only" Mirror-On-A-Port
40
Receive and Transmit" Mirror-On-Two-Ports
40
IEEE 802.1Q VLAN Support
40
Table 5. FID + da Lookup in VLAN Mode
40
Qos Priority Support
41
Port-Based Priority
41
802.1P-Based Priority
41
Figure 8. 802.1P Priority Field Format
41
Table 6. FID + SA Lookup in VLAN Mode
41
802.1P Priority Field Re-Mapping
42
Diffserv-Based Priority
42
Rate-Limiting Support
42
MAC Address Filtering Function
43
Queue Management Unit (QMU)
44
Transmit Queue (TXQ) Frame Format
44
Table 7. Frame Format for Transmit Queue
44
Table 8. Transmit Control Word Bit Fields
44
Frame Transmitting Path Operation in TXQ
45
Table 9. Transmit Byte Count Format
45
Table 10. Register Setting for Transmit Function Block
45
Driver Routine for Transmitting Packets from Host Processor to KSZ8852
46
Figure 9. Host TX Single Frame in Manual Enqueue Flow Diagram
46
Receive Queue (RXQ) Frame Format
47
Table 11. Frame Format for Receive Queue
47
Frame Receiving Path Operation in RXQ
48
Driver Routine for Receiving Packets from the KSZ8852 to the Host Processor
48
Table 12. Register Settings for Receive Function Block
48
Figure 10. Host RX Single or Multiple Frames in Auto-Dequeue Flow Diagram
49
Device Clocks
50
Table 13. KSZ8852 Device Clocks
50
Power
51
Figure 11. Recommended Low-Voltage Power Connection Using an External Low-Voltage-Regulator
51
Table 14. Voltage Options and Requirements
51
Internal Low Voltage LDO Regulator
52
Figure 12. Recommended Low-Voltage Power Connections Using the Internal Low-Voltage Regulator
52
Power Management
53
Normal Operation Mode
53
Energy Detect Mode
53
Table 15. Power Management and Internal Blocks
53
Global Soft Power-Down Mode
54
Energy-Efficient Ethernet (EEE)
54
Figure 13. Traffic Activity and EEE
54
Wake-On-LAN
55
Detection of Energy
55
Detection of Linkup
55
Wake-Up Packet
55
Magic Packet
55
Interrupt Generation on Power Management Related Events
56
To Generate an Interrupt on the PME Signal Pin
56
To Generate an Interrupt on the INTRN Signal Pin
56
Interfaces
57
Bus Interface Unit (BIU) / Host Interface
57
Supported Transfers
57
Physical Data Bus Size
57
Table 16. Available Interfaces
57
Little and Big Endian Support
58
Asynchronous Interface
58
Table 17. Bus Interface Unit Signal Grouping
58
BIU Summary
59
Figure 14. KSZ8852 8-Bit and 16-Bit Data Bus Connections
59
Serial EEPROM Interface
60
Table 18. KSZ8852 Serial EEPROM Format
60
Device Registers
61
Figure 15. Interface and Register Mapping
61
Table 19. Mapping of Functional Areas Within the Address Space
62
Register Map of CPU Accessible I/O Registers
63
I/O Registers
63
Internal I/O Register Space Mapping for Switch Control and Configuration (0X000 - 0X0Ff)
63
Internal I/O Register Space Mapping for Host Interface Unit (0X100 - 0X16F)
69
Internal I/O Register Space Mapping for the QMU (0X170 − 0X1Ff)
71
Special Control Registers (0X700 − 0X7Ff)
73
Register Bit Definitions
74
Internal I/O Register Mapping for Switch Control and Configuration (0X000 - 0X0Ff)
74
Chip ID and Enable Register (0X00 - 0X001): CIDER
74
Switch Global Control Register 1 (0X002 - 0X003): SGCR1
74
Switch Global Control Register 2 (0X004 - 0X005): SGCR2
76
Switch Global Control Register 3 (0X006 - 0X007): SGCR3
77
0X008 - 0X00B: Reserved
77
Switch Global Control Register 6 (0X00C - 0X00D): SGCR6
78
Switch Global Control Register 7 (0X00E - 0X00F): SGCR7
79
MAC Address Register 1 (0X010 - 0X011): MACAR1
80
MAC Address Register 2 (0X012 - 0X013): MACAR2
80
MAC Address Register 3 (0X014 - 0X015): MACAR3
80
Type-Of-Service (TOS) Priority Control Registers
81
TOS Priority Control Register 1 (0X016-- 0X017): TOSR1
81
TOS Priority Control Register 2 (0X018 - 0X019): TOSR2
82
TOS Priority Control Register 3 (0X01A - 0X01B): TOSR3
83
TOS Priority Control Register 4 (0X01C - 0X1D): TOSR4
83
TOS Priority Control Register 5 (0X01E - 0X1F): TOSR5
84
TOS Priority Control Register 6 (0X020 - 0X021): TOSR6
85
TOS Priority Control Register 7 (0X022 - 0X023): TOSR7
85
TOS Priority Control Register 8 (0X024 - 0X025): TOSR8
86
Indirect Access Data Registers
87
Indirect Access Data Register 1 (0X026 - 0X027): IADR1
87
Indirect Access Data Register 2 (0X028 - 0X029): IADR2
87
Indirect Access Data Register 3 (0X02A - 0X02B): IADR3
87
Indirect Access Data Register 4 (0X02C - 0X02D): IADR4
87
Indirect Access Data Register 5 (0X02E - 0X02F): IADR5
88
Indirect Access Control Register (0X030 - 0X031): IACR
88
Power Management Control and Wake-Up Event Status
89
Power Management Control and Wake-Up Event Status (0X032 - 0X033): PMCTRL
89
Power Management Event Enable Register (0X034 - 0X035): PMEE
90
Go Sleep Time and Clock Tree Power-Down Control Registers
91
Go Sleep Time Register (0X036 - 0X037): GST
91
Clock Tree Power-Down Control Register (0X038 - 0X039): CTPDC
91
0X03A - 0X04B: Reserved
91
PHY and MII Basic Control Registers
92
PHY 1 and MII Basic Control Register (0X04C-- 0X04D): P1MBCR
92
PHY 1 and MII Basic Status Register (0X04E - 0X04F): P1MBSR
93
PHY 1 PHYID Low Register (0X050 - 0X051): PHY1ILR
94
PHY 1 PHYID High Register (0X052 - 0X053): PHY1IHR
94
PHY 1 Auto-Negotiation Advertisement Register (0X054 - 0X055): P1ANAR
95
PHY 1 Auto−Negotiation Link Partner Ability Register (0X056 - 0X057): P1ANLPR
96
PHY 2 and MII Basic Control Register (0X058 - 0X059): P2MBCR
96
PHY 2 and MII Basic Status Register (0X05A - 0X05B): P2MBSR
98
PHY2 PHYID Low Register (0X05C - 0X05D): PHY2ILR
99
PHY 2 PHYID High Register (0X05E - 0X05F): PHY2IHR
99
PHY 2 Auto-Negotiation Advertisement Register (0X060 - 0X061): P2ANAR
99
PHY 2 Auto-Negotiation Link Partner Ability Register (0X062 -0X063): P2ANLPR
100
0X0X064 - 0X065: Reserved
100
PHY1 Special Control and Status Register (0X066 - 0X067): P1PHYCTRL
100
0X068 --0X069: Reserved
100
PHY2 Special Control and Status Register (0X06A - 0X06B): P2PHYCTRL
101
Port 1 Control Registers
102
Port 1 Control Register 1 (0X06C - 0X06D): P1CR1
102
Port 1 Control Register 2 (0X06E - 0X06F): P1CR2
104
Port 1 VID Control Register (0X070 - 0X071): P1VIDCR
105
Port 1 Control Register 3 (0X072 - 0X073): P1CR3
105
Port 1 Ingress Rate Control Register 0 (0X074 - 0X075): P1IRCR0
106
Table 20. Ingress or Egress Data Rate Limits
106
Port 1 Ingress Rate Control Register 1 (0X076 - 0X077): P1IRCR1
107
Port 1 Egress Rate Control Register 0 (0X078 - 0X079): P1ERCR0
107
Port 1 Egress Rate Control Register 1 (0X07A - 0X07B): P1ERCR1
107
Port 1 PHY Special Control/Status, Linkmd (0X07C - 0X07D): P1SCSLMD
108
Port 1 Control Register 4 (0X07E - 0X07F): P1CR4
109
Port 1 Status Register (0X080 - 0X081): P1SR
110
0X082 - 0X083: Reserved
111
Port 2 Control Registers
112
Port 2 Control Register 1 (0X084 - 0X085): P2CR1
112
Port 2 Control Register 2 (0X086 - 0X087): P2CR2
114
Port 2 VID Control Register (0X088 - 0X089): P2VIDCR
115
Port 2 Control Register 3 (0X08A-0X08B): P2CR3
115
Port 2 Ingress Rate Control Register 0 (0X08C - 0X08D): P2IRCR0
116
Port 2 Ingress Rate Control Register 1 (0X08E - 0X08F): P2IRCR1
116
Port 2 Egress Rate Control Register 0 (0X090 - 0X091): P2ERCR0
117
Port 2 Egress Rate Control Register 1 (0X092 - 0X093): P2ERCR1
117
Port 2 PHY Special Control/Status, Linkmd (0X094 - 0X095): P2SCSLMD
118
Port 2 Control Register 4 (0X096 - 0X097): P2CR4
119
Port 2 Status Register (0X098 - 0X099): P2SR
121
0X09A - 0X09B: Reserved
122
Port 3 Control Registers
123
Port 3 Control Register 1 (0X09C - 0X09D): P3CR1
123
Port 3 Control Register 2 (0X09E - 0X09F): P3CR2
124
Port 3 VID Control Register (0X0A0 - 0X0A1): P3VIDCR
125
Port 3 Control Register 3 (0X0A2 - 0X0A3): P3CR3
125
Port 3 Ingress Rate Control Register 0 (0X0A4 - 0X0A5): P3IRCR0
126
Port 3 Ingress Rate Control Register 1 (0X0A6 - 0X0A7): P3IRCR1
126
Port 3 Egress Rate Control Register 0 (0X0A8 - 0X0A9): P3ERCR0
126
Port 3 Egress Rate Control Register 1 (0X0Aa - 0X0Ab): P3ERCR1
127
Switch Global Control Registers
128
Switch Global Control Register 8 (0X0Ac - 0X0Ad): SGCR8
128
Switch Global Control Register 9 (0X0Ae - 0X0Af): SGCR9
129
Source Address Filtering Registers
130
Source Address Filtering MAC Address 1 Register Low (0X0B0 - 0X0B1): SAFMACA1L
130
Source Address Filtering MAC Address 1 Register Middle (0X0B2 - 0X0B3): SAFMACA1M
130
Source Address Filtering MAC Address 1 Register High (0X0B4 - 0X0B5): SAFMACA1H
130
Source Address Filtering MAC Address 2 Register Low (0X0B6 - 0X0B7): SAFMACA2L
130
Source Address Filtering MAC Address 2 Register Middle (0X0B8 - 0X0B9): SAFMACA2M
130
Source Address Filtering MAC Address 2 Register High (0X0Ba - 0X0Bb): SAFMACA2H
130
0X0Bc - 0X0C7: Reserved
130
TXQ Rate Control Registers
131
Port 1 TXQ Rate Control Register 1 (0X0C8 - 0X0C9): P1TXQRCR1
131
Port 1 TXQ Rate Control Register 2 (0X0Ca - 0X0Cb): P1TXQRCR2
131
Port 2 TXQ Rate Control Register 1 (0X0Cc - 0X0Cd): P2TXQRCR1
132
Port 2 TXQ Rate Control Register 2 (0X0Ce - 0X0Cf): P2TXQRCR2
132
Port 3 TXQ Rate Control Register 1 (0X0D0 - 0X0D1): P3TXQRCR1
133
Port 3 TXQ Rate Control Register 2 (0X0D2 - 0X0D3): P3TXQRCR2
133
0X0D4 - 0X0Db: Reserved
133
Auto-Negotiation Next Page Registers
134
Port 1 Auto-Negotiation Next Page Transmit Register (0X0Dc - 0X0Dd): P1ANPT
134
Port 1 Auto-Negotiation Link Partner Received Next Page Register (0X0De - 0X0Df): P1ALPRNP
135
EEE and Link Partner Advertisement Registers
136
Port 1 EEE and Link Partner Advertisement Register (0X0E0 - 0X0E1): P1EEEA
136
Port 1 EEE Wake Error Count Register (0X0E2 - 0X0E3): P1EEEWEC
137
Port 1 EEE Control/Status and Auto-Negotiation Expansion Register (0X0E4 - 0X0E5): P1EEECS
137
Port 1 LPI Recovery Time Counter Register (0X0E6): P1LPIRTC
139
Buffer Load to LPI Control 1 Register (0X0E7): BL2LPIC1
139
Port 2 Auto−Negotiation Next Page Transmit Register (0X0E8 - 0X0E9): P2ANPT
139
Port 2 Auto-Negotiation Link Partner Received Next Page Register (0X0Ea - 0X0Eb): P2ALPRNP
140
Port 2 EEE and Link Partner Advertisement Register (0X0Ec - 0X0Ed): P2EEEA
140
Port 2 EEE Wake Error Count Register (0X0Ee - 0X0Ef): P2EEEWEC
141
Port 2 EEE Control/Status and Auto-Negotiation Expansion Register (0X0F0 - 0X0F1): P2EEECS
142
Port 2 LPI Recovery Time Counter Register (0X0F2): P2LPIRTC
143
PCS EEE Control Register (0X0F3): PCSEEEC
144
Empty TXQ to LPI Wait Time Control Register (0X0F4 - 0X0F5): ETLWTC
144
Buffer Load to LPI Control 2 Register (0X0F6 - 0X0F7): BL2LPIC2
144
0X0F8 - 0X0Ff: Reserved
144
Internal I/O Register Space Mapping for Interrupts, BIU, and Global Reset (0X100 - 0X1Ff)
145
0X100 - 0X107: Reserved
145
Chip Configuration Register (0X108 - 0X109): CCR
145
0X10A - 0X10F: Reserved
145
Host MAC Address Registers: MARL, MARM and MARH
146
Host MAC Address Register Low (0X110 - 0X111): MARL
146
Host MAC Address Register Middle (0X112 - 0X113): MARM
146
Host MAC Address Register High (0X114 - 0X115): MARH
146
0X116 - 0X121: Reserved
146
EEPROM Control Register (0X122 - 0X123): EEPCR
147
Memory bist Info Register (0X124 - 0X125): MBIR
147
Global Reset Register (0X126 - 0X127): GRR
148
0X128 - 0X129: Reserved
148
Wake-Up Frame Control Register (0X12A - 0X12B): WFCR
149
0X12C - 0X12F: Reserved
149
Wake-Up Frame 0 CRC0 Register (0X130 - 0X131): WF0CRC0
149
Wake-Up Frame 0 CRC1 Register (0X132- 0X133): WF0CRC1
150
Wake-Up Frame 0 Byte Mask 0 Register (0X134 - 0X135): WF0BM0
150
Wake-Up Frame 0 Byte Mask 1 Register (0X136 - 0X137): WF0BM1
150
Wake-Up Frame 0 Byte Mask 2 Register (0X138 - 0X139): WF0BM2
150
Wake-Up Frame 0 Byte Mask 3 Register (0X13A - 0X13B): WF0BM3
150
0X13C - 0X13F: Reserved
150
Wake-Up Frame 1 CRC0 Register (0X140 - 0X141): WF1CRC0
151
Wake-Up Frame 1 CRC1 Register (0X142 - 0X143): WF1CRC1
151
Wake-Up Frame 1 Byte Mask 0 Register (0X144 - 0X145): WF1BM0
151
Wake-Up Frame 1 Byte Mask 1 Register (0X146 - 0X147): WF1BM1
151
Wake-Up Frame 1 Byte Mask 2 Register (0X148 - 0X149): WF1BM2
152
Wake-Up Frame 1 Byte Mask 3 Register (0X14A - 0X14B): WF1BM3
152
0X14C - 0X14F: Reserved
152
Wake-Up Frame 2 CRC0 Register (0X150 - 0X151): WF2CRC0
152
Wake-Up Frame 2 CRC1 Register (0X152 - 0X153): WF2CRC1
152
Wake-Up Frame 2 Byte Mask 0 Register (0X154 - 0X155): WF2BM0
152
Wake-Up Frame 2 Byte Mask 1 Register (0X156 - 0X157): WF2BM1
153
Wake-Up Frame 2 Byte Mask 2 Register (0X158 - 0X159): WF2BM2
153
Wake-Up Frame 2 Byte Mask 3 Register (0X15A - 0X15B): WF2BM3
153
0X15C - 0X15F: Reserved
153
Wake-Up Frame 3 CRC0 Register (0X160 - 0X161): WF3CRC0
154
Wake-Up Frame 3 CRC1 Register (0X162 - 0X163): WF3CRC1
154
Wake-Up Frame 3 Byte Mask 0 Register (0X164 - 0X165): WF3BM0
154
Wake-Up Frame 3 Byte Mask 1 Register (0X166 - 0X167): WF3BM1
154
Wake-Up Frame 3 Byte Mask 2 Register (0X168 - 0X169): WF3BM2
154
Wake-Up Frame 3 Byte Mask 3 Register (0X16A - 0X16B): WF3BM3
155
0X16C - 0X16F: Reserved
155
Internal I/O Register Space Mapping for the Queue Management Unit (QMU) (0X170 - 0X1Ff)
156
Transmit Control Register (0X170 - 0X171): TXCR
156
Transmit Status Register (0X172 - 0X173): TXSR
157
Receive Control Register 1 (0X174 - 0X175): RXCR1
157
Receive Control Register 2 (0X176 - 0X177): RXCR2
158
TXQ Memory Information Register (0X178 - 0X179): TXMIR
159
0X17A - 0X17B: Reserved
159
Receive Frame Header Status Register (0X17C - 0X17D): RXFHSR
159
Receive Frame Header Byte Count Register (0X17E - 0X17F): RXFHBCR
160
TXQ Command Register (0X180 - 0X181): TXQCR
161
RXQ Command Register (0X182 - 0X183): RXQCR
161
TX Frame Data Pointer Register (0X184 - 0X185): TXFDPR
162
RX Frame Data Pointer Register (0X186 - 0X187): RXFDPR
163
0X188 - 0X18B: Reserved
163
RX Duration Timer Threshold Register (0X18C - 0X18D): RXDTTR
163
RX Data Byte Count Threshold Register (0X18E - 0X18F): RXDBCTR
163
Internal I/O Register Space Mapping for Interrupt Registers (0X190 - 0X193)
164
Interrupt Enable Register (0X190 - 0X191): IER
164
Interrupt Status Register (0X192-- 0X193): ISR
165
0X194 - 0X19B: Reserved
166
Internal I/O Register Space Mapping for the Queue Management Unit (QMU) (0X19C - 0X1B9)
167
RX Frame Count and Threshold Register (0X19C -0X19D): RXFCTR
167
TX Next Total Frames Size Register (0X19E - 0X19F): TXNTFSR
167
MAC Address Hash Table Register 0 (0X1A0 - 0X1A1): MAHTR0
167
Multicast Table Register 0
167
MAC Address Hash Table Register 1 (0X1A2 - 0X1A3): MAHTR1
168
Multicast Table Register 1
168
MAC Address Hash Table Register 2 (0X1A4 - 0X1A5): MAHTR2
168
Multicast Table Register 2
168
MAC Address Hash Table Register 3 (0X1A6 - 0X1A7): MAHTR3
168
Multicast Table Register 3
168
0X1A8 - 0X1Af: Reserved
168
Flow Control Low Water Mark Register (0X1B0 - 0X1B1): FCLWR
168
Flow Control High Water Mark Register (0X1B2 - 0X1B3): FCHWR
169
Flow Control Overrun Water Mark Register (0X1B4 - 0X1B5): FCOWR
169
0X1B6 - 0X1B7: Reserved RX Frame Count Register (0X1B8 - 0X1B9): RXFC
169
0X1Ba - 0X747: Reserved
170
Analog Control 1 Register (0X748 - 0X749): ANA_CNTRL_1
170
0X74A - 0X74B: Reserved
170
Analog Control 3 Register (0X74C - 0X74D): ANA_CNTRL_3
170
0X74E - 0X7Ff: Reserved
170
Management Information Base (MIB) Counters
171
Table 21. Format of Per-Port MIB Counters
171
Table 22. Port 1 MIB Counters - Indirect Memory Offset
172
MIB Counter Examples
173
Additional MIB Information
173
Table 23. "All Ports Dropped Packet" MIB Counter Format
173
Table 24. "All Ports Dropped Packet" MIB Counters− Indirect Memory Offsets
173
Static MAC Address Table
174
Table 25. Static MAC Table Format (8 Entries)
174
Static MAC Table Lookup Examples
175
Dynamic MAC Address Table
176
Dynamic MAC Address Lookup Example
176
Table 26. Dynamic MAC Address Table Format (1024 Entries)
176
VLAN Table
177
VLAN Table Lookup Examples
177
Table 27. VLAN Table Format (16 Entries)
177
Absolute Maximum Ratings
178
Operating Ratings
178
Electrical Characteristics
178
Timing Specifications
183
Host Interface Read / Write Timing
183
Figure 16. Host Interface Read/Write Timing
183
Table 28. Host Interface Read/Write Timing Parameters
183
Auto−Negotiation Timing
184
Figure 17. Auto-Negotiation Timing
184
Table 29. Auto-Negotiation Timing Parameters
184
Serial EEPROM Interface Timing
185
Figure 18. Serial EEPROM Timing
185
Table 30. Serial EEPROM Timing Parameters
185
Reset Timing and Power Sequencing
186
Figure 19. KSZ8852 Reset and Power Sequence Timing
186
Table 31. Reset Timing Parameters (8, 9, 10)
186
Reset Circuit Guidelines
187
Figure 20. Sample Reset Circuit
187
Figure 21. Recommended Reset Circuit for Interfacing with a CPU/FPGA Reset Output
187
Reference Circuits - LED Strap-In Pins
188
Figure 22. Typical LED Strap-In Circuit
188
Reference Clock - Connection and Selection
189
Selection of Reference Crystal
189
Figure 23. 25Mhz Crystal and Oscillator Clock Connections
189
Table 32. Typical Reference Crystal Characteristics
189
Selection of Isolation Transformers
190
Table 33. Transformer Selection Criteria
190
Table 34. Qualified Single Port Magnetic
190
Package Information and Recommended Landing Pattern
191
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