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Micrel KS8852HLE Manual

Two-port 10/100 mb/s ethernet switch with 8 or 16-bit host interface
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General Description

The KSZ8852 product line consists of industrial capable
Ethernet switches, providing integrated communication for
a range of Industrial Ethernet and general Ethernet
applications.
The KSZ8852 product enables distributed, daisy-chained
topologies preferred for industrial Ethernet networks.
Conventional centralized (i.e., star-wired) topologies are
also supported for fault tolerant arrangements.
A flexible 8 or 16-bit general bus interface is provided for
interfacing to an external host processor.
The
wire-speed,
store-and-forward
provides a full complement of QoS and congestion control
features optimized for real-time Ethernet.
LinkMD is a registered trademark of Micrel, Inc.
ETHERSYNCH is a trademark of Micrel, Inc.
Magic Packet is a registered trademark of Advanced Micro Devices, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 •
June 23, 2014
Two-Port 10/100 Mb/s Ethernet Switch with
The KSZ8852 product is built upon Micrel's industry-
leading Ethernet technology, with features designed to
offload host processing and streamline your overall design:
• Wire-speed Ethernet switching fabric with extensive
• Two integrated 10/100BASE-TX PHY transceivers,
• Full-featured QoS support
• Flexible management options that support common
A robust assortment of power management features
including energy-efficient Ethernet (EEE) have been
designed in to satisfy energy-efficient environments.
switching
fabric
Datasheets and support documentation are available on
Micrel's web site at: www.micrel.com.
KS8852HLE
8 or 16-Bit Host Interface
Revision 1.0
filtering
featuring the industry's lowest power consumption
standard interfaces
KSZ8852 Top Level Architecture
http://www.micrel.com
Revision 1.0

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Summary of Contents for Micrel KS8852HLE

  • Page 1: General Description

    ETHERSYNCH is a trademark of Micrel, Inc. Magic Packet is a registered trademark of Advanced Micro Devices, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com June 23, 2014 Revision 1.0...

  • Page 2: Functional Diagram

    Micrel, Inc. KSZ8852HLE Functional Diagram KSZ8852HLE Functional Diagram June 23, 2014 Revision 1.0...

  • Page 3: Features

    Micrel, Inc. KSZ8852HLE Features Advanced Switch Capabilities • Non-blocking store-and-forward switch fabric assures Management Capabilities fast packet delivery by utilizing 1024 entry forwarding • The KSZ8852 includes all the functions of a table 10/100BASE-T/TX switch system which combines a • IEEE 802.1Q VLAN for up to 16 groups with full range of...

  • Page 4: Power And Power Management

    Micrel, Inc. KSZ8852HLE Additional Features Power and Power Management • Single 25MHz +50 ppm reference clock requirement • Single 3.3V power supply with optional VDD I/O for • Comprehensive programmable two LED indicators 1.8V, 2.5V or 3.3V support for link, activity, full/half duplex and 10/100 •...

  • Page 5: Ordering Information

    64−Pin 10x10mm Extended (115°C) Industrial Temperature −40°C to +115°C KSZ8852HLEYA LQFP with Range Switch exposed pad KSZ8852HLE-EVAL KSZ8852 Evaluation Board Note: 1. Contact Micrel for availability. Revision History Revision Date Summary of Changes 11/21/13 Initial Draft June 23, 2014 Revision 1.0...

  • Page 6: Table Of Contents

    Micrel, Inc. KSZ8852HLE Contents General Description ................................1 Functional Diagram ................................. 2 Features ....................................3 Management Capabilities ..............................3 Robust PHY Ports ................................3 MAC Ports ................................... 3 Advanced Switch Capabilities ............................. 3 Comprehensive Configuration Registers Access ........................ 3 Host Interface ..................................3 Power and Power Management ............................
  • Page 7 Micrel, Inc. KSZ8852HLE Address Filtering Function ..............................35 Switch Block ..................................37 Switching Engine ................................37 Spanning Tree Support ..............................37 Rapid Spanning Tree Support ............................38 Discarding State ................................38 Learning State ................................38 Forwarding State ................................38 Tail Tagging Mode ................................. 38 IGMP Support ..................................
  • Page 8 Micrel, Inc. KSZ8852HLE Register Map of CPU Accessible I/O Registers ........................63 I/O Registers ..................................63 Internal I/O Register Space Mapping for Switch Control and Configuration (0x000 - 0x0FF) ........63 Internal I/O Register Space Mapping for Host Interface Unit (0x100 - 0x16F) .............. 69 Internal I/O Register Space Mapping for the QMU (0x170 −...
  • Page 9 Micrel, Inc. KSZ8852HLE PHY2 Special Control and Status Register (0x06A - 0x06B): P2PHYCTRL ..............101 Port 1 Control Registers ..............................102 Port 1 Control Register 1 (0x06C - 0x06D): P1CR1 ......................102 Port 1 Control Register 2 (0x06E - 0x06F): P1CR2 ......................104 Port 1 VID Control Register (0x070 - 0x071): P1VIDCR ....................
  • Page 10 Micrel, Inc. KSZ8852HLE Port 1 Auto-Negotiation Link Partner Received Next Page Register (0x0DE - 0x0DF): P1ALPRNP ......135 EEE and Link Partner Advertisement Registers ......................... 136 Port 1 EEE and Link Partner Advertisement Register (0x0E0 – 0x0E1): P1EEEA ............136 Port 1 EEE Wake Error Count Register (0x0E2 - 0x0E3): P1EEEWEC .................
  • Page 11 Micrel, Inc. KSZ8852HLE Wake-Up Frame 3 Byte Mask 2 Register (0x168 – 0x169): WF3BM2 ................154 Wake-Up Frame 3 Byte Mask 3 Register (0x16A - 0x16B): WF3BM3 ................155 0x16C – 0x16F: Reserved ............................... 155 Internal I/O Register Space Mapping for the Queue Management Unit (QMU) (0x170 - 0x1FF) ........156 Transmit Control Register (0x170 - 0x171): TXCR ......................
  • Page 12 Micrel, Inc. KSZ8852HLE Host Interface Read / Write Timing ..........................183 Auto−Negotiation Timing ..............................184 Serial EEPROM Interface Timing ............................ 185 Reset Timing and Power Sequencing ..........................186 Reset Circuit Guidelines ..............................187 Reference Circuits – LED Strap-In Pins ..........................188 Reference Clock –...

  • Page 13: List Of Figures

    Micrel, Inc. KSZ8852HLE List of Figures Figure 1. Typical Straight Cable Connection ........................26 Figure 2. Typical Crossover Cable Connection ........................27 Figure 3. Auto-Negotiation and Parallel Operation ....................... 28 Figure 4. Near-End and Far-End Loopback .......................... 30 Figure 5. Destination Address Lookup Flow Chart in Stage One ..................32 Figure 6.

  • Page 14: List Of Tables

    Micrel, Inc. KSZ8852HLE List of Tables Table 1. MDI/MDI-X Pin Definitions ............................26 Table 2. MAC Address Filtering Scheme ..........................36 Table 3. Spanning Tree States ............................. 37 Table 4. Tail Tag Rules ................................. 39 Table 5. FID + DA Lookup in VLAN Mode ..........................40 Table 6.

  • Page 15: Acronyms

    Micrel, Inc. KSZ8852HLE Acronyms Bus Interface Unit The host interface function that performs code conversion, buffering, and the like required for communications to and from a network. BPDU Bridge Protocol Data Unit A packet containing ports, addresses, etc. to make sure data being passed through a bridged network arrives at its proper destination.
  • Page 16 Micrel, Inc. KSZ8852HLE Acronyms (Continued) MDI-X Medium Dependent An Ethernet port connection that allows networked end stations Interface Crossover (i.e., PCs or workstations) to connect to each other using a null−modem, or crossover, cable. For 10/100 full−duplex networks, an end point (such as a computer) and a switch are wired so that each transmitter connects to the far end receiver.

  • Page 17: Pin Configuration

    Micrel, Inc. KSZ8852HLE Pin Configuration 64-Pin LQFP (top view) (Bottom paddle is GND) June 23, 2014 Revision 1.0...

  • Page 18: Pin Description

    Micrel, Inc. KSZ8852HLE Pin Description Pin Number Pin Name Type Pin Function Port 1 physical receive (MDI) or transmit (MDIX) signal (− differential). RXM1 RXP1 Port 1 physical receive (MDI) or transmit (MDIX) signal (+ differential). AGND Analog Ground. Port 1 physical transmit (MDI) or receive (MDIX) signal (− differential).
  • Page 19 Micrel, Inc. KSZ8852HLE Pin Description (Continued) Pin Number Pin Name Type Pin Function Shared Data Bus Bit [12] or BE0 This is data bit (D12) access when CMD = “0”. This is Byte Enable 0 (BE0, 1st byte SD12/BE0 I/O (PD) enable and active high) at double-word boundary access in 16-bit bus mode when CMD = “1”.
  • Page 20 Micrel, Inc. KSZ8852HLE Pin Description (Continued) Pin Number Pin Name Type Pin Function DGND Digital Ground This pin can be used in two ways; as the pin to input a low voltage to the device if the VDD_L internal low voltage regulator is not used, or as the low voltage output if the internal low voltage regulator is used.
  • Page 21 Micrel, Inc. KSZ8852HLE Pin Description (Continued) Pin Number Pin Name Type Pin Function EEPROM Serial Clock Output EESK O(PD) A serial output clock is used to load configuration data into the KSZ8852 from the external EEPROM when it is present.
  • Page 22 Micrel, Inc. KSZ8852HLE Pin Description (Continued) Pin Number Pin Name Type Pin Function Reset RSTN Hardware reset pin (Active Low). This reset input is required to be low for a minimum of 10ms after supply voltages VDD_IO and 3.3V are stable.

  • Page 23: Strapping Options

    Micrel, Inc. KSZ8852HLE Strapping Options Pin Number Pin Name Type Pin Function During Power-up / Reset EEPROM Select PME/ Pull-Up = EEPROM present IPD/O EEPROM NC or Pull-Down (default) = EEPROM not present This pin value is latched into register CCR, bit [9] at the end of the Power-Up/Reset time.

  • Page 24: Functional Description

    Readers should note that two different terminologies are used in this datasheet to describe the direction of data flow. In the standard terminology that is used for all Micrel switches, directions are described from the point of view of the switch core: “transmit”...

  • Page 25: Physical (Phy) Block

    Micrel, Inc. KSZ8852HLE Physical (PHY) Block 100BASE-TX Transmit The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion, and MLT3 encoding and transmission. The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit stream.

  • Page 26: Mdi/Mdi−X Auto Crossover

    Micrel, Inc. KSZ8852HLE MDI/MDI−X Auto Crossover To eliminate the need for crossover cables between similar devices, the KSZ8852 supports HP-Auto MDI/MDI-X and IEEE 802.3u standard MDI/MDI-X auto crossover. HP-Auto MDI/MDI-X is the default. The auto-sense function detects remote transmit and receive pairs and correctly assigns these transmit and receive pairs for the KSZ8852 device.

  • Page 27: Crossover Cable

    Micrel, Inc. KSZ8852HLE Crossover Cable A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device. Figure 2 shows a typical crossover cable connection between two chips or hubs (two MDI-X devices).

  • Page 28: Auto Negotiation

    Micrel, Inc. KSZ8852HLE Auto Negotiation The KSZ8852 conforms to the auto-negotiation protocol as described by IEEE 802.3. It allows each port to operate at either 10BASE-T or 100BASE-TX. Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the best common mode of operation.

  • Page 29: Linkmd ® Cable Diagnostics

    Micrel, Inc. KSZ8852HLE ® LinkMD Cable Diagnostics The KSZ8852 LinkMD uses time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems such as open circuits, short circuits, and impedance mismatches. LinkMD works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs and then analyzes the shape of the reflected signal.

  • Page 30: Loopback Support

    Micrel, Inc. KSZ8852HLE Loopback Support The KSZ8852 provides two loopback modes. One is Near-End (Remote) Loopback to support remote diagnosing of failures on line side, and the other is Far-end loopback to support local diagnosing of failures through all blocks of the device.

  • Page 31: Media Access Controller (Mac) Block

    Micrel, Inc. KSZ8852HLE MAC (Media Access Controller) Block Mac Operation The KSZ8852 strictly abides by IEEE 802.3 standards to maximize compatibility. Additionally, there is an added MAC filtering function to filter unicast packets. The MAC filtering function is useful in applications such as VoIP where restricting certain packets reduces congestion and thus improves performance.

  • Page 32: Figure 5. Destination Address Lookup Flow Chart In Stage One

    Micrel, Inc. KSZ8852HLE Figure 5. Destination Address Lookup Flow Chart in Stage One June 23, 2014 Revision 1.0...

  • Page 33: Figure 6. Destination Address Resolution Flow Chart In Stage Two

    Micrel, Inc. KSZ8852HLE Figure 6. Destination Address Resolution Flow Chart in Stage Two June 23, 2014 Revision 1.0...

  • Page 34: Inter Packet Gap (Ipg)

    Micrel, Inc. KSZ8852HLE Inter Packet Gap (IPG) If a frame is successfully transmitted, then the minimum 96-bit time for IPG is measured between two consecutive packets. If the current packet is experiencing collisions, the minimum 96-bit time for IPG is measured from carrier sense (CRS) to the next transmit packet.

  • Page 35: Broadcast Storm Protection

    Micrel, Inc. KSZ8852HLE Note: These bits are not set in default, since this is not the IEEE standard. Broadcast Storm Protection The KSZ8852 has an intelligent option to protect the switch system from receiving too many broadcast packets. As the broadcast packets are forwarded to all ports except the source port, an excessive number of switch resources (bandwidth and available space in transmit queues) may be utilized.

  • Page 36: Table 2. Mac Address Filtering Scheme

    Micrel, Inc. KSZ8852HLE Table 2. MAC Address Filtering Scheme Receive Control Register (0x174 − 0x175): RXCR1 Address RX Physical RX Multicast Item Description RX ALL RX Inverse Filtering Mode Address Address (Bit [4]) (Bit [1]) (Bit [11]) (Bit [8]) All Rx frames are passed only if the DA...

  • Page 37: Switch Block

    Micrel, Inc. KSZ8852HLE Switch Block Switching Engine The KSZ8852 features a high−performance switching engine to move data to and from the MAC’s packet buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency. The switching engine has a 32KByte internal frame buffer.

  • Page 38: Rapid Spanning Tree Support

    Micrel, Inc. KSZ8852HLE Rapid Spanning Tree Support There are three operational states assigned to each port for RSTP (Discarding, Learning, and Forwarding): • Discarding ports do not participate in the active topology and do not learn MAC addresses. • Discarding state: the state includes three states of the disable, blocking and listening of STP.

  • Page 39: Igmp Support

    Micrel, Inc. KSZ8852HLE Table 4. Tail Tag Rules Ingress to Port 3 (Host −> KSZ8852) Bit [1:0] Destination Port Normal (Address Look up) Port 1 Port 2 Port 1 and Port 2 Bit [3:2] Frame Priority Priority 0 Priority 1...

  • Page 40: Port Mirroring Support

    Micrel, Inc. KSZ8852HLE Port Mirroring Support KSZ8852 supports “Port Mirroring” comprehensively as illustrated in the following sub-sections: “Receive Only” Mirror-on-a-Port All the packets received on the port are mirrored on the sniffer port. For example, Port 1 is programmed to be “receive sniff”...

  • Page 41: Qos Priority Support

    Micrel, Inc. KSZ8852HLE Table 6. FID + SA Lookup in VLAN Mode FID+SA Found in Action Dynamic MAC Table? Learn and add FID+SA to the Dynamic MAC Address Table Update time stamp QoS Priority Support The KSZ8852 provides quality-of-service (QoS) for applications such as VoIP and video conferencing. The KSZ8852 offer 1, 2, and 4 priority queues option per port.

  • Page 42: 802.1P Priority Field Re-Mapping

    Micrel, Inc. KSZ8852HLE 802.1p based priority is enabled by bit[5]of registers P1CR1, P2CR1, and P3CR1 for Ports 1, 2, and the host port, respectively. The KSZ8852 provides the option to insert or remove the priority tagged frame's header at each individual egress port.

  • Page 43: Mac Address Filtering Function

    Micrel, Inc. KSZ8852HLE MAC Address Filtering Function When a packet is received, the destination MAC address is looked up in both the static and dynamic MAC address tables. If the address is not found in either of these tables, then the destination MAC address is “unknown”. By default, an unknown unicast packet is forwarded to all ports except the port at which it was received.

  • Page 44: Queue Management Unit (Qmu)

    Micrel, Inc. KSZ8852HLE Queue Management Unit (QMU) The Queue Management Unit (QMU) manages packet traffic on port 3 between the internal MAC and the external host processor interface. It has built−in packet memory for receive and transmit functions called transmit queue (TXQ) and receive queue (RXQ).

  • Page 45: Frame Transmitting Path Operation In Txq

    Micrel, Inc. KSZ8852HLE The transmit byte count specifies the total number of bytes to be transmitted from the TXQ. Its format is given Table Table 9. Transmit Byte Count Format Description 15 − 11 Reserved. TXBC Transmit Byte Count: Transmit Byte Count. Hardware uses the byte count information to conserve the TX buffer memory for better utilization of the packet memory.

  • Page 46: Driver Routine For Transmitting Packets From Host Processor To Ksz8852

    Micrel, Inc. KSZ8852HLE Driver Routine for Transmitting Packets from Host Processor to KSZ8852 The transmit routine is called by the upper layer to transmit a contiguous block of data through the Ethernet controller. It is the user’s choice to decide how the transmit routine is implemented. If the Ethernet controller encounters an error while transmitting the frame, it’s the user’s choice to decide whether the driver should attempt to retransmit the same frame or...

  • Page 47: Receive Queue (Rxq) Frame Format

    Micrel, Inc. KSZ8852HLE Receive Queue (RXQ) Frame Format The frame format for the receive queue is shown in Table 11. The first word contains the status information for the frame received. The second word is the total number of bytes of the RX frame. Following that is the packet data area. The packet data area holds the frame itself.

  • Page 48: Frame Receiving Path Operation In Rxq

    Micrel, Inc. KSZ8852HLE Frame Receiving Path Operation in RXQ This section describes the typical register settings for receiving packets from KSZ8852 to the host processor via the generic bus interface. Users can use the default value for most of the receive registers.

  • Page 49: Figure 10. Host Rx Single Or Multiple Frames In Auto-Dequeue Flow Diagram

    Micrel, Inc. KSZ8852HLE Figure 10. Host RX Single or Multiple Frames in Auto-Dequeue Flow Diagram In order to read received frames from RXQ without error, the software driver must follow these steps: 1. When a receive interrupt occurs and the software driver writes a “1” to clear the RX interrupt in the ISR register; the KSZ8852 will update the Rx frame counter (RXFC) register for this interrupt.

  • Page 50: Device Clocks

    Micrel, Inc. KSZ8852HLE Device Clocks A 25MHz crystal or oscillator clock is required to operate the device. This clock is used as input to a PLL clock synthesizer which generates 125MHz, 62.5MHz, and 31.25MHz clocks for the KSZ8852 system timing.

  • Page 51: Power

    Micrel, Inc. KSZ8852HLE Power The KSZ8852 device requires a single 3.3V supply to operate. An internal low voltage LDO provides the necessary low voltage (nominal ~1.3V) to power the analog and digital logic cores. The various I/O’s can be operated at 1.8V, 2.5V, and 3.3V.

  • Page 52: Internal Low Voltage Ldo Regulator

    Micrel, Inc. KSZ8852HLE Internal Low Voltage LDO Regulator The KSZ8852 reduces board cost and simplifies board layout by integrating a low-noise internal low-voltage LDO regulator to supply the nominal ~1.3V core power voltage for a single 3.3V power supply solution. If it is desired to take advantage of an external low-voltage supply that is available, the internal low-voltage regulator can be disabled to save power.

  • Page 53: Power Management

    Micrel, Inc. KSZ8852HLE Power Management The KSZ8852 supports enhanced power management features in low power state with energy detection to ensure low- power dissipation during device idle periods. There are three operation modes under the power management function which is controlled by two bits in the power management control and wake-up event status register (PMCTRL, 0x032 –...

  • Page 54: Global Soft Power-Down Mode

    Micrel, Inc. KSZ8852HLE Global Soft Power-Down Mode Soft power-down mode is entered by setting bits [1:0] = “10” in PMCTRL register. When the device is in this mode, all PLL clocks are disabled, the PHYs and the MACs are off, all internal registers value will change to their default value (except the BIU, QMU registers), and the host CPU interface is only used to wake-up this device from the current soft power-down mode to normal operation mode by setting bits [1:0] = “00”...

  • Page 55: Wake-On-Lan

    Micrel, Inc. KSZ8852HLE Wake-On-LAN Wake-on-LAN is considered a power-management feature in that it can be used to communicate to a specific network device and tell it to “wake up” from sleep mode and be prepared to transfer data. The KSZ8852 can be programmed to notify the host of the wake-up detected condition.

  • Page 56: Interrupt Generation On Power Management Related Events

    Micrel, Inc. KSZ8852HLE 66 −11 22 33 44 55 66 − 11 22 33 44 55 66 − 11 22 33 44 55 66 − 11 22 33 44 55 66 − 11 22 33 44 55 66 − 11 22 33 44 55 66 −...

  • Page 57: Interfaces

    Micrel, Inc. KSZ8852HLE Interfaces The KSZ8852 device incorporates a number of interfaces to enable it to be designed into a standard network environment as well as a vendor unique environment. The available interfaces and details of each usage are provided in Table 16.

  • Page 58: Little And Big Endian Support

    Micrel, Inc. KSZ8852HLE Table 17. Bus Interface Unit Signal Grouping Signal Type Function Shared Data Bus 16-bit Mode & CMD = “0” SD[15:0] = D[15:0] data 16-bit Mode & CMD = “1”: SD[10:2] = A[10:2] Address SD[15:12] = BE[3:0] Byte enable...

  • Page 59: Biu Summary

    Micrel, Inc. KSZ8852HLE In order for software to read back the previous CMD register write value when CMD is “1”, the BIU qualifies both the CSN pin and the RDN pin to read the Address A[10:2] and BE[3:0] value (in 16−bit mode) back from the KSZ8852 when CMD pin is high.

  • Page 60: Serial Eeprom Interface

    Micrel, Inc. KSZ8852HLE Serial EEPROM Interface A serial EEPROM interface has been incorporated into the device to enable loading the MAC address into the device at power-up time with a value from an external serial EEPROM. This feature is turned on using a strapping option on pin 46.

  • Page 61: Device Registers

    Micrel, Inc. KSZ8852HLE Device Registers The KSZ8852 device has a rich set of registers available to manage the functionality of the device. Access to these registers is via the host interface (BIU). The device can be programmed to automatically load register locations 0x110 - 0x115 with a MAC address stored in Word locations 01h - 03h in an external serial EEPROM.

  • Page 62: Table 19. Mapping Of Functional Areas Within The Address Space

    Micrel, Inc. KSZ8852HLE Table 19. Mapping of Functional Areas within the Address Space Register Locations Device Area Description Registers which control the overall functionality of the Switch, 0x000 - 0x0FF Switch Control and Configuration MAC, and PHYs Registers used to indirectly address and access four distinct areas within the device.

  • Page 63: Register Map Of Cpu Accessible I/O Registers

    Micrel, Inc. KSZ8852HLE Register Map of CPU Accessible I/O Registers The registers in the address range 00h through 7FFh can be read or written by a local CPU attached to the host interface. If enabled, registers 0x110 - 0x115 can be loaded at power on time by contents in the serial EEPROM. These registers are used for configuring the MAC address of the device.
  • Page 64 Micrel, Inc. KSZ8852HLE Internal I/O Register Space Mapping for Switch Control and Configuration (0x000 - 0x0FF) (Continued) I/O Register Offset Location Register Name Default Value Description 16-Bit 8-Bit 0x01E 0x01E - 0x01F TOSR5 0x0000 TOS Priority Control Register 5 [15:0]...
  • Page 65 Micrel, Inc. KSZ8852HLE Internal I/O Register Space Mapping for Switch Control and Configuration (0x000 - 0x0FF) (Continued) I/O Register Offset Location Register Name Default Value Description 16-Bit 8-Bit 0x054 PHY 1 Auto-Negotiation Advertisement Register 0x054 - 0x055 P1ANAR 0x05E1 [15:0]...
  • Page 66 Micrel, Inc. KSZ8852HLE Internal I/O Register Space Mapping for Switch Control and Configuration (0x000 - 0x0FF) (Continued) I/O Register Offset Location Register Name Default Value Description 16-Bit 8-Bit 0x078 0x078 - 0x079 P1ERCR0 0x0000 Port 1 Egress Rate Control Register 0 [15:0]...
  • Page 67 Micrel, Inc. KSZ8852HLE Internal I/O Register Space Mapping for Switch Control and Configuration (0x000 - 0x0FF) (Continued) I/O Register Offset Location Register Name Default Value Description 16-Bit 8-Bit 0x09C 0x09C - 0x09D P3CR1 0x0000 Port 3 Control Register 1 [15:0]...
  • Page 68 Micrel, Inc. KSZ8852HLE Internal I/O Register Space Mapping for Switch Control and Configuration (0x000 - 0x0FF) (Continued) I/O Register Offset Location Default Register Name Description Value 16-Bit 8-Bit 0x0CA 0x0CA - 0x0CB P1TXQRCR2 0x8182 Port 1 TXQ Rate Control Register 2 [15:0]...

  • Page 69: Internal I/O Register Space Mapping For Host Interface Unit (0X100 - 0X16F)

    Micrel, Inc. KSZ8852HLE Internal I/O Register Space Mapping for Switch Control and Configuration (0x000 - 0x0FF) (Continued) I/O Register Offset Location Register Name Default Value Description 16-Bit 8-Bit 0x0EE 0x0EE - 0x0EF P2EEEWEC 0x0000 Port 2 EEE Wake Error Count Register [15:0] 0x0EF Port 2 EEE Control/Status and Auto−Negotiation...
  • Page 70 Micrel, Inc. KSZ8852HLE Internal I/O Register Space Mapping for Host Interface Unit (0x100 - 0x16F) (Continued) I/O Register Offset Location Register Name Default Value Description 16-Bit 8-Bit 0x12A 0x12A - 0x12B WFCR 0x0000 Wake-Up Frame Control Register [15:0] 0x12B 0x12C...

  • Page 71: Internal I/O Register Space Mapping For The Qmu (0X170 − 0X1Ff)

    Micrel, Inc. KSZ8852HLE Internal I/O Register Space Mapping for Host Interface Unit (0x100 - 0x16F) (Continued) I/O Register Offset Location Register Name Default Value Description 16-Bit 8-Bit 0x156 0x156 - 0x157 WF2BM1 0x0000 Wake-Up Frame 2 Byte Mask 1 Register [15:0]...
  • Page 72 Micrel, Inc. KSZ8852HLE − Internal I/O Register Space Mapping for the QMU (0x170 0x1FF) (Continued) I/O Register Offset Location Register Name Default Value Description 16-Bit 8-Bit 0x17C 0x17C - 0x17D RXFHSR 0x0000 Receive Frame Header Status Register [15:0] 0x17D 0x17E...

  • Page 73: Special Control Registers (0X700 − 0X7Ff)

    Micrel, Inc. KSZ8852HLE Internal I/O Register Space Mapping for the QMU (0x170 - 0x1FF) (Continued) I/O Register Offset Location Register Name Default Value Description 16-Bit 8-Bit 0x1A6 0x1A6 - 0x1A7 MAHTR3 0x0000 MAC Address Hash Table Register 3 [15:0] 0x1A7...

  • Page 74: Register Bit Definitions

    Micrel, Inc. KSZ8852HLE Register Bit Definitions The section provides details of the bit definitions for the registers summarized in the previous section. Writing to a bit or register defined as reserved could potentially cause unpredictable results. If it is necessary to write to registers which contain both writable and reserved bits in the same register, the user should first read back the reserved bits (RO or RW), then “OR”...
  • Page 75 Micrel, Inc. KSZ8852HLE Switch Global Control Register 1 (0x002 - 0x003): SGCR1 (Continued) Default Description Frame Length Field Check 1 = Enable checking frame length field in the IEEE packets. If the actual length does not match, the packet will be dropped (for Length/Type field < 1500).

  • Page 76: Switch Global Control Register 2 (0X004 - 0X005): Sgcr2

    Micrel, Inc. KSZ8852HLE Switch Global Control Register 2 (0x004 – 0x005): SGCR2 This register contains global control bits for the switch function. Default Description 802.1Q VLAN Enable 1 = 802.1Q VLAN mode is turned on. VLAN table must be set up before the operation.

  • Page 77: Switch Global Control Register 3 (0X006 - 0X007): Sgcr3

    Micrel, Inc. KSZ8852HLE Switch Global Control Register 2 (0x004 – 0x005): SGCR2 (Continued) Default Description Huge Packet Support 1 = Accepts packet sizes up to 1916 bytes (inclusive). This bit setting overrides setting from bit 1 of the same register.

  • Page 78: Switch Global Control Register 6 (0X00C - 0X00D): Sgcr6

    Micrel, Inc. KSZ8852HLE Switch Global Control Register 6 (0x00C - 0x00D): SGCR6 This register contains global control bits for the switch function. Default Description Tag_0x7 15−14 IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its VLAN Tag has a value of 0x7.

  • Page 79: Switch Global Control Register 7 (0X00E - 0X00F): Sgcr7

    Micrel, Inc. KSZ8852HLE Switch Global Control Register 7 (0x00E - 0x00F): SGCR7 This register contains global control bits for the switch function. Default Description 15−10 0x02 Reserved Port LED Mode When read, these two bits provide the current setting of the LED display mode for P1/2LED1 and P1/2LED0 as defined as below.

  • Page 80: Mac Address Register 1 (0X010 - 0X011): Macar1

    Micrel, Inc. KSZ8852HLE MAC Address Register 1 (0x010 - 0x011): MACAR1 This register contains the two MSBs of the MAC address for the switch function. This MAC address is used for sending PAUSE frames. Default Description MACA[47:32] 15−0 0x0010 Specifies MAC Address 1 for sending PAUSE frame.

  • Page 81: Type-Of-Service (Tos) Priority Control Registers

    Micrel, Inc. KSZ8852HLE Type-of-Service (TOS) Priority Control Registers TOS Priority Control Register 1 (0x016-– 0x017): TOSR1 The IPv4/IPv6 type-of-service (TOS) priority control registers are used to define a 2-bit priority to each of the 64 possible values in the 6-bit differentiated services code point (DSCP) field in the IP header of ingress frames.

  • Page 82: Tos Priority Control Register 2 (0X018 - 0X019): Tosr2

    Micrel, Inc. KSZ8852HLE TOS Priority Control Register 2 (0x018 - 0x019): TOSR2 This register contains the TOS priority control bits for the switch function. Default Description DSCP[31:30] 15−14 The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic Class value are 0x3c.

  • Page 83: Tos Priority Control Register 3 (0X01A - 0X01B): Tosr3

    Micrel, Inc. KSZ8852HLE TOS Priority Control Register 3 (0x01A - 0x01B): TOSR3 This register contains the TOS priority control bits for the switch function. Default Description DSCP[47:46] 15−14 The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic Class value are 0x5c.

  • Page 84: Tos Priority Control Register 5 (0X01E - 0X1F): Tosr5

    Micrel, Inc. KSZ8852HLE TOS Priority Control Register 4 (0x01C - 0x1D): TOSR4 (Continued) Default Description DSCP[57:56] 9−8 The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic Class value are 0x70. DSCP[55:54] 7−6...

  • Page 85: Tos Priority Control Register 6 (0X020 - 0X021): Tosr6

    Micrel, Inc. KSZ8852HLE TOS Priority Control Register 6 (0x020 - 0x021): TOSR6 This register contains the TOS priority control bits for the switch function. Default Description DSCP[95:94] 15−14 The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic Class value is 0xbc.

  • Page 86: Tos Priority Control Register 8 (0X024 - 0X025): Tosr8

    Micrel, Inc. KSZ8852HLE TOS Priority Control Register 7 (0x022 - 0x023): TOSR7 (Continued) Default Description DSCP[103:102] 7−6 The value in this field is used as the frame’s priority when bits [7:2] of the IP TOS/DiffServ/Traffic Class value are 0xcc. DSCP[101:100] 5−4...

  • Page 87: Indirect Access Data Registers

    Micrel, Inc. KSZ8852HLE Indirect Access Data Registers Indirect Access Data Register 1 (0x026 - 0x027): IADR1 This register is used to indirectly read or write the data in the Management Information Base (MIB) Counters, Static MAC Address Table, Dynamic MAC Address...

  • Page 88: Indirect Access Data Register 5 (0X02E - 0X02F): Iadr5

    Micrel, Inc. KSZ8852HLE Indirect Access Data Register 5 (0x02E - 0x02F): IADR5 This register is used to indirectly read or write the data in the Management Information Base (MIB) Counters, Static MAC Address Table, Dynamic MAC Address Table, or the VLAN Table.

  • Page 89: Power Management Control And Wake-Up Event Status

    Micrel, Inc. KSZ8852HLE Power Management Control and Wake-Up Event Status Power Management Control and Wake-Up Event Status (0x032 – 0x033): PMCTRL This register controls the power management mode and provides Wake-Up event status. Default Description 15−6 0x000 Reserved Wake-Up Frame Detect Status 1 = A wake-up frame has been detected at the host QMU (Write a “1”...

  • Page 90: Power Management Event Enable Register (0X034 - 0X035): Pmee

    Micrel, Inc. KSZ8852HLE Power Management Event Enable Register (0x034 - 0x035): PMEE This register contains the power management event enable control bits. Default Description 15−5 0x000 Reserved PME Polarity: 1 = The PME pin is active high. 0 = The PME pin is active low.

  • Page 91: Go Sleep Time And Clock Tree Power-Down Control Registers

    Micrel, Inc. KSZ8852HLE Go Sleep Time and Clock Tree Power-Down Control Registers Go Sleep Time Register (0x036 - 0x037): GST This register contains the value which is used to control the minimum go−sleep time period when the device transitions from normal power state to low power state in energy detect mode.

  • Page 92: Phy And Mii Basic Control Registers

    [12]). It also determines duplex if auto-negotiation is enabled but fails. When AN is enabled, this bit should be set to zero. Collision Test Not supported. Reserved HP_MDI-X 1 = HP Auto MDI-X mode. Bit [15] in P1SR 0 = Micrel Auto MDI-X mode. June 23, 2014 Revision 1.0...

  • Page 93: Phy 1 And Mii Basic Status Register (0X04E - 0X04F): P1Mbsr

    Micrel, Inc. KSZ8852HLE PHY 1 and MII Basic Control Register (0x04C - 0x04D): P1MBCR (Continued) Default Description Bit is Same As: Force MDI-X 1 = Force MDI-X. Bit [9] in P1CR4 0 = Normal operation. Disable Auto MDI-X 1 = Disable Auto MDI-X.

  • Page 94: Phy 1 Phyid Low Register (0X050 - 0X051): Phy1Ilr

    Micrel, Inc. KSZ8852HLE PHY 1 and MII Basic Status Register (0x04E - 0x04F): P1MBSR (Continued) Default Description Bit is Same As: Auto-Negotiation Complete 1 = Auto-negotiation complete. Bit [6] in P1SR 0 = Auto-negotiation not completed. Reserved Bit [8] in P1SR Auto-Negotiation Capable 1 = Auto-negotiation capable.

  • Page 95: Phy 1 Auto-Negotiation Advertisement Register (0X054 - 0X055): P1Anar

    Micrel, Inc. KSZ8852HLE PHY 1 Auto-Negotiation Advertisement Register (0x054 - 0x055): P1ANAR This register contains the auto-negotiation advertisement bits for the switch Port 1 function. Default Description Bit is Same As: Next page Not supported. Reserved Remote fault Not supported.

  • Page 96: Phy 1 Auto−Negotiation Link Partner Ability Register (0X056 - 0X057): P1Anlpr

    Micrel, Inc. KSZ8852HLE PHY 1 Auto−Negotiation Link Partner Ability Register (0x056 - 0x057): P1ANLPR This register contains the auto−negotiation link partner ability bits for the switch Port 1 function. Default Description Bit is Same As: Next page Not supported. LP ACK Not supported.
  • Page 97 Collision Test Not supported. Reserved HP_MDI-X 1 = HP Auto MDI-X mode. Bit [15] in P2SR 0 = Micrel Auto MDI-X mode. Force MDI-X 1 = Force MDI-X. Bit [9] in P2CR4 0 = Normal operation. Disable Auto MDI-X 1 = Disable Auto MDI-X.

  • Page 98: Phy 2 And Mii Basic Status Register (0X05A - 0X05B): P2Mbsr

    Micrel, Inc. KSZ8852HLE PHY 2 and MII Basic Status Register (0x05A - 0x05B): P2MBSR This register contains the Media Independent Interface (MII) status bits for the switch Port 2 function Default Description Bit is Same As: T4 Capable 1 = 100BASE-T4 capable.

  • Page 99: Phy2 Phyid Low Register (0X05C - 0X05D): Phy2Ilr

    Micrel, Inc. KSZ8852HLE PHY2 PHYID Low Register (0x05C - 0x05D): PHY2ILR This register contains the PHY ID (low) for the switch Port 2 function. Default Description PHY 2 ID Low Word 15−0 0x1430 Low order PHY 2 ID bits. PHY 2 PHYID High Register (0x05E - 0x05F): PHY2IHR This register contains the PHY ID (high) for the switch Port 2 function.

  • Page 100: Phy 2 Auto-Negotiation Link Partner Ability Register (0X062 -0X063): P2Anlpr

    Micrel, Inc. KSZ8852HLE PHY 2 Auto-Negotiation Link Partner Ability Register (0x062 -0x063): P2ANLPR This register contains the auto-negotiation link partner ability bits for the switch Port 2 function. Default Description Bit is Same As: Next page Not supported. LP ACK Not supported.

  • Page 101: Phy2 Special Control And Status Register (0X06A - 0X06B): P2Phyctrl

    Micrel, Inc. KSZ8852HLE PHY2 Special Control and Status Register (0x06A - 0x06B): P2PHYCTRL This register contains control and status information of PHY 2. Default Description Bit is Same As: 15-6 0x000 Reserved Polarity Reverse 1 = Polarity is reversed. Bit [13] in P2SR 0 = Polarity is not reversed.

  • Page 102: Port 1 Control Registers

    Micrel, Inc. KSZ8852HLE Port 1 Control Registers Port 1 Control Register 1 (0x06C - 0x06D): P1CR1 This register contains control bits for the switch Port 1 function. Default Description Reserved Port 1 LED Direct Control These bits directly control the Port 1 LED pins.
  • Page 103 Micrel, Inc. KSZ8852HLE Port 1 Control Register 1 (0x06C - 0x06D): P1CR1 (Continued) Default Description Port−Based Priority Classification 00 = Ingress packets on Port 1 are classified as priority 0 queue if “DiffServ” or “802.1p” classification is not enabled or fails to classify.

  • Page 104: Port 1 Control Register 2 (0X06E - 0X06F): P1Cr2

    Micrel, Inc. KSZ8852HLE Port 1 Control Register 2 (0x06E - 0x06F): P1CR2 This register contains control bits for the switch Port 1 function. Default Description Reserved Ingress VLAN Filtering 1 = The switch discards packets whose VID port membership in VLAN table bits [18:16] does not include the ingress port VID.

  • Page 105: Port 1 Vid Control Register (0X070 - 0X071): P1Vidcr

    Micrel, Inc. KSZ8852HLE Port 1 VID Control Register (0x070 - 0x071): P1VIDCR This register contains the control bits for the switch Port 1 function. This register has two main uses. It is associated with the ingress of untagged packets and used for egress tagging as well as being used for address lookup and providing a default VID for the ingress of untagged or null−VID−tagged packets.

  • Page 106: Port 1 Ingress Rate Control Register 0 (0X074 - 0X075): P1Ircr0

    Micrel, Inc. KSZ8852HLE Port 1 Ingress Rate Control Register 0 (0x074 - 0x075): P1IRCR0 This register contains the Port 1 ingress rate limiting control for priority 1 and priority 0. Description Default Reserved Ingress Data Rate Limit for Priority 1 Frames 14−8...

  • Page 107: Port 1 Ingress Rate Control Register 1 (0X076 - 0X077): P1Ircr1

    Micrel, Inc. KSZ8852HLE Port 1 Ingress Rate Control Register 1 (0x076 - 0x077): P1IRCR1 This register contains the Port 1 ingress rate limiting control bits for priority 3 and priority 2. Default Description Reserved Ingress Data Rate Limit for Priority 3 Frames 14−8...

  • Page 108: Port 1 Phy Special Control/Status, Linkmd (0X07C - 0X07D): P1Scslmd

    Micrel, Inc. KSZ8852HLE Port 1 PHY Special Control/Status, LinkMD (0x07C - 0x07D): P1SCSLMD This register contains the LinkMD control and status information of PHY 1. Default Description Bit is Same As: CDT_10m_Short 1 = Less than 10 meter short. CDT_Result [00] = Normal condition.

  • Page 109: Port 1 Control Register 4 (0X07E - 0X07F): P1Cr4

    Micrel, Inc. KSZ8852HLE Port 1 Control Register 4 (0x07E - 0x07F): P1CR4 This register contains the control bits for the switch Port 1 function. Default Description Bit is Same As: Reserved Disable Transmit 1 = Disable the port’s transmitter. Bit [1] in P1MBCR 0 = Normal operation.

  • Page 110: Port 1 Status Register (0X080 - 0X081): P1Sr

    Default Description Bit is Same As: HP_MDI-X 1 = HP Auto-MDI-X mode. Bit [5] in P1MBCR 0 = Micrel Auto-MDI-X mode. Reserved Polarity Reverse 1 = Polarity is reversed. Bit [5] in P1PHYCTRL 0 = Polarity is not reversed. Transmit Flow Control Enable 1 = Transmit flow control feature is active.

  • Page 111: 0X082 - 0X083: Reserved

    Micrel, Inc. KSZ8852HLE Port 1 Status Register (0x080 - 0x081): P1SR (Continued) Default Description Bit is Same As: Operation Speed 1 = Link speed is 100Mbps. 0 = Link speed is 10Mbps. Operation Duplex 1 = Link duplex is full.

  • Page 112: Port 2 Control Registers

    Micrel, Inc. KSZ8852HLE Port 2 Control Registers Port 2 Control Register 1 (0x084 - 0x085): P2CR1 This register contains control bits for the switch Port 2 function. Default Description Reserved Port 2 LED Direct Control These bits directly control the Port 2 LED pins.
  • Page 113 Micrel, Inc. KSZ8852HLE Port 2 Control Register 1 (0x084 - 0x085): P2CR1 (Continued) Default Description Port-Based Priority Classification 00 = Ingress packets on Port 2 are classified as priority 0 queue if “DiffServ” or “802.1p” classification is not enabled or fails to classify.

  • Page 114: Port 2 Control Register 2 (0X086 - 0X087): P2Cr2

    Micrel, Inc. KSZ8852HLE Port 2 Control Register 2 (0x086 - 0x087): P2CR2 This register contains the control bits for the switch Port 2 function. Default Description Reserved Ingress VLAN Filtering 1 = The switch discards packets whose VID port membership in VLAN table bits [18:16] does not include the ingress port VID.

  • Page 115: Port 2 Vid Control Register (0X088 - 0X089): P2Vidcr

    Micrel, Inc. KSZ8852HLE Port 2 Control Register 2 (0x086 - 0x087): P2CR2 (Continued) Default Description User Priority Ceiling 1 = If the packet’s “priority field” is greater than the “user priority field” in the port VID control register bit[15:13], replace the packet’s “priority field” with the “user priority field”...

  • Page 116: Port 2 Ingress Rate Control Register 0 (0X08C - 0X08D): P2Ircr0

    Micrel, Inc. KSZ8852HLE Port 2 Control Register 3 (0x08A - 0x08B): P2CR3 (Continued) Default Description Count Inter Frame Gap Count IFG Bytes. 1 = Each frame’s minimum inter frame gap. IFG bytes (12 per frame) are included in ingress and egress rate limiting calculations.

  • Page 117: Port 2 Egress Rate Control Register 0 (0X090 - 0X091): P2Ercr0

    Micrel, Inc. KSZ8852HLE Port 2 Egress Rate Control Register 0 (0x090 - 0x091): P2ERCR0 This register contains the Port 2 egress rate limiting control bits for priority 1 and priority 0 frames. Default Description Reserved Egress Data Rate Limit for Priority 1 Frames 14−8...

  • Page 118: Port 2 Phy Special Control/Status, Linkmd (0X094 - 0X095): P2Scslmd

    Micrel, Inc. KSZ8852HLE Port 2 PHY Special Control/Status, LinkMD (0x094 - 0x095): P2SCSLMD This register contains the LinkMD control and status information of PHY 2. Default Description Bit is Same As: CDT_10m_Short 1 = Less than 10 meter short. CDT_Result [00] = Normal condition.

  • Page 119: Port 2 Control Register 4 (0X096 - 0X097): P2Cr4

    Micrel, Inc. KSZ8852HLE Port 2 Control Register 4 (0x096 - 0x097): P2CR4 This register contains the control bits for the switch Port 2 function. Default Description Bit is Same As: Reserved Disable Transmit 1 = Disable the port’s transmitter. Bit[1] in P2MBCR 0 = Normal operation.
  • Page 120 Micrel, Inc. KSZ8852HLE Port 2 Control Register 4 (0x096 - 0x097): P2CR4 (Continued) Default Description Bit is Same As: Force Duplex 1 = Force full duplex if auto-negotiation is disabled. Bit [8] in P2MBCR 0 = Force half duplex if auto-negotiation is disabled.

  • Page 121: Port 2 Status Register (0X098 - 0X099): P2Sr

    Description Bit is Same As: HP_MDIX 1 = HP Auto MDI-X mode. Bit [5] in P2MBCR 0 = Micrel Auto MDI-X mode. Reserved Polarity Reverse 1 = Polarity is reversed. Bit [5] in P2PHYCTRL 0 = Polarity is not reversed.

  • Page 122: 0X09A - 0X09B: Reserved

    Micrel, Inc. KSZ8852HLE Port 2 Status Register (0x098 - 0x099): P2SR (Continued) Default Description Bit is Same As: Partner 100BT Half-Duplex Capability 1 = Link partner 100BT half-duplex capable. Bit [7] in P2ANLPR 0 = Link partner not 100BT half-duplex capable.

  • Page 123: Port 3 Control Registers

    Micrel, Inc. KSZ8852HLE Port 3 Control Registers Port 3 Control Register 1 (0x09C - 0x09D): P3CR1 This register contains control bits for the switch Port 3 function. Default Description 15−10 0x00 Reserved Drop Tagged Packet Enable 1 = Enable to drop tagged ingress packets.

  • Page 124: Port 3 Control Register 2 (0X09E - 0X09F): P3Cr2

    Micrel, Inc. KSZ8852HLE Port 3 Control Register 2 (0x09E - 0x09F): P3CR2 This register contains control bits for the switch Port 3 function. Default Description Reserved Ingress VLAN Filtering 1 = The switch discards packets whose VID port membership in VLAN table bits [18:16] does not include the ingress port VID.

  • Page 125: Port 3 Vid Control Register (0X0A0 - 0X0A1): P3Vidcr

    Micrel, Inc. KSZ8852HLE Port 3 VID Control Register (0x0A0 - 0x0A1): P3VIDCR This register contains control bits for the switch Port 3 function. This P3VIDCR Control register serves two purposes: 7. Associated with the ingress untagged packets, and used for egress tagging.

  • Page 126: Port 3 Ingress Rate Control Register 0 (0X0A4 - 0X0A5): P3Ircr0

    Micrel, Inc. KSZ8852HLE Port 3 Ingress Rate Control Register 0 (0x0A4 - 0x0A5): P3IRCR0 This register contains the Port 3 ingress rate limiting control bits for priority 1 and priority 0. Default Description Reserved Ingress Data Rate Limit for Priority 1 Frames 14−8...

  • Page 127: Port 3 Egress Rate Control Register 1 (0X0Aa - 0X0Ab): P3Ercr1

    Micrel, Inc. KSZ8852HLE Port 3 Egress Rate Control Register 1 (0x0AA - 0x0AB): P3ERCR1 This register contains the Port 3 egress rate limiting control bits for priority 3 and priority 2. Default Description Reserved Egress Data Rate Limit for Priority 3 Frames 14−8...

  • Page 128: Switch Global Control Registers

    Micrel, Inc. KSZ8852HLE Switch Global Control Registers Switch Global Control Register 8 (0x0AC - 0x0AD): SGCR8 This register contains the global control bits for the switch function. Default Description Two Queue Priority Mapping These bits determine the mapping between the priority of the incoming frames and the destination on- chip queue in a two queue configuration which uses egress queues 0 and 1.

  • Page 129: Switch Global Control Register 9 (0X0Ae - 0X0Af): Sgcr9

    Micrel, Inc. KSZ8852HLE Switch Global Control Register 9 (0x0AE - 0x0AF): SGCR9 This register contains the global control bits for the switch function. Default Description 15−11 0x00 Reserved Forwarding Invalid Frame 10−8 Define the forwarding port for frame with invalid VID. Bit [10] stands for the host port, bit [9] for Port 2, and bit [8] for Port 1.

  • Page 130: Source Address Filtering Registers

    Micrel, Inc. KSZ8852HLE Source Address Filtering Registers Source Address Filtering MAC Address 1 Register Low (0x0B0 - 0x0B1): SAFMACA1L Register bit fields for the low word of MAC Address 1. Default Value Description Source Filtering MAC Address1 Low 15−0 0x0000 The least significant word of MAC Address 1.

  • Page 131: Txq Rate Control Registers

    Micrel, Inc. KSZ8852HLE TXQ Rate Control Registers Port 1 TXQ Rate Control Register 1 (0x0C8 - 0x0C9): P1TXQRCR1 This register contains the q2 and q3 rate control bits for Port 1. Default Value Description Port 1 Transmit Queue 2 (high) Ratio Control 0 = Strict priority.

  • Page 132: Port 2 Txq Rate Control Register 1 (0X0Cc - 0X0Cd): P2Txqrcr1

    Micrel, Inc. KSZ8852HLE Port 2 TXQ Rate Control Register 1 (0x0CC - 0x0CD): P2TXQRCR1 This register contains the q2 and q3 rate control bits for Port 2. Default Value Description Port 2 Transmit Queue 2 (high) Ratio Control 0 = Strict priority. Port 2 will transmit all the packets from this priority queue 2 before transmit lower priority queue.

  • Page 133: Port 3 Txq Rate Control Register 1 (0X0D0 - 0X0D1): P3Txqrcr1

    Micrel, Inc. KSZ8852HLE Port 3 TXQ Rate Control Register 1 (0x0D0 - 0x0D1): P3TXQRCR1 This register contains the q2 and q3 rate control bits for Port 3. Default Value Description Port 3 Transmit Queue 2 (high) Ratio Control 0 = Strict priority. Port 3 will transmit all the packets from this priority queue 2 before transmit lower priority queue.

  • Page 134: Auto-Negotiation Next Page Registers

    Micrel, Inc. KSZ8852HLE Auto-Negotiation Next Page Registers Port 1 Auto-Negotiation Next Page Transmit Register (0x0DC - 0x0DD): P1ANPT This register contains the Port 1 auto-negotiation next page transmit related bits. Default Description Next Page Next page (NP) is used by the next page function to indicate whether or not this is the last next page to be transmitted.

  • Page 135: Port 1 Auto-Negotiation Link Partner Received Next Page Register (0X0De - 0X0Df): P1Alprnp

    Micrel, Inc. KSZ8852HLE Port 1 Auto-Negotiation Link Partner Received Next Page Register (0x0DE - 0x0DF): P1ALPRNP This register contains the Port 1 auto-negotiation link partner received next page related bits. Default Description Next Page Next Page (NP) is used by the next page function to indicate whether or not this is the last next page to be transmitted.

  • Page 136: Eee And Link Partner Advertisement Registers

    Micrel, Inc. KSZ8852HLE EEE and Link Partner Advertisement Registers Port 1 EEE and Link Partner Advertisement Register (0x0E0 – 0x0E1): P1EEEA This register contains the Port 1 EEE advertisement and link partner advertisement information. Default Description Reserved 10GBASE-KR EEE 1 = Link Partner EEE is supported for 10GBASE-KR.

  • Page 137: Port 1 Eee Wake Error Count Register (0X0E2 - 0X0E3): P1Eeewec

    Micrel, Inc. KSZ8852HLE Port 1 EEE Wake Error Count Register (0x0E2 - 0x0E3): P1EEEWEC This register contains the Port 1 EEE wake error count information. Default Value Description Port 1 EEE Wake Error Count This counter is incremented by each transition of lpi_wake_timer_done from FALSE to TRUE. It 15−0...
  • Page 138 Micrel, Inc. KSZ8852HLE Port 1 EEE Control/Status and Auto−Negotiation Expansion Register (0x0E4 - 0x0E5): P1EEECS (Continued) Default Description RX LPI Indication 1 = Indicates that the receive PCS is currently receiving low power idle (LPI) signals. 0 = Indicates that the PCS is not currently receiving low power idle (LPI) signals.

  • Page 139: Port 1 Lpi Recovery Time Counter Register (0X0E6): P1Lpirtc

    Micrel, Inc. KSZ8852HLE Port 1 LPI Recovery Time Counter Register (0x0E6): P1LPIRTC This register contains the Port 1 LPI recovery time counter information. Default Value Description Port 1 LPI Recovery Time Counter This register specifies the time that the MAC device has to wait before it can start to send out 7−0...

  • Page 140: Port 2 Auto-Negotiation Link Partner Received Next Page Register (0X0Ea - 0X0Eb): P2Alprnp

    Micrel, Inc. KSZ8852HLE Port 2 Auto-Negotiation Link Partner Received Next Page Register (0x0EA - 0x0EB): P2ALPRNP This register contains the Port 2 auto-negotiation link partner received next page related bits. Default Description Next Page Next page (NP) is used by the next page function to indicate whether or not this is the last next page to be transmitted.

  • Page 141: Port 2 Eee Wake Error Count Register (0X0Ee - 0X0Ef): P2Eeewec

    Micrel, Inc. KSZ8852HLE Default Description 10GBASE-T EEE 1 = Link Partner EEE is supported for 10GBASE-T. 0 = Link Partner EEE is not supported for 10GBASE-T. 1000BASE-T EEE 1 = Link Partner EEE is supported for 1000BASE-T. 0 = Link Partner EEE is not supported for 1000BASE-T.

  • Page 142: Port 2 Eee Control/Status And Auto-Negotiation Expansion Register (0X0F0 - 0X0F1): P2Eeecs

    Micrel, Inc. KSZ8852HLE Port 2 EEE Control/Status and Auto-Negotiation Expansion Register (0x0F0 - 0x0F1): P2EEECS This register contains the Port 2 EEE control/status and auto-negotiation expansion information. Default Description Reserved Hardware 100BT EEE Enable Status 1 = 100BT EEE is enabled by hardware based NP exchange.

  • Page 143: Port 2 Lpi Recovery Time Counter Register (0X0F2): P2Lpirtc

    Micrel, Inc. KSZ8852HLE Port 2 EEE Control/Status and Auto-Negotiation Expansion Register (0x0F0 - 0x0F1): P2EEECS (Continued) Default Description Reserved Received Next Page Location Able 1 = Received next page storage location is specified by bits [6:5]. 0 = Received next page storage location is not specified by bits [6:5].

  • Page 144: Pcs Eee Control Register (0X0F3): Pcseeec

    Micrel, Inc. KSZ8852HLE PCS EEE Control Register (0x0F3): PCSEEEC This register contains the PCS EEE control information. Default Description Reserved Reserved 5−2 Reserved Port 2 Next Page Enable 1 = Enable next page exchange during auto-negotiation. 0 = Skip next page exchange during auto-negotiation.

  • Page 145: Internal I/O Register Space Mapping For Interrupts, Biu, And Global Reset (0X100 - 0X1Ff)

    Micrel, Inc. KSZ8852HLE Internal I/O Register Space Mapping for Interrupts, BIU, and Global Reset (0x100 - 0x1FF) 0x100 - 0x107: Reserved Chip Configuration Register (0x108 - 0x109): CCR This register indicates the chip configuration mode based on strapping and bonding options.

  • Page 146: Host Mac Address Registers: Marl, Marm And Marh

    Micrel, Inc. KSZ8852HLE Host MAC Address Registers: MARL, MARM and MARH These host MAC address registers are loaded starting at word location 0x1 of the EEPROM upon hardware reset. The software driver can read or write these registers values, but it will not modify the original host MAC address values in the EEPROM.

  • Page 147: Eeprom Control Register (0X122 - 0X123): Eepcr

    Micrel, Inc. KSZ8852HLE EEPROM Control Register (0x122 - 0x123): EEPCR To support an external EEPROM, the PME/EEPROM pin should be pulled−up to high; otherwise, it should be pulled−down to low. If an external EEPROM is not used, the software should program the host MAC address. If an EEPROM is used in the design, the chip host MAC address can be loaded from the EEPROM immediately after reset.

  • Page 148: Global Reset Register (0X126 - 0X127): Grr

    Micrel, Inc. KSZ8852HLE Memory BIST Info Register (0x124 - 0x125): MBIR (Continued) Default Value Description RXMBF RX Memory BIST Completed − 0 = Completion has not occurred for the Memory built-in self-test 1 = Indicates completion of the RX Memory built-in self-test.

  • Page 149: Wake-Up Frame Control Register (0X12A - 0X12B): Wfcr

    Micrel, Inc. KSZ8852HLE Wake-Up Frame Control Register (0x12A - 0x12B): WFCR This register holds control information programmed by the CPU to control the Wake-Up frame function. Default Value Description 15−8 0x00 Reserved MPRXE Magic Packet RX Enable When set, it enables the Magic Packet pattern detection.

  • Page 150: Wake-Up Frame 0 Crc1 Register (0X132- 0X133): Wf0Crc1

    Micrel, Inc. KSZ8852HLE Wake-Up Frame 0 CRC1 Register (0x132- 0x133): WF0CRC1 This register contains the expected CRC values of the Wake-Up frame 0 pattern. The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard; it is taken over the bytes specified in the Wake-Up byte mask registers.

  • Page 151: Wake-Up Frame 1 Crc0 Register (0X140 - 0X141): Wf1Crc0

    Micrel, Inc. KSZ8852HLE Wake-Up Frame 1 CRC0 Register (0x140 – 0x141): WF1CRC0 This register contains the expected CRC values of the Wake-Up frame 1 pattern. The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard; it is taken over the bytes specified in the Wake-Up byte mask registers.

  • Page 152: Wake-Up Frame 1 Byte Mask 2 Register (0X148 - 0X149): Wf1Bm2

    Micrel, Inc. KSZ8852HLE Wake-Up Frame 1 Byte Mask 2 Register (0x148 – 0x149): WF1BM2 This register contains the next 16 bytes mask values of the Wake-Up frame 1 pattern. Setting bit [0] selects the 33rd byte of the Wake-Up frame 1. Setting bit [15] selects the 48th byte of the Wake-Up frame 1.

  • Page 153: Wake-Up Frame 2 Byte Mask 1 Register (0X156 - 0X157): Wf2Bm1

    Micrel, Inc. KSZ8852HLE Wake-Up Frame 2 Byte Mask 1 Register (0x156 – 0x157): WF2BM1 This register contains the next 16 bytes mask values of the Wake-Up frame 2 pattern. Setting bit [0] selects the 17th byte of the Wake-Up frame 2. Setting bit [15] selects the 32nd byte of the Wake-Up frame 2.

  • Page 154: Wake-Up Frame 3 Crc0 Register (0X160 - 0X161): Wf3Crc0

    Micrel, Inc. KSZ8852HLE Wake-Up Frame 3 CRC0 Register (0x160 – 0x161): WF3CRC0 This register contains the expected CRC values of the Wake-Up frame 3 pattern. The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in the Wake-Up byte mask registers.

  • Page 155: Wake-Up Frame 3 Byte Mask 3 Register (0X16A - 0X16B): Wf3Bm3

    Micrel, Inc. KSZ8852HLE Wake-Up Frame 3 Byte Mask 3 Register (0x16A - 0x16B): WF3BM3 This register contains the last 16 bytes mask values of the Wake-Up frame 3 pattern. Setting bit [0] selects the 49th byte of the Wake-Up frame 3. Setting bit [15] selects the 64th byte of the Wake-Up frame 3.

  • Page 156: Internal I/O Register Space Mapping For The Queue Management Unit (Qmu) (0X170 - 0X1Ff)

    Micrel, Inc. KSZ8852HLE Internal I/O Register Space Mapping for the Queue Management Unit (QMU) (0x170 - 0x1FF) Transmit Control Register (0x170 - 0x171): TXCR This register holds control information programmed by the CPU to control the QMU transmit module function.

  • Page 157: Transmit Status Register (0X172 - 0X173): Txsr

    Micrel, Inc. KSZ8852HLE Transmit Status Register (0x172 - 0x173): TXSR This register keeps the status of the last transmitted frame in the QMU transmit module. Default Value Description 15−14 Reserved TXLC Transmit Late Collision This bit is set when a transmit late collision occurs.

  • Page 158: Receive Control Register 2 (0X176 - 0X177): Rxcr2

    Micrel, Inc. KSZ8852HLE Receive Control Register 1 (0x174 - 0x175): RXCR1 (Continued) Default Value Description RXBE Receive Broadcast Enable When this bit is set, the RX module is enabled to receive all the broadcast frames. RXME Receive Multicast Enable When this bit is set, the RX module is enabled to receive all the multicast frames (including broadcast frames).

  • Page 159: Txq Memory Information Register (0X178 - 0X179): Txmir

    Micrel, Inc. KSZ8852HLE Receive Control Register 2 (0x176 - 0x177): RXCR2 (Continued) Default Value Description RXICMPFCC Receive ICMP Frame Checksum Check Enable While this bit is set, any received ICMP frame (only a non−fragmented frame) with an incorrect checksum will be discarded. If this bit is not set, the frame will not be discarded even though there is an ICMP checksum error.

  • Page 160: Receive Frame Header Byte Count Register (0X17E - 0X17F): Rxfhbcr

    Micrel, Inc. KSZ8852HLE Receive Frame Header Status Register (0x17C - 0x17D): RXFHSR (Continued) Default Value Description RXBF Receive Broadcast Frame − When this bit is set, it indicates that this frame has a broadcast address. RXMF Receive Multicast Frame −...

  • Page 161: Txq Command Register (0X180 - 0X181): Txqcr

    Micrel, Inc. KSZ8852HLE TXQ Command Register (0x180 - 0x181): TXQCR This register is programmed by the host CPU to issue a transmit command to the TXQ. The present transmit frame in the TXQ memory is queued for transmit. Default Value Description 15−3...

  • Page 162: Tx Frame Data Pointer Register (0X184 - 0X185): Txfdpr

    Micrel, Inc. KSZ8852HLE RXQ Command Register (0x182 - 0x183): RXQCR (Continued) Default Value Description RXDBCTE RX Data Byte Count Threshold Enable When this bit is written as “1”, the device will enable the RX interrupt (bit [13] in ISR) when the number of received bytes in the RXQ buffer exceeds the threshold set in the RX Data Byte Count Threshold register (0x18E, RXDBCTR).

  • Page 163: Rx Frame Data Pointer Register (0X186 - 0X187): Rxfdpr

    Micrel, Inc. KSZ8852HLE RX Frame Data Pointer Register (0x186 - 0x187): RXFDPR Bits [10:0] of this register determine the address to be accessed within the RXQ frame buffer. When the auto increment function is set, it will automatically increment the RXQ Pointer on read accesses to the data register. The counter is incremented is by one for every byte access, by two for every word access, and by four for every double word access.

  • Page 164: Internal I/O Register Space Mapping For Interrupt Registers (0X190 - 0X193)

    Micrel, Inc. KSZ8852HLE Internal I/O Register Space Mapping for Interrupt Registers (0x190 - 0x193) Interrupt Enable Register (0x190 - 0x191): IER This register enables the interrupts from the QMU and other sources. Default Value Description LCIE Link Change Interrupt Enable 1 = When this bit is set, the link change interrupt is enabled.

  • Page 165: Interrupt Status Register (0X192-- 0X193): Isr

    Micrel, Inc. KSZ8852HLE Interrupt Enable Register (0x190 - 0x191): IER (Continued) Default Value Description RXMPDIE Receive Magic Packet Detect Interrupt Enable 1 = When this bit is set, the receive Magic Packet detect interrupt is enabled. 0 = When this bit is reset, the receive Magic Packet detect interrupt is disabled.

  • Page 166: 0X194 - 0X19B: Reserved

    Micrel, Inc. KSZ8852HLE Interrupt Status Register (0x192 - 0x193): ISR (Continued) Default Value Description TXPSIS Transmit Process Stopped Interrupt Status RO (W1C) When this bit is set, it indicates that the transmit process has stopped. This edge-triggered interrupt status is cleared by writing a “1” to this bit.

  • Page 167: Internal I/O Register Space Mapping For The Queue Management Unit (Qmu) (0X19C - 0X1B9)

    Micrel, Inc. KSZ8852HLE Internal I/O Register Space Mapping for the Queue Management Unit (QMU) (0x19C - 0x1B9) RX Frame Count and Threshold Register (0x19C -0x19D): RXFCTR This register is used to program the received frame count threshold. Default Value Description 15−8...

  • Page 168: Mac Address Hash Table Register 1 (0X1A2 - 0X1A3): Mahtr1

    Micrel, Inc. KSZ8852HLE MAC Address Hash Table Register 1 (0x1A2 - 0x1A3): MAHTR1 Multicast Table Register 1 Default Value Description HT1 Hash Table 1 When the appropriate bit is set, if the packet received with DA matches the CRC, the hashing function is received without being filtered.

  • Page 169: Flow Control High Water Mark Register (0X1B2 - 0X1B3): Fchwr

    Micrel, Inc. KSZ8852HLE Flow Control High Water Mark Register (0x1B2 - 0x1B3): FCHWR This register is used to control the flow control for high water mark in QMU RX queue. Default Value Description 15−12 − Reserved FCHWC Flow Control High Water Mark Configuration 11−0...

  • Page 170: 0X1Ba - 0X747: Reserved

    Micrel, Inc. KSZ8852HLE RX Frame Count Register (0x1B8 - 0x1B9): RXFC This register indicates the current total amount of received frame count in RXQ frame buffer Default Value Description RXFC RX Frame Count Indicates the total received frames in RXQ frame buffer when the receive interrupt (bit [13] = 15−8...

  • Page 171: Management Information Base (Mib) Counters

    Micrel, Inc. KSZ8852HLE Management Information Base (MIB) Counters The KSZ8852 provides 34 MIB counters for each port. These counters are used to monitor the port activity for network management. The MIB counters are formatted “per port” and “all ports dropped packet” as shown in Table Table 21.

  • Page 172: Table 22. Port 1 Mib Counters - Indirect Memory Offset

    Micrel, Inc. KSZ8852HLE Table 22. Port 1 MIB Counters - Indirect Memory Offset Offset Counter Name Description RxLoPriorityByte Rx lo-priority (default) octet count including bad packets RxHiPriorityByte Rx hi-priority octet count including bad packets RxUndersizePkt Rx undersize packets w/ good CRC...

  • Page 173: Mib Counter Examples

    Micrel, Inc. KSZ8852HLE Table 23. "All Ports Dropped Packet" MIB Counter Format Default Description 30−16 − Reserved 15−0 0x0000 Counter Value Note: “All ports dropped packet” MIB Counters do not indicate overflow or validity; therefore, the application must keep track of overflow and valid conditions.“...

  • Page 174: Static Mac Address Table

    Micrel, Inc. KSZ8852HLE Static MAC Address Table The KSZ8852 supports both a static and a dynamic MAC address table. In response to a destination address (DA) look up, the KSZ8852 searches both tables to make a packet forwarding decision. In response to a source address (SA) look up, only the dynamic table is searched for aging, migration and learning purposes.

  • Page 175: Static Mac Table Lookup Examples

    Micrel, Inc. KSZ8852HLE Static MAC Table Lookup Examples: 12. Static Address Table Read (read the second entry at indirect address offset 0x01) Write to Reg. IACR with 0x1001 (set indirect address and trigger a read static MAC table operation) Then: Read Reg.

  • Page 176: Dynamic Mac Address Table

    Micrel, Inc. KSZ8852HLE Dynamic MAC Address Table The Dynamic MAC Address (Table 26) is a read only table. Table 26. Dynamic MAC Address Table Format (1024 Entries) Default Value Description Data Not Ready 1 = Specifies that the entry is not ready, continue retrying until bit is set to “0”.

  • Page 177: Vlan Table

    Micrel, Inc. KSZ8852HLE VLAN Table The KSZ8852 uses the VLAN table to perform look-ups. If 802.1Q VLAN mode is enabled (SGCR2[15]), this table will be used to retrieve the VLAN information that is associated with the ingress packet. This information includes FID (Filter ID),...

  • Page 178: Absolute Maximum Ratings

    Micrel, Inc. KSZ8852HLE Operating Ratings Absolute Maximum Ratings Supply Voltage Supply Voltage (VDD_A3.3, VDD_IO) ..–0.5V to +5.0V VDD_A3.3 ........+3.135V to +3.465V Supply Voltage (VDD_AL, VDD_L) ....–0.5V to +1.8V VDD_L, VDD_AL, VDD_COL ....+1.25V to +1.4V Input Voltage (All Inputs) ......–0.5V to +5.0V VDD_IO (3.3V) ......
  • Page 179 Micrel, Inc. KSZ8852HLE Electrical Characteristics (Continued) Symbol Condition Parameter/Symbol Min. Typ. Max. Units Supply Current for 100BASE-TX Operation (Internal Low Voltage Regulator Off; VDD_A3.3 and VDD_IO = 3.3V; VDD_L, VDD_AL and VDD_COL = 1.4V) VDD_A3.3 VDD_IO 100% Traffic on both ports...
  • Page 180 Micrel, Inc. KSZ8852HLE Symbol Condition Parameter/Symbol Units Supply Current for 10BASE-T Operation (Internal Low Voltage Regulator On; VDD_A3.3 = 3.3V, VDD_IO = 3.3V) VDD_A3.3 100% traffic on both ports VDD_IO PDISS Device VDD_A3.3 Link, no traffic on both ports VDD_IO...
  • Page 181 Micrel, Inc. KSZ8852HLE Electrical Characteristics (Continued) Symbol Parameter Conditions Min. Typ. Max. Units VDD_IO = 2.5V or 3.3V; internal Output Voltage at VDD_L regulator enabled; measured at pins 1.32 40 and 51 CMOS Inputs (VDD_IO = 3.3V/2.5V/1.8V) Input High Voltage 2.1/1.7/1.3...
  • Page 182 Micrel, Inc. KSZ8852HLE Electrical Characteristics (Continued) Symbol Parameter Conditions Min. Typ. Max. Units I/O Pin Internal Pull-Up and Pull-Down Effective Resistance I/O Pin Effective Pull-Up R1.8PU Resistance kΩ VDD_IO = 1.8V I/O Pin Effective Pull-Down R1.8PD Resistance I/O Pin Effective Pull-Up R2.5PU...

  • Page 183: Timing Specifications

    Micrel, Inc. KSZ8852HLE Timing Specifications Host Interface Read / Write Timing Figure 16. Host Interface Read/Write Timing Table 28. Host Interface Read/Write Timing Parameters Symbol Description Min. Typ. Max. Unit CSN, CMD valid to RDN, WRN active RDN active to Read Data SD[15:0] valid Note: This is the SD output delay after RDN becomes active until valid read data is available.

  • Page 184: Auto−Negotiation Timing

    Micrel, Inc. KSZ8852HLE Auto−Negotiation Timing Figure 17. Auto-Negotiation Timing Table 29. Auto-Negotiation Timing Parameters Timing Parameter Description Min. Typ. Max. Unit FLP burst to FLP burst FLP burst width FLPW Clock/Data pulse width Clock pulse to data pulse 55.5 69.5 µs...

  • Page 185: Serial Eeprom Interface Timing

    Micrel, Inc. KSZ8852HLE Serial EEPROM Interface Timing Figure 18. Serial EEPROM Timing Table 30. Serial EEPROM Timing Parameters Timing Parameter Description Min. Typ. Max. Unit fSCL EESK Clock Frequency Setup Time for Start Bit Hold Time for Start Bit Hold Time for Data...

  • Page 186: Reset Timing And Power Sequencing

    Micrel, Inc. KSZ8852HLE Reset Timing and Power Sequencing The KSZ8852 reset timing requirement is summarized in Figure 19 Table Figure 19. KSZ8852 Reset and Power Sequence Timing (8, 9, 10) Table 31. Reset Timing Parameters Timing Parameter Description Min. Max.

  • Page 187: Reset Circuit Guidelines

    Micrel, Inc. KSZ8852HLE Reset Circuit Guidelines Figure 20 is the recommended reset circuit for powering up the KSZ8852 device if reset is triggered by the power supply. Figure 20. Sample Reset Circuit Figure 21 is the recommended reset circuit for applications where reset is driven by another device (e.g., CPU or FPGA).

  • Page 188: Reference Circuits - Led Strap-In Pins

    Micrel, Inc. KSZ8852HLE Reference Circuits – LED Strap-In Pins The pull−up and pull−down reference circuits for the P1LED0/H816 and P2LED0/LEBE strapping pins are shown in Figure The supply voltage for the LEDs must be at least ~2.2V, depending on the particular LED and the load resistor used. If VDD_IO is 1.8V, then a different (higher voltage) supply must be used for the LEDs.

  • Page 189: Reference Clock - Connection And Selection

    Micrel, Inc. KSZ8852HLE Reference Clock – Connection and Selection Figure 23 shows a crystal or external clock source, such as an oscillator, as the reference clock for the KSZ8852. The reference clock is 25MHz for all operating modes of the KSZ8852. If an oscillator is used, connect it to X1, and leave X2 unconnected.

  • Page 190: Selection Of Isolation Transformers

    Micrel, Inc. KSZ8852HLE Selection of Isolation Transformers A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common−mode choke is recommended for exceeding FCC requirements. Table 33 gives recommended transformer characteristics. Table 33. Transformer Selection Criteria...

  • Page 191: Package Information And Recommended Landing Pattern

    Micrel, Inc. KSZ8852HLE (11) Package Information and Recommended Landing Pattern 64-Pin 10mm × 10mm LQFP Note: 11. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com. June 23, 2014 Revision 1.0...
  • Page 192 (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.
  • Page 193 Micrel, Inc. KSZ8852HLE Template Revision History Date Change Description/Edits by: Rev. 2007 Previous version 07/09/09 Verified/changed all style fonts to Arial. Fixed margins. Added Feature subheading style. Added Template Revision History. 7/16/09 Changed subheading from 10pt to 11pt; changed subheading 2 from Italic to non-Italic; created subheading 3 which is 10pt Italic.

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