Sign In
Upload
Manuals
Brands
Maxim Manuals
Extender
DS33Z41
User Manuals: Maxim DS33Z41 IMUX Ethernet Mapper
Manuals and User Guides for Maxim DS33Z41 IMUX Ethernet Mapper. We have
1
Maxim DS33Z41 IMUX Ethernet Mapper manual available for free PDF download: User Manual
Maxim DS33Z41 User Manual (167 pages)
Quad IMUX Ethernet Mapper
Brand:
Maxim
| Category:
Extender
| Size: 1 MB
Table of Contents
General Description
1
Table of Contents
2
1 Description
7
C Ommitted
7
2 Feature Highlights
8
General
8
Link Aggregation (Inverse Multiplexing)
8
Hdlc
8
Committed Information Rate (Cir) Controller
8
Support
8
Sdram Interface
9
Mac Interface
9
Microprocessor Interface
9
Test and Diagnostics
9
Specifications Compliance
10
Table 2-1. T1 Related Telecommunications Specifications
10
S Erial I Nterface
8
3 Applications
11
Figure 3-1. Quad T1/E1 SCT to DS33Z41
11
4 Acronyms and Glossary
12
Time Slot Numbering Schemes
12
5 Major Operating Modes
13
6 Block Diagrams
13
Figure 6-1. Detailed Block Diagram
13
7 Pin Descriptions
14
Pin Functional Description
14
Table 7-1. Detailed Pin Descriptions
14
Sdram Controller
18
Jtag Interface
19
Queue Status
19
Power Supplies
20
Figure 7-1. DS33Z41 256-Ball CSBGA Pinout
21
8 Functional Description
22
Processor Interface
23
Read-Write/Data Strobe Modes
23
Clear on Read
23
Interrupt and Pin Modes
23
Clock Structure
24
Table 8-1. Clock Selection for the Ethernet (LAN) Interface
24
Figure 8-1. Clocking for the DS33Z41
25
Ethernet Interface Clock Modes
26
I Nitialization and
27
Reset and
27
Serial Interface Clock Modes
26
Resets and Low-Power Modes
27
Table 8-2. Reset Functions
27
Initialization and Configuration
28
Global Resources
28
Per-Port Resources
28
Device Interrupts
29
Figure 8-2. Device Interrupt Information Flow Diagram
30
Serial Interface
31
Link Aggregation (Imux)
31
Figure 8-3. IMUX Interface to T1/E1 Transceivers
32
Figure 8-4. Diagram of Data Transmission with IMUX Operation
32
Microprocessor Requirements
33
Figure 8-5. Command Structure for IMUX Function
34
IMUX Command Protocol
34
Table 8-3. Commands Sent and Received on the IMUX Links
34
Table 8-4. Command and Status for the IMUX for Processor Communication
35
Data Transfer
36
Out of Frame (OOF) Monitoring
36
Connections and Queues
37
Arbiter
38
Table 8-5. Registers Related to Connections and Queues
38
Flow Control
39
Table 8-6. Options for Flow Control
39
Full-Duplex Flow Control
40
Figure 8-6. Flow Control Using Pause Control Frame
41
Half-Duplex Flow Control
41
Host-Managed Flow Control
41
Ethernet Interface Port
42
Figure 8-7. IEEE 802.3 Ethernet Frame
42
DTE and DCE Mode
43
Table 8-7. Registers Related to the Ethernet Port
43
Figure 8-8. Configured as DTE Connected to an Ethernet PHY in MII Mode
44
Figure 8-9. DS33Z41 Configured as a DCE in MII Mode
45
Nterface
46
Ethernet Mac
46
Table 8-8. MAC Control Registers
46
Table 8-9. MAC Status Registers
46
Figure 8-10. RMII Interface
47
MII Mode
47
RMII Mode
47
PHY MII Management Block and MDIO Interface
48
Bert
48
BERT Features
48
Figure 8-11. MII Management Frame
48
Egister
49
Receive Data Interface
49
Repetitive Pattern Synchronization
49
Figure 8-12. PRBS Synchronization State Diagram
49
Pattern Monitoring
50
Pattern Generation
50
Figure 8-13. Repetitive Pattern Synchronization State Diagram
50
Transmit Packet Processor
52
Receive Packet Processor
53
Encoding and Decoding
55
Figure 8-14. LAPS Encoding of MAC Frames Concept
55
Figure 8-15. X.86 Encapsulation of the MAC Field
56
Committed Information Rate Controller
58
Figure 8-16. CIR in the WAN Transmit Path
59
9 Device Registers
60
Table 9-1. Register Address Map
60
Register Bit Maps
61
Global Register Bit Map
61
Table 9-2. Global Register Bit Map
61
Arbiter Register Bit Map
62
BERT Register Bit Map
62
Table 9-3. Arbiter Register Bit Map
62
Table 9-4. BERT Register Bit Map
62
Serial Interface Register Bit Map
63
Table 9-5. Serial Interface Register Bit Map
63
Ethernet Interface Register Bit Map
65
Table 9-6. Ethernet Interface Register Bit Map
65
MAC Register Bit Map
66
Table 9-7. MAC Indirect Register Bit Map
66
Global Register Definitions
68
Arbiter Registers
81
Arbiter Register Bit Descriptions
81
Bert Registers
82
Serial Interface Registers
89
Serial Interface Transmit and Common Registers
89
Serial Interface Transmit Register Bit Descriptions
89
Transmit HDLC Processor Registers
90
Registers
97
Receive Serial Interface
99
Ethernet Interface Registers
112
Ethernet Interface Register Bit Descriptions
112
MAC Registers
124
10 Functional Timing
140
MII and Rmii Interfaces
140
Figure 10-1. MII Transmit Functional Timing
140
Figure 10-2. MII Transmit Half Duplex with a Collision Functional Timing
140
Figure 10-3. MII Receive Functional Timing
141
Figure 10-4. RMII Transmit Interface Functional Timing
141
Figure 10-5 RMII Receive Interface Functional Timing
141
11 Operating Parameters
142
Table 11-1. Recommended DC Operating Conditions
142
Table 11-2. DC Electrical Characteristics
142
Figure 12-1. JTAG Functional Block Diagram
159
Jtag Tap Controller State Machine Description
160
Figure 12-2. TAP Controller State Diagram
162
Instruction Register
162
Bypass
163
Clamp
163
Extest
163
Highz
163
Idcode
163
Sample:preload
163
Table 12-1. Instruction Codes for IEEE 1149.1 Architecture
163
Boundary Scan Register
164
Bypass Register
164
Identification Register
164
Jtag ID Codes
164
Table 12-2. ID Code Structure
164
Test Registers
164
Figure 12-3. JTAG Functional Timing
165
Jtag Functional Timing
165
Table 11-3. Thermal Characteristics
143
Table 11-4. Theta-JA Vs. Airflow
143
Thermal Characteristics
143
Figure 11-1. Transmit MII Interface
144
MII Interface
144
Table 11-5. Transmit MII Interface
144
Figure 11-2. Receive MII Interface Timing
145
Table 11-6. Receive MII Interface
145
Figure 11-3. Transmit RMII Interface
146
Rmii Interface
146
Table 11-7. Transmit RMII Interface
146
Figure 11-4. Receive RMII Interface Timing
147
Table 11-8. Receive RMII Interface
147
Figure 11-5. MDIO Timing
148
Mdio Interface
148
Table 11-9. MDIO Interface
148
Figure 11-6. Transmit WAN Timing
149
Table 11-10. Transmit WAN Interface
149
Transmit Wan Interface
149
Figure 11-7. Receive WAN Timing
150
Receive Wan Interface
150
Table 11-11. Receive WAN Interface
150
Sdram Timing
151
Table 11-12. SDRAM Interface Timing
151
Figure 11-8. SDRAM Interface Timing
152
Figure 11-9. Receive IBO Channel Interleave Mode Timing
153
Figure 11-10. Transmit IBO Channel Interleave Mode Timing
154
Microprocessor Bus Ac Characteristics
155
Table 11-13. AC Characteristics-Microprocessor Bus Timing
155
Figure 11-11. Intel Bus Read Timing (MODEC = 00)
156
Figure 11-12. Intel Bus Write Timing (MODEC = 00)
156
Figure 11-13. Motorola Bus Read Timing (MODEC = 01)
157
Figure 11-14. Motorola Bus Write Timing (MODEC = 01)
157
Figure 11-15. JTAG Interface Timing Diagram
158
Jtag Interface Timing
158
Table 11-14. JTAG Interface Timing
158
12 Jtag Information
159
13 Package Information
166
MM X 14 MM (56-G6035-001)
166
14 Document Revision History
167
Advertisement
Advertisement
Related Products
Maxim DS33R11
Maxim Maxim DS3232 Series
Maxim Maxim DS3232S
Maxim Maxim DS3232SN
Maxim Dallas Semiconductor DS3171
Maxim Dallas Semiconductor DS3172
Maxim Dallas Semiconductor DS3173
Maxim Dallas Semiconductor DS3174
Maxim DS80C400
Maxim Dallas DS83C530
Maxim Categories
Outdoor Light
Motherboard
Tiller
Kitchen Appliances
Grill
More Maxim Manuals
Login
Sign In
OR
Sign in with Facebook
Sign in with Google
Upload manual
Upload from disk
Upload from URL