Maxim Dallas Semiconductor DS3171 Manuals

Manuals and User Guides for Maxim Dallas Semiconductor DS3171. We have 1 Maxim Dallas Semiconductor DS3171 manual available for free PDF download: General Description Manual

Maxim Dallas Semiconductor DS3171 General Description Manual

Maxim Dallas Semiconductor DS3171 General Description Manual (234 pages)

Brand: Maxim | Category: Transceiver | Size: 1 MB

Table of Contents

1 Block Diagrams

3
2 Applications

12
- Figure 2-1. Four-Port DS3/E3 Line Card
  12
3 Feature Details

13
- Global Features
  13
- Receive Ds3/E3 Liu Features
  13
- Receive Ds3/E3 Framer Features
  13
- Transmit Ds3/E3 Formatter Features
  13
- Transmit Ds3/E3 Liu Features
  14
- Jitter Attenuator Features
  14
- Clock Rate Adapter Features
  14
- Hdlc Overhead Controller Features
  14
- Feac Controller Features
  14
- Trail Trace Buffer Features
  15
- Bit Error Rate Tester (Bert) Features
  15
- Loopback Features
  15
- Microprocessor Interface Features
  15
- Test Features
  15
4 Standards Compliance

16
- Table 4-1. Standards Compliance
  16
5 Acronyms and Glossary

17
6 Major Operational Modes

18
7 Major Line Interface Operating Modes

21
8 Pin Descriptions

25
9 Initialization and Configuration

48
- Monitoring and Debugging
  49
- Table 9-1. Configuration of Port Register Settings
  49
10 Functional Description

50
- Processor Bus Interface
  50
  - 8/16 Bit Bus Widths
    50
  - Ready Signal (RDY)
    50
  - Byte Swap Modes
    50
  - Read-Write / Data Strobe Modes
    50
  - Clear on Read / Clear on Write Modes
    50
  - Global Write Method
    51
  - Interrupt and Pin Modes
    51
  - Interrupt Structure
    51
- Clocks
  52
- Reset and Power-Down
  60
- Figure 10-4. Example IO Pin Clock Muxing
  60
- Figure 10-5. Reset Sources
  61
- Table 10-10. Reset and Power-Down Sources
  62
- Global Resources
  63
- Per Port Resources
  69
- Ds3/E3 Framer / Formatter
  78
- Hdlc Overhead Controller
  96
  - General Description
    96
  - Features
    96
  - Figure 10-20. HDLC Controller Block Diagram
    96
  - Transmit FIFO
    97
  - Transmit HDLC Overhead Processor
    97
  - Receive HDLC Overhead Processor
    98
  - Receive FIFO
    98
- Trail Trace Controller
  99
  - General Description
    99
  - Features
    99
  - Figure 10-21. Trail Trace Controller Block Diagram
    99
  - Functional Description
    100
  - Transmit Data Storage
    100
  - Transmit Trace ID Processor
    100
  - Transmit Trail Trace Processing
    100
  - Receive Trace ID Processor
    100
  - Receive Trail Trace Processing
    101
  - Receive Data Storage
    101
  - Figure 10-22. Trail Trace Byte (DT = Trail Trace Data)
    101
- Feac Controller
  102
  - General Description
    102
  - Features
    102
  - Functional Description
    102
  - Figure 10-23. FEAC Controller Block Diagram
    102
  - Figure 10-24. FEAC Codeword Format
    103
- Line Encoder/Decoder
  104
  - General Description
    104
  - Features
    104
  - B3ZS/HDB3 Encoder
    104
  - Figure 10-25. Line Encoder/Decoder Block Diagram
    104
  - Transmit Line Interface
    105
  - Receive Line Interface
    105
  - B3ZS/HDB3 Decoder
    105
  - Figure 10-26. B3ZS Signatures
    106
  - Figure 10-27. HDB3 Signatures
    106
- Bert
  107
- Liu-Line Interface Unit
  111
  - General Description
    111
  - Features
    111
  - Figure 10-31. LIU Functional Diagram
    111
  - Detailed Description
    112
  - Transmitter
    112
  - Figure 10-32. DS3/E3 LIU Block Diagram
    112
  - Receiver
    113
  - Table 10-33. Transformer Characteristics
    113
  - Table 10-34. Recommended Transformers
    114
  - Figure 10-33. Receiver Jitter Tolerance
    115
11 Overall Register Map

116
- Table 11-1. Global and Test Register Address Map
  117
- Table 11-2. Per Port Register Address Map
  118
12 Register Maps and Descriptions

119
- Registers Bit Maps
  119
  - Global Register Bit Map
    119
  - Table 12-1. Global Register Bit Map
    119
  - Table 12-2. Port Register Bit Map
    120
  - Table 12-3. BERT Register Bit Map
    120
  - Table 12-4. Line Register Bit Map
    121
  - HDLC Register Bit Map
    122
  - Table 12-5. HDLC Register Bit Map
    122
  - Table 12-6. FEAC Register Bit Map
    122
  - Table 12-7. Trail Trace Register Bit Map
    123
  - T3 Register Bit Map
    124
  - E3 G.751 Register Bit Map
    124
  - Table 12-8. T3 Register Bit Map
    124
  - Table 12-9. E3 G.751 Register Bit Map
    124
  - E3 G.832 Register Bit Map
    125
  - Table 12-10. E3 G.832 Register Bit Map
    125
  - Clear Channel Register Bit Map
    126
  - Table 12-11. Clear Channel Register Bit Map
    126
- Global Registers
  127
  - Register Bit Descriptions
    127
  - Table 12-12. Global Register Map
    127
- Per Port Common
  134
  - Register Bit Descriptions
    134
  - Table 12-13. Per Port Common Register Map
    134
- Bert
  144
  - BERT Register Map
    144
  - BERT Register Bit Descriptions
    144
  - Table 12-14. BERT Register Map
    144
- B3ZS/HDB3 Line Encoder/Decoder
  152
- Hdlc
  157
- Feac Controller
  165
- Trail Trace
  170
- Ds3/E3 Framer
  176
13 Jtag Information

210
- Jtag Description
  210
- Figure 13-1. JTAG Block Diagram
  210
- Jtag Tap Controller State Machine Description
  211
- Figure 13-2. JTAG TAP Controller State Machine
  211
- Jtag Instruction Register and Instructions
  213
- Table 13-1. JTAG Instruction Codes
  213
- Jtag ID Codes
  214
- Jtag Functional Timing
  214
- Io Pins
  214
- Figure 13-3. JTAG Functional Timing
  214
- Table 13-2. JTAG ID Codes
  214
14 Pin Assignments

215
15 Package Information

218
- 400-Lead Te-Pbga (27 MM X 27 MM , 1.27 MM Pitch ) (56-G6003-003)
  218
16 Package Thermal Information

219
600 DC Electrical Characteristics

220
18 Ac Timing Characteristics

222
- Figure 18-1. Clock Period and Duty Cycle Definitions
  222
19 Revision History

234

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