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Maxim DS33Z41 User Manual

Quad imux ethernet mapper
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GENERAL DESCRIPTION

The DS33Z41 extends a 10/100 Ethernet LAN
segment by encapsulating MAC frames in HDLC or
X.86 (LAPS) for transmission over up to four
interleaved PDH/TDM data streams using robust,
balanced, and programmable inverse multiplexing.
The Interleave Bus (IBO) serial link supports
seamless bidirectional interconnection with Dallas
Semiconductor's T1/E1 framers and transceivers.
The device performs store-and-forward of packets
with full wire-speed transport capability. The built-in
Committed
Information
provides fractional bandwidth allocation up to the
line rate in increments of 512kbps.
FUNCTIONAL DIAGRAM
Serial
Port
BERT
HDLC/X.86
Mapper
10/100
MAC
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
Rate
(CIR)
Controller
DS33Z41
Up to 4
IBO
Transceivers
or Framers
Config.
Loader
µC
SDRAM
10/100
MII/RMII
Ethernet
PHY
Quad IMUX Ethernet Mapper
FEATURES
10/100 IEEE 802.3 Ethernet MAC (MII and
RMII) Half/Full Duplex with Automatic Flow
Control
Layer 1 Inverse Multiplexing Allows Bonding of
Up to 4 T1/E1/J1 or DSL Links
Supports Up to 7.75ms Differential Delay
Channel (Byte) Interleaved Bus Operation
In-Band OAM and Signaling Capability
HDLC/LAPS Encapsulation with Programmable
FCS, Interframe Fill
Committed Information Rate Controller Provides
Fractional Allocation in 512kbps Increments
Programmable BERT for the Serial Interface
External 16MB, 100MHz SDRAM Buffering
Parallel Microprocessor Interface
1.8V Operation with 3.3V Tolerant I/O
IEEE 1149.1 JTAG Support
Features continued on page 8.
APPLICATIONS
Bonded Transparent LAN Service
LAN Extension
Ethernet Delivery Over T1/E1/J1, T3/E3, OC-1/EC-1,
G.SHDSL, or HDSL2/4
ORDERING INFORMATION
PART
DS33Z41
1 of 167
DS33Z41
TEMP RANGE
PIN-PACKAGE
169 CSBGA
-40°C to +85°C
REV: 122006

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  • Page 1: General Description

    Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. Quad IMUX Ethernet Mapper FEATURES 10/100 IEEE 802.3 Ethernet MAC (MII and...

  • Page 2: Table Of Contents

    DESCRIPTION ...7 FEATURE HIGHLIGHTS ...8 ...8 ENERAL GGREGATION NVERSE HDLC ...8 OMMITTED NFORMATION X.86 S ...8 UPPORT SDRAM I ...9 NTERFACE MAC I ...9 NTERFACE ICROPROCESSOR NTERFACE EST AND IAGNOSTICS 2.10 S PECIFICATIONS COMPLIANCE APPLICATIONS...11 ACRONYMS AND GLOSSARY...12 MAJOR OPERATING MODES ...13 BLOCK DIAGRAMS ...13 PIN DESCRIPTIONS...14 UNCTIONAL...
  • Page 3 8.14 E MAC...46 THERNET 8.14.1 MII Mode ...47 8.14.2 RMII Mode ...47 8.14.3 PHY MII Management Block and MDIO Interface ...48 8.15 BERT ...48 8.15.1 BERT Features ...48 8.15.2 Receive Data Interface ...49 8.15.3 Repetitive Pattern Synchronization...49 8.15.4 Pattern Monitoring...50 8.15.5 Pattern Generation...50 8.16 T RANSMIT...
  • Page 4 12.2.2 BYPASS...163 12.2.3 EXTEST ...163 12.2.4 CLAMP...163 12.2.5 HIGHZ ...163 12.2.6 IDCODE ...163 12.3 JTAG ID C ...164 ODES 12.4 T ...164 EGISTERS 12.4.1 Boundary Scan Register ...164 12.4.2 Bypass Register...164 12.4.3 Identification Register ...164 12.5 JTAG F UNCTIONAL IMING 13 PACKAGE INFORMATION ...166 13.1 169-B CSBGA, 14...
  • Page 5 Figure 8-7. IEEE 802.3 Ethernet Frame ... 42 Figure 8-8. Configured as DTE Connected to an Ethernet PHY in MII Mode ... 44 Figure 8-9. DS33Z41 Configured as a DCE in MII Mode ... 45 Figure 8-10. RMII Interface... 47 Figure 8-11.
  • Page 6 DS33Z41 Quad IMUX Ethernet Mapper LIST OF TABLES Table 2-1. T1 Related Telecommunications Specifications ... 10 Table 7-1. Detailed Pin Descriptions ... 14 Table 8-1. Clock Selection for the Ethernet (LAN) Interface ... 24 Table 8-2. Reset Functions ... 27 Table 8-3.

  • Page 7: C Ommitted

    The Ethernet interface can be configured for 10Mbps or 100Mbps service. The DS33Z41 encapsulates Ethernet traffic with HDLC or X.86 (LAPS) to be transmitted over the WAN interface. The WAN interface also receives encapsulated Ethernet packets and transmits the extracted packets over the Ethernet port.

  • Page 8: S Erial I Nterface

    FEATURE HIGHLIGHTS 2.1 General • 169-pin, 14mm x 14mm CSBGA package • 1.8V supply with 3.3V tolerant inputs and outputs • IEEE 1149.1 JTAG boundary scan • Software access to device ID and silicon revision • Development support includes evaluation kit, driver source code, and reference designs 2.2 Link Aggregation (Inverse Multiplexing) •...

  • Page 9: Sdram Interface

    2.6 SDRAM Interface • Interface for 128Mb, 32-bit-wide SDRAM • SDRAM Interface speed up to 100MHz • Auto Refresh Timing • Automatic Precharge • Master clock provided to the SDRAM • No external components required for SDRAM connectivity 2.7 MAC Interface •...

  • Page 10: Specifications Compliance

    DS33Z41 Quad IMUX Ethernet Mapper 2.10 Specifications compliance The DS33Z41 meets relevant telecommunications specifications. The following table provides the specifications and relevant sections that are applicable to the DS33Z41. Table 2-1. T1 Related Telecommunications Specifications IEEE 802.3-2002—CSMA/CD access method and physical layer specifications RFC1662—PPP in HDLC-like Framing...

  • Page 11: Applications

    Ethernet Delivery Over T1/E1/J1, T3/E3, OC-1/EC-1, G.SHDSL, or HDSL2/4 Refer also to Application Note 3411: DS33Z11—Ethernet LAN to Unframed T1/E1 WAN Bridge for an example of a complete LAN to WAN design. Figure 3-1. Quad T1/E1 SCT to DS33Z41 HDLC/X.86 Serial...

  • Page 12: Acronyms And Glossary

    4 ACRONYMS AND GLOSSARY • BERT—Bit Error Rate Tester • DCE—Data Communication Interface • DTE—Data Terminating Interface • FCS—Frame Check Sequence • HDLC—High Level Data Link Control • MAC—Media Access Control • MII—Media Independent Interface • RMII—Reduced Media Independent Interface •...

  • Page 13: Major Operating Modes

    DS33Z41 Quad IMUX Ethernet Mapper 5 MAJOR OPERATING MODES Operation of the DS33Z41 operation requires a host microprocessor for initialization and maintenance of the link aggregation functions. Microprocessor control is possible through the 8-bit parallel control port. More information on microprocessor control is available in Section 8.1.

  • Page 14: Pin Descriptions

    This required clock can be up to 50MHz and should have ±100ppm accuracy. When in MII mode in DCE operation, the DS33Z41 uses this input to generate the RX_CLK and TX_CLK outputs as required for the Ethernet PHY interface. When the MII interface is used with DTE operation, this clock is not required and should be tied low.
  • Page 15 Transmit Enable (MII): This pin is asserted high when data TXD [3:0] is being provided by the DS33Z41. The signal is deasserted prior to the first nibble of the next frame. This signal is synchronous with the rising edge TX_CLK. It is asserted with the first bit of the preamble.
  • Page 16 DCE Mode. MII Management data IO (MII). Data path for control information between the PHY and DS33Z41. When not used, pull to logic high externally through a 10kΩ resistor. The MDC and MDIO pins are used to write or read up to 32 Control and Status Registers in 32 PHY Controllers.
  • Page 17 11 = Reserved. Do not use. DCE or DTE Selection. The user must set this pin high for DCE Mode selection or low for DTE Mode. In DCE Mode, the DS33Z41 MAC port can be directly connected to another MAC. In DCE Mode, the Transmit clock (TX_CLK) and Receive clock (RX_CLK) are output by the DS33Z41.

  • Page 18: Sdram Controller

    At all other times, these pins are high impedance. Note: All SDRAM operations are controlled entirely by the DS33Z41. No user programming for SDRAM buffering is required. SDRAM Address Bus 0 to 11. The 12 pins of the SDRAM address bus output the row address first, followed by the column address.

  • Page 19: Queue Status

    SDRAM CLK Out. System clock output to the SDRAM. This clock is a buffered version of SYSCLKI. System Clock In. 100MHz System Clock input to the DS33Z41, used for internal operation. This clock is buffered and provided at SDCLKO for the SDRAM interface. The DS33Z41 also provides a divided version output at the REF_CLKO pin.

  • Page 20: Power Supplies

    NAME TYPE G5–G10, H2, H5, VDD3.3 H7–H10 D3, D2, E3, F4, J4, K4, VDD1.8 L3, F10, E11, E12, D12, M13, A9, A12, B10, C10, D1, D5, E7, E8, F6, F8, F12, F13, J5, J6, J11, J7, J8, J9, J10, K3, K5, K7, K8, K9, K10, K12...

  • Page 21: Figure 7-1. Ds33Z41 256-Ball Csbga Pinout

    Figure 7-1. DS33Z41 256-Ball CSBGA Pinout RMIIMIIS VDD1.8 VDD1.8 JTCLK RD / WR / VDD1.8 JTDI TCLKI TSER VDD1.8 RSYNC RCLKI TSYNC SDMASK[1] RSER VDD3 SDATA[10] SCAS SDATA[11] SDATA[12] SDATA[8] VDD1.8 SDATA[13] SDATA[14] VDD1.8 SDATA[15] SDATA[1] VDD1.8 SDATA[7] SDATA[0] SDATA[3]...

  • Page 22: Functional Description

    Ethernet PHY and MAC devices. The Ethernet interfaces can be individually configured for 10Mbps or 100Mbps service, in DTE and DCE configurations. The DS33Z41 MAC interface can be configured to reject frames with bad FCS and short frames (less than 64 bytes).

  • Page 23: Processor Interface

    DS33Z41 Quad IMUX Ethernet Mapper 8.1 Processor Interface Microprocessor control of the DS33Z41 is accomplished through the 20 interface pins of the microprocessor port. The 8-bit parallel data bus can be configured for Intel or Motorola modes of operation with the two MODEC[1:0] pins.

  • Page 24: Clock Structure

    8.2 Clock Structure The DS33Z41 clocks sources and functions are as follows: • Serial Transmit Data (TCLKI) and Serial Receive Data (RCLKI) clock inputs are used to transfer data from the serial interface. These clocks can be gapped. • System Clock (SYSCLKI) input. Used for internal operation. This clock input cannot be a gapped clock. A clock supply with ±100ppm frequency accuracy is suggested.

  • Page 25: Figure 8-1. Clocking For The Ds33Z41

    DS33Z41 Quad IMUX Ethernet Mapper Figure 8-1. Clocking for the DS33Z41 50 or 25 Mhz Oscillator Buffer REF_CLK Microport Div by 1,2,4,8,10 Output clocks: 50,25 Mhz,2.5 Mhz TSER TX_CLK1 HDLC TCLKI1 Serial Line 1 IMUX RMII Interface RX_CLK1 Arbiter RCLKI1 RSER X.86...

  • Page 26: Serial Interface Clock Modes

    PHY. While using MII mode with DCE operation, the MII clocks (TX_CLK and RX_CLK) are output by the DS33Z41, and are derived from the 25MHz REF_CLK input. More information on MII mode can be found in Section 8.14.1.

  • Page 27: I Nitialization And

    Serial interface Reset Queue Pointer Reset There are several features in the DS33Z41 to reduce power consumption. The reset bit in the minimizes power usage in the Serial Interface. Additionally, the RST pin or GL.CR1.RST bit may be held in reset indefinitely to keep the device in a low-power mode.

  • Page 28: Initialization And Configuration

    DS33Z41 Quad IMUX Ethernet Mapper 8.4 Initialization and Configuration EXAMPLE DEVICE INITIALIZATION SEQUENCE: STEP 1: Reset the device by pulling the RST pin low or by using the software reset bits outlined in Section 8.3. Clear all reset bits. Allow 5 milliseconds for the reset recovery.

  • Page 29: Device Interrupts

    DS33Z41 Quad IMUX Ethernet Mapper 8.7 Device Interrupts Figure 8-2 diagrams the flow of interrupt conditions from their source status bits through the multiple levels of information registers and mask bits to the interrupt pin. When an interrupt occurs, the host can read the Global Latched Status registers GL.LIS, GL.SIS, GL.IBIS, GL.TRQIS, GL.IMXSLS, GL.IMXDFDELS, and GL.IMXOOFLS...

  • Page 30: Figure 8-2. Device Interrupt Information Flow Diagram

    Figure 8-2. Device Interrupt Information Flow Diagram Receive FCS Errored Packet Receive Aborted Packet Receive Invalid Packet Detected Receive Small Packet Detected Receive Large Packet Detected Receive FCS Errored Packet Count Receive Aborted Packet Count Receive Size Violation Packet Count <Reserved>...

  • Page 31: Serial Interface

    The DS33Z41 has a link aggregation feature that allows data from the Ethernet interface to be inverse multiplexed over up to 4 bonded T1/E1 links. The T1/E1 data streams are input and output from the DS33Z41 on an 8.192Mbps Interleaved Bus (IBO). The IMUX function is shown graphically in...

  • Page 32: Figure 8-3. Imux Interface To T1/E1 Transceivers

    Figure 8-3. IMUX Interface to T1/E1 Transceivers T1E1 T1E1 Framer T1E1 T1E1 Framer T1E1 Framer T1E1 Framer Figure 8-4. Diagram of Data Transmission with IMUX Operation Data on IBO Bus From TSER . . . 128 Byte Sequence 02 128 Byte Sequence 01 L4 32 L3 32 L2 32...

  • Page 33: Microprocessor Requirements

    HDLC/X.86 encoded data. The HDLC/X.86 encoding and decoding is data is only available when the DS33Z41 has performed an IMUX function. Hence on the line the FCS for a given HDLC packet could transport on a separate link than the HDLC data.

  • Page 34: Imux Command Protocol

    8.9.2 IMUX Command Protocol The format for all commands sent and received in Channel 2 of the IBO Serial Interface is shown in The MSB for all commands is a “1”. The next 6 bits contain the actual opcode for the command. The LSB is the even parity calculation for the byte.

  • Page 35: Table 8-4. Command And Status For The Imux For Processor Communication

    The command and status registers for the IMUX function are detailed below: Table 8-4. Command and Status for the IMUX for Processor Communication REGISTER IMUX Configuration Register IMUX Command Register IMUX Sync Status Register IMUX Sync Latched Status Register IMUX Interrupt Mask Register Differential Delay Register Differential Delay Error Interrupt Enable Register...

  • Page 36: Out Of Frame (Oof) Monitoring

    DS33Z41 Quad IMUX Ethernet Mapper 8.9.3 Out of Frame (OOF) Monitoring Once the links are in synchronization, frame synchronization monitoring is started. The device will declare an out of frame (OOF) if 2 consecutive sequence errors are received. The device automatically adjusts for single-frame slips by increasing or decreasing the expected frame sequence number.

  • Page 37: Connections And Queues

    The Receive Queue functions in a similar manner. Note that the user must ensure that sizes and watermarks are set in accordance with the configuration speed of the Ethernet and Serial interfaces. The DS33Z41 does not provide error indication if the user creates a connection and queue that overwrites data for another connection queue.

  • Page 38: Arbiter

    It is recommended that the user reset the queue pointers for the connection after disconnection. The pointers must be reset before a connection is made. If this disconnect/connect procedure is not followed, incorrect data may be transmitted. The proper procedure for setting up a connection follows: •...

  • Page 39: Flow Control

    8.12 Flow Control Flow control may be required to ensure that data queues do not overflow and packets are not lost. The DS33Z41 allows for optional flow control based on the queue high watermark or through host processor intervention. There are 2 basic mechanisms that are used for flow control: •...

  • Page 40: Full-Duplex Flow Control

    96 packets from the maximum size of the queue and the low threshold 96 packets lower than the high threshold. The DS33Z41 will send a pause frame as the queue has crossed the high threshold and a frame is received. Pause is sent every time a frame is received in the “high threshold state.”...

  • Page 41: Half-Duplex Flow Control

    DS33Z41 Quad IMUX Ethernet Mapper Figure 8-6. Flow Control Using Pause Control Frame Receive Queue Low Water Receive Queue High Data Water Mark Initiate Flow control Receive Queue Growth 8.12.2 Half-Duplex Flow control Half duplex flow control uses a jamming sequence to exert backpressure on the transmitting node. The receiving node jams the first 4 bytes of a packet that are received from the MAC in order to cause collisions at the distant end.

  • Page 42: Ethernet Interface Port

    50MHz. In MII operation, the interface contains 17 signals and a clock reference of 25MHz. The DS33Z41 can be configured to RMII or MII interface by the Hardware pin RMIIMIIS. If the port is configured for MII in DCE mode, REF_CLK must be 25MHz. The DS33Z41 will internally generate the TX_CLK and RX_CLK outputs (at 25MHz for 100Mbps, 2.5MHz for 10Mbps) required for DCE mode from the REF_CLK input.

  • Page 43: Dte And Dce Mode

    Mode it can be connected to an Ethernet PHY. In DCE mode, the port can be connected to MII/RMII MAC devices other than an Ethernet PHY. The DTE/DCE connections for the DS33Z41 in MII mode are shown in the following two figures.

  • Page 44: Figure 8-8. Configured As Dte Connected To An Ethernet Phy In Mii Mode

    Figure 8-8. Configured as DTE Connected to an Ethernet PHY in MII Mode Arbiter DS33Z41 RXD[3:0] RXD[3:0] RXDV RXDV RX_CLK RX_CLK RX_ERR RX_ERR RX_CRS RX_CRS COL_DET COL_DET TXD[3:0] TXD[3:0] TX_CLK TX_CLK TX_EN TX_EN MDIO MDIO 44 of 167 Ethernet Phy...

  • Page 45: Figure 8-9. Ds33Z41 Configured As A Dce In Mii Mode

    Figure 8-9. DS33Z41 Configured as a DCE in MII Mode Arbiter DS33Z41 TXD[3:0] RXD[3:0] TX_EN RXDV RX_CLK TX_CLK RX_ERR TX_ERR RX_CRS RX_CRS COL_DET COL_DET TXD[3:0] RXD[3:0] TX_CLK RX_CLK TX_EN RXDV MDIO MDIO 45 of 167...

  • Page 46: Nterface

    SU.MACWD0-3 registers to be written with 4 bytes of data. The address must be written to SU.MACAWH. A write command is issued by writing a zero to SU.MACRWC.MCRW and a one to SU.MACRWC.MCS (MAC command status). MCS is cleared by the DS33Z41 when the operation is complete. Reading from the MAC registers requires the address for the read operation.

  • Page 47: Mii Mode

    8.14.1 MII Mode The Ethernet interface can be configured for MII operation by setting the hardware pin RMIIMIIS low. The MII interface consists of 17 pins. For instructions on clocking the Ethernet Interface while in MII mode, see Section 8.2.2. Diagrams of system connections for MII operation are shown in 8.14.2 RMII Mode The Ethernet interface can be configured for RMII operation by setting the hardware pin RMIIMIIS high.

  • Page 48: Phy Mii Management Block And Mdio Interface

    Data Register. These indirect registers are accessed through the MAC Control Registers defined in The MDC clock is internally generated and runs at 1.67MHz. Note that the DS33Z41 provides a single MII Management port, and all control registers for this function are located in MAC 1.

  • Page 49: Egister

    DS33Z41 Quad IMUX Ethernet Mapper 8.15.2 Receive Data Interface 8.15.2.1 Receive Pattern Detection The Receive BERT receives only the payload data and synchronizes the receive pattern generator to the incoming pattern. The receive pattern generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or bit 1 to the most significant bit (MSB) or bit 32.

  • Page 50: Pattern Monitoring

    DS33Z41 Quad IMUX Ethernet Mapper Figure 8-13. Repetitive Pattern Synchronization State Diagram Sync 1 bit error Verify Match Pattern Matches 8.15.4 Pattern Monitoring Pattern monitoring monitors the incoming data stream for Out Of Synchronization (OOS) condition, bit errors, and counts the incoming bits. An OOS condition is declared when the synchronization state machine is not in the “Sync”...
  • Page 51 DS33Z41 Quad IMUX Ethernet Mapper 8.15.5.2 Performance Monitoring Update All counters stop counting at their maximum count. A counter register is updated by asserting (low to high transition) the performance monitoring update signal (PMU). During the counter register update process, the performance monitoring status signal (PMS) is deasserted.

  • Page 52: Transmit Packet Processor

    8.16 Transmit Packet Processor The Transmit Packet Processor accepts data from the Transmit FIFO performs bit reordering, FCS processing, packet error insertion, stuffing, packet abort sequence insertion, inter-frame padding, and packet scrambling. The data output from the Transmit Packet Processor to the Transmit Serial Interface is a serial data stream (bit synchronous mode).

  • Page 53: Receive Packet Processor

    DS33Z41 Quad IMUX Ethernet Mapper 8.17 Receive Packet Processor The Receive Packet Processor accepts data from the Receive Serial Interface performs packet descrambling, packet delineation, inter-frame fill filtering, packet abort detection, destuffing, packet size checking, FCS error monitoring, FCS byte extraction, and bit reordering. The data coming from the Receive Serial Interface is a serial data stream.
  • Page 54 DS33Z41 Quad IMUX Ethernet Mapper FCS byte extraction discards the FCS bytes. If FCS extraction is enabled, the FCS bytes are extracted from the packet and discarded. If FCS extraction is disabled, the FCS bytes are stored in the receive FIFO with the packet.

  • Page 55: Encoding And Decoding

    Ethernet frames, but does not inflict dynamic bandwidth expansion as HDLC does. LAPS encapsulated frames can be used to send data onto a SONET/SDH network. The DS33Z41 expects a byte synchronization signal to provide the byte boundary for the X.86 receiver. This is provided by the RSYNC pin.

  • Page 56: Figure 8-15. X.86 Encapsulation Of The Mac Field

    FCS for MAC FCS for LAPS Flag(0x7E) The DS33Z41 will encode the MAC Frame with the LAPS encapsulation on a complete serial stream if configured for X.86 mode in the register LI.TX86E. The DS33Z41 provides the following functions: • Control Registers for Address, SAPI, Destination Address, Source Address.
  • Page 57 The X86 received frame is aborted if: • If 7d, 7E is detected. This is an abort packet sequence in X.86. • Invalid FCS is detected. • The received frame has less than 6 octets. • Control, SAPI and address field are mismatched to the programmed value. •...

  • Page 58: Committed Information Rate Controller

    8.19 Committed Information Rate Controller The DS33Z41 provides a CIR provisioning facility. The CIR can be used to restrict the transport of received MAC data to the serial port at a programmable rate. This is shown in from the Receive MAC to Transmit HDLC. This can be used for provisioning and billing functions towards the WAN.

  • Page 59: Figure 8-16. Cir In The Wan Transmit Path

    DS33Z41 Quad IMUX Ethernet Mapper Figure 8-16. CIR in the WAN Transmit Path 50 or 25 Mhz Oscillator Buffer REF_CLKI Microport Div by 1,2,4,8,10 Output clocks: 50,25 Mhz,2.5 Mhz TSER TX_CLK1 HDLC TCLKI1 Serial Line 1 IMUX RMII Interface RX_CLK1...

  • Page 60: Device Registers

    0000h – 003Fh 0040h – 007Fh Port 1 Reserved address space: 0180h - 07FFh. Table 9-1 Arbiter BERT 0080h – 00BFh 60 of 167 shows the register map for the DS33Z41. Serial Interface Ethernet Interface 00C0h – 013Fh 0140h – 017Fh...

  • Page 61: Register Bit Maps

    ITSYNC3 ITSYNC2 ITSYNC1 IMUXDFD6 IMUXDFD5 IMUXDFD4 TOOFIE3 TOOFIE2 TOOFIE1 TOOFLS3 TOOFLS2 TOOFLS1 SREFT6 SREFT5 SREFT4 61 of 167 contain the registers of the DS33Z41. Bits ID03 ID02 ID01 ID11 ID10 ID09 REF_CLKO INTM REFCLKS IMUXIE C1MRPRR C1HWPRR C1MHPR IMUXC3 IMUXC2...

  • Page 62: Arbiter Register Bit Map

    9.1.2 Arbiter Register Bit Map Table 9-3. Arbiter Register Bit Map 040h AR.RQSC1 RQSC1[7] 041h AR.TQSC1 TQSC1[7] 9.1.3 BERT Register Bit Map Table 9-4. BERT Register Bit Map 080h BCR 081h Reserved 082h BPCLR 083h BPCHR 084h BSPB0R BSP7 085h BSPB1R BSP15 086h BSPB2R BSP23...

  • Page 63: Serial Interface Register Bit Map

    9.1.4 Serial Interface Register Bit Map Table 9-5. Serial Interface Register Bit Map 0C0h Reserved 0C1h LI.RSTPD 0C2h LI.LPBK 0C3h Reserved 0C4h LI.TPPCL 0C5h LI.TIFGC TIFG7 0C6h LI.TEPLC TPEN7 0C7h LI.TEPHC MEIMS 0C8h LI.TPPSR 0C9h LI.TPPSRL 0CAh LI.TPPSRIE 0CBh Reserved 0CCh LI.TPCR0 TPC7...
  • Page 64 103h LI.RMPSCH RMX15 104h LI.RPPSR 105h LI.RPPSRL REPL 106h LI.RPPSRIE REPIE 107h Reserved 108h LI.RPCB0 RPC7 109h RPC15 LI.RPCB1 10Ah LI.RPCB2 RPC23 10Ch LI.RFPCB0 RFPC7 10Dh RFPC15 LI.RFPCB1 10Eh LI.RFPCB2 RFPC23 10Fh Reserved 110h LI.RAPCB0 RAPC7 111h LI.RAPCB1 RAPC15 112h LI.RAPCB2 RAPC23 113h Reserved...

  • Page 65: Ethernet Interface Register Bit Map

    9.1.5 Ethernet Interface Register Bit Map Table 9-6. Ethernet Interface Register Bit Map 140h SU.MACRADL MACRA7 141h SU.MACRADH MACRA15 142h SU.MACRD0 MACRD7 143h SU.MACRD1 MACRD15 144h MACRD23 145h SU.MACRD3 MACRD31 146h MACWD7 SU.MACWD0 147h MACWD15 SU.MACWD1 148h SU.MACWD2 MACWD23 149h SU.MACWD3 MACD31 14Ah...

  • Page 66: Mac Register Bit Map

    9.1.6 MAC Register Bit Map Table 9-7. MAC Indirect Register Bit Map SU.MACCR 0000h 31:24 0001h 23:16 0002h 15:8 0003h BOLMT1 BOLMT0 SU.MACAH 0004h 31:24 0005h 23:16 15:8 0006h PADR47 0007h PADR39 SU.MACAL PADR31 0008h 31:24 0009h 23:16 PADR23 000Ah 15:8 PADR15 000Bh...
  • Page 67 110h RESERVED – initialize to FF 111h RESERVED – initialize to FF RESERVED – 112h initialize to FF 113h RESERVED – initialize to FF 200h SU.RxFrmCtr RXFRMC31 RXFRMC30 RXFRMC29 RXFRMC28 RXFRMC27 RXFRMC26 RXFRMC25 RXFRMC24 31:24 23:16 201h RXFRMC23 RXFRMC22 RXFRMC21 RXFRMC20 RXFRMC19 RXFRMC18 RXFRMC17 RXFRMC16 202h 15:8 RXFRMC15 RXFRMC14 RXFRMC13 RXFRMC12 RXFRMC11 RXFRMC10...

  • Page 68: Global Register Definitions

    9.2 Global Register Definitions Functions contained in the global registers include: framer reset, LIU reset, device ID, BERT interrupt status, framer interrupt status, IBO configuration, MCLK configuration, and BPCLK configuration. These registers are preserved to provide code compatibility with the multiport devices in this product family. The global registers bit descriptions are presented below.
  • Page 69 Register Name: Register Description: Register Address: Bit # Name — — Default Bit 2: REF_CLKO OFF (REF_CLKO). This bit determines the REF_CLKO output mode. 1 = REF_CLKO is disabled and outputs an active-low signal. 0 = REF_CLKO is active and in accordance with RMII/MII Selection Bit 1: INT Pin Mode (INTM).
  • Page 70 Register Name: GL.RTCAL Register Description: Global Receive and Transmit Serial Port Clock Activity Latched Status Register Address: Bit # Name — — Default Bit 4: Receive Serial Interface Clock Activity Latched Status 1 (RLCALS1). This bit is set to 1 if the receive clock for Serial Interface 1 has activity.
  • Page 71 Register Name: Register Description: Register Address: Bit # Name — — Default Bit 4: Serial Interface 1 Tx Interrupt Enable (LINE1TIE). Setting this bit to 1 enables an interrupt on LIN1TIS. Bit 0: Serial Interface 1 Rx Interrupt Enable (LINE1RIE). Setting this bit to 1 enables an interrupt on LIN1RIS. Register Name: Register Description: Register Address:...
  • Page 72 Register Name: Register Description: Register Address: Bit # Name — — Default Bit 4: Transmit Queue 1 Interrupt Enable (TQ1IE). Setting this bit to 1 enables an interrupt on TQ1IS. Bit 0: Receive Queue 1 Interrupt Enable (RQ1IE). Setting this bit to 1 enables an interrupt on RQ1IS. Register Name: Register Description: Register Address:...
  • Page 73 Register Name: Register Description: Register Address: Bit # Name — — Default Bit 0: LINE1[0]. This bit is preserved to provide software compatibility with multiport devices. The LINE1[0] bit selects the Ethernet port that is to be connected to the Serial Interface. Note that bidirectional connection is assumed between the Serial and Ethernet Interfaces.
  • Page 74 Register Name: Register Description: Register Address: Bit # Name — T1E1 Default Bit 6: T1E1 Mode (T1E1). This bit determines if IMUX if for T1 or E1 Mode. 0 = T1 Mode 1 = E1 Mode Bit 5: Receive Enable (RXE). If this bit is set to 1, data will be received from the Serial Interface and passed to the packet processor.
  • Page 75 Register Name: Register Description: Register Address: Bit # Name ITSYNC4 ITSYNC3 Default Bit 7: IMUX Transmit Sync 4 (ITSYNC4). If this bit is set to 1, the device has received a rsync command for the portion of the 8.192Mbps link from the distant node. This status bit indicates that the distant end is in sync. Bit 6: IMUX Transmit Sync 3 (ITSYNC3).
  • Page 76 Register Name: Register Description: Register Address: Bit # Name ITSYNCLS4 ITSYNCLS3 Default Bit 7: IMUX Transmit Sync Latched Status 4 (ITSYNCLS4). This is a latched status bit for ITSYNC4. Bit 6: IMUX Transmit Sync Latched Status 3 (ITSYNCLS3). This is a latched status bit for ITSYNC3. Bit 5: IMUX Transmit Sync Latched Status 2 (ITSYNCLS2).
  • Page 77 Register Name: Register Description: Register Address: Bit # Name TOOFIE4 TOOFIE3 Default Bit 7: IMUX Transmit OOF Interrupt Enable 4 (TOOFIE4). Setting this bit to 1 enables an interrupt on TOOFLS4. Bit 6: IMUX Transmit OOF Interrupt Enable 3 (TOOFIE3). Setting this bit to 1 enables an interrupt on TOOFLS3.
  • Page 78 — — Default Bit 1: BIST DONE (BISTDN). If this bit is set to 1, the DS33Z41 has completed the BIST Test initiated by BISTE. The pass fail result is available in BISTPF. GL.IMXOOFLS Inverse MUX Out Of Frame Latched Status...
  • Page 79 Bit 0: BIST Pass-Fail (BISTPF). This bit is equal to 0 after the DS33Z41 performs BIST testing on the SDRAM and the test passes. This bit is set to 1 if the test failed. This bit is valid only after the BIST test is complete and the BIST DN bit is set.
  • Page 80 Register Name: Register Description Register Address: Bit # Name SREFT7 SREFT6 Default Bits 7 to 0: SDRAM Refresh Time Control (SREFT7 to SREFT0). These 8 bits are used to control the SDRAM refresh frequency. The refresh rate will be equal to this register value x 8 x 100MHz. Note: This register has a non-zero default value.

  • Page 81: Arbiter Registers

    The queue address size is defined in increments of 32 packets. The range of bytes will depend on the external SDRAM connected to the DS33Z41. Transmit queue is the data queue for data arriving on the WAN that is sent to the MAC. Note that queue size of 0 is not allowed and should never be set.

  • Page 82: Bert Registers

    9.4 BERT Registers Register Name: Register Description: Register Address: Bit # Name — Default Bit 7: This bit must be kept low for proper operation. Bit 6: Performance Monitoring Update (PMU). This bit causes a performance monitoring update to be initiated. A 0 to 1 transition causes the performance monitoring registers to be updated with the latest data, and the counters reset (0 or 1).
  • Page 83 Register Name: Register Description: Register Address: Bit # Name — QRSS Default The BERT’s BPCLR, BPCHR, and BSPB registers are used for polynomial-based pattern generation, with a formula of x + 1. The initial value for x (the seed) is placed in the BSPB (bert seed/pattern) register. The BERT generates a series of bits by iteration of the formula.
  • Page 84 Register Name: Register Description: Register Address: Bit # Name BSP7 BSP6 Default Bits 7 to 0: BERT Pattern (BSP7 to BPS0). Lower eight bits of 32 bits. Register description follows next register. Register Name: Register Description: Register Address: Bit # Name BSP15 BSP14...
  • Page 85 Register Name: Register Description: Register Address: Bit # Name — — Default Bits 5 to 3: Transmit Error Insertion Rate (TEIR2 to TEIR0). These three bits indicate the rate at which errors are inserted in the output data stream. One out of every 10 value of 0 disables error insertion at a specific rate.
  • Page 86 Register Name: Register Description: Register Address: Bit # Name — — Default — — Bit 3: Performance Monitor Update Status Latched (PMSL). This bit is set when the PMS bit transitions from 0 to 1. Bit 2: Bit Error Detected Latched (BEL). This bit is set when a bit error is detected. Bit 1: Bit Error Count Latched (BECL).
  • Page 87 Register Name: Register Description: Register Address: Bit # Name BEC7 BEC6 Default Bits 7 to 0: Bit Error Count (BEC7 to BEC0). Lower eight bits of 24 bits. Register description below. Register Name: Register Description: Register Address: Bit # Name BEC15 BEC14 Default...
  • Page 88 Register Name: Register Description: Register Address: Bit # Name BC15 BC14 Default Bits 7 to 0: Bit Count (BC15 to BC8). Eight bits of a 32-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name BC23 BC22 Default Bits 7 to 0: Bit Count (BC23 to BC16).

  • Page 89: Serial Interface Registers

    9.5 Serial Interface Registers The Serial Interface contains the Serial HDLC transport circuitry and the associated serial port. The Serial Interface register map consists of registers that are common functions, transmit functions, and receive functions. Bits that are underlined are read-only; all other bits can be written. All reserved registers and bits with “-“ designation should be written to zero, unless specifically noted in the register definition.

  • Page 90: Transmit Hdlc Processor Registers

    9.5.3 Transmit HDLC Processor Registers Register Name: Register Description: Register Address: Bit # Name — — Default Note: The user should take care not to modify this register value during packet error insertion. Bit 5: Transmit FCS Append Disable (TFAD). This bit controls whether or not an FCS is appended to the end of each packet.
  • Page 91 Register Name: Register Description: Register Address: Bit # Name TIFG7 TIFG6 Default Bits 7 to 0: Transmit Inter-Frame Gapping (TIFG7 to TIFG0). These eight bits indicate the number of additional flags and bytes of inter-frame fill to be inserted between packets. The number of flags and bytes of inter-frame fill between packets is at least the value of TIFG[7:0] plus 1.
  • Page 92 Register Name: Register Description: Register Address: Bit # Name MEIMS TPER6 Default Bit 7: Manual Error Insert Mode Select (MEIMS). When 0, the transmit manual error insertion signal (TMEI) will not cause errors to be inserted. When 1, TMEI will cause an error to be inserted when it transitions from a 0 to a 1.
  • Page 93 Register Name: Register Description: Register Address: Bit # Name — — Default Bit 0: Transmit Errored Packet Insertion Finished (TEPF). This bit is set when the number of errored packets indicated by the TPEN[7:0] bits in the TEPC register have been transmitted. This bit is cleared when errored packet insertion is disabled, or a new errored packet insertion process is initiated.
  • Page 94 Register Name: Register Description: Register Address: Bit # Name TPC7 TPC6 Default Bits 7 to 0: Transmit Packet Count (TPC7 to TPC0). Eight bits of 24-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name TPC15 TPC14 Default Bits 7 to 0: Transmit Packet Count (TPC15 to TPC8).
  • Page 95 Register Name: Register Description: Register Address: Bit # Name TBC7 TBC6 Default Bits 7 to 0: Transmit Byte Count (TBC7 to TBC0). Eight bits of 32-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name TBC15 TBC14 Default Bits 7 to 0: Transmit Byte Count (TBC15 to TBC8).
  • Page 96 Register Name: LI.THPMUU Register Description: Serial Interface Transmit HDLC PMU Update Register Register Address: 0D6h Bit # Name — — Default Bit 0: Transmit PMU Update (TPMUU). This signal causes the transmit cell/packet processor block performance monitoring registers (counters) to be updated. A 0 to 1 transition causes the performance monitoring registers to be updated with the latest data, and the counters reset (0 or 1).

  • Page 97: Registers

    Transmit and Receive paths. The MAC Frame is encapsulated in the X.86 Frame for Transmit and the X.86 headers are checked for in the received data. If X.86 functionality is selected, the X.86 receiver byte boundary is provided by the RSYNC signal and the DS33Z41 provides the transmit byte synchronization TSYNC. No HDLC encapsulation is performed.
  • Page 98 Register Name: Register Description: Register Address: Bit # Name TRSAPIL7 TRSAPIL6 Default Bits 7 to 0: X86 Transmit Receive Control (TRSAPIL7 to TRSAPIL0). This is the address field for the X.86 transmitter and expected value for the receiver. The register is reset to 0x01. Register Name: Register Description: Register Address:...

  • Page 99: Receive Serial Interface

    9.5.5 Receive Serial Interface Serial Receive Registers are used to control the HDLC Receiver associated with each Serial Interface. Note that throughout this document HDLC Processor is also referred to as “Packet Processor”. The receive packet processor block has seventeen registers. Register Name: Register Description: Register Address:...
  • Page 100 Register Name: Register Description: Register Address: Bit # Name RMX15 RMX14 Default Bits 7 to 0: Receive Maximum Packet Size (RMX15 to RMX8). These 16 bits indicate the maximum allowable packet size in bytes. The size includes the FCS bytes, but excludes bit/byte stuffing. Note: If the maximum packet size is less than the minimum packet size, all packets are discarded.
  • Page 101 Register Name: Register Description: Register Address: Bit # Name REPL RAPL Default — — Bit 7: Receive FCS Errored Packet Latched (REPL). This bit is set when a packet with an errored FCS is detected. Bit 6: Receive Aborted Packet Latched (RAPL). This bit is set when a packet with an abort indication is detected.
  • Page 102 Register Name: Register Description: Register Address: Bit # Name REPIE RAPIE Default Bit 7: Receive FCS Errored Packet Interrupt Enable (REPIE). This bit enables an interrupt if the REPL bit in LI.RPPSRL register is set. 0 = interrupt disabled 1 = interrupt enabled Bit 6: Receive Aborted Packet Interrupt Enable (RAPIE).
  • Page 103 Register Name: Register Description: Register Address: Bit # Name RPC7 RPC6 Default Bits 7 to 0: Receive Packet Count (RPC7 to RPC0). Eight bits of a 24-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name RPC15 RPC14 Default...
  • Page 104 Register Name: Register Description: Register Address: Bit # Name RFPC7 RFPC6 Default Bits 7 to 0: Receive FCS Errored Packet Count (RFPC7 to RFPC0). Eight bits of a 24-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name RFPC15 RFPC14...
  • Page 105 Register Name: Register Description: Register Address: Bit # Name RAPC7 RAPC6 Default Bits 7 to 0: Receive Aborted Packet Count (RAPC7 to RAPC0). Eight bits of a 24-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name RAPC15 RAPC14...
  • Page 106 Register Name: Register Description: Register Address: Bit # Name RSPC7 RSPC6 Default Bits 7 to 0: Receive Size Violation Packet Count (RSPC7 to RSPC0). Eight bits of a 24-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name RSPC15 RSPC14...
  • Page 107 Register Name: Register Description: Register Address: Bit # Name RBC7 RBC6 Default Bits 7 to 0: Receive Byte Count (RBC7 to RBC0). Eight bits of a 32-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name RBC15 RBC14 Default...
  • Page 108 Register Name: Register Description: Register Address: Bit # Name REBC7 REBC6 Default Bits 7 to 0: Receive Aborted Byte Count (RBC7 to RBC0). Eight bits of a 32-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name REBC15 REBC14...
  • Page 109 Register Name: LI.RHPMUU Register Description: Serial Interface Receive HDLC PMU Update Register Register Address: 120h Bit # Name — — Default Bit 0: Receive PMU Update (RPMUU). This signal causes the receive cell/packet processor block performance monitoring registers to be updated. A 0 to 1 transition causes the performance monitoring registers to be updated with the latest data, and resets the associated counters.
  • Page 110 Register Name: Register Description: Register Address: Bit # Name — — Default Bit 3: SAPI Octet Not Equal to LI.RX86S.SAPIHNE will generate an interrupt. Bit 2: SAPI Octet Not Equal to LI.RX86S.SAPILNE will generate an interrupt. Bit 1: Control Not Equal to LI.TRX8C generate an interrupt.
  • Page 111 Register Name: Register Description: Register Address: Bit # Name TQHT7 TQHT6 Default Bits 7 to 0: Transmit Queue High Threshold (TQHT7 to TQTH0). The transmit queue high threshold for the connection, in increments of 32 packets of 2048 bytes each. The value of this register is multiplied by 32 * 2048 bytes to determine the byte location of the threshold.

  • Page 112: Ethernet Interface Registers

    9.6 Ethernet Interface Registers The Ethernet Interface registers are used to configure RMII/MII bus operation and establish the MAC parameters as required by the user. The MAC Registers cannot be addressed directly from the Processor port. The registers below are used to perform indirect read or write operations to the MAC registers. The MAC Status Registers are shown in Table 9-7.
  • Page 113 Register Name: Register Description: Register Address: Bit # Name MACRD15 MACRD14 Default Bits 7 to 0: MAC Read Data Byte 1 (MACRD15 to MACRD8). One of four bytes of data read from the MAC. Valid after a read command has been issued and the SU.MACRWC.MCS bit is zero. Register Name: Register Description: Register Address:...
  • Page 114 Register Name: Register Description: Register Address: Bit # Name MACWD15 MACWD14 Default Bits 7 to 0: MAC Write Data Byte 1 (MACWD15 to MACWD08). One of four bytes of data to be written to the MAC. Data has been written after a write command has been issued and the SU.MACRWC.MCS bit is zero. Register Name: Register Description: Register Address:...
  • Page 115 SU.MACAWH and SU.MACAWL. Address information for read operations must be located in SU.MACRADL. The user must also write a 1 to the MCS bit, and the DS33Z41 will clear MCS when the operation is complete. Bit 0: MAC Command Status (MCS). Setting MCS in conjunction with MCRW will initiate a read or write to the MAC registers.
  • Page 116 Register Name: Register Description: Register Address: Bit # Name — — Default Bit 0: Queue Loopback Enable (QLP). If this bit is set to 1, data from the Ethernet Interface receive queue is looped back to the transmit queue. Buffered data from the serial interface will remain until the loopback is removed.
  • Page 117 Register Name: Register Description: Register Address: Bit # Name — — Default Bit 3: No Carrier Queue Flush Bar (NCFQ). If this bit is set to 1, the queue for data passing from Serial Interface to Ethernet Interface will not be flushed when loss of carrier is detected. Bit 2: Transmit Packet Deferred Fail Control Enable (TPDFCB).
  • Page 118 Register Name: Register Description: Register Address: Bit # Name Default Bit 7: Under Run (UR). When this bit is set to 1, the frame was aborted due to a data under run condition of the transmit buffer. Bit 6: Excessive Collisions (EC). When this bit is set to 1, a frame has been aborted after 16 successive collisions while attempting to transmit the current frame.
  • Page 119 Register Name: Register Description: Register Address: Bit # Name Default Bits 7 to 0: Frame Length (FL7 to FL0). These 8 bits are the low byte of the length (in bytes) of the received frame, with FCS and Padding. If Automatic Pad Stripping is enabled, this value is the length of the received packet without PCS or Pad bytes.
  • Page 120 Register Name: Register Description: Register Address: Bit # Name — Default Bit 7: Missed Frame (MF). This bit is set to 1 if the packet is not successfully received from the MAC by the packet Arbiter. Bit 4: Broadcast Frame (BF). This bit is set to 1 if the current frame is a broadcast frame. Bit 3: Multicast Frame (MCF).
  • Page 121 Register Name: Register Description: Register Address: Bit # Name RMPS7 RMPS6 Default Bits 7 to 0: Receiver Maximum Frame (RMPS7 to RMPS0). Eight bits of 16-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name RMPS15 RMPS14 Default Bits 7 to 0: Receiver Maximum Frame (RMPS15 to RMPS8).
  • Page 122 Register Name: Register Description: Register Address: Bit # Name — — Default Bit 3: Receive FIFO Overflow Interrupt Enable (RFOVFIE). If this bit is set, the interrupt is enabled for RFOVFLS. Bit 2: Receive Queue Overflow Interrupt Enable (RQVFIE). If this bit is set, the interrupt is enabled for RQOVFLS.
  • Page 123 Register Name: Register Description: Register Address: Bit # Name — UCFR Default Bit 6: Uncontrolled Control Frame Reject (UCFR). When set to 1, Control Frames other than Pause Frames are allowed. When this bit is equal to zero, non-pause control frames are rejected. Bit 5: Control Frame Reject (CFRR).

  • Page 124: Mac Registers

    9.6.2 MAC Registers The control registers related to the control of the individual MACs are shown in the following tables. The DS33Z41 keeps statistics for the packet traffic sent and received. The register address map is shown in the following Table.
  • Page 125 Bit 12: Late Collision Control (LCC). When set to 1, enables retransmission of a collided packet even after the collision period. When this bit is clear, retransmission of late collisions is disabled. Bit 10: Disable Retry (DRTY). When set to 1, the MAC makes only a single attempt to transmit each frame. If a collision occurs, the MAC ignores the current frame and proceeds to the next frame.
  • Page 126 Register Name: Register Description: Register Address: 0004h: Bit # Name Reserved Reserved Default 0005h: Bit # Name Reserved Reserved Default 0006h: Bit # Name PADR47 PADR46 Default 0007h: Bit # Name PADR39 PADR38 Default Bits 31 to 00: PADR47 to PADR32. These 32 bits should be initialized with the upper 4 bytes of the Physical Address for this MAC device.
  • Page 127 Bit 0: MII Busy (MIIB). This bit is set to 1 by the DS33Z41 during execution of a MII management instruction through the MDIO interface, and is set to zero when the DS33Z41 has completed the instruction. The user should read this bit and ensure that it is equal to zero prior to beginning a MDIO instruction.
  • Page 128 Register Name: Register Description: Register Address: 0018h: Bit # Name Reserved Reserved Default 0019h: Bit # Name Reserved Reserved Default 001Ah: Bit # Name MIID15 MIID14 Default 001Bh: Bit # Name MIID07 MIID06 Default Bits 15 to 0: MII (MDIO) Data (MIID15 to MIID00). These two bytes contain the data to be written to or the data read from the MII management interface (MDIO).
  • Page 129 Bit 0: Flow Control Busy (FCB) The host can set this bit to 1 in order to initiate transmission of a pause frame. During transmission of a pause frame, this bit remains set. The DS33Z41 will clear this bit when transmission of the pause frame has been completed.
  • Page 130 Register Name: Register Description: Register Address: 0100h: Bit # Name Reserved Reserved Default 0101h: Bit # Name Reserved Reserved Default 0102h: Bit # Name Reserved Reserved Default 0103h: Bit # Name MXFRM4 MXFRM3 Default Bits 13 to 3: Maximum Frame Size (MXFRM10 to MXFRM0). These bits indicate the maximum packet size value.
  • Page 131 Register Name: Register Description: Register Address: 010Ch: Bit # Name Reserved Reserved Default 010Dh: Bit # Name Reserved Reserved Default 010Eh: Bit # Name Reserved Reserved Default 010Fh: Bit # Name Reserved Reserved Default Note: Addresses 10Ch through 10Fh must each be initialized with all ones (FFh) for proper software-mode operation.
  • Page 132 Register Name: Register Description: Register Address: 0110h: Bit # Name Reserved Reserved Default 0111h: Bit # Name Reserved Reserved Default 0112h: Bit # Name Reserved Reserved Default 0113h: Bit # Name Reserved Reserved Default Note: Addresses 110h through 113h must each be initialized with all ones (FFh) for proper software-mode operation.
  • Page 133 Register Name: Register Description: Register Address: 0200h: Bit # Name RXFRMC31 RXFRMC30 Default 0201h: Bit # Name RXFRMC23 RXFRMC22 Default 0202h: Bit # Name RXFRMC15 RXFRMC14 Default 0203h: Bit # Name RXFRMC7 RXFRMC6 Default Bits 31 to 0: All Frames Received Counter (RXFRMC31 to RXFRMC0). 32-bit value indicating the number of frames received.
  • Page 134 Register Name: Register Description: Register Address: 0204h: Bit # Name RXFRMOK31 RXFRMOK30 Default 0205h: Bit # Name RXFRMOK23 RXFRMOK22 Default 0206h: Bit # Name RXFRMOK15 RXFRMOK14 Default 0207h: Bit # Name RXFRMOK7 RXFRMOK6 Default Bits 31 to 0: Frames Received OK Counter (RXFRMOK31 to RXFRMOK0). 32-bit value indicating the number of frames received and determined to be valid.
  • Page 135 Register Name: Register Description: Register Address: 0300h: Bit # Name TXFRMC31 TXFRMC30 Default 0301h: Bit # Name TXFRMC23 TXFRMC22 Default 0302h: Bit # Name TXFRMC15 TXFRMC14 Default 0303h: Bit # Name TXFRMC7 TXFRMC6 Default Bits 31 to 0: All Frames Transmitted Counter (TXFRMC31 to TXFRMC0). 32-bit value indicating the number of frames transmitted.
  • Page 136 Register Name: Register Description: Register Address: 0308h: Bit # Name TXBYTEC31 TXBYTEC30 Default 0309h: Bit # Name TXBYTEC23 TXBYTEC22 Default 030Ah: Bit # Name TXBYTEC15 TXBYTEC14 Default 030Bh: Bit # Name TXBYTEC7 TXBYTEC6 Default Bits 31 to 0: All Bytes Transmitted Counter (TXBYTEC31 to TXBYTEC0). 32-bit value indicating the number of bytes transmitted.
  • Page 137 Register Name: Register Description: Register Address: 030Ch: Bit # Name TXBYTEOK31 TXBYTEOK30 Default 030Dh: Bit # Name TXBYTEOK23 TXBYTEOK22 Default 030Eh: Bit # Name TXBYTEOK15 TXBYTEOK14 Default 030Fh: Bit # Name TXBYTEOK7 TXBYTEOK6 Default Bits 31 to 0: Bytes Transmitted OK Counter (TXBYTEOK31 to TXBYTEOK0). 32-bit value indicating the number of bytes transmitted and determined to be valid.
  • Page 138 Register Name: Register Description: Register Address: 0334h: Bit # Name TXFRMU31 TXFRMU30 Default 0335h: Bit # Name TXFRMU23 TXFRMU22 Default 0336h: Bit # Name TXFRMU15 TXFRMU14 Default 0337h: Bit # Name TXFRMU7 TXFRMU6 Default Bits 31 to 0: Frames Aborted Due to FIFO Under Run Counter (TXFRMU31 to TXFRMU0). 32-bit value indicating the number of frames aborted due to FIFO under run.
  • Page 139 Register Name: Register Description: Register Address: 0338h: Bit # Name TXFRMBD31 TXFRMBD30 Default 0339h: Bit # Name TXFRMBD23 TXFRMBD22 Default 033Ah: Bit # Name TXFRMBD15 TXFRMBD14 Default 033Bh: Bit # Name TXFRMBD7 TXFRMBD6 Default Bits 31 to 0: All Frames Aborted Counter (TXFRMBD31 to TXFRMBD0). 32-bit value indicating the number of frames aborted due to any reason.

  • Page 140: Functional Timing

    In Half-Duplex (DTE) Mode, the DS33Z41 supports CRS and COL signals. CRS is active when the PHY detects transmit or receive activity. If there is a collision as indicated by the COL input, the DS33Z41 will replace the data nibbles with jam nibbles. After a “random“ time interval, the packet is retransmitted. The MAC will try to send the packet a maximum of 16 times.

  • Page 141: Figure 10-3. Mii Receive Functional Timing

    Receive Data (RXD[3:0]) is clocked from the external PHY synchronously with RX_CLK. The RX_CLK signal is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation. RX_DV is asserted by the PHY from the first Nibble of the preamble in 100Mbps operation or first nibble of SFD for 10Mbps operation. The data on RXD[3:0] is not accepted by the MAC if RX_DV is low or RX_ERR is high (in DTE mode).

  • Page 142: Operating Parameters

    11 OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Lead with Respect to V Supply Voltage (VDD3.3) Range with Respect to V Supply Voltage (VDD1.8) Range with Respect to V Ambient Operating Temperature Range………………………………………………...…………………–40ºC to +85ºC Junction Operating Temperature Range…………………………………………………..……………..–40ºC to +125ºC Storage Temperature………………………………………………………………………….……………–55ºC to +125ºC Soldering Temperature………………………………………………………..See IPC/JEDEC J-STD-020 specification These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operation...

  • Page 143: Thermal Characteristics

    Note 1: Typical power is 145mW. All outputs loaded with rated capacitance; all inputs between VDD and VSS; inputs with pullups connected to V Note 2: Note 3: RST pin held low, or RST bit set. Note 4: RST pin held low, or RST bit set. All clocks stopped. 11.1 Thermal Characteristics Table 11-3.

  • Page 144: Mii Interface

    11.2 MII Interface Table 11-5. Transmit MII Interface PARAMETER SYMBOL TX_CLK Period TX_CLK Low Time TX_CLK High Time TX_CLK to TXD, TX_EN Delay Figure 11-1. Transmit MII Interface TX_CLK TXD[3:0] TX_EN 10Mbps 144 of 167 100Mbps UNITS...

  • Page 145: Figure 11-2. Receive Mii Interface Timing

    Table 11-6. Receive MII Interface PARAMETER SYMBOL RX_CLK Period RX_CLK Low Time RX_CLK High Time RXD, RX_DV to RX_CLK Setup Time RX_CLK to RXD, RX_DV Hold Time Figure 11-2. Receive MII Interface Timing RX_CLK RXD[3:0] RX_DV 10Mbps 145 of 167 100Mbps UNITS...

  • Page 146: Rmii Interface

    11.3 RMII Interface Table 11-7. Transmit RMII Interface PARAMETER SYMBOL REF_CLK Frequency REF_CLK Period REF_CLK Low Time REF_CLK High Time REF_CLK to TXD, TX_EN Delay Figure 11-3. Transmit RMII Interface REF_CLK TXD[1:0] TX_EN 10Mbps 50MHz ±50ppm 146 of 167 100Mbps 50MHz ±50ppm UNITS...

  • Page 147: Figure 11-4. Receive Rmii Interface Timing

    Table 11-8. Receive RMII Interface PARAMETER SYMBOL REF_CLK Frequence REF_CLK Period REF_CLK Low Time REF_CLK High Time RXD, CRS_DV to REF_CLK Setup Time REF_CLK to RXD, CRS_DV Hold Time Figure 11-4. Receive RMII Interface Timing REF_CLK RXD[1:0] CRS_DV 10Mbps 50MHz ±50ppm 147 of 167 100Mbps...

  • Page 148: Mdio Interface

    11.4 MDIO Interface Table 11-9. MDIO Interface PARAMETER MDC Frequency MDC Period MDC Low Time MDC High Time MDC to MDIO Output Delay MDIO Setup Time MDIO Hold Time Figure 11-5. MDIO Timing MDIO MDIO SYMBOL 148 of 167 UNITS 1.67...

  • Page 149: Transmit Wan Interface

    11.5 Transmit WAN Interface Table 11-10. Transmit WAN Interface PARAMETER TCLKI Frequency TCLKI Period TCLKI Low Time TCLKI High Time TCLKI to TSER Output Delay TSYNC Setup Time TSYNC Hold Time Figure 11-6. Transmit WAN Timing TCLKI TSER TSYNC SYMBOL 149 of 167 19.2 UNITS...

  • Page 150: Receive Wan Interface

    11.6 Receive WAN Interface Table 11-11. Receive WAN Interface PARAMETER RCLKI Frequency RCLKI Period RCLKI Low Time RCLKI High Time RSER Setup Time RSYNC Setup Time RSER Hold Time RSYNC Hold Time Figure 11-7. Receive WAN Timing RCLKI RSER RSYNC SYMBOL 150 of 167 19.2...

  • Page 151: Sdram Timing

    11.7 SDRAM Timing Table 11-12. SDRAM Interface Timing PARAMETER SDCLKO Period SDCLKO Duty Cycle SDCLKO to SDATA Valid Write to SDRAM SDCLKO to SDATA Drive On Write to SDRAM SDCLKO to SDATA Invalid Write to SDRAM SDCLKO to SDATA Drive Off Write to SDRAM SDATA to SDCLKO Setup Time Read from SDRAM...

  • Page 152: Figure 11-8. Sdram Interface Timing

    Figure 11-8. SDRAM Interface Timing SDCLKO (output) SDATA (output) SDATA (input) SRAS, SCAS, SWE, SDCS (output) SDA, SBA (output) SDMASK (output) 152 of 167...

  • Page 153: Figure 11-9. Receive Ibo Channel Interleave Mode Timing

    DS33Z41 Quad IMUX Ethernet Mapper Figure 11-9. Receive IBO Channel Interleave Mode Timing LINK #1, CHANNEL #1 RSYNC L3 C32 L4 C32 L1 C1 L2 C1 L3 C1 L4 C1 L1 C2 L2 C2 L3 C2 L4 C2 RSER BIT LEVEL DETAIL...

  • Page 154: Figure 11-10. Transmit Ibo Channel Interleave Mode Timing

    DS33Z41 Quad IMUX Ethernet Mapper Figure 11-10. Transmit IBO Channel Interleave Mode Timing Note 1: 8.192MHz bus configuration. Note 2: Unused channels filled with FFh. 154 of 167...

  • Page 155: Microprocessor Bus Ac Characteristics

    11.8 Microprocessor Bus AC Characteristics Table 11-13. AC Characteristics—Microprocessor Bus Timing (VDD3.3 = 3.3V ±5%,VDD1.8 = 1.8 ± 5% T PARAMETER Setup Time for A[12:0] Valid to CS Active Setup Time for CS Active to either RD, or WR Active Delay Time from Either RD or DS Active to DATA[7:0] Valid Hold Time from Either RD or WR Inactive to...

  • Page 156: Figure 11-11. Intel Bus Read Timing (Modec = 00)

    Figure 11-11. Intel Bus Read Timing (MODEC = 00) Address Valid ADDR[12:0] DATA[7:0] Figure 11-12. Intel Bus Write Timing (MODEC = 00) Address Valid ADDR[12:0] DATA[7:0] Data Valid 156 of 167...

  • Page 157: Figure 11-13. Motorola Bus Read Timing (Modec = 01)

    Figure 11-13. Motorola Bus Read Timing (MODEC = 01) Address Valid ADDR[12:0] DATA[7:0] Figure 11-14. Motorola Bus Write Timing (MODEC = 01) Address Valid ADDR[12:0] DATA[7:0] Data Valid 157 of 167...

  • Page 158: Jtag Interface Timing

    11.9 JTAG Interface Timing Table 11-14. JTAG Interface Timing (VDD3.3 = 3.3V ±5%, VDD1.8 = 1.8V ±5%, Tj = -40°C to +85°C.) PARAMETER JTCLK Clock Period JTCLK Clock High:Low Time JTCLK to JTDI, JTMS Setup Time JTCLK to JTDI, JTMS Hold Time JTCLK to JTDO Delay JTCLK to JTDO HIZ Delay JTRST Width Low Time...

  • Page 159: Jtag Information

    12 JTAG INFORMATION The device supports the standard instruction codes SAMPLE:PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. The device contains the following as required by IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Test Access Port (TAP) TAP Controller Instruction Register...

  • Page 160: Jtag Tap Controller State Machine Description

    DS33Z41 Quad IMUX Ethernet Mapper 12.1 JTAG TAP Controller State Machine Description This section covers the details on the operation of the Test Access Port (TAP) Controller State Machine. The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK.
  • Page 161 DS33Z41 Quad IMUX Ethernet Mapper Update-DR A falling edge on JTCLK while in the Update-DR state will latch the data from the shift register path of the test registers into the data output latches. This prevents changes at the parallel output due to changes in the shift register.

  • Page 162: Instruction Register

    Figure 12-2. TAP Controller State Diagram Test Logic Reset Run Test/ Idle 12.2 Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS LOW will shift the data one stage towards the serial output at JTDO.

  • Page 163: Sample:preload

    Table 12-1. Instruction Codes for IEEE 1149.1 Architecture INSTRUCTION SAMPLE:PRELOAD BYPASS EXTEST CLAMP HIGHZ IDCODE 12.2.1 SAMPLE:PRELOAD This is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The digital I/Os of the device can be sampled at the boundary scan register without interfering with the normal operation of the device by using the Capture-DR state.

  • Page 164: Jtag Id Codes

    DS33Z41 Quad IMUX Ethernet Mapper 12.3 JTAG ID Codes Table 12-2. ID Code Structure REVISION DEVICE CODE MANUFACTURER’S CODE REQUIRED DEVICE ID[31:28] ID[27:12] ID[11:1] ID[0] DS33Z41 0000 0000 0000 0110 0010 000 1010 0001 12.4 Test Registers IEEE 1149.1 requires a minimum of two test registers; the bypass register and the boundary scan register. An optional test register has been included with the device design.

  • Page 165: Jtag Functional Timing

    12.5 JTAG Functional Timing This functional timing for the JTAG circuits shows: • The JTAG controller starting from reset state. • Shifting out the first 4 LSB bits of the IDCODE. • Shifting in the BYPASS instruction (111) while shifting out the mandatory X01 pattern. •...

  • Page 166: Package Information

    DS33Z41 Quad IMUX Ethernet Mapper 13 PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a link to the latest package outline information.) 13.1 169-Ball CSBGA, 14mm x 14mm (56-G6035-001)

  • Page 167: Document Revision History

    Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.

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