Maxim DS21Q55 Quad Transceiver Manuals

Manuals and User Guides for Maxim DS21Q55 Quad Transceiver. We have 1 Maxim DS21Q55 Quad Transceiver manual available for free PDF download: User Manual

Maxim DS21Q55 User Manual (248 pages)

Quad T1/E1/J1 Transceiver

Brand: Maxim | Category: Transceiver | Size: 3 MB

Ordering Information
1
Extended
2
Feature Highlights
4
- General
  4
- Line Interface
  4
- Clock Synthesizer
  4
- Jitter Attenuator
  4
- Framer/Formatter
  5
- System Interface
  5
- I Nformation
  6
- HDLC Controllers
  6
- Test and Diagnostics
  6
- Extended System Information Bus
  6
- Control Port
  6
- Table of Contents
  8
Document Revision History
12
2 Block Diagram

13
3 Pin Function Description

14
- Transmit Side Pins
  14
- Receive Side Pins
  16
- Parallel Control Port Pins
  18
- Extended System Information Bus
  20
- Jtag Test Access Port Pins
  20
- Line Interface Pins
  21
- Supply Pins
  22
- Pinout
  23
- Package
  29
4 Parallel Port

30
- Register Map
  30
5 Special Per-Channel Register Operation

36
6 Programming Model

38
- Power-Up Sequence
  39
  - Master Mode Register
    39
- Interrupt Handling
  40
- Status Registers
  40
- Information Registers
  41
- Interrupt Information Registers
  41
7 Clock Map

42
8 T1 Framer/Formatter Control Registers

43
- T1 Control Registers
  43
- T1 Transmit
  45
- T1 Transmit Transparency
  48
- T1 Receive-Side Digital-Milliwatt Code Generation
  48
- T1 Information Register
  50
9 E1 Framer/Formatter Control Registers

52
- E1 Control Registers
  52
- A Utomatic
  55
- Automatic Alarm Generation
  56
- E1 Information Registers
  57
10 Common Control and Status Registers

59
11 I/O Pin Configuration Options

66
12 Loopback Configuration

68
- Per-Channel Loopback
  70
13 Error Count Registers

72
14 Ds0 Monitoring Function

79
- Transmit Ds0 Monitor Registers
  79
- Receive Ds0 Monitor Registers
  80
15 Signaling Operation

81
- Receive Signaling
  81
- Transmit Signaling
  87
16 Per-Channel Idle Code Generation

97
- Idle Code Programming Examples
  98
17 Channel Blocking Registers

103
18 Elastic Stores Operation

106
- Receive Side
  110
  - T1 Mode
    110
  - E1 Mode
    110
- Transmit Side
  111
  - T1 Mode
    111
  - E1 Mode
    111
- Elastic Stores Initialization
  111
- Minimum-Delay Mode
  111
19 Intermediate Crc-4 Updating (E1 Mode Only)

113
20 T1 Bit Oriented Code (Boc) Controller

114
- Transmit Boc
  114
- Receive Boc
  114
21 Additional (Sa) and International (Si) Bit Operation (E1 Only)

118
22 Hdlc Controllers

132
- Basic Operation Details
  132
- Hdlc Configuration
  134
  - FIFO Control
    136
- Hdlc Mapping
  137
  - Receive
    137
  - Transmit
    139
  - FIFO Information
    144
  - Receive Packet Bytes Available
    144
  - Hdlc Fifos
    145
- Receive Hdlc Code Example
  146
- Legacy FDL Support (T1 Mode)
  146
  - Receive Section
    146
  - Transmit Section
    148
- D4/SLC-96 Operation
  148
23 Line Interface Unit (Liu)

149
- Liu Operation
  150
- Liu Receiver
  150
  - Receive Level Indicator
    151
  - Receive G.703 Synchronization Signal (E1 Mode)
    151
  - Monitor Mode
    151
- Liu Transmitter
  152
- Mclk Prescaler
  153
- Jitter Attenuator
  153
- CMI (Code Mark Inversion) Option
  153
- Liu Control Registers
  154
- Recommended Circuits
  164
- Component Specifications
  166
24 Programmable In-Band Loop Code Generation and Detection

170
25 Bert Function

177
- Bert Register Description
  178
- Bert Repetitive Pattern Set
  183
- Bert Bit Counter
  184
- Bert Error Counter
  185
26 Payload Error Insertion Function

186
- Number of Error Registers
  188
  - Number of Errors Left Register
    189
27 Interleaved Pcm Bus Operation

190
- Channel Interleave Mode
  190
- Frame Interleave Mode
  190
28 Extended System Information Bus (Esib)

193
29 Programmable Backplane Clock Synthesizer

197
30 Fractional T1/E1 Support

198
31 Jtag-Boundary-Scan Architecture and Test-Access Port

199
- Instruction Register
  203
- Test Registers
  205
- Boundary Scan Register
  205
- Bypass Register
  205
- Identification Register
  205
32 Functional Timing Diagrams

208
- T1 Mode
  208
- E1 Mode
  218
33 Operating Parameters

231
- Thermal Characteristics
  231
- Recommended DC Operating Conditions
  232
34 Ac Timing Parameters and Diagrams

233
35 Mechanical Descriptions

247

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Maxim DS21Q55 Quad Transceiver Manuals

Maxim DS21Q55 User Manual (248 pages)

Table of Contents

2 Block Diagram

3 Pin Function Description

4 Parallel Port

5 Special Per-Channel Register Operation

6 Programming Model

7 Clock Map

8 T1 Framer/Formatter Control Registers

9 E1 Framer/Formatter Control Registers

10 Common Control and Status Registers

11 I/O Pin Configuration Options

12 Loopback Configuration

13 Error Count Registers

14 Ds0 Monitoring Function

15 Signaling Operation

16 Per-Channel Idle Code Generation

17 Channel Blocking Registers

18 Elastic Stores Operation

19 Intermediate Crc-4 Updating (E1 Mode Only)

20 T1 Bit Oriented Code (Boc) Controller

21 Additional (Sa) and International (Si) Bit Operation (E1 Only)

22 Hdlc Controllers

23 Line Interface Unit (Liu)

24 Programmable In-Band Loop Code Generation and Detection

25 Bert Function

26 Payload Error Insertion Function

27 Interleaved Pcm Bus Operation

28 Extended System Information Bus (Esib)

29 Programmable Backplane Clock Synthesizer

30 Fractional T1/E1 Support

31 Jtag-Boundary-Scan Architecture and Test-Access Port

32 Functional Timing Diagrams

33 Operating Parameters

34 Ac Timing Parameters and Diagrams

35 Mechanical Descriptions

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