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Maxim DS21Q55 User Manual

Quad t1/e1/j1 transceiver
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PRODUCT PREVIEW
X
DS21Q55 Quad T1/E1/J1 Transceiver
FEATURES:
Complete T1 (DS1)/ISDN–PRI/J1 transceiver
functionality
§ Complete E1 (CEPT) PCM-30/ISDN-PRI
transceiver functionality
§ Short- and long-haul line interface for
clock/data recovery and wave shaping
§ CMI coder/decoder
§ Crystal- less jitter attenuator
§ Dual HDLC controllers
§ On-chip programmable BERT generator and
detector
§ Internal software-selectable receive and
transmit side termination resistors
§ Dual two- frame elastic-store slip buffers to
interface backplanes up to 16.384MHz
§ 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz clock output synthesized to
recovered network clock
§ Programmable output clocks for fractional
T1, E1, H0, and H12 applications
§ Interleaving PCM bus operation
§ 8-bit parallel control port, multiplexed or
nonmultiplexed, Intel or Motorola
§ IEEE 1149.1 JTAG-boundary scan
§ 3.3V supply with 5V tolerant I/O
§ Signaling System 7 (SS7) support
1. DESCRIPTION
The DS21Q55 is a quad MCM device featuring independent transceivers that can be software configured
for T1, E1, or J1 operation. Each is composed of a line interface unit (LIU), framer, HDLC controllers,
and a TDM backplane interface, and is controlled via an 8-bit parallel port configured for Intel or
Motorola bus operations. The DS21Q55 is software compatible with the DS2155 single transceiver. It is
pin compatible with the DS21Qx5y family of products.
www.maxim-ic.com
Note: This Product Preview contains preliminary information and is subject to change without notice.
Some revisions of this device may incorporate deviations from published specifications known as errata.
Multiple revisions of any device may be simultaneously available through various sales channels. For
information about device errata, visit: http://dbserv.maxim-ic.com/errata.cfm.
Please contact
telecom.support@dalsemi.com
APPLICATIONS:
§ Routers
§ Channel Service Units (CSUs)
§ Data Service Units (DSUs)
§ Muxes
§ Switches
§ Channel Banks
§ T1/E1 Test Equipment
§ DSL Add/Drop Multiplexers

ORDERING INFORMATION

DS21Q55
DS21Q55N
or search
http://www.maxim-ic.com
information.
27mm BGA (0 C to +70 C)
27mm BGA (-40 C to +85 C)
for updated
DS21Q55

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  • Page 1: Ordering Information

    § Signaling System 7 (SS7) support 1. DESCRIPTION The DS21Q55 is a quad MCM device featuring independent transceivers that can be software configured for T1, E1, or J1 operation. Each is composed of a line interface unit (LIU), framer, HDLC controllers, and a TDM backplane interface, and is controlled via an 8-bit parallel port configured for Intel or Motorola bus operations.

  • Page 2: Extended

    DS21Q55 1. DESCRIPTION The DS21Q55 is a quad MCM devices featuring independent transceivers that can be software configured for T1, E1, or J1 operation. Each is composed of a line interface unit (LIU), framer, HDLC controllers, and a TDM backplane interface, and is controlled via an 8-bit parallel port configured for Intel or Motorola bus operations.
  • Page 3 G.703, G.704, G.706, G.736, G.775, G.823, G.932, I.431, O.151, O.161 § ETSI: ETS 300 011, ETS 300 166, ETS 300 233, CTR4, CTR12 § Japanese: JTG.703, JTI.431, JJ-20.11 (CMI coding only) Please contact telecom.support@dalsemi.com 3 of 248 or search http://www.maxim-ic.com information. DS21Q55 012103 for updated...

  • Page 4: Feature Highlights

    Product Preview 1.1 FEATURE HIGHLIGHTS The DS21Q55 contains all of the features of the previous generation of Dallas Semiconductor’s T1 and E1 transceivers plus many new features. 1.1.1 General § 27mm, 1.27 pitch BGA § 3.3V supply with 5V tolerant inputs and output s §...

  • Page 5: Framer/Formatter

    § Maximum 16.384MHz backplane burst rate § Supports T1 to CEPT (E1) conversion § Programmable output clocks for fractional T1, E1, H0, and H12 applicatio ns § Interleaving PCM bus operation Please contact telecom.support@dalsemi.com 5 of 248 or search http://www.maxim-ic.com information. DS21Q55 012103 for updated...

  • Page 6: I Nformation

    § Supports polled or interrupt-driven environments § Software access to device ID and silicon revision § Software-reset supported Automatic clear on power-up § Flexible register-space resets § Hardware reset pin Please contact telecom.support@dalsemi.com 6 of 248 or search http://www.maxim-ic.com information. DS21Q55 012103 for updated...
  • Page 7 Product Preview DS21Q55 Note: This data sheet assumes a particular nomenclature of the T1 and E1 operating environment. In each 125 s T1 frame, there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sent first followed by channel 1.

  • Page 8: Table Of Contents

    E1 I NFORMATION EGISTERS COMMON CONTROL AND STATUS REGISTERS ...59 I/O PIN CONFIGURATION OPTIONS ...66 Please contact telecom.support@dalsemi.com ...18 ...20 ...20 ...41 EGISTERS ...48 ...48 ILLIWATT ENERATION ...50 ...56 ...57 8 of 248 or search information. http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 9 (FOSCR) ...76 EGISTER (EBCR) ...78 ...79 EGISTERS ...80 EGISTERS ...98 XAMPLES ... 111 1)... 118 ASED OUBLE RAME ETHOD CRC4 M ASED ULTIFRAME ... 132 9 of 248 or search information. 2)... 118 3)... 121 ETHOD http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 10 T1 M ... 208 Please contact telecom.support@dalsemi.com ... 146 )... 146 ... 153 PTION ... 166 ... 178 ... 183 ... 188 ... 190 ... 190 ... 205 ... 205 10 of 248 or search information. http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 11 34.2 AC C ONMULTIPLEXED 34.3 AC C ECEIVE HARACTERISTICS 34.4 AC C RANSMIT HARACTERISTICS MECHANICAL DESCRIPTIONS ...247 Please contact telecom.support@dalsemi.com ... 233 ... 236 HARACTERISTICS ... 239 ... 243 11 of 248 or search http://www.maxim-ic.com information. DS21Q55 012103 for updated...

  • Page 12: Document Revision History

    Product Preview DS21Q55 1.2 DOCUMENT REVISION HISTORY 1) Initial Preliminary Release 12 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated information.

  • Page 13: Block Diagram

    Product Preview 2. BLOCK DIAGRAM A simplified block diagram showing the major components of the DS21Q55 is shown in Figure 4-1. Details are shown in subsequent figures. The block diagram is then divided into three functional blocks: LIU, framer, and backplane interface.

  • Page 14: Pin Function Description

    If enabled, this pin will be sampled on the falling edge of TCLK for data insertion into either the FDL stream (ESF) or the Fs- bit position (D4) or the Z–bit position (ZBTSI) or any combination of the Sa bit positions (E1). Please contact telecom.support@dalsemi.com 14 of 248 or search http://www.maxim-ic.com information. DS21Q55 012103 for updated...
  • Page 15 Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected to TPOSO by tying the LIUC pin high. TPOSI and TNEGI can be tied together in NRZ applications. Please contact telecom.support@dalsemi.com 15 of 248 or search http://www.maxim-ic.com information. DS21Q55 012103 for updated...

  • Page 16: Receive Side Pins

    Received NRZ serial data. Updated on rising edges of RCLK when the receive-side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive-side elastic store is enabled. Please contact telecom.support@dalsemi.com 16 of 248 or search http://www.maxim-ic.com information. DS21Q55 012103 for updated...
  • Page 17 Receive Signaling Freeze Signal Type: Output Set high when the signaling data is frozen via either automatic or manual intervention. Used to alert downstream equipment of the condition. Please contact telecom.support@dalsemi.com 17 of 248 or search http://www.maxim-ic.com information. DS21Q55 012103 for updated...

  • Page 18: Parallel Control Port Pins

    Signal Type: Input A dual-function pin. A zero-to-one transition issues a hardware reset to the DS21Q55 register set. A reset clears all configuration registers. Configuration register contents are set to zero. Leaving TSTRST high will 3-state all output and I/O pins (including the parallel control port).
  • Page 19 Chip Select for transceiver #4 Signal Type: Input Must be low to read or write to transceiver #4 of the device. CS4* is an active-low signal. Please contact telecom.support@dalsemi.com 19 of 248 or search http://www.maxim-ic.com information. DS21Q55 012103 for updated...

  • Page 20: Extended System Information Bus

    This pin is sampled on the rising edge of JTCLK and is used to place the test-access port into the various defined IEEE 1149.1 states. This pin has a 10k pullup resistor. Please contact telecom.support@dalsemi.com 20 of 248 or search http://www.maxim-ic.com information. DS21Q55 012103 for updated...

  • Page 21: Line Interface Pins

    E1 modes. A quartz crystal of 2.048MHz can be applied across MCLK and XTALD instead of the clock source. The clock rate can be 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When using the DS21Q55 in T1-only operation a 1.544MHz (50ppm) clock source can be used. MCLK1 and MCLK2 may be driven from a common clock.

  • Page 22: Supply Pins

    Signal Description: Transmit Analog Signal Ground Signal Type: Supply 0.0V. Should be tied to DV and RV Please contact telecom.support@dalsemi.com and TV pins. and TV pins. and DV pins. pins. 22 of 248 or search information. http://www.maxim-ic.com for updated DS21Q55 012103...

  • Page 23: Pinout

    Product Preview 3.8 Pinout DS21Q55 PIN DESCRIPTION Table 5-1 NOTE: Signal is common to all transceivers unless otherwise stated SYMBOL A7/ALE(AS) BPCLK1 BPCLK2 BPCLK3 BPCLK4 CS1* CS2* CS3* CS4* D0/AD0 D1/AD1 D2/AD2 D3/AD3 D4/AD4 D5/AD5 D6/AD6 D7/AD7 DVDD1 DVDD1 DVDD1...
  • Page 24 Receive Clock Output from the LIU, Transceiver #3. Receive Clock Output from the LIU, Transceiver #4. Read Input (Data Strobe) Receive Frame Sync (before the receive elastic store), Transceiver 24 of 248 or search information. DESCRIPTION http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 25 Receive Signaling Output, Transceiver #1. Receive Signaling Output, Transceiver #2. Receive Signaling Output, Transceiver #3. Receive Signaling Output, Transceiver #4. Receive Signaling Freeze Output, Transceiver #1. Receive Signaling Freeze Output, Transceiver #2. 25 of 248 or search information. DESCRIPTION http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 26 Transmit Link Clock, Transceiver #1. Transmit Link Clock, Transceiver #2. Transmit Link Clock, Transceiver #3. Transmit Link Clock, Transceiver #4. Transmit Link Data, Transceiver #1. Transmit Link Data, Transceiver #2. 26 of 248 or search information. DESCRIPTION http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 27 Transmit Analog Tip Output, Transceiver #4. – Transmit Analog Positive Supply. – Transmit Analog Positive Supply. – Transmit Analog Positive Supply. – Transmit Analog Positive Supply. – Transmit Analog Signal Ground. 27 of 248 or search information. DESCRIPTION http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 28 SYMBOL TVSS2 TVSS3 TVSS4 WR* (R/W*) Please contact telecom.support@dalsemi.com TYPE – Transmit Analog Signal Ground. – Transmit Analog Signal Ground. – Transmit Analog Signal Ground. Write Input (Read/Write). 28 of 248 or search information. DESCRIPTION http://www.maxim-ic.com for updated DS21Q55 012103...

  • Page 29: Package

    Product Preview 3.9 Package DS21Q55 Pin DIAGRAM, 27mm BGA Figure 5-1 The diagram shown below is the lead pattern that will be placed on the target PCB. This is the same pattern that would be seen as viewed from the top.

  • Page 30: Parallel Port

    Product Preview 4. PARALLEL PORT The DS21Q55 is controlled via a nonmultiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by an external microcontroller or microprocessor. The DS21Q55 can operate with either Intel or Motorola bus timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will be selected.
  • Page 31 Transmit Signaling Register 7 Transmit Signaling Register 8 Transmit Signaling Register 9 Transmit Signaling Register 10 Please contact telecom.support@dalsemi.com REGISTER NAME 31 of 248 or search http://www.maxim-ic.com information. DS21Q55 REGISTER PAGE ABBREVIATION IMR9 PCPR PCDR1 PCDR2 PCDR3 PCDR4 INFO4 INFO5...
  • Page 32 Receive Channel Blocking Register 3 Receive Channel Blocking Register 4 Transmit Channel Blocking Register 1 Transmit Channel Blocking Register 2 Please contact telecom.support@dalsemi.com REGISTER NAME 32 of 248 or search http://www.maxim-ic.com information. DS21Q55 REGISTER PAGE ABBREVIATION TS11 TS12 TS13 TS14 TS15 TS16 RS10...
  • Page 33 Receive Spare Code Definition Register 1 Receive Spare Code Definition Register 2 Receive FDL Register Transmit FDL Register Please contact telecom.support@dalsemi.com REGISTER NAME 33 of 248 or search http://www.maxim-ic.com information. DS21Q55 REGISTER PAGE ABBREVIATION TCBR3 TCBR4 H1TC H1FC H1RCS1 H1RCS2 H1RCS3...
  • Page 34 Number Of Errors Left 2 Test Register Test Register Test Register Test Register Test Register Test Register Please contact telecom.support@dalsemi.com REGISTER NAME 34 of 248 or search http://www.maxim-ic.com information. DS21Q55 REGISTER PAGE ABBREVIATION RFDLM1 RFDLM2 TEST IBOC RNAF RSiAF RSiNAF RSa4 RSa5 RSa6...
  • Page 35 Test Register Test Register Test Register *TEST1 to TEST16 registers are used only by the factory. Please contact telecom.support@dalsemi.com REGISTER NAME 35 of 248 or search http://www.maxim-ic.com information. DS21Q55 REGISTER PAGE ABBREVIATION TEST TEST TEST TEST TEST TEST TEST TEST...

  • Page 36: Special Per-Channel Register Operation

    Please contact telecom.support@dalsemi.com Write 11h to PCPR Write 00h to PCDR1 Write 0fh to PCDR2 Write 18h to PCDR3 Write 00h to PCDR4 RFCS BRCS THSCS 36 of 248 or search http://www.maxim-ic.com information. PEICS TFCS BTCS for updated DS21Q55 012103...
  • Page 37 Per-Channel Data Register 4 Register Address: Bit # Name Default CH32 CH31 Please contact telecom.support@dalsemi.com CH14 CH13 CH12 CH22 CH21 CH20 CH30 CH29 CH28 37 of 248 or search http://www.maxim-ic.com information. CH11 CH10 CH19 CH18 CH17 CH27 CH26 CH25 for updated DS21Q55 012103...

  • Page 38: Programming Model

    DS21Q55 6. PROGRAMMING MODEL The DS21Q55 register map is divided into three groups: T1 specific features, E1 specific features, and common features. The typical programming sequence begins with issuing a reset to the device, selecting T1 or E1 operation in the master mode register, enabling T1 or E1 functions, and enabling the common functions.

  • Page 39: Power-Up Sequence

    The LIRST (LIC2.6) should be toggled from zero to one to reset the line interface circuitry. (It will take the DS21Q55 about 40ms to recover from the LIRST bit being toggled.) Finally, after the TSYSCLK and RSYSCLK inputs are stable, the receive and transmit elastic stores sho uld be reset (this step can be skipped if the elastic stores are disabled).

  • Page 40: Interrupt Handling

    The user will always proceed a read of any of the status registers with a write. The byte written to the register will inform the DS21Q55 which bits the user wishes to read and have cleared. The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and a zero in the bit positions he or she does not wish to obtain the latest information on.

  • Page 41: Information Registers

    Register Description: Interrupt Information Register 1 Register Address: Bit # Name Default Register Name: IIR2 Register Description: Interrupt Information Register 2 Register Address: Bit # Name Default Please contact telecom.support@dalsemi.com 41 of 248 or search http://www.maxim-ic.com information. for updated DS21Q55 012103...

  • Page 42: Clock Map

    Product Preview 7. CLOCK MAP Figure 9-1 shows the clock map of the DS21Q55. The routing for the transmit and receive clocks are shown for the various loopback modes and jitter attenuator positions. Although there is only one jitter attenuator, which can be placed in the receive or transmit path, two are shown for simplification and clarity.

  • Page 43: T1 Framer/Formatter Control Registers

    8. T1 FRAMER/FORMATTER CONTROL REGISTERS The T1 framer portion of the DS21Q55 is configured via a set of nine control registers. Typically, the control registers are only accessed when the system is first powered up. Once the device has been initialized, the control registers will only need to be accessed when there is a change in the system configuration.
  • Page 44 Bit 6/Receive Frame Mode Select (RFM). 0 = D4 framing mode 1 = ESF framing mode Bit 7/Unused, must be set to zero for proper operation. Please contact telecom.support@dalsemi.com RB8ZS RSLC96 RZSE 44 of 248 or search information. RZBTSI RD4YM http://www.maxim-ic.com for updated DS21Q55 012103...

  • Page 45: T1 Transmit

    Bit 7/Transmit Japanese CRC6 Enable (TJC). 0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation) 1 = use Japanese standard JT–G704 CRC6 calculation Please contact telecom.support@dalsemi.com TCPT TSSE GB7S TFDLS 45 of 248 or search http://www.maxim-ic.com information. TYEL for updated DS21Q55 012103...
  • Page 46 0 = SLC– 96/Fs-bit insertion disabled 1 = SLC– 96/Fs-bit insertion enabled Bit 7/Transmit B8ZS Enable (TB8ZS). 0 = B8ZS disabled 1 = B8ZS enabled Please contact telecom.support@dalsemi.com TZSE FBCT2 FBCT1 TD4YM 46 of 248 or search http://www.maxim-ic.com information. TZBTSI TB7ZS for updated DS21Q55 012103...
  • Page 47 Bit 5/Unused, must be set to zero for proper operation. Bit 6/Unused, must be set to zero for proper operation. Bit 7/Unused, must be set to zero for proper operation. Please contact telecom.support@dalsemi.com 47 of 248 or search http://www.maxim-ic.com information. TLOOP for updated DS21Q55 012103...

  • Page 48: T1 Transmit Transparency

    Product Preview DS21Q55 8.2 T1 Transmit Transparency The software-signaling insertion-enable registers, SSIE1–SSIE4, can be used to select signaling insertion from the transmit-signaling registers, TS1–TS12, on a per-channel basis. Setting a bit in the SSIEx register allows signaling data to be sourced from the signaling registers for that channel.
  • Page 49 0 = do not affect the receive data associated with this channel 1 = replace the receive data associated with this channel with digital-milliwatt code Please contact telecom.support@dalsemi.com CH14 CH13 CH12 CH22 CH21 CH20 49 of 248 or search http://www.maxim-ic.com information. CH11 CH10 CH19 CH18 CH17 for updated DS21Q55 012103...

  • Page 50: T1 Information Register

    Bit 7/Receive Pulse Density Violation Event (RPDV). Set when the receive data stream does not meet the ANSI T1.403 requirements for pulse density. Please contact telecom.support@dalsemi.com COFA 16ZD 50 of 248 or search information. SEFE B8ZS http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 51 10E-3 error rate, and they should not falsely trigger on a framed, all-ones signal. The blue alarm criteria in the DS21Q55 has been set to achieve this performance. It is recommended that the RBL bit be qua lified with the RLOS bit.

  • Page 52: E1 Framer/Formatter Control Registers

    9. E1 FRAMER/FORMATTER CONTROL REGISTERS The E1 framer portion of the DS21Q55 is configured via a set of four control registers. Typically, the control registers are only accessed when the system is first powered up. Once the device has been initialized, the control registers will only need to be accessed when there is a change in the system configuration.
  • Page 53 915 or more CRC4 code words out of 1000 received in error Two consecutive MF alignment words received in error Sa6S Sa5S Sa4S 53 of 248 or search http://www.maxim-ic.com information. ITU SPEC. G.706 4.1.1 4.1.2 G.706 4.2 and 4.3.2 G.732 5.2 RCLA for updated DS21Q55 012103...
  • Page 54 0 = FAS bits/Sa bits/Remote Alarm sourced internally from the TAF and TNAF registers 1 = FAS bits/Sa bits/Remote Alarm sourced from TSER Please contact telecom.support@dalsemi.com TUA1 TSiS TSA1 THDB3 54 of 248 or search http://www.maxim-ic.com information. TG802 TCRC4 for updated DS21Q55 012103...

  • Page 55: A Utomatic

    Bit 7/Sa8-Bit Select (Sa8S). Set to one to source the Sa8 bit from the TLINK pin; set to zero to not source the Sa8 bit. See Functional Timing Diagrams for details. Please contact telecom.support@dalsemi.com Sa6S Sa5S Sa4S AEBE 55 of 248 or search http://www.maxim-ic.com information. AAIS for updated DS21Q55 012103...

  • Page 56: Automatic Alarm Generation

    RAI alarm. RAI generation conforms to ETS 300 011 specifications and a constant remote alarm will be transmitted if the DS21Q55 cannot find CRC4 multiframe synchronization within 400ms as per G.706.

  • Page 57: E1 Information Registers

    The CRC4 sync counter will rollover. CSC0 is the LSB of the 6-bit counter. (Note: The second LSB, CSC1, is not accessible. CSC1 is omitted to allow resolution to >400ms using 5 bits.) Please contact telecom.support@dalsemi.com CRCRC CSC3 CSC2 CSC0 FASSA 57 of 248 or search http://www.maxim-ic.com information. FASRC CASRC CASSA CRC4SA for updated DS21Q55 012103...
  • Page 58 Bit 3 of nonalign frame set to zero for three consecutive occasions More than two zeros in two frames (512 bits) 58 of 248 or search http://www.maxim-ic.com information. DS21Q55 SPEC. G.775/G.962 O.162 2.1.4 O.162 1.6.1.2 G.965 012103 for updated...

  • Page 59: Common Control And Status Registers

    1 = transmit CRC-4 generation operates according to G.706 Intermediate Path Recalculation method Bit 7/Unused, must be set to zero for proper operation. Please contact telecom.support@dalsemi.com DICAI TCSS1 TRANSMIT CLOCK SOURCE 59 of 248 or search http://www.maxim-ic.com information. TCSS0 RLOSF for updated DS21Q55 012103...
  • Page 60 Bit 6/Receive Unframed All Ones Clear Event (RUA1C). Set when the unframed all ones condition is no longer detected. Bit 7/Receive Yellow Alarm Clear Event (RYELC). (T1 only) Set when the yellow alarm condition is no longer detected. Please contact telecom.support@dalsemi.com FRCLC RLOSC RYEL 60 of 248 or search information. RUA1 FRCL RLOS http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 61 0 = interrupt masked 1 = interrupt enabled Bit 7/Receive Yellow Alarm Clear Event (RYELC). 0 = interrupt masked 1 = interrupt enabled Please contact telecom.support@dalsemi.com FRCLC RLOSC RYEL 61 of 248 or search information. RUA1 FRCL RLOS http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 62 Bit 7/Spare Code Detected Condition (LSPARE). (T1 only) Set when the spare code as defined in the RSCD1/2 registers is being received. See Programmable In-Band Loop Code Generation and Detection for details. Please contact telecom.support@dalsemi.com LOTC LORC V52LNK 62 of 248 or search http://www.maxim-ic.com information. RDMA for updated DS21Q55 012103...
  • Page 63 1 = interrupt enabled–interrupts on rising and falling edges Bit 7/Spare Code Detected Condition (LSPARE). 0 = interrupt masked 1 = interrupt enabled–interrupts on rising and falling edges Please contact telecom.support@dalsemi.com LOTC LORC V52LNK 63 of 248 or search http://www.maxim-ic.com information. RDMA for updated DS21Q55 012103...
  • Page 64 Bit 6/Receive Signaling All Ones Event (RSA1). (E1 only) Set when the contents of timeslot 16 contains fewer than three zeros over 16 consecutive frames. This alarm is not disabled in the CCS signaling mode. Please contact telecom.support@dalsemi.com RSA0 64 of 248 or search http://www.maxim-ic.com information. RCMF for updated DS21Q55 012103...
  • Page 65 Bit 5/Receive Signaling All Zeros Event (RSA0). 0 = interrupt masked 1 = interrupt enabled Bit 6/Receive Signaling All Ones Event (RSA1). 0 = interrupt masked 1 = interrupt enabled Please contact telecom.support@dalsemi.com RSA0 65 of 248 or search http://www.maxim-ic.com information. RCMF for updated DS21Q55 012103...

  • Page 66: I/O Pin Configuration Options

    IOCR1.4 = 0). 0 = RSYNC will output a pulse at every multiframe 1 = RSYNC will output a pulse at every other multiframe Please contact telecom.support@dalsemi.com RSMS1 RSIO TSDW 66 of 248 or search information. TSIO http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 67 Bit 6/TCLK Invert (TCLKINV). 0 = no inversion 1 = invert Bit 7/RCLK Invert (RCLKINV). 0 = no inversion 1 = invert Please contact telecom.support@dalsemi.com RSYNCINV TSYNCINV 67 of 248 or search information. TSSYNCINV H100EN TSCLKM http://www.maxim-ic.com for updated DS21Q55 RSCLKM 012103...

  • Page 68: Loopback Configuration

    TPOSO and TNEGO pins. Data will continue to pass through the receive side framer of the device as it would normally and the data from the transmit side formatter will be ignored. 0 = loopback disabled 1 = loopback enabled Please contact telecom.support@dalsemi.com LIUC 68 of 248 or search http://www.maxim-ic.com information. for updated DS21Q55 012103...
  • Page 69 Bit 7/Unused, must be set to zero for proper operation. Please contact telecom.support@dalsemi.com LIU and Framer Separated LIU and Framer Separated LIU and Framer Connected LIU and Framer Separated 69 of 248 or search http://www.maxim-ic.com information. DS21Q55 012103 for updated...

  • Page 70: Per-Channel Loopback

    Bits 0 to 7/Per-Channel Loopback Enable for Channels 9 to 16 (CH9 to CH16). 0 = loopback disabled 1 = enable loopback. Source data from the corresponding receive channel Please contact telecom.support@dalsemi.com CH14 CH13 CH12 70 of 248 or search http://www.maxim-ic.com information. CH11 CH10 for updated DS21Q55 012103...
  • Page 71 0 = loopback disabled 1 = enable loopback. Source data from the corresponding receive channel Please contact telecom.support@dalsemi.com CH22 CH21 CH20 CH30 CH29 CH28 71 of 248 or search http://www.maxim-ic.com information. CH19 CH18 CH17 CH27 CH26 CH25 for updated DS21Q55 012103...

  • Page 72: Error Count Registers

    Product Preview 13. ERROR COUNT REGISTERS The DS21Q55 contains four counters that are used to accumulate line coding errors, path errors, and synchronization errors. Counter update options include one second boundaries, 42ms (T1 mode only), 62ms (E1 mode only) or manually. See Error Counter Configuration Register (ERCNT). When updated automatically, the user can use the interrupt from the timer to determine when to read these registers.

  • Page 73: Line Code Violation Count Register (Lcvcr)

    WHAT IS COUNTED IN THE LCVCRs (T1RCR2.5) BPVs BPVs + 16 Consecutive Zeros BPVs (B8ZS Code Words Not Counted) BPVs + 8 Consecutive Zeros WHAT IS COUNTED IN THE LCVCRs BPVs 73 of 248 or search information. http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 74 Bits 0 to 7/Line Code Violation Counter Bits 0 to 7 (LCVC0 to LCVC7). LCV0 is the LSB of the 16-bit code violation count. Please contact telecom.support@dalsemi.com LCVC13 LCVC12 LCVC11 LCVC5 LCVC4 LCVC3 74 of 248 or search information. LCVC10 LCVC9 LCCV8 LCVC2 LCVC1 LCVC0 http://www.maxim-ic.com for updated DS21Q55 012103...

  • Page 75: Path Code Violation Count Register (Pcvcr)

    COUNT Fs ERRORS? WHAT IS COUNTED IN THE PCVCRs Errors in the Ft Pattern Errors in Both the Ft and Fs Patterns Don’t Care Errors in the CRC6 Code Words 75 of 248 or search information. http://www.maxim-ic.com for updated DS21Q55 012103...

  • Page 76: Frames Out Of Sync Count Register (Foscr)

    PCVC10 PCVC9 PCVC8 PCVC2 PCVC1 PCVC0 WHAT IS COUNTED IN THE FOSCRs Number of Multiframes Out of Sync Errors in the Ft Pattern Number of Multiframes Out of Sync Errors in the FPS Pattern http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 77 Product Preview DS21Q55 The FOSCR1 (FOSCR1) is the most significant word and FOSCR2 is the least significant word of a 16- bit counter that records frames out of sync. 77 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated...

  • Page 78: E-Bit Counter Register (Ebcr)

    Bits 0 to 7/E-Bit Counter Bits 0 to 7 (EB0 to EB7). EB0 is the LSB of the 16-bit E-bit count. Please contact telecom.support@dalsemi.com FOS13 FOS12 FOS11 FOS5 FOS4 FOS3 EB13 EB12 EB11 78 of 248 or search information. FOS10 FOS9 FOS8 FOS2 FOS1 FOS0 EB10 http://www.maxim-ic.com for updated DS21Q55 012103...

  • Page 79: Ds0 Monitoring Function

    14. DS0 MONITORING FUNCTION The DS21Q55 has the ability to monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction the user will determine which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the TDS0SEL register.

  • Page 80: Receive Ds0 Monitor Registers

    Bits 0 to 7/Receive DS0 Channel Bits (B1 to B8). Receive-channel data that has been selected by the receive-channel monitor-select register. B8 is the LSB of the DS0 channel (last bit to be received). Please contact telecom.support@dalsemi.com RCM4 RCM3 RCM2 80 of 248 or search http://www.maxim-ic.com information. RCM1 RCM0 for updated DS21Q55 012103...

  • Page 81: Signaling Operation

    SIMPLIFIED DIAGRAM OF RECEIVE SIGNALING PATH Figure 17-1 T1/E1 DATA STREAM SIGNALING EXTRACTION RECEIVE SIGNALING REGISTERS CHANGE OF STATE INDICATION REGISTERS Please contact telecom.support@dalsemi.com PER-CHANNEL CONTROL RSER ONES RE-INSERTION RSYNC CONTROL SIGNALING RSIG BUFFERS 81 of 248 or search http://www.maxim-ic.com information. DS21Q55 012103 for updated...

  • Page 82: Processor-Based Receive Signaling

    15.1.1.1 Change Of State In order to avoid constant monitoring of the receive signaling registers, the DS21Q55 can be programmed to alert the host whe n any specific channel or channels undergo a change of their signaling state. RSCSE1 through RSCSE4 for E1 and RSCSE1 through RSCSE3 for T1 are used to select which channels can cause a change of state indicatio n.
  • Page 83 Bit 5/Unused, must be set to zero for proper operation. Bit 6/Unused, must be set to zero for proper operation. Bit 7/Unused, must be set to zero for proper operation. Please contact telecom.support@dalsemi.com 83 of 248 or search http://www.maxim-ic.com information. for updated DS21Q55 012103...
  • Page 84 CH1 -B CH3 -A CH3 -B CH5 -A CH5 -B CH7 -A CH7 -B CH9 -A CH9 -B CH11-A CH11-B CH13-A CH13-B CH15-A CH15-B CH17-A CH17-B CH19-A CH19-B RS10 CH21-A CH21-B RS11 CH23-A CH23-B RS12 http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 85 CH3-C CH3-D CH5-C CH5-D CH7-C CH7-D CH9-C CH9-D CH11-C CH11-D CH13-C CH13-D CH15-C CH15-D CH17-C CH17-D RS10 CH19-C CH19-D RS11 CH21-C CH21-D RS12 CH23-C CH23-D RS13 CH25-C CH25-D RS14 CH27-C CH27-D RS15 CH29-C CH29-D RS16 http://www.maxim-ic.com for updated DS21Q55 012103...

  • Page 86: Interrupt I

    CH13 CH12 CH11 CH21 CH20 CH19 CH29 CH28 CH27 86 of 248 or search information. (LSB) RSCSE1 CH10 RSCSE2 CH18 CH17 RSCSE3 CH26 CH25 RSCSE4 (LSB) RSINFO1 CH10 RSINFO2 CH18 CH17 RSINFO3 CH26 CH25 RSINFO4 http://www.maxim-ic.com for updated DS21Q55 012103...

  • Page 87: Transmit Signaling

    Signaling data can be sourced from the TS registers on a per-channel basis by utilizing the software- signaling insertion-enable registers, SSIE1 through SSIE4. Please contact telecom.support@dalsemi.com TRANSMIT SIGNALING REGISTERS SIGNALING BUFFERS T1TCR1.4 PER-CHANNEL CONTROL PCPR.3 87 of 248 or search http://www.maxim-ic.com information. DS21Q55 TSER TSIG 012103 for updated...
  • Page 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Phone Channel Please contact telecom.support@dalsemi.com 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 88 of 248 or search http://www.maxim-ic.com information. DS21Q55 012103 for updated...
  • Page 89 CH3-C CH3-D CH5-C CH5-D CH7-C CH7-D CH9-C CH9-D CH11-C CH11-D CH13-C CH13-D CH15-C CH15-D CH17-C CH17-D TS10 CH19-C CH19-D TS11 CH21-C CH21-D TS12 CH23-C CH23-D TS13 CH25-C CH25-D TS14 CH27-C CH27-D TS15 CH29-C CH29-D TS16 http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 90 TS1 to TS16 Register Description: Transmit Signaling Registers (E1 Mode, CCS Format) Register Address: 50h to 5Fh (MSB) Please contact telecom.support@dalsemi.com 90 of 248 or search http://www.maxim-ic.com information. (LSB) TS10 TS11 TS12 TS13 TS14 TS15 TS16 for updated DS21Q55 012103...
  • Page 91 CH23-B 91 of 248 or search information. (LSB) CH1-C CH1-D CH3-C CH3-D CH5-C CH5-D CH7-C CH7-D CH9-C CH9-D CH11-C CH11-D CH13-C CH13-D CH15-C CH15-D CH17-C CH17-D CH19-C CH19-D TS10 CH21-C CH21-D TS11 CH23-C CH23-D TS12 http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 92 CH1 -A CH1 -B CH3 -A CH3 -B CH5 -A CH5 -B CH7 -A CH7 -B CH9 -A CH9-B CH11-A CH11-B CH13-A CH13-B CH15-A CH15-B CH17-A CH17-B CH19-A CH19-B TS10 CH21-A CH21-B TS11 CH23-A CH23-B TS12 http://www.maxim-ic.com for updated DS21Q55 012103...

  • Page 93: Software Signaling Insertion Enable Registers, E1 Cas Mode

    0 = do not source signaling data from the TS registers for this channel 1 = source signaling data from the TS registers for this channel Please contact telecom.support@dalsemi.com CH13 CH12 CH11 93 of 248 or search http://www.maxim-ic.com information. UCAW CH10 for updated DS21Q55 012103...
  • Page 94 0 = do not source signaling data from the TS registers for this channel 1 = source signaling data from the TS registers for this channel Please contact telecom.support@dalsemi.com CH20 CH19 CH18 CH28 CH27 CH26 94 of 248 or search http://www.maxim-ic.com information. CH17 CH16 LCAW CH25 CH24 CH23 for updated DS21Q55 012103...

  • Page 95: Software Signaling Insertion Enable Registers, T1 Mode

    0 = do not source signaling data from the TSx registers for this channel 1 = source signaling data from the TSx registers for this channel Please contact telecom.support@dalsemi.com CH14 CH13 CH12 CH22 CH21 CH20 95 of 248 or search http://www.maxim-ic.com information. CH11 CH10 CH19 CH18 CH17 for updated DS21Q55 012103...
  • Page 96 Product Preview DS21Q55 17.2.4 Hardware-Based Transmit Signaling In hardware-based mode, signaling data is input via the TSIG pin. This signaling PCM stream is buffered and inserted to the data stream being input at the TSER pin. Signaling data can be input on a per-channel basis via the transmit-hardware signaling-channel select (THSCS) function.

  • Page 97: Per-Channel Idle Code Generation

    When operated in the T1 mode, only the first 24 channels are used; the remaining channels, CH25–CH32 are not used. The DS21Q55 contains a 64-byte idle code array accessed by the idle array address register (IAAR) and the per-channel idle code register (PCICR). The contents of the array contain the idle codes to be substituted into the appropriate transmit or receive channels.

  • Page 98: Idle Code Programming Examples

    Write RCICE3 = FEh ;enable idle code substitution for receive channels 18 through 24 Write RCICE4 = FFh ;enable idle code substitution for receive channels 25 through 32 Please contact telecom.support@dalsemi.com 98 of 248 or search http://www.maxim-ic.com information. DS21Q55 012103 for updated...
  • Page 99 0 = do not insert data from the idle code array into the transmit data stream Please contact telecom.support@dalsemi.com IAA5 IAA4 IAA3 CH14 CH13 CH12 99 of 248 or search http://www.maxim-ic.com information. IAA2 IAA1 IAA0 CH11 CH10 for updated DS21Q55 012103...
  • Page 100 Product Preview DS21Q55 1 = insert data from the idle code array into the transmit data stream 100 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated information.
  • Page 101 1 = insert data from the idle code array into the receive data stream Please contact telecom.support@dalsemi.com CH22 CH21 CH20 CH30 CH29 CH28 CH14 CH13 CH12 101 of 248 or search http://www.maxim-ic.com information. CH19 CH18 CH17 CH27 CH26 CH25 CH11 CH10 for updated DS21Q55 012103...
  • Page 102 1 = insert data from the idle code array into the receive data stream Please contact telecom.support@dalsemi.com CH22 CH21 CH20 CH30 CH29 CH28 102 of 248 or search http://www.maxim-ic.com information. CH19 CH18 CH17 CH27 CH26 CH25 for updated DS21Q55 012103...

  • Page 103: Channel Blocking Registers

    TCHBLK pin will be held high during the entire corresponding channel time. Channels 25 through 32 are ignored when the device is operated in the T1 mode. Also, the DS21Q55 can internally generate and output a bursty clock on a per-channel basis (N x 64kbps / 56kbps). See Fractional T1/E1 Support.
  • Page 104 1 = force the TCHBLK pin high during this channel time Please contact telecom.support@dalsemi.com CH22 CH21 CH20 CH30 CH29 CH28 CH14 CH13 CH12 104 of 248 or search http://www.maxim-ic.com information. CH19 CH18 CH17 CH27 CH26 CH25 CH11 CH10 for updated DS21Q55 012103...
  • Page 105 0 = force the TCHBLK pin to remain low during this channel time 1 = force the TCHBLK pin high during this channel time Please contact telecom.support@dalsemi.com CH22 CH21 CH20 CH30 CH29 CH28 105 of 248 or search http://www.maxim-ic.com information. CH19 CH18 CH17 CH27 CH26 CH25 for updated DS21Q55 012103...

  • Page 106: Elastic Stores Operation

    DS21Q55 18. ELASTIC STORES OPERATION The DS21Q55 contains dual two- frame, fully independent elastic stores, one for the receive direction and one for the transmit direction. The transmit- and receive-side elastic stores can be enabled/disabled independent of each other. Also, each elastic store can interface to either a 1.544MHz or 2.048MHz/4.096MHz/8.192MHz/16.384MHz backplane without regard to the backplane rate the other...
  • Page 107 Should be toggled after TSYSCLK has been applied and is stable. Must be cleared and set again for a subsequent align. See Elastic Stores Initialization for details. Please contact telecom.support@dalsemi.com TESMDM TESE RESALGN 107 of 248 or search information. RESR RESMDM RESE http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 108 Bit 5/Transmit Elastic Store Full Event (TESF). 0 = interrupt masked 1 = interrupt enabled Please contact telecom.support@dalsemi.com TESF TESEM TSLIP TESF TESEM TSLIP 108 of 248 or search http://www.maxim-ic.com information. RESF RESEM RSLIP RESF RESEM RSLIP for updated DS21Q55 012103...
  • Page 109 Product Preview DS21Q55 109 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated information.

  • Page 110: Receive Side

    Product Preview DS21Q55 18.1 Receive Side See the IOCR1 and IOCR2 registers for information on clock and I/O configurations. If the receive-side elastic store is enabled, then the user must provide either a 1.544MHz or 2.048MHz clock at the RSYSCLK pin. For higher rate system-clock applications, see the Interleaved PCM Bus Operation section.

  • Page 111: Transmit Side

    8 Clocks < Delay < 1 Frame ESCR.6 1 Frame < Delay < 2 Frames ESCR.3 ½ Frame < Delay < 1 ½ Frames ESCR.7 ½ Frame < Delay < 1 ½ Frames 111 of 248 or search information. DELAY http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 112 Product Preview DS21Q55 respective network clock signals, the elastic store reset bits (ESCR.2 and ESCR.6) should be toggled from a zero to a one to ensure proper operation. 112 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated...

  • Page 113: Intermediate Crc-4 Updating (E1 Mode Only)

    Product Preview 19. G.706 INT ERMEDIATE CRC-4 UPDATING (E1 MODE ONLY) The DS21Q55 can implement the G.706 CRC-4 recalculation at intermediate path points. When this mode is enabled, the data stream presented at TSER will already have the FAS/NFAS, CRC multiframe alignment word, and CRC-4 checksum in timeslot 0.

  • Page 114: T1 Bit Oriented Code (Boc) Controller

    Product Preview DS21Q55 20. T1 BIT ORIENTED CODE (BOC) CONTROLLER The DS21Q55 contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode. 20.1 Transmit BOC Bits 0 through 5 in the TFDL register contain the BOC message to be transmitted.
  • Page 115 Bit 6/Unused, must be set to zero for proper operation. Bit 7/Unused, must be set to zero for proper operation. Please contact telecom.support@dalsemi.com RBOCE RBF1 IDENTIFICATION None 115 of 248 or search http://www.maxim-ic.com information. DS21Q55 RBF0 SBOC 012103 for updated...
  • Page 116 Bit 5/BOC Clear Event (BOCC). Set when 30 FDL bits occur without an abort sequence. Please contact telecom.support@dalsemi.com RBOC5 RBOC4 RBOC3 BOCC RFDLAD RFDLF 116 of 248 or search information. RBOC2 RBOC1 RBOC0 TFDLE RMTCH RBOC http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 117 0 = interrupt masked 1 = interrupt enabled Bit 5/BOC Clear Event (BOCC). 0 = interrupt masked 1 = interrupt enabled Please contact telecom.support@dalsemi.com BOCC RFDLAD RFDLF TFDLE 117 of 248 or search information. RMTCH RBOC http://www.maxim-ic.com for updated DS21Q55 012103...

  • Page 118: Additional (Sa) And International (Si) Bit Operation (E1 Only)

    21. ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION (E1 ONLY) The DS21Q55, when operated in the E1 mode, provides for access to both the Sa and the Si bits via three different methods. The first method is via a hardware scheme using the RLINK/RLC LK and TLINK/TLCLK pins.
  • Page 119 Bit 3/Additional Bit 5 (Sa5). Bit 4/Additional Bit 4 (Sa4). Bit 5 / Remote Alarm (A). Bit 6/Frame Nonalignment Signal Bit (1). Bit 7/International Bit (Si). Please contact telecom.support@dalsemi.com 119 of 248 or search http://www.maxim-ic.com information. for updated DS21Q55 012103...
  • Page 120 Bit 3/Additional Bit 5 (Sa5). Bit 4/Additional Bit 4 (Sa4). Bit 5/Remote Alarm (used to transmit the alarm A). Bit 6/Frame Nonalignment Signal Bit (1). Bit 7/International Bit (Si). Please contact telecom.support@dalsemi.com 120 of 248 or search http://www.maxim-ic.com information. for updated DS21Q55 012103...

  • Page 121: Internal Register Scheme Based O Ncrc4 Multiframe (Method 3)

    Bit 4/Si Bit of Frame 6(SiF6). Bit 5/Si Bit of Frame 4(SiF4). Bit 6/Si Bit of Frame 2(SiF2). Bit 7/Si Bit of Frame 0(SiF0). Please contact telecom.support@dalsemi.com SiF4 SiF6 SiF8 SiF10 121 of 248 or search http://www.maxim-ic.com information. SiF12 SiF14 for updated DS21Q55 012103...
  • Page 122 Bit 6/Remote Alarm Bit of Frame 3(RRAF3). Bit 7/Remote Alarm Bit of Frame 1(RRAF1). Please contact telecom.support@dalsemi.com SiF5 SiF7 SiF9 RRAF5 RRAF7 RRAF9 RRAF11 122 of 248 or search information. SiF11 SiF13 SiF15 RRAF13 RRAF15 http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 123 Bit 5/Sa5 Bit of Frame 5(RSa5F5). Bit 6/Sa5 Bit of Frame 3(RSa5F3). Bit 7/Sa5 Bit of Frame 1(RSa5F1). Please contact telecom.support@dalsemi.com RSa4F5 RSa4F7 RSa4F9 RSa5F5 RSa5F7 RSa5F9 123 of 248 or search information. RSa4F11 RSa4F13 RSa4F15 RSa5F11 RSa5F13 RSa5F15 http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 124 Bit 5/Sa7 Bit of Frame 5(RSa7F5). Bit 6/Sa7 Bit of Frame 3(RSa7F3). Bit 7/Sa7 Bit of Frame 1(RSa4F1). Please contact telecom.support@dalsemi.com RSa6F5 RSa6F7 RSa6F9 RSa7F5 RSa7F7 RSa7F9 124 of 248 or search information. RSa6F11 RSa6F13 RSa6F15 RSa7F11 RSa7F13 RSa7F15 http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 125 Bit 4/Sa8 Bit of Frame 7(RSa8F7). Bit 5/Sa8 Bit of Frame 5(RSa8F5). Bit 6/Sa8 Bit of Frame 3(RSa8F3). Bit 7/Sa8 Bit of Frame 1(RSa8F1). Please contact telecom.support@dalsemi.com RSa8F5 RSa8F7 RSa8F9 125 of 248 or search information. RSa8F11 RSa8F13 RSa8F15 http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 126 Bit 4/Si Bit of Frame 6(TsiF6). Bit 5/Si Bit of Frame 4(TsiF4). Bit 6/Si Bit of Frame 2(TsiF2). Bit 7/Si Bit of Frame 0(TsiF0). Please contact telecom.support@dalsemi.com TsiF4 TsiF6 TsiF8 TsiF10 126 of 248 or search http://www.maxim-ic.com information. TsiF12 TsiF14 for updated DS21Q55 012103...
  • Page 127 Bit 6/Remote Alarm Bit of Frame 3(TRAF3). Bit 7/Remote Alarm Bit of Frame 1(TRAF1). Please contact telecom.support@dalsemi.com TsiF5 TsiF7 TsiF9 TRAF5 TRAF7 TRAF9 TRAF11 127 of 248 or search information. TsiF11 TsiF13 TSiF15 TRAF13 TRAF15 http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 128 Bit 5/Sa5 Bit of Frame 5(TSa5F5). Bit 6/Sa5 Bit of Frame 3(TSa5F3). Bit 7/Sa5 Bit of Frame 1(TSa5F1). Please contact telecom.support@dalsemi.com TSa4F5 TSa4F7 TSa4F9 TSa4F11 TSa5F5 TSa5F7 TSa5F9 TSa5F11 128 of 248 or search information. TSa4F13 TSa4F15 TSa5F13 TSa5F15 http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 129 Bit 5/Sa7 Bit of Frame 5(TSa7F5). Bit 6/Sa7 Bit of Frame 3(TSa7F3). Bit 7/Sa7 Bit of Frame 1(TSa4F1). Please contact telecom.support@dalsemi.com TSa6F5 TSa6F7 TSa6F9 TSa6F11 TSa7F5 TSa7F7 TSa7F9 TSa7F11 129 of 248 or search information. TSa6F13 TSa6F15 TSa7F13 TSa7F15 http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 130 Bit 4/Sa8 Bit of Frame 7(TSa8F7). Bit 5/Sa8 Bit of Frame 5(TSa8F5). Bit 6/Sa8 Bit of Frame 3(TSa8F3). Bit 7/Sa8 Bit of Frame 1(TSa8F1). Please contact telecom.support@dalsemi.com TSa8F5 TSa8F7 TSa8F9 TSa8F11 130 of 248 or search information. TSa8F13 TSa8F15 http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 131 0 = do not insert data from the TSiAF register into the transmit data stream 1 = insert data from the TSiAF register into the transmit data stream Please contact telecom.support@dalsemi.com 131 of 248 or search http://www.maxim-ic.com information. for updated DS21Q55 012103...

  • Page 132: Hdlc Controllers

    Product Preview DS21Q55 22. HDLC CONTROLLERS This device has two enhanced HDLC controllers, HDLC #1 and HDLC #2. Each controller is configurable for use with time slots, or Sa4 to Sa8 bits (E1 Mode) or the FDL (T1 Mode). Each HDLC controller has 128 byte buffers in both the transmit and receive paths.
  • Page 133 Selects which bits in a channel will be used or which Sa bits will be used by the transmit HDLC controller FIFOs Access to 128-byte receive FIFO Access to 128-byte transmit FIFO 133 of 248 or search information. FUNCTION http://www.maxim-ic.com for updated DS21Q55 012103...

  • Page 134: Hdlc Configuration

    Bit 7/Number Of Flags Select (NOFS). 0 = send one flag between consecutive messages 1 = send two flags between consecutive messages Please contact telecom.support@dalsemi.com THMS TEOM 134 of 248 or search http://www.maxim-ic.com information. TZSD TCRCD for updated DS21Q55 012103...
  • Page 135 Bit 7/Receive HDLC Reset (RHR). Will reset the receive HDLC controller and flush the receive FIFO. Must be cleared and set again for a subsequent reset. 0 = normal operation 1 = reset receive HDLC controller and flush the receive FIFO Please contact telecom.support@dalsemi.com 135 of 248 or search http://www.maxim-ic.com information. RSFD for updated DS21Q55 012103...

  • Page 136: Fifo Control

    Bit 6/Unused, must be set to zero for proper operation. Bit 7/Unused, must be set to zero for proper operation. Please contact telecom.support@dalsemi.com TFLWM TFLWM0 RFHWM2 RECEIVE FIFO WATERMARK (BYTES) TRANSMIT FIFO WATERMARK (BYTES) 136 of 248 or search http://www.maxim-ic.com information. DS21Q55 RFHWM1 RFHWM0 012103 for updated...

  • Page 137: Hdlc Mapping

    Bit 7/Receive HDLC Channel Select Bit 7 (RHCS7). Select Channel 8, 16, 24, or 32. Please contact telecom.support@dalsemi.com CHANNELS RHCS5 RHCS4 RHCS3 137 of 248 or search information. 1–8 9–16 17–24 25–32 RHCS2 RHCS1 RHCS0 http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 138 Bit 7/Receive Channel Bit 8 Suppress Enable (RCB8SE). MSB of the channel. Set to one to stop this bit from being used. Please contact telecom.support@dalsemi.com RCB6SE RCB5SE RCB4SE 138 of 248 or search information. RCB3SE RCB2SE RCB1SE http://www.maxim-ic.com for updated DS21Q55 012103...

  • Page 139: Transmit

    Bit 7/Transmit HDLC Channel Select Bit 7 (THCS7). Select Channel 8, 16, 24, or 32. Please contact telecom.support@dalsemi.com CHANNELS THCS5 THCS4 THCS3 THCS2 139 of 248 or search information. 1–8 9–16 17–24 25–32 THCS1 THCS0 http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 140 Bit 7/Transmit Channel Bit 8 Suppress Enable (TCB1SE). MSB of the channel. Set to one to stop this bit from being used. Please contact telecom.support@dalsemi.com TCB6SE TCB5SE TCB4SE 140 of 248 or search information. TCB3SE TCB2SE TCB1SE http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 141 Bit 6/Transmit Message End Event (TMEND). Set when the transmit HDLC controller has finished sending a message. This is a latched bit and will be cleared when read. Please contact telecom.support@dalsemi.com RHWM 141 of 248 or search http://www.maxim-ic.com information. TLWM for updated DS21Q55 012103...
  • Page 142 Bit 5/Receive Packet End Event (RPE). 0 = interrupt masked 1 = interrupt enabled Bit 6/Transmit Message End Event (TMEND). 0 = interrupt masked 1 = interrupt enabled Please contact telecom.support@dalsemi.com RHWM 142 of 248 or search http://www.maxim-ic.com information. TLWM for updated DS21Q55 012103...
  • Page 143 TMEND bit set. An abort is automatically sent. This bit is latched and will be cleared when read. Please contact telecom.support@dalsemi.com TFULL REMPTY PACKET STATUS H2UDR H2OBT 143 of 248 or search http://www.maxim-ic.com information. H1UDR H1OBT for updated DS21Q55 012103...

  • Page 144: Fifo Information

    1 = bytes indicated by RPBA0 through RPBA6 are the beginning or continuation of a message. The host does not need to check the INFO5 or INFO6 register. Please contact telecom.support@dalsemi.com TFBA5 TFBA4 TFBA3 TFBA2 RPBA5 RPBA4 RPBA3 RPBA2 144 of 248 or search information. TFBA1 TFBA0 RPBA1 RPBA0 http://www.maxim-ic.com for updated DS21Q55 012103...

  • Page 145: Hdlc Fifos

    Bit 7/Receive HDLC Data Bit 7 (RHD7). MSB of a HDLC packet data byte. Please contact telecom.support@dalsemi.com THD5 THD4 THD3 RHD5 RHD4 RHD3 145 of 248 or search information. THD2 THD1 THD0 RHD2 RHD1 RHD0 http://www.maxim-ic.com for updated DS21Q55 012103...

  • Page 146: Receive Hdlc Code Example

    The T1RCR2.3 bit should always be set to a one when the device is extracting the FDL. More on how to use the DS21Q55 in FDL applications in this legacy support mode is covered in a separate application note.
  • Page 147 Bit 6/Receive FDL Match Bit 6 (RFDLM6). Bit 7/Receive FDL Match Bit 7 (RFDLM7). MSB of the FDL Match Code. Please contact telecom.support@dalsemi.com RFDL5 RFDL4 RFDL3 RFDLM5 RFDLM4 RFDLM3 147 of 248 or search information. RFDL2 RFDL1 RFDL0 RFDLM2 RFDLM1 RFDLM0 http://www.maxim-ic.com for updated DS21Q55 012103...

  • Page 148: Transmit Section

    TFDL and RFDL registers. Please see the separate application note for a detailed description of how to implement a SLC–96 function. Please contact telecom.support@dalsemi.com TFDL5 TFDL4 TFDL3 TFDL2 148 of 248 or search information. TFDL1 TFDL0 http://www.maxim-ic.com for updated DS21Q55 012103...

  • Page 149: Line Interface Unit (Liu)

    Product Preview 23. LINE INTERFACE UNIT (LIU) The LIU in the DS21Q55 contains three sections: the receiver, which handles clock and data recovery; the transmitter, whic h wave-shapes and drives the network line; and the jitter attenuator. These three sections are controlled by the line interface control registers (LIC1–LIC4), which are described below.

  • Page 150: Liu Operation

    TPOSI and TNEGI is sent via the jitter attenuation MUX to the wave shaping circuitry and line driver. The DS21Q55 will drive the E1 or T1 line from the TTIP and TRING pins via a coupling transformer. The line driver can handle both CEPT 30/ISDN-PRI lines for E1 and long-haul (CSU) or short-haul (DSX-1) lines for T1.

  • Page 151: Receive Level Indicator

    Monitor applications in both E1 and T1 require various flat g ain settings for the receive-side circuitry. The DS21Q55 can be programmed to support these applications via the monitor mode control bits MM1 and MM0 in the LIC3 register (Figure 25-2).

  • Page 152: Liu Transmitter

    TCLK. The transmitter couples to the E1 or T1 transmit twisted pair (or coaxial cable in some E1 applications) via a 1:2 step- up transformer. In order for the device to create the proper waveforms, the transformer used must meet the specifications listed in Table 25-1. The DS21Q55 has the option of using software-selectable transmit termination.

  • Page 153: Mclk Prescaler

    23.5 Jitter Attenuator The DS21Q55 contains an onboard jitter attenuator that can be set to a depth of either 32 bits or 128 bits via the JABDS bit (LIC1.2). The 128-bit mode is used in applications where large excursions of wander are expected.

  • Page 154: Liu Control Registers

    TT1 of the LICR4 register, users can then select the proper internal source termination. Line build-outs 100 and 101 are for backwards compatibility with older products only. Please contact telecom.support@dalsemi.com JABDS 154 of 248 or search http://www.maxim-ic.com information. for updated DS21Q55 012103...
  • Page 155 DSX-1 (533 to 655 feet) -7.5dB CSU -15dB CSU -22.5dB CSU Please contact telecom.support@dalsemi.com N (1) RETURN LOSS 21dB 21dB N (1) RETURN LOSS 155 of 248 or search http://www.maxim-ic.com information. DS21Q55 Rt (1) 6.2O 11.6O Rt (1) 012103 for updated...
  • Page 156 0 = use Transmit AGC, TLBC bits 0–5 are “don’t care” 1 = do not use Transmit AGC, TLBC bits 0–5 set nominal level Bit 7/Unused, must be set to zero for proper operation. Please contact telecom.support@dalsemi.com 156 of 248 or search information. http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 157 Bit 7/E1/T1 Select (ETS). 0 = T1 Mode Selected 1 = E1 Mode Selected Please contact telecom.support@dalsemi.com IBPV TUA1 JAMUX 157 of 248 or search http://www.maxim-ic.com information. SCLD CLDS 0, then the device for updated DS21Q55 012103...
  • Page 158 0 = sample TPOSI and TNEGI on falling edge of TCLKI 1 = sample TPOSI and TNEGI on rising edge of TCLKI Bit 7/Unused, must be set to zero for proper operation. Please contact telecom.support@dalsemi.com RCES RSCLKE 158 of 248 or search http://www.maxim-ic.com information. TSCLKE TAOZ for updated DS21Q55 012103...
  • Page 159 1 = invert CMI signal at TTIP and RTIP Bit 7/CMI Enable (CMIE). 0 = disable CMI mode 1 = enable CMI mode Please contact telecom.support@dalsemi.com MPS1 MPS0 CONFIGURATION CONFIGURATION MPS0 JAMUX (LIC2.3) MPS0 JAMUX (LIC2.3) 159 of 248 or search http://www.maxim-ic.com information. for updated DS21Q55 012103...
  • Page 160 -15.0 to -17.5 -17.5 to -20.0 -20.0 to -22.5 -22.5 to -25.0 -25.0 to -27.5 -27.5 to -30.0 -30.0 to –32.5 -32.5 to -35.0 -35.0 to -37.5 Less than -37.5 160 of 248 or search http://www.maxim-ic.com information. for updated DS21Q55 012103...
  • Page 161 RLT0 — RLT0 Receive Level (dB) Greater than -2.5 -2.5 -5.0 -7.5 -10.0 -12.5 -15.0 -17.5 -20.0 -22.5 -25.0 -27.5 -30.0 -32.5 -35.0 Less than -37.5 161 of 248 or search information. — — — http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 162 CCR4.4 through CCR4.7. The level must remain below the programmed threshold for approximately 50ms for this bit to be set. This is a double interrupt bit. Please contact telecom.support@dalsemi.com RSCOS JALT LRCL 162 of 248 or search information. TCLE TOCD LOLITC http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 163 0 = interrupt masked 1 = interrupt enabled Bit 6/Timer Event (TIMER). 0 = interrupt masked 1 = interrupt enabled Please contact telecom.support@dalsemi.com RSCOS JALT LRCL 163 of 248 or search information. TCLE TOCD LOLITC http://www.maxim-ic.com for updated DS21Q55 012103...

  • Page 164: Recommended Circuits

    R = 37.5O for 75O coaxial E1 lines, 60O for 120O twisted pair E1 lines, or 50O for 100O twisted pair T1 lines. 3) C = 1µF ceramic. Please contact telecom.support@dalsemi.com TTIP TRING RTIP RRING 0.1µF 164 of 248 or search http://www.maxim-ic.com information. DS21Q55 0.1µF .01µF 0.1µF 10µF 0.1µF 10µF for updated DS21Q55 012103...
  • Page 165 The 68 F is used to keep the local power-plane potential within tolerance during a surge. Please contact telecom.support@dalsemi.com 0.1µF 0.1µF 0.1µF 165 of 248 or search information. DS21Q55 0.1µF .01µF TTIP 0.1µF 10µF TRING 0.1µF 10µF RTIP RRING http://www.maxim-ic.com...

  • Page 166: Component Specifications

    Primary (Device Side) Secondary Please contact telecom.support@dalsemi.com RECOMMENDED VALUE 1:1 (receive) and 1:2 (transmit) ±2% 600 H minimum 1.0 H maximum 40pF maximum 1.0O maximum 2.0O maximum 1.2O maximum 1.2O maximum 166 of 248 or search http://www.maxim-ic.com information. DS21Q55 012103 for updated...
  • Page 167 1.15 0.00 0.95 0.00 1.05 0.15 0.90 0.27 1.05 0.23 0.50 0.35 -0.07 0.23 -0.45 0.93 0.05 0.46 -0.45 1.16 0.05 0.66 -0.20 0.93 -0.05 1.16 -0.05 TIME (ns) 167 of 248 or search information. http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 168 Product Preview JITTER TOLERANCE (T1 MODE) Figure 25-8 TR 62411 (Dec. 90) JITTER TOLERANCE (E1 MODE) Figure 25-9 Please contact telecom.support@dalsemi.com DS21Q55 Tolerance ITU-T G.823 FREQUENCY (Hz) DS21Q55 Tolerance Minimum Tolerance Level as per ITU G.823 2.4k FREQUENCY (Hz) 168 of 248 or search information.
  • Page 169 Product Preview JITTER ATTENUATION (T1 MODE) Figure 25-10 -20dB -40dB -60dB JITTER ATTENUATION (E1 MODE) Figure 25-11 -20dB DS21Q55 -40dB E1 MODE -60dB Please contact telecom.support@dalsemi.com DS21Q55 T1 MODE FREQUENCY (Hz) TBR12 Prohibited Area Prohibited Area FREQUENCY (Hz) 169 of 248 or search information.

  • Page 170: Programmable In-Band Loop Code Generation And Detection

    24. PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION The DS21Q55 has the ability to generate and detect a repeating bit pattern from 1 bit to 8 bits or 16 bits in length. This function is available only in T1 mode . To transmit a pattern, the user will load the pattern to be sent into the transmit code definition registers (TCD1 and TCD2) and select the proper length of the pattern by setting the TC0 and TC1 bits in the in-band code-control (IBCC) register.
  • Page 171 Bits 6 to 7/Transmit Code Length Definition Bits (TC0 to TC1). Please contact telecom.support@dalsemi.com RUP2 RUP1 RUP0 RDN0 LENGTH SELECTED (Bits) RUP0 LENGTH SELECTED (Bits) LENGTH SELECTED (Bits) 16/8/4/2/1 171 of 248 or search information. RDN2 RDN1 RDN0 8/16 8/16 http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 172 Bit 6/Transmit Code Definition Bit 6 (C6). A “don’t care” if a 5-, 6-, or 7-bit length is selected. Bit 7/Transmit Code Definition Bit 7 (C7). A “don’t care” if a 5-, 6-, or 7-bit length is selected. Please contact telecom.support@dalsemi.com 172 of 248 or search http://www.maxim-ic.com information. for updated DS21Q55 012103...
  • Page 173 Bit 6/Receive -Up Code Definition Bit 6 (C6). A “don’t care” if a 1-bit to 7-bit length is selected. Bit 7/Receive -Up Code Definition Bit 7 (C7). A “don’t care” if a 1-bit to 7-bit length is selected. Please contact telecom.support@dalsemi.com 173 of 248 or search http://www.maxim-ic.com information. for updated DS21Q55 012103...
  • Page 174 Bit 6/Receive -Down Code Definition Bit 6 (C6). A “don’t care” if a 1-bit length is selected. Bit 7/Receive -Down Code Definition Bit 7 (C7). First bit of the repeating pattern. Please contact telecom.support@dalsemi.com 174 of 248 or search http://www.maxim-ic.com information. for updated DS21Q55 012103...
  • Page 175 Bit 6/Unused, must be set to zero for proper operation. Bit 7/Unused, must be set to zero for proper operation. Please contact telecom.support@dalsemi.com RSC2 RSC0 LENGTH SELECTED (Bits) 8/16 175 of 248 or search http://www.maxim-ic.com information. RSC1 RSC0 for updated DS21Q55 012103...
  • Page 176 Bit 6/Receive -Spare Code Definition Bit 6 (C6). A “don’t care” if a 1-bit to 7-bit length is selected. Bit 7/Receive -Spare Code Definition Bit 7 (C7). A “don’t care” if a 1-bit to 7-bit length is selected. Please contact telecom.support@dalsemi.com 176 of 248 or search http://www.maxim-ic.com information. for updated DS21Q55 012103...

  • Page 177: Bert Function

    Product Preview DS21Q55 25. BERT FUNCTION The BERT (Bit Error Rate Tester) block can generate and detect both pseudorandom and repeating-bit patterns. It is used to test and stress data-communication links. The BERT block is capable of generating and detecting the following patterns: §...

  • Page 178: Bert Register Description

    This bit should be toggled from low to high whenever the host wishes to load a new pattern. Must be cleared and set again for a subsequent loads. Please contact telecom.support@dalsemi.com RINV PATTERN DEFINITION . A 2 - 1 pattern with 14 consecutive zero 178 of 248 or search http://www.maxim-ic.com information. RESYNC for updated DS21Q55 012103...
  • Page 179 Can be used for verifying error detection features. EIB2 EIB1 Please contact telecom.support@dalsemi.com EIB0 RPL3 RPL1 RPL0 EIB0 ERROR RATE INSERTED No errors automatically inserted 10E-1 10E-2 10E-3 10E-4 10E-5 10E-6 10E-7 179 of 248 or search information. RPL2 RPL1 RPL0 http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 180 0 = BERT will not sample data from the F-bit position (framed) 1 = BERT will sample data from the F-bit position (unframed) Bit 7/Unused, must be set to zero for proper operation. Please contact telecom.support@dalsemi.com TBAT TFUS 180 of 248 or search http://www.maxim-ic.com information. BERTDIR BERTEN for updated DS21Q55 012103...
  • Page 181 Bit 6/BERT Bit Error Detected (BED) Event (BBED). A latched bit that is set when a bit error is detected. The receive BERT must be in synchronization for it detect bit errors. Cleared when read. Please contact telecom.support@dalsemi.com BBCO BEC0 BRA1 181 of 248 or search information. BRA0 BRLOS BSYNC http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 182 Bits 0 to 7/Alternating Word Count Rate Bits 0 to 7 (ACNT0 to ACNT7). ACNT0 is the LSB of the 8-bit alternating word count rate counter. Please contact telecom.support@dalsemi.com BBCO BEC0 BRA1 ACNT5 ACNT4 ACNT3 182 of 248 or search information. BRA0 BRLOS BSYNC ACNT2 ACNT1 ACNT0 http://www.maxim-ic.com for updated DS21Q55 012103...

  • Page 183: Bert Repetitive Pattern Set

    Please contact telecom.support@dalsemi.com RPAT5 RPAT4 RPAT3 RPAT13 RPAT12 RPAT11 RPAT21 RPAT20 RPAT19 RPAT29 RPAT28 RPAT27 183 of 248 or search information. RPAT2 RPAT1 RPAT0 RPAT10 RPAT9 RPAT8 RPAT18 RPAT17 RPAT16 RPAT26 RPAT25 RPAT24 http://www.maxim-ic.com for updated DS21Q55 012103...

  • Page 184: Bert Bit Counter

    Bits 0 to 7/BERT Bit Counter Bits 24 to 31 (BBC24 to BBC31). BBC31 is the MSB of the 32-bit counter. Please contact telecom.support@dalsemi.com BBC5 BBC4 BBC3 BBC13 BBC12 BBC11 BBC10 BBC21 BBC20 BBC19 BBC18 BBC29 BBC28 BBC27 BBC26 184 of 248 or search information. BBC2 BBC1 BBC0 BBC9 BBC8 BBC17 BBC16 BBC25 BBC24 http://www.maxim-ic.com for updated DS21Q55 012103...

  • Page 185: Bert Error Counter

    Bits 0 to 7/Error Counter Bits 16 to 23 (EC16 to EC23). EC23 is the MSB of the 24-bit counter. Please contact telecom.support@dalsemi.com EC13 EC12 EC11 EC21 EC20 EC19 185 of 248 or search http://www.maxim-ic.com information. EC10 EC18 EC17 EC16 for updated DS21Q55 012103...

  • Page 186: Payload Error Insertion Function

    26. PAYLOAD ERROR INSERTION FUNCTION An error- insertion function is available in the DS21Q55 and is used to create errors in the payload portion of the T1 frame in the transmit path. Errors can be inserted over the entire frame or on a per-channel basis.
  • Page 187 NOEx registers to be loaded into the error insertion circuitry on the next clock cycle. Subsequent updates require that the WNOE bit be set to zero and then one once again. Please contact telecom.support@dalsemi.com ERROR RATE 187 of 248 or search http://www.maxim-ic.com information. for updated DS21Q55 012103...

  • Page 188: Number Of Error Registers

    Bits 0 to 1/Number of Errors Counter Bits 8 to 9 (C8 to C9). Bit C9 is the MSB of the 10-bit counter. Please contact telecom.support@dalsemi.com READ No errors left to be inserted One error left to be inserted Two errors left to be inserted 1023 errors left to be inserted 188 of 248 or search http://www.maxim-ic.com information. for updated DS21Q55 012103...

  • Page 189: Number Of Errors Left Register

    Name Default Bits 0 to 1/Number of Errors Left Counter Bits 8 to 9 (C8 to C9). Bit C9 is the MSB of the 10-bit counter. Please contact telecom.support@dalsemi.com 189 of 248 or search http://www.maxim-ic.com information. for updated DS21Q55 012103...

  • Page 190: Interleaved Pcm Bus Operation

    In many architectures, the PCM outputs of individual framers are combined into higher speed PCM buses to simplify transport across the system backplane. The DS21Q55 can be configured to allow PCM data to be multiplexed into higher speed buses eliminating external hardware, saving board space and cost. The DS21Q55 can be configured for channel or frame interleave.
  • Page 191 IBS0 IBOSEL IBOEN DEVICE POSITION Device on bus Device on bus Device on bus Device on bus Device on bus Device on bus Device on bus Device on bus 191 of 248 or search http://www.maxim-ic.com information. for updated DS21Q55 012103...
  • Page 192 Product Preview IBO EXAMPLE Figure 29-1 RSYSCLK TSYSCLK RSYNC TSSYNC RSIG TSIG TSER DS21Q55 #1 RSER RSYSCLK TSYSCLK RSYNC TSSYNC RSIG TSIG TSER DS21Q55 #2 RSER Please contact telecom.support@dalsemi.com RSYSCLK TSYSCLK RSYNC TSSYNC RSIG TSIG TSER DS21Q55 #3 RSER RSYSCLK...

  • Page 193: Extended System Information Bus (Esib)

    There are three device pins involved in forming a ESIB group. These are ESIBS0, ESIBS1, and ESIBRD. A 10k pullup resistor must be provided on ESIBS0, ESIBS1, and ESIBRD. ESIB GROUP OF FOUR DS21Q55s Figure 30-1 Please contact telecom.support@dalsemi.com DS21Q55 # 1 ESIB0 CPU I/F ESIB1 ESIBRD...
  • Page 194 Bit 6/Unused, must be set to zero for proper operation. Bit 7/Unused, must be set to zero for proper operation. Please contact telecom.support@dalsemi.com ESIBSEL2 ESIBSEL1 BUS BIT DRIVEN 194 of 248 or search information. ESIBSEL0 ESIEN http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 195 ESSLIP STATUS OUTPUT (T1 MODE) RYEL SIGCHG ESSLIP 195 of 248 or search http://www.maxim-ic.com information. ESI3SEL2 ESI3SEL1 ESI3SEL0 STATUS OUTPUT (E1 MODE) RUA1 RDMA V52LNK SIGCHG ESSLIP STATUS OUTPUT (E1 MODE) RUA1 RDMA V52LNK SIGCHG ESSLIP for updated DS21Q55 012103...
  • Page 196 ESIBSEL0 to ESIBSEL2 bits of the ESIBCR2 register. Please contact telecom.support@dalsemi.com DISn DISn DISn DRLOSn DRLOSn DRLOSn UST1n UST1n UST1n UST2n UST2n UST2n 196 of 248 or search http://www.maxim-ic.com information. DISn DISn DISn DRLOSn DRLOSn DRLOSn UST1n UST1n UST1n UST2n UST2n UST2n for updated DS21Q55 012103...

  • Page 197: Programmable Backplane Clock Synthesizer

    Product Preview 29. PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER The DS21Q55 contains an on-chip clock synthesizer that generates a user-selectable clock referenced to the recovered receive clock (RCLK). The synthesizer uses a phase- locked loop to generate low-jitter clocks. Common applications include generation of port and back plane system clocks.

  • Page 198: Fractional T1/E1 Support

    Product Preview 30. FRACTIONAL T1/E1 SUPPORT The DS21Q55 can be programmed to output gapped clocks for selected channels in the receive and transmit paths to simplify connections into a USART or LAPD controller in fractional T1/E1 or ISDN- PRI applications. This is accomplished by assigning an alternate function to the RCHCLK and TCHCLK pins.

  • Page 199: Jtag-Boundary-Scan Architecture And Test-Access Port

    31. JTAG-BOUNDARY-SCAN ARCHITECTURE AND TEST-ACCESS PORT The DS21Q55 is an MCM consisting of 4 DS2155s. Each device has its on JTAG state machine and therefore is treated as 4 separate devices when testing. The following description refers to the DS2155 JTAG function.
  • Page 200 Product Preview DS21Q55 TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK (Figure 34-2). Test-Logic-Reset Upon power-up, the TAP controller will be in the test-logic-reset state. The instruction register will contain the IDCODE instruction.
  • Page 201 Product Preview DS21Q55 Select-IR-Scan All test registers retain their previous state. The instruction register will remain unchanged during this state. With JTMS LOW, a rising edge on JTCLK moves the controller into the capture-IR state and will initiate a scan sequence for the instruction register. JTMS HIGH during a rising edge on JTCLK puts the controller back into the test- logic-reset state.
  • Page 202 Select Select DR-Scan IR-Scan Capture DR Capture IR Shift DR Shift IR Exit DR Exit IR Pause DR Pause IR Exit2 DR Exit2 IR Update DR Update IR 202 of 248 or search http://www.maxim-ic.com information. for updated DS21Q55 012103...

  • Page 203: Instruction Register

    INSTRUCTION CODES FOR IEEE 1149.1 ARCHITECTURE Table 34-1 INSTRUCTION SAMPLE/PRELOAD BYPASS EXTEST CLAMP HIGH-Z IDCODE Please contact telecom.support@dalsemi.com SELECTED REGISTER Boundary Scan Bypass Boundary Scan Bypass Bypass Device Identification 203 of 248 or search information. INSTRUCTION CODES http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 204 Device ID Contact Factory 4 bits 16 bits DEVICE ID CODES Table 34-3 DEVICE DS2155 DS21354 DS21554 DS21352 Please contact telecom.support@dalsemi.com JEDEC 00010100001 16-BIT ID 0010h 0005h 0003h 0004h 204 of 248 or search http://www.maxim-ic.com information. DS21Q55 012103 for updated...

  • Page 205: Test Registers

    Product Preview DS21Q55 DS21552 0002h 31.2 Test Registers IEEE 1149.1 requires a minimum of two test registers: the bypass register and the boundary scan register. An optional test register has been included with the DS2155 design. This test register is the identification register and is used with the IDCODE instruction and the test- logic-reset state of the TAP controller.
  • Page 206 ESIBS0 TSYNC.cntl – 0 = TSYNC is an input; 1 = TSYNC is an output TSYNC TPOSI TNEGI TCLKI TCLKO TNEGO TPOSO – – TCLK TSER 206 of 248 or search information. CONTROL BIT DESCRIPTION http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 207 0 = ESIBRD is an input;1 = ESIBRD is an output RLINK RLCLK – RCLK – – RDATA (NXA) RPOSI RNEGI RCLKI RCLKO RNEGO RPOSO RCHCLK RSIGF RSIG RSER RMSYNC 207 of 248 or search http://www.maxim-ic.com information. CONTROL BIT DESCRIPTION for updated DS21Q55 012103...

  • Page 208: Functional Timing Diagrams

    4) RLINK data (Fs-bits) is updated one bit prior to even frames and held for two frames. Please contact telecom.support@dalsemi.com TYPE RFSYNC RSYNC.cntl – RSYNC RLOS/LOTC RSYSCLK 208 of 248 or search http://www.maxim-ic.com information. CONTROL BIT DESCRIPTION 0 = RSYNC is an input; 1 = RSYNC is an output for updated DS21Q55 012103...
  • Page 209 7) RLINK data (Z bits) is updated one bit time before odd frames and held for four frames. Please contact telecom.support@dalsemi.com 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 209 of 248 or search information. http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 210 1) RCHBLK is programmed to block channel 24. 2) Shown is RLINK/RLCLK in the ESF framing mode. Please contact telecom.support@dalsemi.com CHANNEL 24 CHANNEL 24 C/A D/B 210 of 248 or search information. CHANNEL 1 CHANNEL 1 http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 211 2) RSYNC is in the input mode (IOCR1.4 = 1). 3) RCHBLK is programmed to block channel 24. Please contact telecom.support@dalsemi.com CHANNEL 24 CHANNEL 24 C/A D/B 211 of 248 or search information. CHANNEL 1 CHANNEL 1 http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 212 4) RCHBLK is forced to one in the same channels as RSER (Note 1). 5) The F-bit position is passed through the receive-side elastic store. Please contact telecom.support@dalsemi.com CHANNEL 32 LSB MSB CHANNEL 32 C/A D/B C/A D/B 212 of 248 or search information. CHANNEL 1 CHANNEL 1 http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 213 3) TSYNC in the multiframe mode (IOCR1.2 = 1). 4) TLINK data (Fs-bits) is sampled during the F-bit position of even frames for insertion into the outgoing T1 stream when enabled via T1TCR1.2. Please contact telecom.support@dalsemi.com 213 of 248 or search http://www.maxim-ic.com information. for updated DS21Q55 012103...
  • Page 214 6) TLINK data (Z bits) sampled during the F-bit time of frames 1, 5, 9, 13, 17, and 21 and inserted into the outgoing stream if enabled via T1TCR1.2. Please contact telecom.support@dalsemi.com 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 214 of 248 or search information. http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 215 3) TCHBLK is programmed to block channel 2. 4) Shown is TLINK/TLCLK in the ESF framing mode. Please contact telecom.support@dalsemi.com CHANNEL 2 LSB MSB CHANNEL 2 DON'T CARE 215 of 248 or search http://www.maxim-ic.com information. DS21Q55 LSB MSB for updated 012103...
  • Page 216 1) TCHBLK is programmed to block channel 24 (if the TPCSI bit is set, then the signaling data at TSIG will be ignored during channel 24). Please contact telecom.support@dalsemi.com CHANNEL 24 CHANNEL 1 F MSB CHANNEL 24 C/A D/B 216 of 248 or search http://www.maxim-ic.com information. DS21Q55 CHANNEL 1 012103 for updated...
  • Page 217 MSB bit position of channel 1. (Normally the transmit side formatter overwrites the F-bit position unless the formatter is programmed to pass-through the F-bit position). Please contact telecom.support@dalsemi.com CHANNEL 32 LSB MSB CHANNEL 32 C/A D/B 217 of 248 or search information. CHANNEL 1 CHANNEL 1 http://www.maxim-ic.com for updated DS21Q55 012103...

  • Page 218: E1 Mode

    4) RLINK will always output all five Sa bits as well as the rest of the receive data stream. 5) This diagram assumes the CAS MF begins in the RAF frame. Please contact telecom.support@dalsemi.com 218 of 248 or search http://www.maxim-ic.com information. for updated DS21Q55 012103...
  • Page 219 4) RSIG normally contains the CAS multiframe-alignment nibble (0000) in channel 1. Please contact telecom.support@dalsemi.com CHANNEL 1 A Sa4 Sa5 Sa6 Sa7 Sa8 CHANNEL 1 Note 4 Sa4 Sa5 Sa6 Sa7 Sa8 219 of 248 or search information. CHANNEL 2 CHANNEL 2 http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 220 2) RSYNC in the output mode (IOCR1.4 = 0). 3) RSYNC in the input mode (IOCR1.4 = 1). 4) RCHBLK is programmed to block channel 24. Please contact telecom.support@dalsemi.com CHANNEL 24/32 220 of 248 or search information. CHANNEL 1/2 http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 221 4) RSIG normally contains the CAS multiframe-alignment nibble (0000) in channel 1. Please contact telecom.support@dalsemi.com CHANNEL 32 LSB MSB CHANNEL 32 221 of 248 or search information. CHANNEL 1 LSB MSB CHANNEL 1 Note 4 http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 222 222 of 248 or search information. F1 C2 F2 C2 F1 C2 F2 C2 F1 C2 F2 C2 F3 C2 F4 C2 F1 C2 F2 C2 F3 C2 F4 C2 FRAMER2, CHANNEL 1 FRAMER2, CHANNEL 1 http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 223 Please contact telecom.support@dalsemi.com FRAMER #1, CHANNELS 1 through 32 BIT LEVEL DETAIL (4.096MHz bus configurtation) FRAMER 1, CHANNEL 1 FRAMER 1, CHANNEL 1 223 of 248 or search information. FRAMER1, CHANNEL 2 FRAMER1, CHANNEL 2 http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 224 1 of timeslot 26. Please contact telecom.support@dalsemi.com RCLK / RSYSCLK TCLK / TSYSCLK CHANNEL 25 RSER / TSER RCHCLK / TCHCLK RCHBLK / TCHBLK 224 of 248 or search http://www.maxim-ic.com information. DS21Q55 CHANNEL 26 LSB MSB 012103 for updated...
  • Page 225 4) This diagram assumes both the CAS MF and the CRC4 MF begin with the TAF frame. 5) TLINK and TLCLK are not synchronous with TSSYNC. Please contact telecom.support@dalsemi.com 9 10 11 12 13 14 15 16 1 225 of 248 or search information. 9 10 http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 226 5) The signaling data at TSIG during channel 1 is normally overwritten in the transmit formatter with the CAS multiframe-alignment nibble (0000). 6) Shown is a TNAF frame boundary. Please contact telecom.support@dalsemi.com CHANNEL 2 LSB MSB CHANNEL 2 DON'T CARE 226 of 248 or search http://www.maxim-ic.com information. DS21Q55 012103 for updated...
  • Page 227 Product Preview DS21Q55 TRANSMIT SIDE BOUNDARY TIMING, TSYSCLK = 1.544MHz (With Elastic Store Enabled) Figure 35-20 TSYSCLK CHANNEL 23 CHANNEL 24 CHANNEL 1 LSB MSB F MSB TSER TSSYNC TCHCLK TCHBLK NOTES: 1) The F-bit position in the TSER data is ignored.
  • Page 228 TSER TSSYNC CHANNEL 31 TSIG TCHCLK TCHBLK NOTE: 1) TCHBLK is programmed to block channel 31. Please contact telecom.support@dalsemi.com CHANNEL 32 LSB MSB CHANNEL 32 228 of 248 or search information. CHANNEL 1 CHANNEL 1 http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 229 229 of 248 or search information. F1 C2 F2 C2 F1 C2 F2 C2 F1 C2 F2 C2 F3 C2 F4 C2 F1 C2 F2 C2 F3 C2 F4 C2 FRAMER2, CHANNEL 1 FRAMER2, CHANNEL 1 http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 230 Please contact telecom.support@dalsemi.com FRAMER #1, CHANNELS 1 through 32 BIT LEVEL DETAIL (4.096MHz bus configurtation) FRAMER 1, CHANNEL 1 FRAMER 1, CHANNEL 1 230 of 248 or search information. FRAMER1, CHANNEL 2 FRAMER1, CHANNEL 2 http://www.maxim-ic.com for updated DS21Q55 012103...

  • Page 231: Operating Parameters

    Product Preview 33. OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS* Voltage Range on Any Pin Relative to Ground Operating Temperature Range for DS21Q55 Operating Temperature Range for DS21Q55N Storage Temperature Range Soldering Temperature * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied.

  • Page 232: Recommended Dc Operating Conditions

    Product Preview RECOMMENDED DC OPERATING CONDITIONS (0 C to +70 C for DS21Q55; -40 C to +85 C for DS21Q55N) PARAMETER Logic 1 Logic 0 Supply CAPACITANCE PARAMETER Input Capacitance Output Capacitance DC CHARACTERISTICS (0 C to +70 C; V = 3.3V 5% for DS21Q55;...

  • Page 233: Ac Timing Parameters And Diagrams

    Capacitive test loads are 40pF for bus signals, 20pF for all others. 34.1 Multipexed Bus AC Characteristics AC CHARACTERISTICS–MULTIPLEXED PARALLEL PORT (MUX = 1) (0 C to +70 C; V = 3.3V 5% for DS21Q55; -40 C to +85 C; V = 3.3V 5% for DS21Q55N) PARAMETER...
  • Page 234 INTEL BUS WRITE TIMING (BTS = 0 / MUX = 1) Figure 37-2 t ASD t ASD AD0-AD7 Please contact telecom.support@dalsemi.com t CYC ASED t DDR t CYC ASED 234 of 248 or search information. http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 235 MOTOROLA BUS TIMING (BTS = 1 / MUX = 1) Figure 37-3 t ASD PW EL R/W* AD0-AD7 (read) t ASL AD0-AD7 (write) Please contact telecom.support@dalsemi.com t ASED t CYC t RWS t CS 235 of 248 or search http://www.maxim-ic.com information. DS21Q55 PW EH t CH 012103 for updated...

  • Page 236: Nonmultiplexed Bus Ac Characteristics

    Product Preview 34.2 Nonmultiplexed Bus AC Characteristics AC CHARACTERISTICS–NONMULTIPLEXED PARALLEL PORT (MUX = 0) (0 C to +70 C; V = 3.3V 5% for DS21Q55; -40 C to +85 C; V = 3.3V 5% for DS21Q55N) PARAMETER Setup Time for A0 to A7, Valid to...
  • Page 237 0ns min. 0ns min. Please contact telecom.support@dalsemi.com Address Valid Data Valid 5ns min. / 20ns max. 0ns min. 75ns max. 10ns min. 75ns min. 237 of 248 or search information. 0ns min. 10ns min. 0ns min. http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 238 Please contact telecom.support@dalsemi.com Address Valid Data Valid 5ns min. / 20ns max. 0ns min. 75ns max. Address Valid 10ns min. 75ns min. 238 of 248 or search information. 0ns min. 10ns t7 t8 min. 0ns min. http://www.maxim-ic.com for updated DS21Q55 012103...

  • Page 239: Receive Side Ac Characteristics

    Product Preview 34.3 Receive Side AC Characteristics AC CHARACTERISTICS–RECEIVE SIDE (0 C to +70 C; V = 3.3V 5% for DS21Q55; 40 C to +85 C; V = 3.3V 5% for DS21Q55N) PARAMETER RCLKO Period RCLKO Pulse Width RCLKO Pulse Width...
  • Page 240 2) Shown is RLINK/RLCLK in the ESF framing mode. 3) No relationship between RCHCLK and RCHBLK and other signals is implied. Please contact telecom.support@dalsemi.com F Bit t D2 t D2 t D2 t D1 240 of 248 or search http://www.maxim-ic.com information. DS21Q55 012103 for updated...
  • Page 241 2) RSYNC is in the input mode. 3) F-bit when CCR1.3 = 0, MSB of TS0 when CCR1.3 = 1. Please contact telecom.support@dalsemi.com SEE NOTE 3 t SU 241 of 248 or search http://www.maxim-ic.com information. t SP for updated DS21Q55 012103...
  • Page 242 Product Preview RECEIVE LINE INTERFACE TIMING Figure 37-10 RCLKO t DD RPOSO, RNEGO RCLKI RPOSI, RNEGI Please contact telecom.support@dalsemi.com t SU t HD 242 of 248 or search information. t LP t CP http://www.maxim-ic.com for updated DS21Q55 012103...

  • Page 243: Transmit Ac Characteristics

    Product Preview 34.4 Transmit AC Characteristics AC CHARACTERISTICS–TRANSMIT SIDE (0 C to +70 C; V = 3.3V 5% for DS21Q55; -40 C to +85 C; V = 3.3V 5% for DS21Q55N) PARAMETER TCLK Period TCLK Pulse Width TCLKI Period TCLKI Pulse Width...
  • Page 244 5) TLINK is only sampled during F-bit locations. 6) No relationship between TCHCLK and TCHBLK and the other signals is implied. Please contact telecom.support@dalsemi.com t SU t HD t D2 244 of 248 or search information. http://www.maxim-ic.com for updated DS21Q55 012103...
  • Page 245 1) TSER is only sampled on the falling edge of TSYSCLK when the transmit-side elastic store is enabled. 2) TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit-side elastic store is enabled. Please contact telecom.support@dalsemi.com t HD t D3 245 of 248 or search http://www.maxim-ic.com information. DS21Q55 012103 for updated...
  • Page 246 Product Preview DS21Q55 TRANSMIT LINE INTERFACE TIMING Figure 37-13 TCLKO TPOSO, TNEGO t DD TCLKI t SU TPOSI, TNEGI t HD 246 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated information.

  • Page 247: Mechanical Descriptions

    Product Preview DS21Q55 35. MECHANICAL DESCRIPTIONS 247 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated information.
  • Page 248 Product Preview DS21Q55 248 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated information.

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