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User Manuals: Marvell GT-64260A MIPS System Controller
Manuals and User Guides for Marvell GT-64260A MIPS System Controller. We have
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Marvell GT-64260A MIPS System Controller manual available for free PDF download: Design Manual
Marvell GT-64260A Design Manual (163 pages)
Brand:
Marvell
| Category:
Controller
| Size: 1 MB
Table of Contents
Table of Contents
3
Related Documentation
11
Section 1. Introduction
11
2 Section 2. GT-64260A Overview
12
Figure 1: GT-64260A Interfaces
12
Figure 2: Typical GT-64260A System Configuration
13
CPU Pinout Description
14
3 Section 3. CPU Interface Functional Overview
14
Table 1: CPU Interface Pin Information
14
Bus Mode
17
Cache Coherency
18
MPX Bus Mode
18
Table 2: GT-64260A Supported Features in MPX Bus Mode
18
Figure 3: PCI Reads from Cache Coherent Regions
19
Table 3: IDMA Address Base/Top Registers
19
Table 4: PCI Address Base/Top Registers
20
Specific Cpus Aspects
21
Figure 4: PPC750FX CPU Keeper
23
Multi-GT or Multi-Slave Modes
24
Figure 5: Multi-GT System Architecture
25
Table 5: Multi-GT Device ID
25
CPU Bus Multiple Masters
26
Table 6: Multi-GT Mode Transaction Translation
26
Figure 6: 2 Cpus Connection through Internal 60X Arbiter
27
Figure 7: Two Cpus Connected through an External Arbiter
28
Figure 8: Interrupt Pins' Connectivity
30
Figure 9: CPU to CPU Cache Coherency Data Flow
30
Figure 10: IBM Riscwatchtm JTAG to HRESET, TRST, and SRESET Pin Connector
31
Figure 11: Motorola JTAG to HRESET and TRST Pin Connector
31
Powerpc COP/JTG Interface
31
Figure 12: JTAG/COP 16 Pin Connectors
32
4 Section 4. SDRAM Interface Functional Overview
33
Pinout Description
33
Table 7: SDRAM Interface Pinout Description
33
Memory Connection
35
Table 8: SDRAM Interface Pinout Description
36
Table 9: SDRAM Memory Space
36
Figure 13: SDRAM Connection for Regular Sdram/Heavy Load Mode
37
Figure 14: SDRAM Connection for Registered SDRAM Mode
38
SDRAM Address Control
39
Table 10: ECC Bank Selection
39
ECC Support
40
SDRAM Initialization
40
Memory Banks and
42
Figure 15: Two Read Interleaving from Different Virtual Banks
43
Figure 16: Single Read Access to Non-Open Page
44
Figure 17: Single Read Access to Open Page
44
5 Section 5. PCI Interface Functional Overview
46
Figure 18: Typical P2P System Configuration
46
P2P Capability
46
Figure 19: I/O P2P Transaction Example
47
Table 11: PCI P2P Configuration Register Initialization Example
47
PCI Arbitration
48
Table 12: Internal PCI Arbiter in Multiplexing
48
32-Bit PCI System
49
Delayed Read
49
Cache Coherency
50
Message Signaled Interrupt (MSI)
50
6 Device Interface Functional Overview
51
Device Connection
51
Figure 20: Three Device Connection Example
52
8-Bit Device
53
Figure 21: 8-Bit Device Connection Example
54
16-Bit Device
55
Figure 22: 16-Bit Device Connection Example
55
32-Bit Device
56
Figure 23: 32-Bit Device Connection Example
57
Figure 24: Device Burst Read Example
58
Signals Timing
58
Figure 25: Device Burst Write Example
59
Ready Support
59
Figure 26: SCD Pipeline Sync Burst SRAM Read Example
60
Figure 27: DCD Pipeline Sync Burst SRAM Read Example
60
7 Communication Interface Functional Overview
61
Syncburst SRAM
60
Ethernet Controllers
61
Cache Coherency
62
MPSC Controllers
62
Figure 28: SDMA Descriptor Format
63
MPSC and Ethernet SW Implications
63
Figure 29: Rx Descriptor Chain
65
Figure 30: Disconnecting the Descriptor Chain
66
Figure 31: Releasing the Descriptor Chain
67
I2C Interface
70
Figure 32: GT-64260A I2C Interface Connection to SDRAM DIMMS
71
Baud Rate Generator
72
8 Multi -Purpose Pin Interface Functional Overview
74
General Purpose Pin (GPP)
74
Figure 33: GPP Configured as Input
75
Interrupt Outputs
75
DMA Acknowledge
76
DMA Request
76
Figure 34: MPP Interrupt Outputs
76
PCI Arbiter
76
BRG Clock
77
9 Jtag Interface Functional Overview
78
DMA End of Transfer
77
Initialization Active
77
Timer Counter Enable
77
Unified Memory Architecture Control
77
Idma Unit Functional Overview
79
Figure 35: DMA Controller General Flow
80
Cache Coherency
81
11 Section 11. Interrupt Controller Functional Overview
82
Chain Mode
81
Figure 36: Interrupt Routing Example
83
Figure 37: GT-64260A Interrupt Routing Architecture
84
Figure 38: Interrupt Handling Procedure
85
Figure 39: External Interrupt Controller
86
Using External Interrupt Controller
86
Doorbell
87
Messaging
87
Section 12. Messaging Units Functional Overview
87
Circular Queue
88
Figure 40: Inbound Circular Queue
88
Figure 41: Outbound Circular Queue
89
Figure 42: GT-64260A Overshoot/Undershoot Voltage
90
Cpu Interface Design Considerations
91
Section 13. Design Consideration Overview
90
CPU Interface Connectivity
91
Table 13: CPU Interface Configuration at Reset
91
Electrical Specification
92
Figure 43: GT-64260A Test Circuit (Cload = 15Pf)
92
Termination Topology
92
Timing Requirements
92
Figure 44: Test Circuit Results (Cload = 15Pf)
93
Figure 45: GT-64260A Test Circuit (Rload = 50 Ohm)
94
Figure 46: Test Circuit Results (Rload = 50 Ohm)
94
Figure 47: GT-64260A to CPU Point-To-Point Configuration
95
Table 14: Typical CPU AC Timings
95
Table 15: Single-GT and Single CPU AC Timing
95
Figure 48: 1 Ns Delay Trace Simulation
96
Figure 49: 0.8 Ns Delay Trace Simulation
97
Figure 50: GT-64260A to Multiple CPU Configuration
98
Table 16: Single-GT and Multiple CPU AC Timing
98
Figure 51: 0.5 Ns Delay Trace Simulation (Maximum Distance 2.5 Inches)
99
Figure 52: 0.5 Ns Delay Trace Simulation (Maximum Distance 4 Inches)
100
Figure 53: Multiple GT-64260As to a Single CPU Configuration
101
Table 17: Multiple GT-64260As and a Single CPU AC Timing
101
Figure 54: 1.1 Ns Delay Trace Simulation
102
Figure 55: 0.8 Ns Delay Trace Simulation
103
Figure 56: Layout for a Single GT-64260A to a Single CPU
104
Layout Instructions
104
Figure 57: Layout for a Single GT-64260A to Multiple Cpus
105
Sdram Interface Design Considerations
106
Electrical Specification
106
Interface Connectivity
106
Termination Topology
106
Figure 58: SDRAM Configuration Example
107
Figure 59: SDRAM Simulation Example
107
Figure 60: SDRAM Configuration Example (with Resistors)
108
Figure 61: SDRAM Simulation Example (with Resistors)
109
Table 18: Signal Topology Categories
109
Timing Requirements
109
Figure 62: DIMM Clock Topology
111
Figure 63: GT-64260A Data Reference Point
112
Figure 64: SDRAM Data Reference Point
113
Figure 65: Selected Memory Configuration Data Topology
114
Table 19: Trace Length for Data Topologies
114
Figure 66: DIMM Connector Package Model
115
Table 20: GT-64260A SDRAM Interface AC Timing
115
Table 21: Typical SDRAM Interface AC Timing
115
Figure 67: 0.8 Ns Delay Trace Simulation (2.1 Ns Fly Time Reference Point)
116
Figure 68: 0.8 Ns Delay Trace Simulation (1.54 Ns Fly Time Reference Point)
117
Figure 69: GT-64260A Test Circuit (Cload = 50Pf)
118
Figure 70: GT-64260A Chip Select Reference Point
119
Figure 71: Chip Select Signal Routing on the DIMM Module
120
Table 22: Trace Length for Data Topologies
121
Table 23: GT-64260A CS AC Timing
121
Table 24: Typical SDRAM CS AC Timing
121
Figure 72: 0.8 Ns Delay Trace Simulation (2.8 Ns Fly Time Reference Point)
122
Figure 73: GT-64260A Double Cycle Signals AC Timing
123
Figure 74: Double Cycle Signal Routing on the DIMM Module
124
Table 25: Trace Length for Double Cycle Signal Topologies
124
Table 26: GT-64260A Double Cycle Signals AC Timing
125
Table 27: Typical SDRAM CS AC Timing
125
Figure 75: 0.8 Ns Delay Trace Simulation (2.0 Ns Fly Time Reference Point)
126
Layout Instructions
126
Figure 76: Device Placement Example
127
Pci Interface Design Considerations
128
Electrical Definition
128
Interface Connectivity
128
Termination Topology
128
Timing Requirements
128
Table 28: PCI AC Timing for 33 Mhz and 66 Mhz (from the PCI Specification Document, Rev. 2.2)
129
Table 29: GT-64260A PCI Interface AC Timing
129
Figure 77: GT-64260A Test Circuit (Cload = 20Pf)
131
Figure 78: GT-64260A GNT* Signals Reference Point
132
Figure 79: 2.1 Ns Fly Time Reference Point
133
Layout Instructions
133
Figure 80: MII Interface Connection
134
Interface Connectivity
134
Section 17. Ethernet Interface Design Considerations
134
Electrical Specification
135
Figure 81: RMII Interface Connection
135
Termination Topology
135
Timing Requirements
135
Table 30: RMII AC Timing for 50 Mhz (from RMII Specification Rev. 1.2 Document)
136
Table 31: Ethernet RMII Interface
136
Figure 82: GT-64260A RMII Signals Reference Point
137
Figure 83: 2.1 Ns Fly Time Reference Point
138
Layout Instructions
138
Figure 84: PHY Placement
139
De-Coupling Recommendations
140
Section 18. Power Supply
140
Table 32: GT-64260A Voltages
140
Figure 85: GT-64260A Power Supply Pin Map
142
Section 19. Clocks
143
Reset Configurations
144
Section 20. Reset
144
Communication Unit
145
Section 21. Bringing up the System (Debugging)
145
Section 22. Revision History
146
Table 33: Revision History
146
I2C Eeprom Example
147
SDRAM Mode Register/Code
149
Appendix B. Sdram Mode Register /Code
150
Ecc Initialization - Example Code
150
Appendix C. Ecc Initialization- Examplecode
152
Appendix D. Big and Little Endian Support
152
Communication Descriptors152
152
Internal Register152
152
Table 34: Big and Little Endian Bit Ordering
152
PCI Interface
153
Swapping Options
153
Table 35: PCI Big Endian Bit Ordering
153
Table 36: Data Swapping
154
Table 37: Master Swapping
155
Table 38: Master Swapping
156
Table 39: Swapping for All Eight Options
156
Appendix E. Communication Example Code
158
Ethernet Initialization
158
Ethernet API
159
Mpsc Api
160
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