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Marvell GT-64260A Design Manual

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GT-64260A Design Guide
Doc. No. MV-S300165-00, Rev. A
May 21, 2002

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Summary of Contents for Marvell GT-64260A

  • Page 1 GT-64260A Design Guide Doc. No. MV-S300165-00, Rev. A May 21, 2002...
  • Page 2 No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any particular purpose.

  • Page 3: Table Of Contents

    PCI Arbitration........................... 48 Delayed Read ..........................49 32-bit PCI System........................49 Cache Coherency........................50 Message Signaled Interrupt (MSI) ................... 50 CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary Document Classification: Proprietary Information Page 3...
  • Page 4 GT-64260A Design Guide .......... 51 ECTION EVICE NTERFACE UNCTIONAL VERVIEW Device Connection ........................51 8-bit Device ..........................53 16-bit Device ..........................55 32-bit Device ..........................56 Signals Timing .......................... 58 Ready Support .......................... 59 Syncburst SRAM ........................60 ......61...
  • Page 5 15.4 Timing Requirements ......................109 15.5 Layout Instructions.........................126 16. PCI I .......... 128 ECTION NTERFACE ESIGN ONSIDERATIONS 16.1 Interface Connectivity......................128 16.2 Electrical Definition.........................128 CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary Document Classification: Proprietary Information Page 5...
  • Page 6 GT-64260A Design Guide 16.3 Termination Topology......................128 16.4 Timing Requirements......................128 16.5 Layout Instructions ........................ 133 17. E ......... 134 ECTION THERNET NTERFACE ESIGN ONSIDERATIONS 17.1 Interface Connectivity ......................134 17.2 Electrical Specification ......................135 17.3 Termination Topology......................135 17.4 Timing Requirements......................135 17.5 Layout Instructions ........................
  • Page 7 D.4 Swapping Options........................153 E. C ............158 PPENDIX OMMUNICATION XAMPLE E.1 Ethernet Initialization......................158 E.2 Ethernet API..........................159 E.3 MPSC API..........................160 CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary Document Classification: Proprietary Information Page 7...
  • Page 8 Table 22: Trace Length for Data Topologies ...................... 121 Table 25: Trace Length for Double Cycle Signal Topologies ................124 Table 26: GT-64260A Double Cycle Signals AC Timing ..................125 Table 27: Typical SDRAM CS AC Timing ......................125 Table 28: PCI AC Timing for 33 MHz and 66 MHz (From the PCI Specification Document, Rev. 2.2) ....129 Table 29: GT-64260A PCI Interface AC Timing ....................
  • Page 9 Figure 29: Rx Descriptor Chain ..........................65 Figure 30: Disconnecting the Descriptor Chain .....................66 Figure 31: Releasing the Descriptor Chain......................67 Figure 32: GT-64260A I2C Interface Connection to SDRAM DIMMS ..............71 Figure 33: GPP Configured as Input ........................75 Figure 34: MPP Interrupt Outputs..........................76 Figure 35: DMA Controller General Flow ......................80...
  • Page 10 Figure 54: 1.1 ns Delay Trace Simulation ......................102 Figure 55: 0.8 ns Delay Trace Simulation ......................103 Figure 56: Layout for a Single GT-64260A to a Single CPU ................104 Figure 57: Layout for a Single GT-64260A to Multiple CPUs ................105 Figure 58: SDRAM Configuration Example ......................107 Figure 59: SDRAM Simulation Example ......................107...

  • Page 11: Section 1. Introduction

    Related Documentation Section 1. Introduction This design guide provides information for designing a system using the GT-64260A. This guide is intended for internal and external reference and is subject to future changes and modifications. Use this document as an addition to the GT-64260A datasheet and evaluation/reference design schematics.

  • Page 12: Section 2. Gt-64260A Overview

    Section 2. GT-64260A Overview The GT-64260A is a bridge from the PowerPC processor to the PCI bus, as well as a high-speed memory control- ler for external ROM and external peripherals. In addition, the GT-64260A integrates three 10/100 Mbps Ethernet ports and two MPSC controllers.

  • Page 13: Figure 2: Typical Gt-64260A System Configuration

    GT-64260A Overview Figure 2: Typical GT-64260A System Configuration Boot 2 Gigabyte DRAM Flash SDRAM i/f Device i/f PCI0 i/f OC-48 Back Plane CPU I/f Routing Framing Tranceiver PowerPC ASIC Unit PCI0 i/f 8xIDMA 3x10/100 2xMPSC GPP Box Mang. UART Monitor CONFIDENTIAL Copyright ©...

  • Page 14: Section 3. Cpu Interface Functional Overview

    (such as SDRAM, ROM, PCI, etc.). Generally, there is a point-to-point connection between the GT-64260A and the CPU. In other cases, it depends on the system architecture, such as multi-GT-64260A, multiple CPU, or exter- nal arbiter. The following table describes the pin information and details of the GT-64260A CPU interface.
  • Page 15 0 = SysClk asynchronous to be tied to GND. TClk. 1 = CPU interface is running with TClk. SysRst* Section 20. "Reset" on The GT-64260A main reset page 144. pin. When in the reset state, all output pins (except for SDRAM address and control pins) are put into tri-state.
  • Page 16 (See the MPC75x user manual) DTI[2] pulled down. For all other configu- rations 10K-Ohm pull-down. BR0*/ When using the GT-64260A To avoid unstable GT_BG* internal arbiter, connect to the states at reset, a primary CPU BR* pin. 10K-Ohm Pull-up is When using an external arbiter, recommended.

  • Page 17: Bus Mode

    60x Bus Mode The GT-64260A can act as master and slave on the 60x bus. In this mode, the GT-64260A 60x internal arbiter sup- ports three masters on the bus; two external 60x compatible masters, and an internal 60x master. The GT-64260A is configured to 60x bus mode by having the AD[7:6] signals sampled to b’00’...

  • Page 18: Mpx Bus Mode

    The GT-64260A supports full cache coherency between the SDRAM and CPU caches. Any access to the SDRAM (from PCI or IDMA) may result in a snoop transaction driven by the GT-64260A on the CPU bus. The SDRAM access to a cache coherent region is always suspended until the snoop is resolved. In case of a HIT in a modified line in CPU cache, the SDRAM access might be suspended until the line write-back to SDRAM is completed.

  • Page 19: Table 3: Idma Address Base/Top Registers

    PCI bus The GT-64260A supports up to four SDRAM address windows in which IDMA cache coherency is maintained. The address windows do not correlate to specific chip selects and may cross CS boundaries. The GT-64260A also supports eight configurational address ranges (four for each PCI interface) that help maintain PCI cache coherency.

  • Page 20: Table 4: Pci Address Base/Top Registers

    CleanBlock FlushBlock bits [13:12] to the correct value, depending on the CPU type. See the GT-64260A datasheet’s "CPU Interface" sec- tion for more information. Configure cache coherent windows for the desired interface with the PCI cache coherency registers (0x1F00 - 0x1F38) and the IDMA cache coherency registers (0x380 - 0x3B8).

  • Page 21: Specific Cpus Aspects

    In MPX bus mode, a cache-inhibited instruction fetch performs a 16 byte transaction on the bus. Since the MPC745x’s first transaction after boot is 32/16 byte read and the GT-64260A does not support burst longer than 8 byte from 8-bits or 16-bits wide devices, implement one of the following solutions.
  • Page 22 Therefore, when using one of these CPUs, it must be configured to work in 2.5V on the CPU bus by configuring the CPU’s BVSEL pin to the correct value at reset. In addition, the GT-64260A’s CPU interface must be configured to 2.5V at reset by setting AD31 to ’0’.

  • Page 23: Figure 4: Ppc750Fx Cpu Keeper

    Theoretically, two keepers can end up in contention during power up. However, since this would be unstable, any noise event would knock it to a '1' or '0'. CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary...

  • Page 24: Multi-Gt Or Multi-Slave Modes

    Multi-GT or Multi-slave Modes It is possible to connect up to four GT-64260A or other 60x-bus compliant slave devices to the 60x bus without the need for any glue logic.This capability (referred to as "Multi-GT" mode) adds significant system design flexibility.

  • Page 25: Table 5: Multi-Gt Device Id

    Table 1, “CPU Interface Pin Information,” on page 14). All TA* outputs from the GT-64260A devices must be tied together to drive the CPU TA* input. All AACK* outputs from the GT-64260A devices must be tied together to drive the CPU AACK* input.

  • Page 26: Cpu Bus Multiple Masters

    0x100. A write transaction to address 0x00000000 gets a response from the GT-64260A configured as ID=’00’. This transaction is translated to a write to its internal regis- ter offset at 0x000.

  • Page 27: Figure 6: 2 Cpus Connection Through Internal 60X Arbiter

    The BR0*/GT_BG* pin is used as the GT-64260A bus grant. • The BR1*/GT_DBG* pin is used as the GT-64260A data bus grant. Figure 7 describes the connection of two CPUs and a GT-64260A to an external arbiter: CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A...

  • Page 28: Figure 7: Two Cpus Connected Through An External Arbiter

    Inter-Processor Interrupts (IPIs). The GT-64260A achieves the same goal by masking the BR1* pin from the internal arbiter. This causes the arbiter to think that only CPU0 needs the bus and it does not grant the bus to CPU1. To enable CPU1 arbitration, set the CPU Master Control register’s...
  • Page 29 The TBEN pin provided on the PowerPC CPUs can be used to implement this clock control function. Instead of using a dedicated pin for this purpose, the GT-64260A uses an MPP pin to enable this synchronization. The MPP must be configured to function as a general purpose output and must be connected to all of the CPUs’...

  • Page 30: Figure 8: Interrupt Pins' Connectivity

    Figure 9: CPU to CPU Cache Coherency Data Flow 1. CPU1 initailizes the read cache block transaction to cache coherent memory. 2. CPU0 signs to CPU1 and to the GT-64260A that this cache block is valid in its cache. 4. CPU1 reads the updated block from SDRAM.

  • Page 31: Powerpc Cop/Jtg Interface

    It is recommended to implement both connections on the board since different ICE tools require different connec- tions. Figure 12 describes the JTAG/COP 16-pins connectors. CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary Document Classification: Proprietary Information Page 31...

  • Page 32: Figure 12: Jtag/Cop 16 Pin Connectors

    GT-64260A Design Guide Figure 12: JTAG/COP 16 Pin Connectors Top View Pins 10, 12, and 14 are no-connects. Pin 14 is not physically present. No pin Note The JTAG pins for the COP interface must not be chained with other devices in the system.

  • Page 33: Section 4. Sdram Interface Functional Overview

    Section 4. SDRAM Interface Functional Overview The GT-64260A SDRAM controller supports 16/64/128/256/512 MB density SDRAM and registered SDRAM at 133 MHz. It also supports up to four banks of SDRAM and can address up to 4 GB (1 GB per bank – physical SCS*).
  • Page 34 GT-64260A Design Guide Table 7: SDRAM Interface Pinout Description (Continued) P in Name Inpu t/ SD RA M D evice or R equ ir ed D escr ipt ion Ou tpu t DI MM Con nect or E xt ern al...

  • Page 35: Memory Connection

    DRAM specification (100 us of idle cycles before DRAM initialization). Memory Connection The GT-64260A supports 16, 64, 128, 256 and 512 MB SDRAM devices. Each SDRAM physical bank (SCS[3:0]) can be built from different SDRAM devices. The DRAM density is configured via the DRAM Bank Parameter regis- ters.

  • Page 36: Table 8: Sdram Interface Pinout Description

    GT-64260A Design Guide Table 8: SDRAM Interface Pinout Description (Continued) S DR AM A ddr essi ng x1 6 128 Mb A0 - A11 A0 - A11 A0 - A11 A0 - A11 (4 virtual banks) Column A0 - A9, A11...

  • Page 37: Figure 13: Sdram Connection For Regular Sdram/Heavy Load Mode

    SDRAM connection for registered SDRAM mode. It uses four, 16-bit wide devices con- nected in parallel to achieve a 64-bit data path. CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary Document Classification: Proprietary Information...

  • Page 38: Figure 14: Sdram Connection For Registered Sdram Mode

    8-bit ECC (72-bit wide) to check the ECC. On partial writes, the GT-64260A reads all 64-bits of data and 8-bit ECCs to check the ECC. The GT-64260A then modifies the data bytes (less than 8B) and the ECC bank writes the updated data back.

  • Page 39: Sdram Address Control

    Note The row and column address translation is different for 16 Mb, 64/128Mb, or 256/512 MB SDRAMs. For more information, see the GT-64260A datasheet’s "SDRAM Density" section. CONFIDENTIAL Copyright © 2002 Marvell Doc.

  • Page 40: Sdram Initialization

    GT-64260A Design Guide SDRAM Initialization The DRAM controller executes the SDRAM initialization sequence as soon as the GT-64260A goes out of reset (SysRst* de-assert). The DRAM controller performs a MRS (Mode Register Setting) cycle based on the default DRAM parameters (CL = 3, burst length = 4, burst order = linear). If the serial ROM initialization is enabled, the DRAM controller postpones the above DRAM initialization sequence until the serial ROM initialization completes.
  • Page 41 [9] and the bits [23:16], at offset 0x494 ErrProp ThrEcc to ‘0’. This prevents the GT-64260A from generating an interrupt or propagating the ECC error to other interfaces. In the SDRAM Timing Parameters register, at offset 0x4b4, set the ECCEn bit [13] to ’1’...

  • Page 42: Memory Banks And

    Use the IDMA engines, with DTL of 8B, to copy the boot code to the SDRAM from the boot device. It is impor- tant to use DTL = 8 Bytes to prevent the GT-64260A from performing a Read Modify Write to the SDRAM before the ECC initialization.

  • Page 43: Figure 15: Two Read Interleaving From Different Virtual Banks

    [3:0], at offset 0x44c, 0x450, 0x454 and 0x458 to ‘1’. The figure below shows a single read access to a non-open page when the open pages are disabled. CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary...

  • Page 44: Figure 16: Single Read Access To Non-Open Page

    GT-64260A Design Guide Figure 16: Single Read Access to Non-open Page 25ns 50ns 75ns TCLK DAdr[12:0] 0x0000 SDQM* SDATA SRAS* SCAS* DWr* • Cycle 2: Row activating. • Cycle 4: Column cycle (command). • Cycle 6: Fetch first data – can be 2 or 3 cycles (depends on the CL parameters).
  • Page 45 • The refresh counter expires. The DRAM controller closes all of the open pages and performs a refresh to all banks. CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary Document Classification: Proprietary Information Page 45...

  • Page 46: Section 5. Pci Interface Functional Overview

    GT-64260A Design Guide Section 5. PCI Interface Functional Overview The GT-64260A supports two 64-bit PCI interfaces, compliant with the PCI specification, Rev. 2.2. Each PCI inter- face can be individually configured to a 32- or 64-bit configuration. The GT-64260A PCI0 interface supports ComactPCI Hot Swap. For more information on the CompactPCI Hot- Swap feature, see the GT-64260A datasheet’s "Hot Swap"...

  • Page 47: Table 11: Pci P2P Configuration Register Initialization Example

    5.1.1 Memory and I/O P2P Transactions To support access between the two PCI interfaces, the GT-64260A contains two 32-bit Memory BARs and one 32- bit I/O BAR. It also supports two additional Memory BARs for 64-bit addressing (DAC). A PCI address hit in one of the P2P BARs results in transferring the transaction to the other PCI interface memory space.

  • Page 48: Pci Arbitration

    When the internal arbiter is enabled the GT-64260A PCI arbiter REQ*/GNT* pins are multiplexed on the MPP pins. Each internal PCI arbiter (PCI0 and PCI1) supports up to six external PCI devices and the GT-64260A PCI device (seven PCI devices per PCI interface).

  • Page 49: Delayed Read

    All IO reads are treated as delayed read. 32-bit PCI System The GT-64260A can be configured to work in a 32-bit PCI bus mode. Each PCI interface (PCI0 and PCI1) can be individually configured to 32- or 64-bit modes. CONFIDENTIAL Copyright ©...

  • Page 50: Cache Coherency

    Set the message address in the PCI MSI Message Address registers, at offsets 0x54 and 0xd4. If DAC is needed, set the PCI MSI Message Upper Address registers, at offsets 0x58 and 0xd8. The GT-64260A ini- tiates a write transaction to this address as soon as an interrupt is pending.

  • Page 51: Device Interface Functional Overview

    • Device1_CS* = ‘NOT’(Address[30]) ‘OR’ (CSTiming* ‘OR’ CS*0) Figure 20 shows an example of how three devices are connected through the GT-64260A device interface connec- tion. Note Since CSTiming* is tri-stated at reset assertion and CS pins qualification may be incorrect, connect a pull- up resistor on the CSTiming* pin.

  • Page 52: Figure 20: Three Device Connection Example

    Device1_CS* Notes • Since the AD bus is used to configure the GT-64260A at reset, the latch and/or transceivers must NOT implement "bus hold". • The CS* pins must be qualified with CSTiming* to generate the specific device chip select (e.g., Device_CS* = [CSTiming* ‘OR’...

  • Page 53: 8-Bit Device

    Device Interface Functional Overview 8-bit Device The GT-64260A device controller supports 8-, 16-, or 32-bit wide devices. The device width is specified in the Device Bank Parameters register’s bits DevWidth [21:20], at offsets 0x45c, 0x460, 0x464, 0x468, and 0x46c. The...

  • Page 54: Figure 21: 8-Bit Device Connection Example

    GT-64260A Design Guide Figure 21: 8-bit Device Connection Example 8-bit Device WR*0 Write Data A[28:3] A[2:0] BAdr[2:0] GT-64260A AD[31:0] Latch Device_CS* CONFIDENTIAL Doc. No. MV-S300165-00, Rev. A Copyright © 2002 Marvell Page 54 Document Classification: Proprietary Information May 21, 2002, Preliminary...

  • Page 55: 16-Bit Device

    Connect the Wr0* pin to one device and connect the other device to the AD[7:0] bus and to the Wr1* pin. Figure 22 shows the connection of a 16-bit wide device to the GT-64260A. for more information, on the 16-bit device connection, see the GT-64260A datasheet’s "Interfacing With 8/16/32-bit Devices" section.

  • Page 56: 32-Bit Device

    OE* pins. Connect Wr[1:0] and AD[15:0] to one 16-bit device and connect Wr[3:2] and AD[31:16] to the other 16- bit device. Use a similar connection for 4x8-bit configuration. Figure 23 shows the connection of 32-bit wide device to the GT-64260A. For more information on the 32-bit device connection, see the GT-64260A datasheet’s "Interfacing With 16/16/32-bit Devices" section. CONFIDENTIAL Doc.

  • Page 57: Figure 23: 32-Bit Device Connection Example

    Figure 23: 32-bit Device Connection Example WR*3 Write3 WR*2 Write2 32-bit Device WR*1 Write1 WR*0 Write0 Data A[26:3] A[2:0] BAdr[2:0] GT-64260A AD[31:0] Latch Device_CS* CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary Document Classification: Proprietary Information Page 57...

  • Page 58: Signals Timing

    Signals Timing Note For more information on device bus signals, see the GT-64260A datasheet’s "Pin Information" section. The GT-64260A provides programmable access timing for various device implementations. The programmable parameters for device access have a 1 clock cycle granularity and are set per CS* (bank). All programmable access timings are set in the corresponding Device Bank Parameters register (Offsets: 0x45c, 0x460, 0x464, 0x468).

  • Page 59: Ready Support

    Ready* pin. Note In the GT-64260A datasheet, the Ready* pin AC timing refers to the sampled mode. There is no AC timing for the non-sampled mode. For more information, see the GT-64260A datasheet’s "AC Timing" section.

  • Page 60: Syncburst Sram

    GT-64260A Design Guide Syncburst SRAM Syncburst SRAM devices can be connected to the GT-64260A device interface. It is recommended to use pipe- lined syncburst SRAM devices since they are designed for 133 MHz or higher frequencies. When using a Single Cycle Deselect (SCD) pipelined syncburst SRAM, an external logic must be used to extend the CS and Read (DevRW*) pins for one cycle on read transactions because the SRAM outputs are disabled within one clock cycle after deselect.

  • Page 61: Communication Interface Functional Overview

    Baud Rate Generators (BRG) Ethernet Controllers There are three 10/100 Mbps full duplex Ethernet ports in the GT-64260A. Each port is fully compliant with the IEEE 802.3 and 802.3u standards and integrates MAC function and a dual speed MII interface. The Ethernet ports can be configured to MII or RMII (three Ethernet ports configuration is available only with RMII).

  • Page 62: Mpsc Controllers

    The CPU defines the part of the memory as cached and the rest as uncached. In addition, cache coherent regions will be defined in the GT-64260A for IDMA transactions. In this solution, the communication driver maintains a sep- arate set of buffers (and descriptors) that it will use for IDMA I/O of the communication interface. These buffers are located in the cached memory and configured in the GT-64260A as cache coherent.

  • Page 63: Mpsc And Ethernet Sw Implications

    Communication Interface Functional Overview MPSC and Ethernet SW Implications outside the snoop regions defined in the GT-64260A. As a result, the communication unit does not drive any snoop cycles when it is accessing to memory. This solution increases software complexity and since the buffer pool is shared among many devices in the soft- ware, this creates additional complications.
  • Page 64 GT-64260A Design Guide Although similar, the MPSC SDMA and the Ethernet SDMA differ in the SDMA descriptors’ command status field (different for each protocol) and the Tx descriptors’ shadow Byte Count field. The descriptors are 16 byte in size and do not require enormous processing resources.

  • Page 65: Figure 29: Rx Descriptor Chain

    Next desc pointer Own = CPU cmd status buffer size Byte count Dummy buffer pointer Next desc pointer CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary Document Classification: Proprietary Information Page 65...

  • Page 66: Figure 30: Disconnecting The Descriptor Chain

    GT-64260A Design Guide For each receive packet: • Disconnect the descriptors that formed this packet by moving the head pointer to the next descriptor in the chain. • Pass the descriptors to the application layer. Figure 30 shows an example of disconnecting the descriptor.

  • Page 67: Figure 31: Releasing The Descriptor Chain

    Tail Own = GT cmd status Next desc pointer buffer size Byte count Dummy buffer pointer Next desc pointer CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary Document Classification: Proprietary Information Page 67...
  • Page 68 To demonstrate the communication unit ability, the Board Support Package (BSP) implements an additional appli- cation layer, located in the demoApi.c file that functions as a repeater. This driver uses the communication unit driver’s APIs (see the BSP User Manual) to operate the GT-64260A Com- munication Unit.
  • Page 69 7.4.2.2 Driver ISR When the GT-64260A Communication Unit generates an interrupt, the interrupt controller calls a single ISR that handles the variety interrupt causes. The ISR processes the interrupt in three stages: It reads the Interrupt Cause register, acknowledges the interrupt events, and masks the interrupt events bits.

  • Page 70: I2C Interface

    • Use the internal arbitration control. C Interface The GT-64260A has full I C support. It can act as master generating read/write requests and as a slave respond- ing to read/write requests. It fully supports multiple I C master’s environments.

  • Page 71: Figure 32: Gt-64260A I2C Interface Connection To Sdram Dimms

    Communication Interface Functional Overview I2C Interface Figure 32: GT-64260A I C Interface Connection to SDRAM DIMMS 7.5.2 C Interface Initialization To work with the I C interface, it must be initialized first. The interface initialization sequence is as follows: Reset the I C logic by writing to the I C Soft Reset Register, at offset 0xC01C.

  • Page 72: Baud Rate Generator

    This is not correct for the CPU interface, when the internal base is set to 0xf1000000, the CPU must access the GT-64260A internal registers at 0xf1000000 + offset. It is possible to con- figure to the internal base register through the serial ROM.
  • Page 73 If the BRG output clock is a source clock for the MPSC ports, the BRGs can only use TClk or BclkIn clocks as source clock. For more details, see the errata and restriction document. CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary...

  • Page 74: Multi -Purpose Pin Interface Functional Overview

    MPP Control registers (Offsets: 0xf000, 0xf004, 0xf008, and 0xf00c). The MPP pins can be used as hardware control signals to the various GT-64260A interfaces (UMA control, DMA control, or PCI arbiter signals) or as Gen- eral Purpose Pins. For more information, see the GT-64260A datasheet’s "Pins Multiplexing" section.

  • Page 75: Interrupt Outputs

    Figure 34 describes CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary Document Classification: Proprietary Information Page 75...

  • Page 76: Pci Arbiter

    GT-64260A Design Guide the MPP interrupt outputs. For more information on the interrupt controller, see Section 11, "Interrupt Controller Functional Overview", on page Figure 34: MPP Interrupt Outputs Main Interrupt Cause Register (Low) 0xc18 GPP Pin Main Interrupt Cause Register (High) 0xc68...

  • Page 77: Unified Memory Architecture Control

    Section 20, "Reset", on page 144). Also, the GT-64260A can be configured to act as a UMA master or slave. UMA systems require two additional sig- nals for arbitration of the SDRAM interface. For more information, see the GT-64260A datasheet’s "Unified Mem- ory Architecture Support"...

  • Page 78: Jtag Interface Functional Overview

    MODELS. If the current instruction is IDCODE in the GT-64260A TAP controller implementation, each exit from the SHIFT- DR state will cause the IDCODE to be fetched to DR (all 32 bits). While the controller is in the SHIFT-DR state, it shifts data from TDI to the register and, after the IDCODE was shifted out from the TDO, it starts shifting out that data.

  • Page 79: Idma Unit Functional Overview

    IDMA Unit Functional Overview Section 10. IDMA Unit Functional Overview The GT-64260A IDMA controller transfers blocks of data independent of the local processor or PCI hosts. Data movement can occur from any interface to any interface. The GT-64260A implements eight IDMA channels. Each IDMA engine can move data between any source and destination, such as the SDRAM, Device, PCI_0, PCI_1, or CPU bus.

  • Page 80: Figure 35: Dma Controller General Flow

    GT-64260A Design Guide Figure 35: DMA Controller General Flow Initialize IDMA source, destination,next descriptor, and command. Set Channel active bit. Read burst from source. Write burst to Fetch next destination. descriptor. EOT (enabled and asserted) Halt FetchND asserted Mode Fetch...

  • Page 81: Chain Mode

    10.1 Chain Mode The GT-64260A IDMA engines can be activated in a chain mode. In this mode, the DMA controller loads descrip- tors from memory (SDRAM, PCI, etc.) prior to a DMA transfer. The DMA controller begins the transfer according to the descriptor information loaded for the segment.

  • Page 82: Section 11. Interrupt Controller Functional Overview

    If the interrupt source is an external device driving a GPP input (see 8.1 "General Purpose Pin (GPP)" on page 74), the GT-64260A can be configured to receive a level or edge trigger. If the Comm Unit Arbiter Control register’s GPP_Int bit [10] is set to ‘0’, at offset 0xF300, the external interrupts are treated as edge trigger interrupts.

  • Page 83: Figure 36: Interrupt Routing Example

    PCI_INT1* PCI Device #1 PCI Device #2 The GT-64260A handles interrupts in two stages. It includes a main cause register, summarizing the interrupts generated by each unit, and specific unit cause registers, distinguishing between each specific interrupt event. Figure 37 shows the GT-64260A interrupt routing architecture.

  • Page 84: Figure 37: Gt-64260A Interrupt Routing Architecture

    GT-64260A Design Guide Figure 37: GT-64260A Interrupt Routing Architecture Interrupts Cause Registers Interrupts Mask Registers CPU Cause register CPU Mask register SDRAM Error Address register SDRAM ECC Control Device Interface Cause register Device Interface Mask register IDMAs 0-3 Cause register...

  • Page 85: Figure 38: Interrupt Handling Procedure

    Clean unit Handle interrupt interrupt cause source register (Interrupt SUM in main cause) == '1' Exit interrupt handler CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary Document Classification: Proprietary Information Page 85...

  • Page 86: Using External Interrupt Controller

    11.1 Using External Interrupt Controller The GT-64260A interrupt controller can be connected to an external interrupt controller. This configuration is use- ful when the software must be backward compatible to previous designs.

  • Page 87: Section 12. Messaging Units Functional Overview

    Messaging Units Functional Overview Messaging Section 12. Messaging Units Functional Overview The GT-64260A messaging unit includes hardware hooks for message transfers between PCI devices and the CPU. The messaging unit can be divided into three different messaging types: messaging, doorbell, and I Note The polarity of the messaging unit doorbells, interrupt cause, and interrupt mask registers bits are determined via the Queue Control register’s Polarity bit 8, at offset 0x1C50.

  • Page 88: Circular Queue

    12.3.1 Inbound Circular Queue The PCI device writes to the Inbound Queue Port Virtual register (Offset: 0x1c40 and 0x1cc0) and the GT-64260A asserts an interrupt to the CPU and increments the head pointer. The CPU reads the message, increments the tail pointer, and writes to the Inbound Free Head Pointer register (Offset: 0x1c60 and 0x1ce0).

  • Page 89: Figure 41: Outbound Circular Queue

    The CPU writes to the Outbound Queue Port Virtual Register (Offset: 0x1c44 and 0x1cc4) and increments the head pointer. The GT-64260A asserts an interrupt to the PCI device. The PCI device reads the message and the tail pointer is incremented by the GT-64260A. The PCI device must write to the Outbound Free Head Pointer reg- ister (Offset: 0x1c70 and 0x1cf0).

  • Page 90: Section 13. Design Consideration Overview

    GT-64260A. This figure is applicable to all GT-64260A interfaces, except for the PCI interface. The PCI interface pads are PCI complaint and their max- imum and minimum rating are compliant to the PCI specification 2.2. document section "4.2.2.3 Maximum AC Rat- ings and Device Protection".

  • Page 91: Cpu Interface Design Considerations

    Section 14. CPU Interface Design Considerations The CPU interface is used to connect the GT-64260A and the CPU. The GT-64260A CPU interface is a 60x bus compatible master and slave. In addition, it is a MPX bus compatible slave. Note As an MPX bus compatible slave, this interface only supports "address only bus mastering"...

  • Page 92: Electrical Specification

    14.4.1 Calculating the Reference Point The output delay values in the GT-64260A datasheet’s AC timing table is defined for a specific load. This value includes the rise/fall time of the output. To calculate the signal fly time, the rise/fall time must be measured and a reference measuring point must be set.

  • Page 93: Figure 44: Test Circuit Results (Cload = 15Pf)

    The CPU reference point is measured in a similar way as the GT- 64260A, but with a different test circuit. Figure 45 shows the CPU test circuit (Rload = 50 Ohm). CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary Document Classification: Proprietary Information Page 93...

  • Page 94: Figure 45: Gt-64260A Test Circuit (Rload = 50 Ohm)

    GT-64260A Design Guide Figure 45: GT-64260A Test Circuit (Rload = 50 Ohm) OVdd/2 Output Rload Z0 = 50 ohm Figure 46 shows the results of the test circuit simulation. Figure 46: Test Circuit Results (Rload = 50 Ohm) CONFIDENTIAL Doc. No. MV-S300165-00, Rev. A Copyright ©...

  • Page 95: Table 14: Typical Cpu Ac Timings

    M ax Input Setup Input hold output delay 1. ARTRY* for address only. In this configuration, the signals are connected from the GT-64260A to the CPU in a point-to-point configuration. (See Figure 47.) Figure 47: GT-64260A to CPU Point-to-Point Configuration...

  • Page 96: Figure 48: 1 Ns Delay Trace Simulation

    The fly time is measured from the CPU reference point that was measured in “Calculating the Reference Point” on page 92 (2.1 ns) to the Vil measured on the GT-64260A pin (3.1 ns) in Figure 48 (board simulation). Figure 48: 1 ns Delay Trace Simulation The timing requirements for the CPU to the GT-64260A are: Tcycle >...

  • Page 97: Figure 49: 0.8 Ns Delay Trace Simulation

    For 200 ps delay for 1 inch, the maximum distance is 4 inches. Figure 49 shows a simulation of 0.8 ns delay trace. The fly time is measured from the GT-64260A reference point that was measured in “Calculating the Reference Point” on page 92 (3 ns) to the Vil measured on the CPU pin (3.8 ns) in...

  • Page 98: Table 16: Single-Gt And Multiple Cpu Ac Timing

    Input Setup Input hold output delay 1. ARTRY* for multiple data masters. In this configuration, the signals are connected from the GT-64260A to the CPUs in a ’T’ topology. (See Figure 50.) Figure 50: GT-64260A to Multiple CPU Configuration CPU0...

  • Page 99: Figure 51: 0.5 Ns Delay Trace Simulation (Maximum Distance 2.5 Inches)

    Timing Requirements Figure 51: 0.5 ns Delay Trace Simulation (Maximum Distance 2.5 Inches) The GT-64260A to CPU calculation is the same as in the single GT-64260A and single CPU example. Note For multiple CPU configurations, a separate IBIS model must be used. For more information, contact your local Field Application Engineer (FAE).

  • Page 100: Figure 52: 0.5 Ns Delay Trace Simulation (Maximum Distance 4 Inches)

    GT-64260A Design Guide Figure 52: 0.5 ns Delay Trace Simulation (Maximum Distance 4 Inches) CONFIDENTIAL Doc. No. MV-S300165-00, Rev. A Copyright © 2002 Marvell Page 100 Document Classification: Proprietary Information May 21, 2002, Preliminary...

  • Page 101: Table 17: Multiple Gt-64260As And A Single Cpu Ac Timing

    In multi-GT mode, the ARTRY* signals setup time is 4.9 ns. This is ignored in the timing calculation example, since most applications do not use the ARTRY*. In this configuration, the signals are connected from the GT-64260A to the CPU in a ’T’ topology. See Figure Note The GT-64260A in multi-GT mode is targeted to operate at 100 MHz.

  • Page 102: Figure 54: 1.1 Ns Delay Trace Simulation

    Figure 54 (board simulation). Figure 54: 1.1 ns Delay Trace Simulation The GT-64260A to CPU calculation is the same as the single GT-64260A and a single CPU but the longest path is from one GT-64260A to the other GT-64260A. Note For the multiple GT-64260As configuration, separate AC timings must be used.

  • Page 103: Figure 55: 0.8 Ns Delay Trace Simulation

    10 > 4.2 + 4.5 + Tdelay(fly_time) + 0.5 Tdelay(fly_time) < 0.8 ns Figure 55 shows simulation of 0.8 ns delay trace. The fly time is measured from the GT-64260A reference point that was measured in 14.4.1 "Calculating the Reference Point" on page 92 (3 ns) to the Vil measured on the CPU pin (3.8 ns) in...

  • Page 104: Layout Instructions

    GT- 64260A connected to a single CPU. Figure 57 shows the placement for single a GT-64260A connected to multiple CPUs. Figure 56: Layout for a Single GT-64260A to a Single CPU CPU interface PCI0 SDRAM GT-64260A PCI1 Comm.

  • Page 105: Figure 57: Layout For A Single Gt-64260A To Multiple Cpus

    Device A B C D . . . The placement for multi-GT mode depends on the number of GT-64260A devices and interfaces used on each one of them. Depending on the system configuration and timing simulation, parallel termination on the bi-directional signals can be placed near the CPUs or the GT-64260As.

  • Page 106: Sdram Interface Design Considerations

    For more information, see Section 4. "SDRAM Interface Functional Overview" on page The GT-64260A supports UMA mode as master or slave. The UMA mode is sampled at reset by AD[12] signal for enable/disable setting and AD[13] for master/slave setting. For more information, see Section 20.

  • Page 107: Figure 58: Sdram Configuration Example

    Simulating this configuration with the maximum case (fast corner) of the device gives the results shown in Figure Figure 59: SDRAM Simulation Example CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary Document Classification: Proprietary Information...

  • Page 108: Figure 60: Sdram Configuration Example (With Resistors)

    GT-64260A Design Guide Changing the configuration in Figure 58 by adding serial resistors is shown in Figure Figure 60: SDRAM Configuration Example (With Resistors) SDRAM0 Rs = 40 ohm Z0 = 60 GT-64260A Z0 = 60 Rs = 40 ohm...

  • Page 109: Timing Requirements

    Signal Topology Categories G ro up S ign als in gro up Clock SDRAM_CK[3:0] Data SDATA[63:0] ECC[7:0] Data Mask* SDQM[7:0] CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary Document Classification: Proprietary Information Page 109...
  • Page 110 The simulation represent a configuration of one physical bank with eight devices (single cycle DIMM). 15.4.1 Clock Timing The GT-64260A supports a few SDRAM clock configurations. For more information on the supported configura- tions, see Section 19. "Clocks" on page 143 or AN-82: SDRAM Clocking Schemes in the GT-642xxA .

  • Page 111: Figure 62: Dimm Clock Topology

    15.4.2 Data Timing Since the AC specification of the GT-64260A and of the SDRAM devices is for a given test circuit, the first stage is to calculate the reference point for the timing calculations. The reference point is used as a starting point to mea- sure the signal fly time.

  • Page 112: Figure 63: Gt-64260A Data Reference Point

    GT-64260A Design Guide Figure 63: GT-64260A Data Reference Point The SDRAM output delay AC timing uses a similar test circuit with load of 50 pf (Cl = 50pf). Simulating the SDRAM data signals test circuit will give reference point of 1.54 ns. (See Figure 64.)

  • Page 113: Figure 64: Sdram Data Reference Point

    SDRAM Interface Design Considerations Timing Requirements Figure 64: SDRAM Data Reference Point CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary Document Classification: Proprietary Information Page 113...

  • Page 114: Table 19: Trace Length For Data Topologies

    GT-64260A Design Guide Figure 65 describes the data topology for the selected memory configuration (one physical bank with eight devices). Figure 65: Selected Memory Configuration Data Topology SDRAM Data GT-64260A 10 ohm DIMM Connector Table 19: Trace Length for Data Topologies...

  • Page 115: Table 20: Gt-64260A Sdram Interface Ac Timing

    7.5 > 3.8 + 1.5 + Tdelay(fly_time) + 0.5 Tdelay(fly_time) < 1.7 ns Figure 67 shows a simulation for a 0.8 ns delay trace. The fly time is measured from the GT-64260A reference point determined in Figure 63 on page 112 (2.1 ns) to the Vil measured on the SDRAM pin (2.5 ns) in the figure...

  • Page 116: Figure 67: 0.8 Ns Delay Trace Simulation (2.1 Ns Fly Time Reference Point)

    GT-64260A Design Guide Figure 67: 0.8 ns Delay Trace Simulation (2.1 ns Fly Time Reference Point) Note The data signal fall time is smaller than the test circuit since the load is smaller (8 pf instead of 30 pf). Figure 68 shows a simulation of 0.8 ns delay trace.

  • Page 117: Figure 68: 0.8 Ns Delay Trace Simulation (1.54 Ns Fly Time Reference Point)

    Figure 68: 0.8 ns Delay Trace Simulation (1.54 ns Fly Time Reference Point) 15.4.3 Chip Select Signals The output delay value of the GT-64260A SCS*[3:0] signals in the AC timings table are given for 50 pf load (Cl = 50pf). (See Figure 69.)

  • Page 118: Figure 69: Gt-64260A Test Circuit (Cload = 50Pf)

    GT-64260A Design Guide Figure 69: GT-64260A Test Circuit (Cload = 50pf) GT-64260A Output Cload Simulating the GT-64260A SDRAM interface chip select signals test circuit gives the reference point of 1.3 ns. (See Figure 70.) CONFIDENTIAL Doc. No. MV-S300165-00, Rev. A Copyright ©...

  • Page 119: Figure 70: Gt-64260A Chip Select Reference Point

    Figure 70: GT-64260A Chip Select Reference Point Figure 71 describes the Chip Select signal routing topologies on the DIMM module. Each GT-64260A SCS* signal is connected to two DIMM CS* pins (32-bits data width per SCS*). This means that in the sample memory config- uration (one physical bank with eight devices), the SCS* signal is connected to eight SDRAM devices.

  • Page 120: Figure 71: Chip Select Signal Routing On The Dimm Module

    GT-64260A Design Guide Figure 71: Chip Select Signal Routing on the DIMM Module Add for x16 and Add for x16 This diagram is for CS x8 components and x8 components nets that neither have SDRAM an ECC device nor the stuffing option for one.

  • Page 121: Table 23: Gt-64260A Cs Ac Timing

    7.5 > 3.8 + 1.5 + Tdelay(fly_time) + 0.5 Tdelay(fly_time) < 1.7 ns Figure 72 shows the simulation of 0.8 ns delay trace. The fly time is measured from the GT-64260A reference point that was measured in Figure 70 on page 119 (1.3 ns) to the Vil measured on the SDRAM pin (4.1 ns) in the...

  • Page 122: Figure 72: 0.8 Ns Delay Trace Simulation (2.8 Ns Fly Time Reference Point)

    The output delay value of the GT-64260A DAdr[12:0], SRAS*, SCAS*, and BankSel[1:0] signals in AC timings table are given for 50 pf load (Cl = 50pf). (See Figure 69.) Simulating the GT-64260A SDRAM interface double cycle signal test circuit gives a reference point of 2 ns. (See Figure 73.) CONFIDENTIAL Doc.

  • Page 123: Figure 73: Gt-64260A Double Cycle Signals Ac Timing

    SDRAM Interface Design Considerations Timing Requirements Figure 73: GT-64260A Double Cycle Signals AC Timing CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary Document Classification: Proprietary Information Page 123...

  • Page 124: Table 25: Trace Length For Double Cycle Signal Topologies

    GT-64260A Design Guide Figure 74 describes the double cycle signal routing topologies on the DIMM module. In the selected memory con- figuration, there are eight SDRAM devices placed on the DIMM (1 row DIMM). Figure 74: Double Cycle Signal Routing on the DIMM Module...

  • Page 125: Table 26: Gt-64260A Double Cycle Signals Ac Timing

    7.5 > 3.7 + 1.5 + Tdelay(fly_time) + 0.5 Tdelay(fly_time) < 1.8 ns Figure 75 shows a simulation of 0.8 ns delay trace. The fly time is measured from the GT-64260A reference point that was measured in Figure 73 on page 123 (2 ns) to the Vil measured on the SDRAM pin (3.8 ns) in the figure...

  • Page 126: Layout Instructions

    GT-64260A Design Guide Figure 75: 0.8 ns Delay Trace Simulation (2.0 ns Fly Time Reference Point) Simulating this topology means the calculated fly time is (3.8 - 2 = 1.8 ns). 15.5 Layout Instructions 15.5.1 Device Placement All devices must be placed as closed as possible to each other.

  • Page 127: Figure 76: Device Placement Example

    A B C D . . . 15.5.2 Routing The SDRAM interface traces must be 55 to 65 Ohm impedance. The SDRAM and GT-64260A clocks (see Section 19. "Clocks" on page 143) must be routed on separate layers from the other signals.

  • Page 128: Pci Interface Design Considerations

    GT-64260A Design Guide Section 16. PCI Interface Design Considerations The PCI interface is used to connect the GT-64260A and other PCI devices. The GT-64260A supports two 64-bit PCI interfaces (named PCI0 and PCI1), compliant to PCI specification, Rev. 2.2. 16.1 Interface Connectivity The PCI interfaces connectivity complies to the PCI specification, Rev.

  • Page 129: Table 28: Pci Ac Timing For 33 Mhz And 66 Mhz (From The Pci Specification Document, Rev. 2.2)

    RST# high to first configuration access rhff RST# high to first FRAME# assertion Table 29: GT-64260A PCI Interface AC Timing NOTE: All PCI interface Output Delays, Setup, and Hold times are referred to the PClk rising edge. Sig nal s De sc r ip tion...
  • Page 130 For 66 MHz bus frequency, Section "7.7.5 System Timing Budget". When using the GT-64260A internal PCI arbiter, the MPP interface is used for the arbitration signals. The MPP interface AC timing depends on their functionality. See the GT-64260A datasheet’s "AC Timing" section. The PCI GNT* signals maximum output delay (referred to the corresponding PClk clock) is 6.6 - 7.5 ns, depending on...

  • Page 131: Figure 77: Gt-64260A Test Circuit (Cload = 20Pf)

    PCI Interface Design Considerations Timing Requirements Figure 77: GT-64260A Test Circuit (Cload = 20pf) GT-64260A Output Cload Simulating the GT-64260A GNT* signal from the MPP interface test circuit will give a reference point of 2.1 ns. (See Figure 78.) CONFIDENTIAL Copyright ©...

  • Page 132: Figure 78: Gt-64260A Gnt* Signals Reference Point

    Tcycle > Toutput_delay(GT-64260A) + Tsetup(PCI_spec) + Tdelay(fly_time) + Tclock_skew 15 > 7.5 + 5 + Tdelay(fly_time) + 0.5 Tdelay(fly_time) < 2 ns The fly time is measured from the GT-64260A reference point that is measured in Figure 78 (2.1 ns) to the Vil measured on the SDRAM pin (3.3 ns) in the figure below (board simulation).

  • Page 133: Layout Instructions

    In this topology, the fall time is smaller than the test circuit since the load is smaller. 16.5 Layout Instructions See Section "4.3.6. Physical Requirements" in the PCI Specification, Rev. 2.2. CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary Document Classification: Proprietary Information...

  • Page 134: Section 17. Ethernet Interface Design Considerations

    Section 17. Ethernet Interface Design Considerations The GT-64260A contains up to three Ethernet controllers. Each controller can be configured to operate in MII or RMII mode. Each 10/100 Mbit port is fully compliant with the IEEE 802.3 and 802.3u standards and integrates the MAC func- tion and a dual speed MII interface.

  • Page 135: Electrical Specification

    AC timings for the RMII specifications and for the GT-64260A RMII interfaces. Note The AC timing might be updated in the RMII specification or in the GT-64260A datasheet. Make sure you have the most update documents. For every conflict between this document and the specifications CONFIDENTIAL Copyright ©...

  • Page 136: Table 30: Rmii Ac Timing For 50 Mhz (From Rmii Specification Rev. 1.2 Document)

    20pf The RMII signals output delay is measured using the test circuit in Figure 77 on page 131. Simulating the GT-64260A RMII signals test circuit gives a reference point of 2.1 ns. (See Figure 82.) CONFIDENTIAL Doc. No. MV-S300165-00, Rev. A Copyright ©...

  • Page 137: Figure 82: Gt-64260A Rmii Signals Reference Point

    Tcycle > Toutput_delay(GT-64260A) + Tsetup(PHY) + Tdelay(fly_time) + Tclock_skew 20 > 10 + 4 + Tdelay(fly_time) + 0.5 Tdelay(fly_time) < 5.5 ns The fly time is measured from the GT-64260A reference point in Figure 82 (2.1 ns) to the Vil measured on the SDRAM pin (3.3 ns) in the figure below (board simulation).

  • Page 138: Layout Instructions

    GT-64260A Design Guide Figure 83: 2.1 ns Fly Time Reference Point Note In this topology, the fall time is slower than the test circuit because the load is smaller. 17.5 Layout Instructions 17.5.1 Placement Figure 84 illustrate how the PHYs must be placed.

  • Page 139: Figure 84: Phy Placement

    In addition, each port must be separated from the other ports by at least 15 mm of clearance, when using 5 mm traces. CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary Document Classification: Proprietary Information...

  • Page 140: Section 18. Power Supply

    Ground, common Note For more information on the PLL power supply filtering, see the GT-64260A datasheet’s "PLL Power Filter Circuit" section. All power planes must be de-coupled to ground to provide for reasonable management of the switching currents ( d I/ d t ) to which the plane and its supply path are subjected.
  • Page 141 Connect one 100 nf capacitor to each VCC3.3 power pin. The minimum capacitors/pin must not be smaller than 2:3. Place the capacitors as close as possible to the power pins. It is also recommended to place two 4.7 uf capacitors close to the GT-64260A. See Figure 18.1.2 VCC2.5 De-coupling Connect one 100 nf capacitor to each VCC2.5 power pin.

  • Page 142: Figure 85: Gt-64260A Power Supply Pin Map

    GT-64260A Design Guide Figure 85: GT-64260A Power Supply Pin Map Note For Power sequencing information see AN-67: Powering Up/Powering Down Galileo Technology Devices with Multiple Power Supplies of Different Voltages . CONFIDENTIAL Doc. No. MV-S300165-00, Rev. A Copyright © 2002 Marvell...

  • Page 143: Section 19. Clocks

    For the SDRAM clocking scheme, it is not recommended to use the SDClkOut configuration. For more information on the SDRAM interface clocking, see the GT-64260A datasheet and AN- 82: SDRAM Clocking Schemes in the GT-642xx/A Devices on the secure website.

  • Page 144: Section 20. Reset

    Rst signal. Some systems require the PCI devices to be reset, but not the GT-64260A and the CPU. For example, the CPU gets data from the GT-64260A communication ports and routes it to other GT-64260A interfaces (PCI, MPSC, etc.).

  • Page 145: Section 21. Bringing Up The System (Debugging)

    Tx descriptor pointer and the transmit demand value must be checked to confirm that the packet was sup- posed to be transmitted. The conclusion of such debugging is that the MPSC machine initilization is wrong. CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary Document Classification: Proprietary Information...

  • Page 146: Section 22. Revision History

    GT-64260A Design Guide Section 22. Revision History Table 33: Revision History D ocum ent Ty pe R evis ion D ate Preliminary Revision Rev. A May 21, 2002 CONFIDENTIAL Doc. No. MV-S300165-00, Rev. A Copyright © 2002 Marvell Page 146...

  • Page 147: I2C Eeprom Example

    /* DMA to copy the 8 bit flash to the boot SRAM */ 0x14000900 0x80080000 /* Byte count = 0.5MB */ 0x14000910 0xfff00000 /* Source address */ 0x14000920 CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary Document Classification: Proprietary Information Page 147...
  • Page 148 GT-64260A Design Guide 0x1c000000 /* Destination address */ 0x14000930 0x00000000 /* Next descriptor address = NULL */ 0x14000940 0x80001a00 /* Dummy writes to stall the system until the DMA finishes */ 0x14000c00 0x00000000 0x14000c00 0x00000000 /* Enable Boot from SRAM, switch between the memory windows */...

  • Page 149: Sdram Mode Register/Code

    ! r5 holds the Sdram operation Mode r6, 0x0 ! r6 <= 0 stwbrx r6, 0, (r5) ! ( 0x14000474 ) <= 0x0 CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary Document Classification: Proprietary Information Page 149...

  • Page 150: Ecc Initialization - Example Code

    GT-64260A Design Guide Appendix C. ECC Initialization- Example Code C.1 Assembler Code The following is the Assembler Code to Copy the Boot Device to SDRAM. ! Copy dink to memory..addisr3,0,0 ! Load dram address (0) into r3. addisr4,0,RESET_BASE! Load r4 with base eprom address ! of 0xFFF00000.
  • Page 151 ECC Initialization- Example Code C.2 C Code Example for (offset = 0x100000 ; offset < (SCS0SIZE+SCS1SIZE+SCS2SIZE+SCS3SIZE) ; offset+=0x100000) dmaTransfer(DMA_ENG_4,offset,offset,0x100000,DTL_128BYTES | BLOCK_TRANSFER_MODE,NULL); while (dmaIsChannelActive(DMA_ENG_4)); CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary Document Classification: Proprietary Information Page 151...

  • Page 152: Appendix D. Big And Little Endian Support

    GT-64260A CPU interface. To write to the GT-64260A internal register, the data on the CPU bus must be driven as Big Endian (the order of significance is that the LSB is the leftmost and the MSB is the rightmost). One way of driving the data as Big Endian on the CPU bus is for the CPU's general register to hold the data in Big Endian and use a simple load instruction.

  • Page 153: Pci Interface

    The problem with working in Big Endian is that the PCI is a 32-bit bus. Even with the extension to PCI64, every transaction ends as a 32-bit transaction depending on the master and slave. Big Endianess depends on the bus width. Because of that, the GT-64260A must work on the PCI in Big-32 mode. Table 35:...

  • Page 154: Table 36: Data Swapping

    0x 04030201.08070605 D.4.1 Non PCI-to-PCI Swapping (CPU, DMA, SDMA) Because the GT-64260A works in Dwords (8 Byte) and the PCI works in Words(4 Byte), a restriction exists when working with less than Dword transactions. There are four reasonable cases when working with Big and Little Endian on the core and on the PCI.

  • Page 155: Table 37: Master Swapping

    Pad[63:32] = 0x77665544 In case of starting address with offset 4: First phase Pad[31:0] = don’t care Pad[63:32] = 0x33221100 CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary Document Classification: Proprietary Information Page 155...

  • Page 156: Table 38: Master Swapping

    GT-64260A Design Guide Second phase Pad[31:0] = 0x77665544 Pad[63:32] = don’t care Here is how it looks on a 32 bit PCI bus: In case of starting address with offset 0: First phase - Pad[31:0] = 0x33221100 Second phase Pad[31:0] = 0x77665544...
  • Page 157 Cor e E ndi aness S wa p N eeded Little Little No swap Little Byte swap Little Byte & word swap Word swap CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary Document Classification: Proprietary Information Page 157...

  • Page 158: Appendix E. Communication Example Code

    GT-64260A Design Guide Appendix E. Communication Example Code E.1 Ethernet Initialization /* Initialize the Communication Unit memory pool */ usrMemInit(); /* connect the MPSC and Ethernet as RMII ports */ GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, 0x1102); /* initialize the address table to filter other MAC addresses */ initAddressTable(ETHERNET_DOWNLOADING_PORT,0,1,0);...

  • Page 159: Ethernet Api

    /* if the owner is the GT return ERROR to prevant destroy data */ if(pCurrTxDesc->cmd_sts & OWNER_BY_GT) return ERROR; pFirstTxDesc = pCurrTxDesc; pLastTxDesc = pCurrTxDesc; *(UINT32*)(&(pFirstTxDesc->cmd_sts)) = FIRST | ENABLE_INTERRUPT | PADDING; CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary Document Classification: Proprietary Information Page 159...

  • Page 160: Mpsc Api

    GT-64260A Design Guide for(i = 0 ; i <Transmit->bufferNum ; i++) pCurrTxDesc->bytecnt = Transmit->bufferLen[i]; pCurrTxDesc->buf_ptr = VIRTUAL_TO_PHY(Transmit->buffer[i]); pCurrTxDesc->shadowOwner = SHADOW_OWNER_BY_CPU; pCurrTxDesc->pointerToRxQueue = (UINT32)Transmit; if(i != 0) *(UINT32*)(&(pCurrTxDesc->cmd_sts)) = ENABLE_INTERRUPT | OWNER_BY_GT; pLastTxDesc = pCurrTxDesc; pCurrTxDesc = (TX_DESC*)PHY_TO_VIRTUAL(pCurrTxDesc->next_desc_ptr); *(UINT32*)(&(pLastTxDesc->cmd_sts)) = *(UINT32*)(&(pLastTxDesc->cmd_sts)) | LAST | OWNER_BY_GT | GENERATE_CRC;...
  • Page 161 /* set the register value in an internal table */ SetDefaultRegisterValue(TCRR,tempRegValue); GT_REG_WRITE(TRANSMIT_CLOCK_ROUTING_REGISTER,tempRegValue); /* initialization of the BRG engine */ BRG_DEFAULT_CONFIG_GET(&(cfgTunBrg.config),UART_PORT); CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary Document Classification: Proprietary Information Page 161...
  • Page 162 GT-64260A Design Guide BRG_DEFAULT_BAUD_TUNING_GET(&(cfgTunBrg.tuning),UART_PORT); brgSetConfig(&cfgTunBrg,UART_PORT); /* set the BRG with defaults values */ /* Halt any Rx/Tx activities */ /* stop the MPSC Rx machines */ GT_REG_WRITE(CHR(UARTPort,2) , ABORT_RECEPTION); /* workaround for wrong data read from MPSC internal registers. */ /* wait for the Rx to abort in the MPSC machine */ for(tempRegValue=0;...
  • Page 163 = UARTPort; allocStruct.numberOfDescriptors = MIN_NUMBER_OF_UART_TX_DESC_ALLOC; allocStruct.bufferSize = 0; allocStruct.priority = PRIO0; allocStruct.protocolType = MPSC_PROTOCOL; allocStruct.rxOrTx = TX_DESCRIPTOR; sdmaAllocateDescriptorsForOnePort(&allocStruct); sdmaInitTxDescriptors(UARTPort,MPSC_PROTOCOL,PRIO0); allocBuffersForTxDescriptors(); CONFIDENTIAL Copyright © 2002 Marvell Doc. No. MV-S300165-00, Rev. A May 21, 2002, Preliminary Document Classification: Proprietary Information Page 163...

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