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GT-64260A Design Guide Doc. No. MV-S300165-00, Rev. A May 21, 2002...
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No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any particular purpose.
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Table 22: Trace Length for Data Topologies ...................... 121 Table 25: Trace Length for Double Cycle Signal Topologies ................124 Table 26: GT-64260A Double Cycle Signals AC Timing ..................125 Table 27: Typical SDRAM CS AC Timing ......................125 Table 28: PCI AC Timing for 33 MHz and 66 MHz (From the PCI Specification Document, Rev. 2.2) ....129 Table 29: GT-64260A PCI Interface AC Timing ....................
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Figure 29: Rx Descriptor Chain ..........................65 Figure 30: Disconnecting the Descriptor Chain .....................66 Figure 31: Releasing the Descriptor Chain......................67 Figure 32: GT-64260A I2C Interface Connection to SDRAM DIMMS ..............71 Figure 33: GPP Configured as Input ........................75 Figure 34: MPP Interrupt Outputs..........................76 Figure 35: DMA Controller General Flow ......................80...
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Figure 54: 1.1 ns Delay Trace Simulation ......................102 Figure 55: 0.8 ns Delay Trace Simulation ......................103 Figure 56: Layout for a Single GT-64260A to a Single CPU ................104 Figure 57: Layout for a Single GT-64260A to Multiple CPUs ................105 Figure 58: SDRAM Configuration Example ......................107 Figure 59: SDRAM Simulation Example ......................107...
Related Documentation Section 1. Introduction This design guide provides information for designing a system using the GT-64260A. This guide is intended for internal and external reference and is subject to future changes and modifications. Use this document as an addition to the GT-64260A datasheet and evaluation/reference design schematics.
Section 2. GT-64260A Overview The GT-64260A is a bridge from the PowerPC processor to the PCI bus, as well as a high-speed memory control- ler for external ROM and external peripherals. In addition, the GT-64260A integrates three 10/100 Mbps Ethernet ports and two MPSC controllers.
(such as SDRAM, ROM, PCI, etc.). Generally, there is a point-to-point connection between the GT-64260A and the CPU. In other cases, it depends on the system architecture, such as multi-GT-64260A, multiple CPU, or exter- nal arbiter. The following table describes the pin information and details of the GT-64260A CPU interface.
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0 = SysClk asynchronous to be tied to GND. TClk. 1 = CPU interface is running with TClk. SysRst* Section 20. "Reset" on The GT-64260A main reset page 144. pin. When in the reset state, all output pins (except for SDRAM address and control pins) are put into tri-state.
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(See the MPC75x user manual) DTI[2] pulled down. For all other configu- rations 10K-Ohm pull-down. BR0*/ When using the GT-64260A To avoid unstable GT_BG* internal arbiter, connect to the states at reset, a primary CPU BR* pin. 10K-Ohm Pull-up is When using an external arbiter, recommended.
60x Bus Mode The GT-64260A can act as master and slave on the 60x bus. In this mode, the GT-64260A 60x internal arbiter sup- ports three masters on the bus; two external 60x compatible masters, and an internal 60x master. The GT-64260A is configured to 60x bus mode by having the AD[7:6] signals sampled to b’00’...
The GT-64260A supports full cache coherency between the SDRAM and CPU caches. Any access to the SDRAM (from PCI or IDMA) may result in a snoop transaction driven by the GT-64260A on the CPU bus. The SDRAM access to a cache coherent region is always suspended until the snoop is resolved. In case of a HIT in a modified line in CPU cache, the SDRAM access might be suspended until the line write-back to SDRAM is completed.
PCI bus The GT-64260A supports up to four SDRAM address windows in which IDMA cache coherency is maintained. The address windows do not correlate to specific chip selects and may cross CS boundaries. The GT-64260A also supports eight configurational address ranges (four for each PCI interface) that help maintain PCI cache coherency.
CleanBlock FlushBlock bits [13:12] to the correct value, depending on the CPU type. See the GT-64260A datasheet’s "CPU Interface" sec- tion for more information. Configure cache coherent windows for the desired interface with the PCI cache coherency registers (0x1F00 - 0x1F38) and the IDMA cache coherency registers (0x380 - 0x3B8).
In MPX bus mode, a cache-inhibited instruction fetch performs a 16 byte transaction on the bus. Since the MPC745x’s first transaction after boot is 32/16 byte read and the GT-64260A does not support burst longer than 8 byte from 8-bits or 16-bits wide devices, implement one of the following solutions.
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Therefore, when using one of these CPUs, it must be configured to work in 2.5V on the CPU bus by configuring the CPU’s BVSEL pin to the correct value at reset. In addition, the GT-64260A’s CPU interface must be configured to 2.5V at reset by setting AD31 to ’0’.
Multi-GT or Multi-slave Modes It is possible to connect up to four GT-64260A or other 60x-bus compliant slave devices to the 60x bus without the need for any glue logic.This capability (referred to as "Multi-GT" mode) adds significant system design flexibility.
Table 1, “CPU Interface Pin Information,” on page 14). All TA* outputs from the GT-64260A devices must be tied together to drive the CPU TA* input. All AACK* outputs from the GT-64260A devices must be tied together to drive the CPU AACK* input.
0x100. A write transaction to address 0x00000000 gets a response from the GT-64260A configured as ID=’00’. This transaction is translated to a write to its internal regis- ter offset at 0x000.
Inter-Processor Interrupts (IPIs). The GT-64260A achieves the same goal by masking the BR1* pin from the internal arbiter. This causes the arbiter to think that only CPU0 needs the bus and it does not grant the bus to CPU1. To enable CPU1 arbitration, set the CPU Master Control register’s...
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The TBEN pin provided on the PowerPC CPUs can be used to implement this clock control function. Instead of using a dedicated pin for this purpose, the GT-64260A uses an MPP pin to enable this synchronization. The MPP must be configured to function as a general purpose output and must be connected to all of the CPUs’...
Figure 9: CPU to CPU Cache Coherency Data Flow 1. CPU1 initailizes the read cache block transaction to cache coherent memory. 2. CPU0 signs to CPU1 and to the GT-64260A that this cache block is valid in its cache. 4. CPU1 reads the updated block from SDRAM.
GT-64260A Design Guide Figure 12: JTAG/COP 16 Pin Connectors Top View Pins 10, 12, and 14 are no-connects. Pin 14 is not physically present. No pin Note The JTAG pins for the COP interface must not be chained with other devices in the system.
Section 4. SDRAM Interface Functional Overview The GT-64260A SDRAM controller supports 16/64/128/256/512 MB density SDRAM and registered SDRAM at 133 MHz. It also supports up to four banks of SDRAM and can address up to 4 GB (1 GB per bank – physical SCS*).
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GT-64260A Design Guide Table 7: SDRAM Interface Pinout Description (Continued) P in Name Inpu t/ SD RA M D evice or R equ ir ed D escr ipt ion Ou tpu t DI MM Con nect or E xt ern al...
DRAM specification (100 us of idle cycles before DRAM initialization). Memory Connection The GT-64260A supports 16, 64, 128, 256 and 512 MB SDRAM devices. Each SDRAM physical bank (SCS[3:0]) can be built from different SDRAM devices. The DRAM density is configured via the DRAM Bank Parameter regis- ters.
8-bit ECC (72-bit wide) to check the ECC. On partial writes, the GT-64260A reads all 64-bits of data and 8-bit ECCs to check the ECC. The GT-64260A then modifies the data bytes (less than 8B) and the ECC bank writes the updated data back.
GT-64260A Design Guide SDRAM Initialization The DRAM controller executes the SDRAM initialization sequence as soon as the GT-64260A goes out of reset (SysRst* de-assert). The DRAM controller performs a MRS (Mode Register Setting) cycle based on the default DRAM parameters (CL = 3, burst length = 4, burst order = linear). If the serial ROM initialization is enabled, the DRAM controller postpones the above DRAM initialization sequence until the serial ROM initialization completes.
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[9] and the bits [23:16], at offset 0x494 ErrProp ThrEcc to ‘0’. This prevents the GT-64260A from generating an interrupt or propagating the ECC error to other interfaces. In the SDRAM Timing Parameters register, at offset 0x4b4, set the ECCEn bit [13] to ’1’...
Use the IDMA engines, with DTL of 8B, to copy the boot code to the SDRAM from the boot device. It is impor- tant to use DTL = 8 Bytes to prevent the GT-64260A from performing a Read Modify Write to the SDRAM before the ECC initialization.
GT-64260A Design Guide Section 5. PCI Interface Functional Overview The GT-64260A supports two 64-bit PCI interfaces, compliant with the PCI specification, Rev. 2.2. Each PCI inter- face can be individually configured to a 32- or 64-bit configuration. The GT-64260A PCI0 interface supports ComactPCI Hot Swap. For more information on the CompactPCI Hot- Swap feature, see the GT-64260A datasheet’s "Hot Swap"...
5.1.1 Memory and I/O P2P Transactions To support access between the two PCI interfaces, the GT-64260A contains two 32-bit Memory BARs and one 32- bit I/O BAR. It also supports two additional Memory BARs for 64-bit addressing (DAC). A PCI address hit in one of the P2P BARs results in transferring the transaction to the other PCI interface memory space.
When the internal arbiter is enabled the GT-64260A PCI arbiter REQ*/GNT* pins are multiplexed on the MPP pins. Each internal PCI arbiter (PCI0 and PCI1) supports up to six external PCI devices and the GT-64260A PCI device (seven PCI devices per PCI interface).
Set the message address in the PCI MSI Message Address registers, at offsets 0x54 and 0xd4. If DAC is needed, set the PCI MSI Message Upper Address registers, at offsets 0x58 and 0xd8. The GT-64260A ini- tiates a write transaction to this address as soon as an interrupt is pending.
• Device1_CS* = ‘NOT’(Address[30]) ‘OR’ (CSTiming* ‘OR’ CS*0) Figure 20 shows an example of how three devices are connected through the GT-64260A device interface connec- tion. Note Since CSTiming* is tri-stated at reset assertion and CS pins qualification may be incorrect, connect a pull- up resistor on the CSTiming* pin.
Device1_CS* Notes • Since the AD bus is used to configure the GT-64260A at reset, the latch and/or transceivers must NOT implement "bus hold". • The CS* pins must be qualified with CSTiming* to generate the specific device chip select (e.g., Device_CS* = [CSTiming* ‘OR’...
Device Interface Functional Overview 8-bit Device The GT-64260A device controller supports 8-, 16-, or 32-bit wide devices. The device width is specified in the Device Bank Parameters register’s bits DevWidth [21:20], at offsets 0x45c, 0x460, 0x464, 0x468, and 0x46c. The...
Connect the Wr0* pin to one device and connect the other device to the AD[7:0] bus and to the Wr1* pin. Figure 22 shows the connection of a 16-bit wide device to the GT-64260A. for more information, on the 16-bit device connection, see the GT-64260A datasheet’s "Interfacing With 8/16/32-bit Devices" section.
OE* pins. Connect Wr[1:0] and AD[15:0] to one 16-bit device and connect Wr[3:2] and AD[31:16] to the other 16- bit device. Use a similar connection for 4x8-bit configuration. Figure 23 shows the connection of 32-bit wide device to the GT-64260A. For more information on the 32-bit device connection, see the GT-64260A datasheet’s "Interfacing With 16/16/32-bit Devices" section. CONFIDENTIAL Doc.
Signals Timing Note For more information on device bus signals, see the GT-64260A datasheet’s "Pin Information" section. The GT-64260A provides programmable access timing for various device implementations. The programmable parameters for device access have a 1 clock cycle granularity and are set per CS* (bank). All programmable access timings are set in the corresponding Device Bank Parameters register (Offsets: 0x45c, 0x460, 0x464, 0x468).
Ready* pin. Note In the GT-64260A datasheet, the Ready* pin AC timing refers to the sampled mode. There is no AC timing for the non-sampled mode. For more information, see the GT-64260A datasheet’s "AC Timing" section.
GT-64260A Design Guide Syncburst SRAM Syncburst SRAM devices can be connected to the GT-64260A device interface. It is recommended to use pipe- lined syncburst SRAM devices since they are designed for 133 MHz or higher frequencies. When using a Single Cycle Deselect (SCD) pipelined syncburst SRAM, an external logic must be used to extend the CS and Read (DevRW*) pins for one cycle on read transactions because the SRAM outputs are disabled within one clock cycle after deselect.
Baud Rate Generators (BRG) Ethernet Controllers There are three 10/100 Mbps full duplex Ethernet ports in the GT-64260A. Each port is fully compliant with the IEEE 802.3 and 802.3u standards and integrates MAC function and a dual speed MII interface. The Ethernet ports can be configured to MII or RMII (three Ethernet ports configuration is available only with RMII).
The CPU defines the part of the memory as cached and the rest as uncached. In addition, cache coherent regions will be defined in the GT-64260A for IDMA transactions. In this solution, the communication driver maintains a sep- arate set of buffers (and descriptors) that it will use for IDMA I/O of the communication interface. These buffers are located in the cached memory and configured in the GT-64260A as cache coherent.
Communication Interface Functional Overview MPSC and Ethernet SW Implications outside the snoop regions defined in the GT-64260A. As a result, the communication unit does not drive any snoop cycles when it is accessing to memory. This solution increases software complexity and since the buffer pool is shared among many devices in the soft- ware, this creates additional complications.
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GT-64260A Design Guide Although similar, the MPSC SDMA and the Ethernet SDMA differ in the SDMA descriptors’ command status field (different for each protocol) and the Tx descriptors’ shadow Byte Count field. The descriptors are 16 byte in size and do not require enormous processing resources.
GT-64260A Design Guide For each receive packet: • Disconnect the descriptors that formed this packet by moving the head pointer to the next descriptor in the chain. • Pass the descriptors to the application layer. Figure 30 shows an example of disconnecting the descriptor.
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To demonstrate the communication unit ability, the Board Support Package (BSP) implements an additional appli- cation layer, located in the demoApi.c file that functions as a repeater. This driver uses the communication unit driver’s APIs (see the BSP User Manual) to operate the GT-64260A Com- munication Unit.
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7.4.2.2 Driver ISR When the GT-64260A Communication Unit generates an interrupt, the interrupt controller calls a single ISR that handles the variety interrupt causes. The ISR processes the interrupt in three stages: It reads the Interrupt Cause register, acknowledges the interrupt events, and masks the interrupt events bits.
• Use the internal arbitration control. C Interface The GT-64260A has full I C support. It can act as master generating read/write requests and as a slave respond- ing to read/write requests. It fully supports multiple I C master’s environments.
Communication Interface Functional Overview I2C Interface Figure 32: GT-64260A I C Interface Connection to SDRAM DIMMS 7.5.2 C Interface Initialization To work with the I C interface, it must be initialized first. The interface initialization sequence is as follows: Reset the I C logic by writing to the I C Soft Reset Register, at offset 0xC01C.
This is not correct for the CPU interface, when the internal base is set to 0xf1000000, the CPU must access the GT-64260A internal registers at 0xf1000000 + offset. It is possible to con- figure to the internal base register through the serial ROM.
MPP Control registers (Offsets: 0xf000, 0xf004, 0xf008, and 0xf00c). The MPP pins can be used as hardware control signals to the various GT-64260A interfaces (UMA control, DMA control, or PCI arbiter signals) or as Gen- eral Purpose Pins. For more information, see the GT-64260A datasheet’s "Pins Multiplexing" section.
GT-64260A Design Guide the MPP interrupt outputs. For more information on the interrupt controller, see Section 11, "Interrupt Controller Functional Overview", on page Figure 34: MPP Interrupt Outputs Main Interrupt Cause Register (Low) 0xc18 GPP Pin Main Interrupt Cause Register (High) 0xc68...
Section 20, "Reset", on page 144). Also, the GT-64260A can be configured to act as a UMA master or slave. UMA systems require two additional sig- nals for arbitration of the SDRAM interface. For more information, see the GT-64260A datasheet’s "Unified Mem- ory Architecture Support"...
MODELS. If the current instruction is IDCODE in the GT-64260A TAP controller implementation, each exit from the SHIFT- DR state will cause the IDCODE to be fetched to DR (all 32 bits). While the controller is in the SHIFT-DR state, it shifts data from TDI to the register and, after the IDCODE was shifted out from the TDO, it starts shifting out that data.
IDMA Unit Functional Overview Section 10. IDMA Unit Functional Overview The GT-64260A IDMA controller transfers blocks of data independent of the local processor or PCI hosts. Data movement can occur from any interface to any interface. The GT-64260A implements eight IDMA channels. Each IDMA engine can move data between any source and destination, such as the SDRAM, Device, PCI_0, PCI_1, or CPU bus.
GT-64260A Design Guide Figure 35: DMA Controller General Flow Initialize IDMA source, destination,next descriptor, and command. Set Channel active bit. Read burst from source. Write burst to Fetch next destination. descriptor. EOT (enabled and asserted) Halt FetchND asserted Mode Fetch...
10.1 Chain Mode The GT-64260A IDMA engines can be activated in a chain mode. In this mode, the DMA controller loads descrip- tors from memory (SDRAM, PCI, etc.) prior to a DMA transfer. The DMA controller begins the transfer according to the descriptor information loaded for the segment.
If the interrupt source is an external device driving a GPP input (see 8.1 "General Purpose Pin (GPP)" on page 74), the GT-64260A can be configured to receive a level or edge trigger. If the Comm Unit Arbiter Control register’s GPP_Int bit [10] is set to ‘0’, at offset 0xF300, the external interrupts are treated as edge trigger interrupts.
PCI_INT1* PCI Device #1 PCI Device #2 The GT-64260A handles interrupts in two stages. It includes a main cause register, summarizing the interrupts generated by each unit, and specific unit cause registers, distinguishing between each specific interrupt event. Figure 37 shows the GT-64260A interrupt routing architecture.
11.1 Using External Interrupt Controller The GT-64260A interrupt controller can be connected to an external interrupt controller. This configuration is use- ful when the software must be backward compatible to previous designs.
Messaging Units Functional Overview Messaging Section 12. Messaging Units Functional Overview The GT-64260A messaging unit includes hardware hooks for message transfers between PCI devices and the CPU. The messaging unit can be divided into three different messaging types: messaging, doorbell, and I Note The polarity of the messaging unit doorbells, interrupt cause, and interrupt mask registers bits are determined via the Queue Control register’s Polarity bit 8, at offset 0x1C50.
12.3.1 Inbound Circular Queue The PCI device writes to the Inbound Queue Port Virtual register (Offset: 0x1c40 and 0x1cc0) and the GT-64260A asserts an interrupt to the CPU and increments the head pointer. The CPU reads the message, increments the tail pointer, and writes to the Inbound Free Head Pointer register (Offset: 0x1c60 and 0x1ce0).
The CPU writes to the Outbound Queue Port Virtual Register (Offset: 0x1c44 and 0x1cc4) and increments the head pointer. The GT-64260A asserts an interrupt to the PCI device. The PCI device reads the message and the tail pointer is incremented by the GT-64260A. The PCI device must write to the Outbound Free Head Pointer reg- ister (Offset: 0x1c70 and 0x1cf0).
GT-64260A. This figure is applicable to all GT-64260A interfaces, except for the PCI interface. The PCI interface pads are PCI complaint and their max- imum and minimum rating are compliant to the PCI specification 2.2. document section "4.2.2.3 Maximum AC Rat- ings and Device Protection".
Section 14. CPU Interface Design Considerations The CPU interface is used to connect the GT-64260A and the CPU. The GT-64260A CPU interface is a 60x bus compatible master and slave. In addition, it is a MPX bus compatible slave. Note As an MPX bus compatible slave, this interface only supports "address only bus mastering"...
14.4.1 Calculating the Reference Point The output delay values in the GT-64260A datasheet’s AC timing table is defined for a specific load. This value includes the rise/fall time of the output. To calculate the signal fly time, the rise/fall time must be measured and a reference measuring point must be set.
M ax Input Setup Input hold output delay 1. ARTRY* for address only. In this configuration, the signals are connected from the GT-64260A to the CPU in a point-to-point configuration. (See Figure 47.) Figure 47: GT-64260A to CPU Point-to-Point Configuration...
The fly time is measured from the CPU reference point that was measured in “Calculating the Reference Point” on page 92 (2.1 ns) to the Vil measured on the GT-64260A pin (3.1 ns) in Figure 48 (board simulation). Figure 48: 1 ns Delay Trace Simulation The timing requirements for the CPU to the GT-64260A are: Tcycle >...
For 200 ps delay for 1 inch, the maximum distance is 4 inches. Figure 49 shows a simulation of 0.8 ns delay trace. The fly time is measured from the GT-64260A reference point that was measured in “Calculating the Reference Point” on page 92 (3 ns) to the Vil measured on the CPU pin (3.8 ns) in...
Input Setup Input hold output delay 1. ARTRY* for multiple data masters. In this configuration, the signals are connected from the GT-64260A to the CPUs in a ’T’ topology. (See Figure 50.) Figure 50: GT-64260A to Multiple CPU Configuration CPU0...
Timing Requirements Figure 51: 0.5 ns Delay Trace Simulation (Maximum Distance 2.5 Inches) The GT-64260A to CPU calculation is the same as in the single GT-64260A and single CPU example. Note For multiple CPU configurations, a separate IBIS model must be used. For more information, contact your local Field Application Engineer (FAE).
In multi-GT mode, the ARTRY* signals setup time is 4.9 ns. This is ignored in the timing calculation example, since most applications do not use the ARTRY*. In this configuration, the signals are connected from the GT-64260A to the CPU in a ’T’ topology. See Figure Note The GT-64260A in multi-GT mode is targeted to operate at 100 MHz.
Figure 54 (board simulation). Figure 54: 1.1 ns Delay Trace Simulation The GT-64260A to CPU calculation is the same as the single GT-64260A and a single CPU but the longest path is from one GT-64260A to the other GT-64260A. Note For the multiple GT-64260As configuration, separate AC timings must be used.
10 > 4.2 + 4.5 + Tdelay(fly_time) + 0.5 Tdelay(fly_time) < 0.8 ns Figure 55 shows simulation of 0.8 ns delay trace. The fly time is measured from the GT-64260A reference point that was measured in 14.4.1 "Calculating the Reference Point" on page 92 (3 ns) to the Vil measured on the CPU pin (3.8 ns) in...
GT- 64260A connected to a single CPU. Figure 57 shows the placement for single a GT-64260A connected to multiple CPUs. Figure 56: Layout for a Single GT-64260A to a Single CPU CPU interface PCI0 SDRAM GT-64260A PCI1 Comm.
Device A B C D . . . The placement for multi-GT mode depends on the number of GT-64260A devices and interfaces used on each one of them. Depending on the system configuration and timing simulation, parallel termination on the bi-directional signals can be placed near the CPUs or the GT-64260As.
For more information, see Section 4. "SDRAM Interface Functional Overview" on page The GT-64260A supports UMA mode as master or slave. The UMA mode is sampled at reset by AD[12] signal for enable/disable setting and AD[13] for master/slave setting. For more information, see Section 20.
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The simulation represent a configuration of one physical bank with eight devices (single cycle DIMM). 15.4.1 Clock Timing The GT-64260A supports a few SDRAM clock configurations. For more information on the supported configura- tions, see Section 19. "Clocks" on page 143 or AN-82: SDRAM Clocking Schemes in the GT-642xxA .
15.4.2 Data Timing Since the AC specification of the GT-64260A and of the SDRAM devices is for a given test circuit, the first stage is to calculate the reference point for the timing calculations. The reference point is used as a starting point to mea- sure the signal fly time.
GT-64260A Design Guide Figure 63: GT-64260A Data Reference Point The SDRAM output delay AC timing uses a similar test circuit with load of 50 pf (Cl = 50pf). Simulating the SDRAM data signals test circuit will give reference point of 1.54 ns. (See Figure 64.)
GT-64260A Design Guide Figure 65 describes the data topology for the selected memory configuration (one physical bank with eight devices). Figure 65: Selected Memory Configuration Data Topology SDRAM Data GT-64260A 10 ohm DIMM Connector Table 19: Trace Length for Data Topologies...
7.5 > 3.8 + 1.5 + Tdelay(fly_time) + 0.5 Tdelay(fly_time) < 1.7 ns Figure 67 shows a simulation for a 0.8 ns delay trace. The fly time is measured from the GT-64260A reference point determined in Figure 63 on page 112 (2.1 ns) to the Vil measured on the SDRAM pin (2.5 ns) in the figure...
GT-64260A Design Guide Figure 67: 0.8 ns Delay Trace Simulation (2.1 ns Fly Time Reference Point) Note The data signal fall time is smaller than the test circuit since the load is smaller (8 pf instead of 30 pf). Figure 68 shows a simulation of 0.8 ns delay trace.
Figure 68: 0.8 ns Delay Trace Simulation (1.54 ns Fly Time Reference Point) 15.4.3 Chip Select Signals The output delay value of the GT-64260A SCS*[3:0] signals in the AC timings table are given for 50 pf load (Cl = 50pf). (See Figure 69.)
Figure 70: GT-64260A Chip Select Reference Point Figure 71 describes the Chip Select signal routing topologies on the DIMM module. Each GT-64260A SCS* signal is connected to two DIMM CS* pins (32-bits data width per SCS*). This means that in the sample memory config- uration (one physical bank with eight devices), the SCS* signal is connected to eight SDRAM devices.
GT-64260A Design Guide Figure 71: Chip Select Signal Routing on the DIMM Module Add for x16 and Add for x16 This diagram is for CS x8 components and x8 components nets that neither have SDRAM an ECC device nor the stuffing option for one.
7.5 > 3.8 + 1.5 + Tdelay(fly_time) + 0.5 Tdelay(fly_time) < 1.7 ns Figure 72 shows the simulation of 0.8 ns delay trace. The fly time is measured from the GT-64260A reference point that was measured in Figure 70 on page 119 (1.3 ns) to the Vil measured on the SDRAM pin (4.1 ns) in the...
The output delay value of the GT-64260A DAdr[12:0], SRAS*, SCAS*, and BankSel[1:0] signals in AC timings table are given for 50 pf load (Cl = 50pf). (See Figure 69.) Simulating the GT-64260A SDRAM interface double cycle signal test circuit gives a reference point of 2 ns. (See Figure 73.) CONFIDENTIAL Doc.
GT-64260A Design Guide Figure 74 describes the double cycle signal routing topologies on the DIMM module. In the selected memory con- figuration, there are eight SDRAM devices placed on the DIMM (1 row DIMM). Figure 74: Double Cycle Signal Routing on the DIMM Module...
7.5 > 3.7 + 1.5 + Tdelay(fly_time) + 0.5 Tdelay(fly_time) < 1.8 ns Figure 75 shows a simulation of 0.8 ns delay trace. The fly time is measured from the GT-64260A reference point that was measured in Figure 73 on page 123 (2 ns) to the Vil measured on the SDRAM pin (3.8 ns) in the figure...
GT-64260A Design Guide Figure 75: 0.8 ns Delay Trace Simulation (2.0 ns Fly Time Reference Point) Simulating this topology means the calculated fly time is (3.8 - 2 = 1.8 ns). 15.5 Layout Instructions 15.5.1 Device Placement All devices must be placed as closed as possible to each other.
A B C D . . . 15.5.2 Routing The SDRAM interface traces must be 55 to 65 Ohm impedance. The SDRAM and GT-64260A clocks (see Section 19. "Clocks" on page 143) must be routed on separate layers from the other signals.
GT-64260A Design Guide Section 16. PCI Interface Design Considerations The PCI interface is used to connect the GT-64260A and other PCI devices. The GT-64260A supports two 64-bit PCI interfaces (named PCI0 and PCI1), compliant to PCI specification, Rev. 2.2. 16.1 Interface Connectivity The PCI interfaces connectivity complies to the PCI specification, Rev.
RST# high to first configuration access rhff RST# high to first FRAME# assertion Table 29: GT-64260A PCI Interface AC Timing NOTE: All PCI interface Output Delays, Setup, and Hold times are referred to the PClk rising edge. Sig nal s De sc r ip tion...
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For 66 MHz bus frequency, Section "7.7.5 System Timing Budget". When using the GT-64260A internal PCI arbiter, the MPP interface is used for the arbitration signals. The MPP interface AC timing depends on their functionality. See the GT-64260A datasheet’s "AC Timing" section. The PCI GNT* signals maximum output delay (referred to the corresponding PClk clock) is 6.6 - 7.5 ns, depending on...
Tcycle > Toutput_delay(GT-64260A) + Tsetup(PCI_spec) + Tdelay(fly_time) + Tclock_skew 15 > 7.5 + 5 + Tdelay(fly_time) + 0.5 Tdelay(fly_time) < 2 ns The fly time is measured from the GT-64260A reference point that is measured in Figure 78 (2.1 ns) to the Vil measured on the SDRAM pin (3.3 ns) in the figure below (board simulation).
Section 17. Ethernet Interface Design Considerations The GT-64260A contains up to three Ethernet controllers. Each controller can be configured to operate in MII or RMII mode. Each 10/100 Mbit port is fully compliant with the IEEE 802.3 and 802.3u standards and integrates the MAC func- tion and a dual speed MII interface.
Tcycle > Toutput_delay(GT-64260A) + Tsetup(PHY) + Tdelay(fly_time) + Tclock_skew 20 > 10 + 4 + Tdelay(fly_time) + 0.5 Tdelay(fly_time) < 5.5 ns The fly time is measured from the GT-64260A reference point in Figure 82 (2.1 ns) to the Vil measured on the SDRAM pin (3.3 ns) in the figure below (board simulation).
GT-64260A Design Guide Figure 83: 2.1 ns Fly Time Reference Point Note In this topology, the fall time is slower than the test circuit because the load is smaller. 17.5 Layout Instructions 17.5.1 Placement Figure 84 illustrate how the PHYs must be placed.
Ground, common Note For more information on the PLL power supply filtering, see the GT-64260A datasheet’s "PLL Power Filter Circuit" section. All power planes must be de-coupled to ground to provide for reasonable management of the switching currents ( d I/ d t ) to which the plane and its supply path are subjected.
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Connect one 100 nf capacitor to each VCC3.3 power pin. The minimum capacitors/pin must not be smaller than 2:3. Place the capacitors as close as possible to the power pins. It is also recommended to place two 4.7 uf capacitors close to the GT-64260A. See Figure 18.1.2 VCC2.5 De-coupling Connect one 100 nf capacitor to each VCC2.5 power pin.
For the SDRAM clocking scheme, it is not recommended to use the SDClkOut configuration. For more information on the SDRAM interface clocking, see the GT-64260A datasheet and AN- 82: SDRAM Clocking Schemes in the GT-642xx/A Devices on the secure website.
Rst signal. Some systems require the PCI devices to be reset, but not the GT-64260A and the CPU. For example, the CPU gets data from the GT-64260A communication ports and routes it to other GT-64260A interfaces (PCI, MPSC, etc.).
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GT-64260A Design Guide 0x1c000000 /* Destination address */ 0x14000930 0x00000000 /* Next descriptor address = NULL */ 0x14000940 0x80001a00 /* Dummy writes to stall the system until the DMA finishes */ 0x14000c00 0x00000000 0x14000c00 0x00000000 /* Enable Boot from SRAM, switch between the memory windows */...
GT-64260A Design Guide Appendix C. ECC Initialization- Example Code C.1 Assembler Code The following is the Assembler Code to Copy the Boot Device to SDRAM. ! Copy dink to memory..addisr3,0,0 ! Load dram address (0) into r3. addisr4,0,RESET_BASE! Load r4 with base eprom address ! of 0xFFF00000.
GT-64260A CPU interface. To write to the GT-64260A internal register, the data on the CPU bus must be driven as Big Endian (the order of significance is that the LSB is the leftmost and the MSB is the rightmost). One way of driving the data as Big Endian on the CPU bus is for the CPU's general register to hold the data in Big Endian and use a simple load instruction.
The problem with working in Big Endian is that the PCI is a 32-bit bus. Even with the extension to PCI64, every transaction ends as a 32-bit transaction depending on the master and slave. Big Endianess depends on the bus width. Because of that, the GT-64260A must work on the PCI in Big-32 mode. Table 35:...
0x 04030201.08070605 D.4.1 Non PCI-to-PCI Swapping (CPU, DMA, SDMA) Because the GT-64260A works in Dwords (8 Byte) and the PCI works in Words(4 Byte), a restriction exists when working with less than Dword transactions. There are four reasonable cases when working with Big and Little Endian on the core and on the PCI.
GT-64260A Design Guide Second phase Pad[31:0] = 0x77665544 Pad[63:32] = don’t care Here is how it looks on a 32 bit PCI bus: In case of starting address with offset 0: First phase - Pad[31:0] = 0x33221100 Second phase Pad[31:0] = 0x77665544...
GT-64260A Design Guide Appendix E. Communication Example Code E.1 Ethernet Initialization /* Initialize the Communication Unit memory pool */ usrMemInit(); /* connect the MPSC and Ethernet as RMII ports */ GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, 0x1102); /* initialize the address table to filter other MAC addresses */ initAddressTable(ETHERNET_DOWNLOADING_PORT,0,1,0);...
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GT-64260A Design Guide BRG_DEFAULT_BAUD_TUNING_GET(&(cfgTunBrg.tuning),UART_PORT); brgSetConfig(&cfgTunBrg,UART_PORT); /* set the BRG with defaults values */ /* Halt any Rx/Tx activities */ /* stop the MPSC Rx machines */ GT_REG_WRITE(CHR(UARTPort,2) , ABORT_RECEPTION); /* workaround for wrong data read from MPSC internal registers. */ /* wait for the Rx to abort in the MPSC machine */ for(tempRegValue=0;...
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