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L64105 MPEG-2
LSI L64105 MPEG-2 Manuals
Manuals and User Guides for LSI L64105 MPEG-2. We have
1
LSI L64105 MPEG-2 manual available for free PDF download: Technical Manual
LSI L64105 MPEG-2 Technical Manual (454 pages)
Audio/Video Decoder
Brand:
LSI
| Category:
Media Converter
| Size: 1.24 MB
Table of Contents
Table of Contents
4
Video Interface Registers
16
Chapter 1 Introduction
23
L64105 Overview
24
Memory Utilization
27
Chapter 10 Audio Decoder Module
28
Features
28
Chapter 5 Host Interface
33
Chapter 6 Channel Interface
35
Memory Interface
37
Video Interface
38
Audio Interface
39
Chapter 2 I/O Signal Descriptions
41
Miscellaneous and Test Interfaces
41
Host Interface Registers
45
Video Decoder Registers
50
Memory Interface Registers
57
Microcontroller Registers
60
Video Interface Registers
63
Audio Decoder Registers
67
RAM Test Registers
70
Chapter 3 Register Summary
73
Alphabetical Listing
73
Register 4 (0X004)
90
Register 5 (0X005)
91
Register 6 (0X006)
92
Register 7 (0X007)
93
Registers 9–12 (0X009–0X00C) SCR Value [31:0]
95
Register 17 (0X011)
96
Register 18 (0X012)
97
Registers 20–23 (0X014–0X017 SCR Compare Audio [31:0]
98
Video Decoder Registers
99
Register 65 (0X41)
100
Register 66 (0X042) User Data FIFO Output [7:0]
101
Register 68 (0X044)
102
Register 69 (0X045)
103
Registers 72 and 73 (0X048 and 0X049 Video es Channel Buffer Start Address [13:0]
104
Registers 74 and 75 (0X04A and 0X04B Video es Channel Buffer End Address [13:0]
105
Registers 78 and 79 (0X04E and 0X04F Audio es Channel Buffer End Address [13:0]
106
Audio PES Header/System Channel Buffer Start Address [13:0]
107
Registers 96–98 (0X060–0X062 Video es Channel Buffer Write Address [19:0]
108
Registers 102–104 (0X066–0X068) Video PES Header Channel Buffer Write Address [19:0]
109
Registers 108–110 (0X06C–0X06E) Video es Channel Buffer Compare DTS Address [18:0]
110
Registers 111–113 (0X06F–0X071) Audio es Channel Buffer Compare DTS Address [18:0]
111
Registers 120–122 (0X078–0X07A S/P DIF Channel Buffer Read Address [19:0]
112
Registers 128–130 (0X080–0X082 Picture Start Code Read Address [19:0]
113
Registers 134–136 (0X086–0X088 Video es Channel Buffer Numitems [18:0]
114
Registers 137–139 (0X089–0X08B Audio es Channel Buffer Numitems [18:0]
115
Register 143 (0X08F)
116
Register 144 (0X090)
117
Register 147 (0X093)
118
Register 149 (0X094)
119
Memory Interface Registers
120
Register 193 (0X0C1)
121
Register 194 (0X0C2) Host SDRAM Read Data [7:0]
123
Registers 196–198 (0X0C4–0X0C6 Host SDRAM Target Address [18:0]
124
Registers 202 and 203 (0X0Ca and 0X0Cb Block Transfer Count [15:0]
125
Register 205 (0X0Cd)
126
Register 206 (0X0Ce)
127
Registers 213–215 (0Xd5–0X0D7 DMA SDRAM Target Address [18:0]
128
Register 219 (0X0Db) DMA SDRAM Read Data [7:0]
129
Microcontroller Registers
130
Registers 230 and 231 (0X0E6 and 0X0E7 Anchor Chroma Frame Store 2 Base Address [15:0]
131
Register 236 (0X0Ec)
132
Register 237 (0X0Ed)
133
Register 238 (0X0Ee)
134
Register 239 (0X0Ef)
136
Register 240 (0X0F0)
138
Register 242 (0X0F2) Q Table Entry [7:0]
139
Video Interface Registers
140
Registers 266–268 (0X10A and 0X10C Programmable Background Y/Cb/Cr [7:0]
142
Registers 270–273 (0X10E–0X111 OSD Odd/Even Field Pointers [15:0]
143
Register 275 (0X113)
144
Register 276 (0X114)
145
Register 277 (0X115) Horizontal Filter Scale [7:0]
146
Register 278 (0X116)
147
Register 280 (0X118) Horizontal Pan and Scan Luma/Chroma Word Offset [7:0]
148
Register 283 (0X11B)
149
Registers 285–288 (0X11D–0X120) Display Override Luma/Chroma Frame Store Start Addresses [15:0]
150
Register 290 (0X122)
151
Registers 297–299 (0X129–0X12B) Main Start/End Rows [10:0]
152
Register 304 (0X130) Vcode Even [7:0]
153
Audio Decoder Registers
154
MPEG Bitrate Index Table
155
Register 337 (0X151)
156
Register 338 (0X152)
158
Register 351 (0X15F)
159
Register 354 (0X162)
160
Register 355 (0X163)
161
Register 356 (0X164)
162
Register 357 (0X165)
163
Register 358 (0X166)
164
Register 359 (0X167) PCM FIFO Data in [7:0]
165
Register 362 (0X16A) PCM Scale [7:0]
166
Register 364 (0X16C)
167
ACLK Divider Select [3:0] Code Definitions
168
Register 365 (0X16D)
169
Register 366 (0X16E)
170
Register 367 (0X16F) Host Category [7:0]
171
Register 368 (0X170)
172
RAM Test Registers
173
Registers 387–392 (0X183–0X188) Memory Test Pass/Fail Status Bits
175
Host Interface 5.1 Overview
177
Interface Signals
178
Motorola Mode Write Timing
179
Motorola Mode Read Timing
180
Register Access and Functions
181
General Functions
181
SCR Registers
182
Operation of the SCR Counter
183
Interrupt Registers
185
SDRAM Access
186
Host Reads/Writes
186
Host Read/Write Flowchart
189
Host DMA SDRAM Transfers
190
DMA SDRAM Read/Write Flowchart
193
SDRAM Block Move
194
Block Move Flowchart
195
Channel Interface 6.1 Overview
197
System Syntax
198
Interface Signals Operation
199
Asynchronous Mode
200
Synchronous Validn Inputs
201
Xvalidn Input Synchronization Circuits
202
Synchronous A/Vreqn Outputs
203
Channel Bypass Mode
204
Channel Pause
204
Preparser
205
Host Selection of Streams and Headers
205
Audio Stream Select Enable Bits
206
Pack Header Enable Bits
207
Elementary Streams
208
Elementary Stream Buffering
209
PES Packet Structure
210
PES Packet Structure
211
Preparsing an MPEG-1 System Stream
212
System PES Channel Buffer Map for MPEG-1 Streams
213
Preparsing a Program Stream
214
System Channel Buffer Map for Program Streams
215
Audio es Channel Buffer Map for Linear PCM Audio
216
Error Handling in Program Streams
217
Preparsing A/V PES Packets from a Transport Stream
220
Error Handling in A/V PES Mode
221
Channel Buffer Controller
223
Buffer Reset
224
In the Video Channel
225
Summary
226
A/V PES Mode Channel Interface Operation
227
SDRAM Configurations
230
Chapter 7 Memory Interface
231
SDRAM Timing and Modes
231
SDRAM Timing Requirements for Reads
232
SDRAM Refresh and Arbitration
233
Memory Channel Buffer Allocation
234
Channel Buffer Architectures
236
Memory Frame Store Allocation
237
Normal Mode
238
Reduced Memory Mode (RMM)
239
Summary
240
Video Decoder Block Diagram
245
Chapter 8 Video Decoder Module
246
Postparser Operation
246
Sequence Extension
248
Sequence Display Extension
249
Group of Pictures Header
250
Picture Header
251
Picture Coding Extension
253
Quant Matrix Extension
255
Host Access of Q Table Entries
256
Picture Display Extension
257
Number of Frame Center Offsets
258
Copyright Extension
259
User Data
260
Auxiliary Data FIFO Operation
261
Aux Data FIFO Status
262
User Data FIFO Operation
263
User Data FIFO Registers
264
Video Decoder Pacing
266
Channel Start/Reset and Status Bits
267
Video Decoder Start/Stop
268
Time Line for Frame Picture
270
Time Line for Field Picture
271
Frame Store Modes
272
Frame Store Organization in Normal Mode
273
Reduced Memory Mode
274
Two-Frame Store Mode
276
Trick Modes
277
Single Skip with and Without Display Freeze
279
Repeat Frame
280
Frame Repeat Modes
281
Channel Buffer Underflow Panic Repeat
282
Setting up Rip Forward/Display Override Command
284
Force Broken Link
285
Automatic Rate Control
287
Sequence End Processing
288
Example of Sequence End Processing
289
Error Handling and Concealment
290
Error Conditions Detected
291
Video Interface Block Diagram
295
Television Standard Select
296
Chapter 9 Video Interface
297
Display Areas
297
Display Areas Example
298
Vertical Timing
299
Vertical Timing Vcodes and Fcodes for NTSC
300
Vertical Timing Vcodes and Fcodes for PAL
301
Horizontal Timing
302
Horizontal Input Timing
303
Video Background Modes
304
Still Image Display
305
Luma and Chroma Frame Store Format
306
Display Modes and Vertical Filtering
308
Display Mode Selection Table
309
Reduced Memory Mode
311
Horizontal Postprocessing Filters
312
Frequency Response a
313
Frequency Response B
314
On-Screen Display
315
OSD Modes
316
OSD Area Data Organization
317
OSD Header Control Fields
318
OSD Header Color Fields
319
OSD Storage Formats
321
External OSD
323
Pan and Scan Operation
324
Host Controlled Pan and Scan
325
Bitstream Controlled Pan and Scan
327
Display Freeze
328
Freeze Operation Timing
329
Pulldown Operation
330
Video Output Format and Timing
331
Display Controller Interrupts
332
Audio Decoder Overview
334
Audio Decoder Modes
335
L64105 Audio Decoder Block Diagram
336
Decoding Flow Control
338
Audio Decoder Start/Stop
339
Audio Formatter Play Mode
340
Autostart
341
MPEG Audio Decoder
342
MPEG Audio Bitstream Syntax
343
MPEG Audio Decoding
344
MPEG Audio Decoding Flow
345
Linear PCM Audio Decoder
346
Valid Linear PCM Stream Permutations
347
Synchronization
348
Other Host Controls and Status
350
MPEG Formatter
351
Syntax of the MPEG Data in IEC958 Format
352
Number of IEC958 Frames When Formatting MPEG Data
353
Pause Burst
354
Inserting Pause Bursts in the MPEG Formatter Output
355
Synchronization
356
MPEG Audio Formatter Error Handling
357
PCM FIFO Mode
358
DAC Interface
359
DAC Output Mode: PCM Sample Precision = 20 Bit
360
Biphase Mark Coding
362
IEC958 Syntax
363
IEC958 Channel Status
364
ACLK Divider Select [3:0] Code Definitions
366
Absolute Maximum Ratings
368
DC Characteristics
369
AC Test Load and Waveform for Standard Outputs
370
AC Test Load and Waveform for 3-State Outputs
371
SDRAM Interface AC Timing
372
SDRAM Read Cycle
373
SDRAM Write Cycle
374
Host Interface AC Timing (Motorola Mode)
375
Host Write Timing (Motorola Mode)
376
Host Read Timing (Motorola Mode)
377
Host Interface AC Timing (Intel Mode)
378
Host Write Timing (Intel Mode)
379
Asynchronous Channel Write Timing
380
Synchronous Avalidn/Vvalidn Signals Timing
381
Video Interface Timing
382
Serial PCM Data out Timing
383
Preqn Timing
384
Alphabetical Pin Summary
385
Pin Package Pinout
391
Pin PQFP (PZ) Mechanical Drawing (Sheet 1 of 2)
392
Appendix A Video/Audio Compression and Decompression Concepts
396
Video Encoding
396
A.1 MPEG Macroblock Structure
397
Bitstream Syntax
399
A.3 Typical Sequence of Pictures in Bitstream Order
400
Video Decoding
401
MPEG Audio Encoding
402
A.5 ISO System Stream
403
Audio Decoding
405
Chapter 11 Specifications
396
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