LSI L64105 MPEG-2 Technical Manual

Audio/video decoder

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L64105 MPEG-2

Audio/Video Decoder

Technical Manual

Preliminary

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Page 1 查询L64105供应商捷多邦，专业PCB打样工厂，24小时加急出货 L64105 MPEG-2 Audio/Video Decoder Technical Manual Preliminary ®...
Page 2 LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties.
Page 3 Contents Preface Chapter 1 Introduction An L64105 Application L64105 Overview 1.2.1 Memory Utilization 1.2.2 Error Concealment Features Chapter 2 I/O Signal Descriptions Signals Organization Host Interface Channel Interface Memory Interface Video Interface Audio Interface Miscellaneous and Test Interfaces 2-11 Chapter 3 Register Summary Summary by Register Alphabetical Listing...
Page 4: Table Of Contents
Video Interface Registers 4-58 Audio Decoder Registers 4-72 RAM Test Registers 4-91 Chapter 5 Host Interface Overview Interface Signals Register Access and Functions 5.3.1 General Functions 5.3.2 SCR Registers 5.3.3 Interrupt Registers SDRAM Access 5-10 5.4.1 Host Reads/Writes 5-10 5.4.2 Host DMA SDRAM Transfers 5-14 5.4.3...
Page 5 6.4.2 Detecting Potential Underﬂow Conditions in the Video Channel 6-29 Summary 6-30 Chapter 7 Memory Interface Overview SDRAM Conﬁgurations SDRAM Timing and Modes SDRAM Refresh and Arbitration Memory Channel Buffer Allocation Memory Frame Store Allocation 7.6.1 Luma Store 7.6.2 Chroma Store 7.6.3 Normal Mode 7-10...
Page 6 Video Decoder Pacing 8-24 8.3.1 Channel Start/Reset and Status Bits 8-25 8.3.2 Video Decoder Start/Stop 8-26 Frame Store Modes 8-30 8.4.1 Normal (3-Frame Store) Mode 8-30 8.4.2 Reduced Memory Mode 8-32 8.4.3 Two-Frame Store Mode 8-34 8.4.4 Decode and Display Frame Store Status Indicators 8-34 Trick Modes...
Page 7 9.10 Pan and Scan Operation 9-32 9.10.1 Host Controlled Pan and Scan 9-33 9.10.2 Bitstream Controlled Pan and Scan 9-35 9.10.3 Vertical Pan and Scan 9-35 9.11 Display Freeze 9-36 9.12 Pulldown Operation 9-38 9.13 Video Output Format and Timing 9-39 9.14 Display Controller Interrupts...
Page 8 10.9 S/P DIF Interface 10-29 10.9.1 Biphase Mark Coding 10-30 10.9.2 IEC958 Syntax 10-30 10.9.3 IEC958 Channel Status 10-32 10.10 Clock Divider 10-32 Chapter 11 Speciﬁcations 11.1 Electrical Requirements 11-1 11.2 AC Timing 11-4 11.3 Pinouts and Packaging 11-18 Appendix A Video/Audio Compression and Decompression Concepts Video Compression and Decompression Concepts A.1.1...
Page 9 Register 4 (0x004) Register 5 (0x005) Register 6 (0x006) 4-10 Register 7 (0x007) 4-11 Registers 9–12 (0x009–0x00C) SCR Value [31:0] 4-13 4.10 Registers 13–16 (0x00D–0x010) SCR Compare/Capture [31:0] 4-13 4.11 Register 17 (0x011) 4-14 4.12 Register 18 (0x012) 4-15 4.13 Register 19 (0x013) 4-15 4.14...
Page 10 4.32 Registers 99–101 (0x063–0x065) Audio ES Channel Buffer Write Address [19:0] 4-26 4.33 Registers 102–104 (0x066–0x068) Video PES Header Channel Buffer Write Address [19:0] 4-27 4.34 Registers 108–110 (0x06C–0x06E) Video ES Channel Buffer Read Address [19:0] 4-27 4.35 Registers 108–110 (0x06C–0x06E) Video ES Channel Buffer Compare DTS Address [18:0] 4-28 4.36...
Page 11 4.56 Register 195 (0x0C3) Host SDRAM Write Data [7:0] 4-41 4.57 Registers 196–198 (0x0C4–0x0C6) Host SDRAM Target Address [18:0] 4-42 4.58 Registers 199–201 (0x0C7–0x0C9) Host SDRAM Source Address [18:0] 4-42 4.59 Registers 202 and 203 (0x0CA and 0x0CB) Block Transfer Count [15:0] 4-43 4.60 Register 204 (0x0CC)
Page 12 4.83 Register 243 and 244 (0x0F3 and 0x0F4) Microcontroller PC [11:0] 4-57 4.84 Register 245 (0x0F5) Revision Number [7:0] 4-57 4.85 Register 246 (0x0F6) 4-57 4.86 Register 248 (0x0F8) Reduced Memory Mode (RMM) Bit 4-58 4.87 Register 265 (0x109) 4-58 4.88 Registers 266–268 (0x10A and 0x10C) Programmable Background Y/Cb/Cr [7:0]...
Page 13 4.111 Register 309 (0x135) 4-72 4.112 Register 336 (0x150) 4-72 4.113 Register 337 (0x151) 4-74 4.114 Register 338 (0x152) 4-76 4.115 Register 351 (0x15F) 4-77 4.116 Register 352 (0x160) 4-77 4.117 Register 353 (0x161) 4-77 4.118 Register 354 (0x162) 4-78 4.119 Register 355 (0x163) 4-79 4.120 Register 356 (0x164)
Page 14 5.10 Block Move Flowchart 5-19 Channel Interface Block Diagram Asynchronous Channel Interface Timing xVALIDn Input Synchronization Circuits Synchronous Valid Signals Timing L64105 A/VREQn Circuits Elementary Stream Buffering 6-13 PES Packet Structure 6-15 Preparsing an MPEG-1 System Stream 6-16 System PES Channel Buffer Map for MPEG-1 Streams 6-17 6.10 System Channel Buffer Map for Program Streams...
Page 15 Horizontal Input Timing 9-11 Horizontal Timing for 8-Bit Digital Transmission for NTSC 9-12 Luma and Chroma Frame Store Format 9-14 Frequency Response A 9-21 9.10 Impulse Response A 9-21 9.11 Frequency Response B 9-22 9.12 Impulse Response B 9-22 9.13 OSD Area Data Organization 9-25 9.14...
Page 16: Video Interface Registers
11.9 Asynchronous Channel Write Timing 11-14 11.10 Synchronous AVALIDn/VVALIDn Signals Timing 11-15 11.11 Reset Timing 11-15 11.12 Video Interface Timing 11-16 11.13 Serial PCM Data Out Timing 11-17 11.14 A_ACLK Timing 11-17 11.15 PREQn Timing 11-18 11.16 160-Pin Package Pinout 11-25 11.17 160-Pin PQFP (PZ) Mechanical Drawing (Sheet 1 of 2) 11-26...
Page 17 System Header Enable Bits 6-11 Video PES Header Enable Bits 6-12 Audio PES Header Enable Bits 6-12 Buffer Start and End Address Registers for ES Mode 6-13 Buffer Write and Read Pointer Registers in ES Mode 6-14 6.10 Number of Items in Buffers in ES Mode 6-14 6.11 SDRAM Addresses - Audio PES Header/System...
Page 18 Force Video Background Selections 9-12 Override Display Registers 9-14 Display Mode Selection Table 9-17 Raster Mapper Increment Value by Source Resolution 9-23 OSD Modes 9-24 High Color Modes 9-26 Host Controlled Pan and Scan Registers 9-33 9.10 Freeze Modes 9-36 10.1 Audio Decoder Modes 10-3...
Page 19 Preface This book is the primary reference and Technical Manual for the L64105 MPEG-2 Audio/Video Decoder. It contains functional descriptions, I/O signal and register descriptions, and includes complete physical and electrical speciﬁcations for the L64105. Audience This document assumes that you have some familiarity with ISO/IEC 13818, Generic Coding of Moving Pictures and Associated Audio (MPEG-2), microprocessors, and related support devices.
Page 20 Appendix B, Glossary of Terms and Abbreviations Related Publications L64108 MPEG-2 Transport with Embedded MIPS CPU (CW4001) and Control Chip Technical Manual , LSI Logic Corporation, DB14-000039-00. ISO/IEC 13818, Generic Coding of Moving Pictures and Associated Audio (MPEG-2), International Standard . ISO/IEC Copyright Ofﬁce, Case Postal 56, CH1211 Genève 20, Switzerland.
Page 21 1.5 Mbit/s (MPEG-1), International Standard . ISO/IEC Copyright Ofﬁce, Case Postal 56, CH1211 Genève 20, Switzerland. ITU-R BT.601-5 (10/95), Studio Encoding Parameters of Digital Television for Standard 4:3 and Wide-screen 16:9 Aspect Ratios , http://www.itu.ch/publications/itu-r/iturbt.htm. ITU-R BT.656-3 (10/95), Interface for Digital Component Video Signals in 525-line and 625-line Television Systems Operating at the 4:2:2 Level of Recommendation ITU-R BT.601 (Part A) , http://www.itu.ch/publications/itu-r/iturbt.htm.
Page 22 xxii Preface...
Page 23: Chapter 1 Introduction
MPEG-2 decoding systems based on the MPEG-2 algorithm. The device may be considered a “black box” that receives coded audio and video data and produces decoded audio and video data streams. LSI Logic has optimized the L64105 input/output interfaces for low-cost integration into embedded applications.
Page 24: L64105 Overview
Figure 1.1 A Typical L64105 Application L64X08 EBUS L64X08 L64105 NTSC/PAL Baseband Satellite in L647X4 Integrated MPEG-2 Encoder Video QPSK X-PORT Decoder Demod Audio Stereo DACs Audio S/P DIF L64768 Cable in 4 Mbit 16 Mbit Optional Demod DRAM SDRAM 16 Mbit SDRAM The L64105 accepts an 8-bit, parallel channel input from a transport demultiplexer and, with interaction of a host microcontroller,...
Page 25 Figure 1.2 L64105 Decoder Block Diagram L64105 Decoder Video to CH_DATA[7:0] NTSC/PAL Encoder Channel Video Video Microcontroller Interface Decoder Interface DCK (£ 9 MHz) Control Data Address 64-bit Data Bus Buses Host Interface Status Audio Control Address Bus Clocks to DAC Memory SYSCLK Audio...
Page 26 the L64105 address SDRAM as if it were 8-byte wide RAM. The address converter changes these addresses to chip selects, bank selects, and column and row addresses for the SDRAM. The Video Decoder reads the MPEG video elementary stream from the SDRAM buffer, performs postparsing on it, decompresses it, decodes it, and stores it back in SDRAM.
Page 27: Memory Utilization
The L64105 is an MPEG-2 Main Level, Main Proﬁle decoder. It handles image sizes up to 720 x 480 pixels with a frame rate of 30 fps for NTSC and up to 720 x 576 pixels at 25 fps for PAL. It can also decode MPEG-1 sequences.
Page 28: Features
1.3 Features Video Decoder – ♦ Fully compliant to Main Proﬁle at Main Level of the MPEG-2 video standard, ISO 13818-2. ♦ Decodes an MPEG-2 bitstream, including MPEG-2 Program stream, with private stream support. ♦ Decodes an MPEG-1 bitstream as deﬁned in ISO IS 11172, including the MPEG-1 system layer.
Page 29 Audio Decoder – ♦ Processes MPEG audio with support for Linear PCM data. ♦ Decodes dual-channel MPEG audio, Layer I and II ISO 13818-2, supporting bit rates of 8 Kbps to 448 Kbps and sampling rates of 16, 22.05, 24, 32, 44.1, and 48 kHz. ♦...
Page 30 Introduction...
Page 31 Chapter 2 I/O Signal Descriptions This chapter describes the input/output signals of the L64105. The chapter contains the following sections: ♦ Section 2.1, “Signals Organization,” page 2-1 ♦ Section 2.2, “Host Interface,” page 2-3 ♦ Section 2.3, “Channel Interface,” page 2-5 ♦...
Page 32 Figure 2.1 L64105 I/O Signals BUSMODE PD[7:0] CREF A[8:0] BLANK OSD_ACTIVE Video Interface D[7:0] EXT_OSD[3:0] DSn/WRITEn Host Interface READ/READn DTACKn/RDYn CD_ASDATA WAITn CD_BCLK INTRn DREQn CD_LRCLK PREQn CD_ACLK ASDATA AREQn BCLK VREQ LRCLK Audio Interface CH_DATA[7:0] A_ACLK L64105 Channel AUDIO_SYNCn AVALIDn Interface VVALIDn...
Page 33: Host Interface
2.2 Host Interface BUSMODE Host Controller Select Pin Input This pin must be tied to VSS if the host CPU is an Intel processor or to VDD if it is a Motorola processor. The Intel processor uses two separate pins, READn and WRITEn, for read and write transfers.
Page 34 WRITEn - Intel Mode The external host asserts WRITEn to start a write cycle. READn must be HIGH during a write cycle, and CSn must be LOW during a write cycle. The address is registered on the falling edge of WRITEn. The data is latched by the L64105 on the rising edge of WRITEn.
Page 35: Channel Interface
unmasked interrupt condition has occurred in the chip. The host must read registers 0 through 4 to determine the cause of the interrupt, take the appropriate action, and set the Clear Interrupt Pin bit in Register 6 (page 4-10) to deassert INTRn. DREQn DMA Transfer Request Output...
Page 36 CH_DATA[7:0] Channel Data Bus Input The CH_DATA bus is used to transfer 8-bit, parallel bitstreams into the L64105. The maximum transfer rate over this interface is 20 Mbps in worst case conditions. The peak data rate may increase above this rate depending on system SDRAM usage.
Page 37: Memory Interface
2.4 Memory Interface Important: The length of all connections between the L64105 and SDRAM on a PCB layout must be kept as short as possible, must be matched in length and pin load, and the pin load should be less than 50 pF. SCSn SDRAM Chip Select Output...
Page 38: Video Interface
SWEn SDRAM Write Enable Output The Memory Interface asserts SWEn for SDRAM write cycles and holds it deasserted for SDRAM read cycles. SCLK SDRAM 81-MHz Clock Output The 27-MHz SYSCLK input is multiplied by three using the on-chip PLL to generate the 81-MHz SCLK. Important: SCLK should be connected through a 33-Ω...
Page 39: Audio Interface
Horizontal Sync Input HS is the horizontal sync signal from the PAL/NTSC Encoder. HS is used to reset the horizontal counters in the display controller. HS should be synchronous to SYSCLK. Vertical Sync/Odd-Even Field Indicator Input VS is the vertical sync signal from the PAL/NTSC Encoder.
Page 40 BCLK DAC Bit Clock Output Serial data bit clock used by the L64105’s DAC Interface to serialize the decoded audio data and by the external DAC to clock it in on the rising edge. BCLK is derived from one of the ACLK_ inputs under host control in normal modes and is the CD_BCLK input in CD Bypass mode.
Page 41: Miscellaneous And Test Interfaces
SPDIF_IN External S/P DIF Input This input is directly connected to the SPDIF_OUT pin when the host selects the S/P DIF Bypass mode. SPDIF_OUT S/P DIF Output Output IEC958 formatted output of the L64105’s S/P DIF Interface in normal modes and SPDIF_IN in S/P DIF Bypass mode.
Page 42 81-MHz clock for the SDRAM interface. TM[1:0] Test Mode Input These inputs are used by LSI Logic during manufacturing test. They are not exercised in a customer system. They should both be tied to VSS in the system. ZTEST...
Page 43 Chapter 3 Register Summary Communication with the L64105 Decoder is through 512, 8-bit registers. The registers are named by their decimal address, 0 to 511. They are organized into the eight groups listed in Table 3.1. The registers, ﬁelds, and bits in each group are further detailed in Table 3.2 through Table...
Page 44 Table 3.2 Host Interface Registers Default Addr Addr Value Page (Dec) (Hex) Bit(s) (Hex) Status/Command/Data Ref. Decode Status Interrupt Decode Status Mask Aux/User Data FIFO Ready Interrupt Aux/User Data FIFO Ready Mask First Slice Start Code Detect Interrupt First Slice Start Code Detect Mask Sequence End Code Detect Interrupt Sequence End Code Detect Mask SDRAM Transfer Done Interrupt...
Page 45: Host Interface Registers
Table 3.2 Host Interface Registers (Cont.) Default Addr Addr Value Page (Dec) (Hex) Bit(s) (Hex) Status/Command/Data Ref. Begin Vertical Blank Interrupt Begin Vertical Blank Mask SCR Overﬂow Interrupt SCR Overﬂow Mask SCR Compare Interrupt SCR Compare Mask Pack Data Ready Interrupt Pack Data Ready Mask Audio PES Data Ready Interrupt Audio PES Data Ready Mask...
Page 46 Table 3.2 Host Interface Registers (Cont.) Default Addr Addr Value Page (Dec) (Hex) Bit(s) (Hex) Status/Command/Data Ref. Reserved Audio ES Channel Buffer Underﬂow Interrupt Audio ES Channel Buffer Underﬂow Mask Video ES Channel Buffer Underﬂow Interrupt Video ES Channel Buffer Underﬂow Mask –...
Page 47 Table 3.2 Host Interface Registers (Cont.) Default Addr Addr Value Page (Dec) (Hex) Bit(s) (Hex) Status/Command/Data Ref. – VREQ Status 4-10 – Reserved Clear Interrupt Pin (INTRn) 4-10 Reserved Channel Status 4-11 Channel Start/Reset – Reserved Stream Select [1:0] 4-12 SCR Pause Software Reset Reserved...
Page 48 Table 3.2 Host Interface Registers (Cont.) Default Addr Addr Value Page (Dec) (Hex) Bit(s) (Hex) Status/Command/Data Ref. Capture on Pack Data Ready 4-14 Capture on Audio PES Ready 4-15 Capture on Video PES Ready Reserved Capture on DTS Video 4-15 Capture on DTS Audio –...
Page 49 Table 3.3 Video Decoder Registers Default Addr Addr Value Page (Dec) (Hex) Bit(s) (Hex) Status/Command/Data Ref. Reset Aux Data FIFO 4-17 Aux Data FIFO Status [1:0] – Aux Data Layer ID [2:0] 4-18 Reserved Reset User Data FIFO 4-18 User Data FIFO Status [1:0] –...
Page 50: Video Decoder Registers
Table 3.3 Video Decoder Registers (Cont.) Default Addr Addr Value Page (Dec) (Hex) Bit(s) (Hex) Status/Command/Data Ref. 70, 71 46, 47 Reserved – Video ES Channel Buffer Start Address [7:0] 4-22 – Video ES Channel Buffer Start Address [13:8] Reserved –...
Page 51 Table 3.3 Video Decoder Registers (Cont.) Default Addr Addr Value Page (Dec) (Hex) Bit(s) (Hex) Status/Command/Data Ref. – Audio PES Header/System Channel Buffer Start 4-25 Address [7:0] – Audio PES Header/System Channel Buffer Start Address [13:8] Reserved – Audio PES Header/System Channel Buffer End 4-25 Address [7:0] –...
Page 52 Table 3.3 Video Decoder Registers (Cont.) Default Addr Addr Value Page (Dec) (Hex) Bit(s) (Hex) Status/Command/Data Ref. 105– 69–6B – Reserved – Video ES Channel Buffer Read Address [7:0] 4-27 – Video ES Channel Buffer Compare DTS Address 4-28 [7:0] –...
Page 53 Table 3.3 Video Decoder Registers (Cont.) Default Addr Addr Value Page (Dec) (Hex) Bit(s) (Hex) Status/Command/Data Ref. – Audio PES Header/System Channel Buffer Write 4-29 Address [19:16] Reserved 117– 75–77 – Reserved – S/P DIF Channel Buffer Read Address [7:0] 4-30 –...
Page 54 Table 3.3 Video Decoder Registers (Cont.) Default Addr Addr Value Page (Dec) (Hex) Bit(s) (Hex) Status/Command/Data Ref. Video ES Channel Buffer Numitems [15:8] 4-32 – Video Numitems/Pics in Channel Compare Panic [15:8] Video ES Channel Buffer Numitems [18:16 4-32 – Video Numitems/Pics in Channel Compare Panic [18:16] Reserved...
Page 55 Table 3.3 Video Decoder Registers (Cont.) Default Addr Addr Value Page (Dec) (Hex) Bit(s) (Hex) Status/Command/Data Ref. Audio PES Header Enable [1:0] 4-36 System Header Enable [1:0] Pack Header Enable [1:0] 4-37 Reserved Reserved Audio Packet Error Status 4-37 Video Packet Error Status Reserved –...
Page 56 Table 3.4 Memory Interface Registers Default Addr Addr Value Page (Dec) (Hex) Bit(s) (Hex) Status/Command/Data Ref. Host Read FIFO Empty 4-38 Host Read FIFO Full Host Write FIFO Empty Host Write FIFO Full DMA Read FIFO Empty DMA Read FIFO Full DMA Write FIFO Empty DMA Write FIFO Full Reserved...
Page 57: Memory Interface Registers
Table 3.4 Memory Interface Registers (Cont.) Default Addr Addr Value Page (Dec) (Hex) Bit(s) (Hex) Status/Command/Data Ref. Host SDRAM Source Address [18:16] 4-42 Reserved Block Transfer Count [7:0] 4-43 Block Transfer Count [15:8] PLL Test 4-43 Reserved Clk Out of Sync 4-43 Control for Programmable Delay Path 1 Control for Programmable Delay Path 2...
Page 58 Table 3.4 Memory Interface Registers (Cont.) Default Addr Addr Value Page (Dec) (Hex) Bit(s) (Hex) Status/Command/Data Ref. DMA SDRAM Target Address [7:0] 4-46 DMA SDRAM Target Address [15:8] DMA SDRAM Target Address [18:16] Reserved DMA SDRAM Source Address [7:0] 4-46 DMA SDRAM Source Address [15:8] DMA SDRAM Source Address [18:16] Reserved...
Page 59 Table 3.5 Microcontroller Registers Default Addr Addr Value Page (Dec) (Hex) Bit(s) R/W (Hex) Status/Command/Data Ref. – Anchor Luma Frame Store 1 Base Address [7:0] 4-48 – Anchor Luma Frame Store 1 Base Address [15:8] – Anchor Chroma Frame Store 1 Base Address [7:0] 4-48 –...
Page 60: Microcontroller Registers
Table 3.5 Microcontroller Registers (Cont.) Default Addr Addr Value Page (Dec) (Hex) Bit(s) R/W (Hex) Status/Command/Data Ref. Rip Forward Mode Status 4-52 Rip Forward Mode Enable Rip Forward Display Single Step Status 4-53 Rip Forward Display Single Step Command – Current Display Frame [1:0] –...
Page 61 Table 3.5 Microcontroller Registers (Cont.) Default Addr Addr Value Page (Dec) (Hex) Bit(s) R/W (Hex) Status/Command/Data Ref. – Microcontroller PC [7:0] 4-57 – Microcontroller PC [11:8] Reserved – Revision Number [7:0] 4-57 Decode Start/Stop Command 4-57 Reserved – Reserved Reduced Memory Mode (RMM) 4-58 Reserved 249–...
Page 62 Table 3.6 Video Interface Registers Default Addr Addr Value Page Bit(s) (Hex) Status/Command/Data Ref. 256– 100– Reserved OSD Mode [1:0] 4-58 Reserved – OSD Palette Counter Zero Flag 4-59 Clear OSD Palette Counter Display Override Mode [1:0] Force Video Background [1:0] 4-59 Programmable Background Y[7:0] 4-60...
Page 63: Video Interface Registers
Table 3.6 Video Interface Registers (Cont.) Default Addr Addr Value Page Bit(s) (Hex) Status/Command/Data Ref. Host Top Field First 4-62 – First Field – Odd/Not Even Field 4-63 – Top/Not Bottom Field – Last Field 4-63 Horizontal Filter Enable – Horizontal Filter Select –...
Page 64 Table 3.6 Video Interface Registers (Cont.) Default Addr Addr Value Page Bit(s) (Hex) Status/Command/Data Ref. ITU-R BT.656 Mode 4-67 Sync Active Low Reserved Pixel State Reset Value [1:0] 4-67 CrCb 2s Complement 4-68 VSYNC Input Type Reserved – Display Override Luma Frame Store Start Address 4-68 [7:0] –...
Page 65 Table 3.6 Video Interface Registers (Cont.) Default Addr Addr Value Page Bit(s) (Hex) Status/Command/Data Ref. – Main End Row [10:8] 4-70 Reserved – Main Start Column [7:0] 4-70 – Main End Column [7:0] – Main Start Column [10:8] – Reserved –...
Page 66 Table 3.7 Audio Decoder Registers Default Addr Addr Value Page Bit(s) (Hex) Status/Command/Data Ref. – MPEG - bitrate_index [3:0] 4-72 – MPEG - protection_bit 4-73 – MPEG - layer_code [1:0] 4-74 – MPEG - ID – MPEG - copyright 4-74 –...
Page 67: Audio Decoder Registers
Table 3.7 Audio Decoder Registers (Cont.) Default Addr Addr Value Page Bit(s) (Hex) Status/Command/Data Ref. – PCM FIFO Near Full 4-78 – PCM FIFO Full – Audio Decoder Play Mode Status [1:0] – Audio Decoder Soft Mute Status – Audio Decoder Reconstruct Error –...
Page 68 Table 3.7 Audio Decoder Registers (Cont.) Default Addr Addr Value Page Bit(s) (Hex) Status/Command/Data Ref. PCM Scale [7:0] 4-84 ACLK Select [1:0] Invert LRCLK Reserved User 4-85 Valid ACLK Divider Select [3:0] 4-85 LPCM - Dynamic Range On 4-87 Reserved Reserved IEC - Host Emphasis [2:0] 4-87...
Page 69 Table 3.7 Audio Decoder Registers (Cont.) Default Addr Addr Value Page Bit(s) (Hex) Status/Command/Data Ref. Reserved Pd Selection [1:0] 4-90 Host Pc Info [2:0] Host Pd Value [15:8] 4-91 Host Pd Value [7:0] 371– 173– – Reserved for diagnostic use (Sheet 4 of 4) Table 3.8 RAM Test Registers...
Page 70: Ram Test Registers
Table 3.8 RAM Test Registers (Cont.) Default Addr Addr Value Page Bit(s) (Hex) Status/Command/Data Ref. MemTest01 Pass/Fail Status 4-93 MemTest02 Pass/Fail Status MemTest03 Pass/Fail Status 4-93 MemTest04 Pass/Fail Status MemTest05 Pass/Fail Status MemTest06 Pass/Fail Status MemTest07 Pass/Fail Status MemTest08 Pass/Fail Status MemTest09 Pass/Fail Status 4-93 MemTest10 Pass/Fail Status...
Page 71 Table 3.8 RAM Test Registers (Cont.) Default Addr Addr Value Page Bit(s) (Hex) Status/Command/Data Ref. MemTest17 Pass/Fail Status 4-93 MemTest18 Pass/Fail Status MemTest19 Pass/Fail Status MemTest20 Pass/Fail Status MemTest21 Pass/Fail Status MemTest22 Pass/Fail Status MemTest23 Pass/Fail Status MemTest24 Pass/Fail Status MemTest25 Pass/Fail Status 4-93 MemTest26 Pass/Fail Status...
Page 72 Table 3.8 RAM Test Registers (Cont.) Default Addr Addr Value Page Bit(s) (Hex) Status/Command/Data Ref. MemTest37 Pass/Fail Status 4-93 MemTest38 Pass/Fail Status MemTest39 Pass/Fail Status Reserved Overall MemTest Pass/Fail Status 4-93 393– 189– – Reserved (Sheet 4 of 4) 1. Reset after read. 3-30 Register Summary...
Page 73: Alphabetical Listing
3.2 Alphabetical Listing of Register Bits and Fields Numerics 3:2 Pull Down From Bitstream bit 4-62 ACLK Divider Select [3:0] 4-85 ACLK Select [1:0] 4-84 Anchor Chroma Frame Store 1 Base Address [15:0] 4-48 Anchor Chroma Frame Store 2 Base Address [15:0] 4-49 Anchor Luma Frame Store 1 Base Address [15:0] 4-48...
Page 74 Audio Sync Code Read Address [19:0] 4-31 Audio Sync Error Interrupt bit Audio Sync Recovery Interrupt bit Automatic Field Inversion Correction bit 4-65 Aux Data FIFO Output [7:0] 4-19 Aux Data FIFO Status [1:0] 4-17 Aux Data Layer ID [2:0] 4-18 Aux/User Data FIFO Ready Interrupt bit B Chroma Frame Store Base Address [15:0]...
Page 75 Data Pattern to be Applied to RAM [1:0] 4-92 Decode Start/Stop Command bit 4-57 Decode Status Interrupt bit Display Mode [3:0] 4-63 Display Override Luma/Chroma Frame Store Start Addresses [15:0] 4-68 Display Override Mode [1:0] 4-59 Display Start Command bit 4-72 DMA Mode [1:0] 4-39...
Page 76 Horizontal Filter Scale [7:0] 4-64 Horizontal Filter Select bit 4-63 Horizontal Pan and Scan Luma/Chroma Word Offset [7:0] 4-66 Host Category [7:0] 4-89 Host SDRAM Transfer Byte Ordering bit 4-40 Host Force Broken Link Mode bit 4-54 Host Next GOP/Seq Status bit 4-56 Host Overwrite Quantization [1:0] 4-88...
Page 77 Last Field bit 4-63 Linear PCM - dynscalehigh [7:0] 4-83 Linear PCM - dynscalelow [7:0] 4-83 LPCM - Dynamic Range On bit 4-87 Main Reads Per Line [6:0] 4-65 MAIN Start/End Columns [10:0] 4-70 MAIN Start/End Rows [10:0] 4-70 Memory Test Address [11:0] 4-91 Memory Test Output Select bit 4-92...
Page 78 Override Picture Width [6:0] 4-67 Overwrite Category bit 4-88 Overwrite Quantization Enable bit 4-89 Pack Data Ready Interrupt bit Pack Header Enable [1:0] 4-37 Packet Error Interrupt bit Pan and Scan 1/8 Pixel Offset [2:0] 4-65 Pan and Scan Byte Offset [2:0] 4-65 Pan and Scan From Bitstream bit 4-65...
Page 79 Reduced Memory Mode (RMM) bit 4-58 Refresh Extend [1:0] 4-40 Report End of Test bit 4-92 Reset Audio ES Channel Buffer bit 4-20 Reset Audio PES Header/System Channel Buffer bit 4-20 Reset Aux Data FIFO bit 4-17 Reset Channel Buffers on Error bit 4-20 Reset User Data FIFO bit 4-18...
Page 80 User bit 4-85 User Data FIFO Output [7:0] 4-19 User Data FIFO Status [1:0] 4-18 User Data Layer ID [1:0] 4-19 User Mute Bit 4-82 Valid bit 4-85 VCO Test High Freq [15:0] 4-45 VCO Test Low Freq [15:8] 4-47 Vcode Even [7:0] 4-71 Vcode Even [8]...
Page 81 Video Stream Select Enable [1:0] 4-35 VLC or Run Length Error Interrupt bit Vline Count Init [2:0] 4-66 VREQ Status bit 4-10 VSYNC Input Type bit 4-68 Alphabetical Listing of Register Bits and Fields 3-39...
Page 82 3-40 Register Summary...
Page 83 Chapter 4 Register Descriptions This chapter describes the bit and ﬁeld assignments of all of the registers in the L64105. The chapter contains the following sections: ♦ Section 4.1, “Host Interface Registers,” page 4-2 ♦ Section 4.2, “Video Decoder Registers,” page 4-17 ♦...
Page 84 4.1 Host Interface Registers Figure 4.1 Register 0 (0x000) SDRAM Sequence First Slice Aux/User Audio Sync Decode New Field Transfer End Code Start Code Data FIFO Read Recovery Reserved Status Interrupt Done Detect Detect Ready Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Audio Sync SDRAM...
Page 85 First Slice Start Code Detect Interrupt This bit is set when the decoder detects the ﬁrst slice start code after the picture layer. INTRn is asserted unless the host sets the mask bit. Sequence End Code Detect Interrupt This bit is set when the decoder detects a sequence end code.
Page 86 decoder samples the channel read pointers and maintains the audio sync code read address and the picture start code address. These addresses are the current read pointers which are generally 48 addresses higher than the picture start code and 8 addresses higher than the audio sync code (due to the size of the top of channel FIFOs).
Page 87 Begin Vertical Blank Interrupt The Video Interface module sets this bit and asserts INTRn (if not masked) at the beginning of the vertical blanking interval. This time is deﬁned by the Vcode in the Start of Active Video/End of Active Video (SAV/EAV) timing codes programmed into the Video Interface.
Page 88 Audio PES Data Ready Interrupt This bit is set and INTRn is asserted (if not masked) by the preparser when it detects an audio PES packet. This bit is cleared when read. INTRn is not asserted if the host sets the mask bit. Video PES Data Ready Interrupt This bit is set and INTRn is asserted (if not masked) by the preparser when it detects a video PES packet.
Page 89 the INTRn output signal. The interrupt is used for audio/video synchronization. This bit is cleared when read. INTRn is not asserted if the host sets the mask bit. Figure 4.4 Register 3 (0x003) Video ES Audio ES Video ES Audio ES Channel Channel Channel...
Page 90: Register 4 (0X004)
Figure 4.5 Register 4 (0x004) S/P DIF Audio CRC VLC or Run Channel Packet Audio Sync Context or Illegal Bit Length Read Buffer Error Reserved Error Error Error Error Underﬂow Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt S/P DIF Packet Channel Audio CRC VLC or Run Error...
Page 91: Register 5 (0X005)
Reserved [5:4] Set these bits when writing to this register. Packet Error Interrupt This bit is set and INTRn is asserted (if not masked) when the preparser detects an error while processing packet data. When this interrupt occurs, the host should read the Packet Error Status register (page 4-37) to...
Page 92: Register 6 (0X006)
synchronous with the external device clock (DCK), then the Channel Request Mode bit needs to be set. In this mode, the channel internal request is sampled twice, ﬁrst by the rising edge of internal DCK and then by the falling edge of internal DCK, before being sent out as a REQn signal.
Page 93: Register 7 (0X007)
This separate control is provided for systems with priority interrupts since this will allow the driver software to exit the interrupt handler before completion and service higher priority interrupts. While INTRn is still asserted, the interrupt handler returns to the interrupt routine for the L64105 when it is again the highest priority interrupt.
Page 94 Stream Select [1:0] R/W [3:2] The host must program these bits to set up the L64105 for the format of the input bitstream as shown in the following table. Stream Select [1:0] Bitstream Format 0b00 A/V PES Packets 0b01 MPEG-1 System or MPEG-2 Program Stream 0b10 (Not deﬁned)
Page 95: Registers 9–12 (0X009–0X00C) Scr Value [31:0]
Figure 4.9 Registers 9–12 (0x009–0x00C) SCR Value [31:0] Reg. 9 SCR Value [7:0] SCR Value [15:8] Reg. 10 SCR Value [23:16] Reg. 11 Reg. 12 SCR Value [31:24] These registers contain the current value of the System Clock Reference (SCR) Counter. The host must read Register 9, the LSB, ﬁrst. This captures the upper 24 bits and writes them into Registers 10, 11, and 12.
Page 96: Register 17 (0X011)
Figure 4.11 Register 17 (0x011) Capture on Capture on Capture on Capture on Capture on Capture on SCR Compare/Capture Video PES Audio PES Pack Data Audio Sync Picture Start Mode Ready Ready Ready Code Code SCR Compare/Capture Mode [1:0] R/W 1:0 The value of these two bits sets the operating mode of Registers 13, 14, 15, and 16 as shown in the following table.
Page 97: Register 18 (0X012)
Capture on Audio PES Ready R/W 6 When this bit is set and the L64105 is in the Capture Mode, the SCR Counter value is captured and written to Registers 13 through 16 when the preparser detects Audio PES Ready. Capture on Video PES Ready R/W 7 When this bit is set and the L64105 is in the Capture...
Page 98: Registers 20–23 (0X014–0X017 Scr Compare Audio [31:0]
register. This autostart pulse also clears the Audio Start on Compare bit. The Audio Decoder must be in Pause Mode for the autostart signal to be effective. Video Start on Compare R/W 1 When the L64105 is in the Compare Mode, setting this bit generates a single-cycle, autostart pulse to start the Video Decoder when current value of the SCR Counter is equal to the value in the SCR Compare register.
Page 99: Video Decoder Registers
Setting the Channel Bypass Enable bit (bit 3 in Register 5 - page 4-10) allows the host to write data directly to the video channel through this register, bypassing the parallel channel input port. Figure 4.16 Register 29 (0x01D) Audio Channel Bypass Data [7:0] Audio Channel Bypass Data [7:0] Setting the Channel Bypass Enable bit (bit 3 in Register 5 - page...
Page 100: Register 65 (0X41)
Aux Data Layer ID [2:0] R [4:2] The Aux Data Layer ID indicates the layer origin of the physical parameter of the current Aux Data FIFO output. Reading the ID does NOT change the FIFO status. Reading the current byte in the Auxiliary Data FIFO Output register (page 4-19) may change the Aux Data...
Page 101: Register 66 (0X042) User Data Fifo Output [7:0]
User Data Layer ID [1:0] R [3:2] The User Data Layer ID bits indicate the layer origin of the user data or extra data at the current User Data FIFO output. Reading the ID does NOT change the FIFO status. The host should always read this layer ID register before reading the FIGO output register.
Page 102: Register 68 (0X044)
Figure 4.21 Register 68 (0x044) Reset Audio Reset Video Reset Reset Audio Reset Video PES Header/ PES Header Channel Reserved ES Channel ES Channel Reserved System Channel Buffers on Buffer Buffer Channel Buffer Error Buffer Reset Channel Buffers on Error Setting this bit causes the preparser to reset all channel buffers if it detects a packet sync error.
Page 103: Register 69 (0X045)
Figure 4.22 Register 69 (0x045) Enable Video Video Numitems/Pics Panic Enable Audio Read Reserved Read Compare Mode Select Compare DTS Enable Video Read Compare DTS R/W 0 When this bit is set, the Video ES channel buffer read pointer is compared with the Video ES Channel Buffer Compare DTS Address written in Registers 108, 109, and 110 (page...
Page 104: Registers 72 And 73 (0X048 And 0X049 Video Es Channel Buffer Start Address [13:0]
When INTRn is asserted, the host should read Registers 0 through 4 to determine the cause of the interrupt, take the necessary action, and deassert INTRn by setting the Clear Interrupt Pin bit (Register 6, bit 0, page 4-10). Video Numitems/Pics Panic Mode Select [1:0] R/W [4:3] This ﬁeld allows the host to select a “panic”...
Page 105: Registers 74 And 75 (0X04A And 0X04B Video Es Channel Buffer End Address [13:0]
Interface of the L64105 converts the address to an SDRAM address at a 256-byte boundary in SDRAM. This register should only be updated while the channel is stopped (reset). Figure 4.24 Registers 74 and 75 (0x04A and 0x04B) Video ES Channel Buffer End Address [13:0] Reg.
Page 106: Registers 78 And 79 (0X04E And 0X04F Audio Es Channel Buffer End Address [13:0]
Figure 4.26 Registers 78 and 79 (0x04E and 0x04F) Audio ES Channel Buffer End Address [13:0] Reg. 78 Audio ES Channel Buffer End Address [7:0] Reg. 79 Audio ES Channel Buffer End Address [13:8] Reserved These registers allow the host to program the Audio ES channel buffer end address.
Page 107: Audio Pes Header/System Channel Buffer Start Address [13:0]
address. The Memory Interface of the L64105 converts the address to an SDRAM address at a 256-byte boundary in SDRAM. This register should only be updated while the channel is stopped (reset). Registers 84–87 (0x054–0x057) Reserved [7:0] Figure 4.29 Registers 88 and 89 (0x058 and 0x059) Audio PES Header/System Channel Buffer Start Address [13:0] Reg.
Page 108: Registers 96–98 (0X060–0X062 Video Es Channel Buffer Write Address [19:0]
Figure 4.31 Registers 96–98 (0x060–0x062) Video ES Channel Buffer Write Address [19:0] Reg. 96 Video ES Channel Buffer Write Address [7:0] Read Only Video ES Channel Buffer Write Address [15:8] Reg. 97 Read Only Reg. 98 Video ES Channel Buffer Write Address [19:16] Reserved Read Only These registers contain the current write pointer address of the Video ES...
Page 109: Registers 102–104 (0X066–0X068) Video Pes Header Channel Buffer Write Address [19:0]
Figure 4.33 Registers 102–104 (0x066–0x068) Video PES Header Channel Buffer Write Address [19:0] Reg. 102 Video PES Header Channel Buffer Write Address [7:0] Read Only Video PES Header Channel Buffer Write Address [15:8] Reg. 103 Read Only Video PES Header Channel Buffer Reg.
Page 110: Registers 108–110 (0X06C–0X06E) Video Es Channel Buffer Compare Dts Address [18:0]
Figure 4.35 Registers 108–110 (0x06C–0x06E) Video ES Channel Buffer Compare DTS Address [18:0] Reg. 108 Video ES Channel Buffer Compare DTS Address [7:0] Write Video ES Channel Buffer Compare DTS Address [15:8] Reg. 109 Write Video ES Channel Buffer Compare Reg.
Page 111: Registers 111–113 (0X06F–0X071) Audio Es Channel Buffer Compare Dts Address [18:0]
Figure 4.37 Registers 111–113 (0x06F–0x071) Audio ES Channel Buffer Compare DTS Address [18:0] Reg. 111 Audio ES Channel Buffer Compare DTS Address [7:0] Write Audio ES Channel Buffer Compare DTS Address [15:8] Reg. 112 Write Audio ES Channel Buffer Compare Reg.
Page 112: Registers 120–122 (0X078–0X07A S/P Dif Channel Buffer Read Address [19:0]
Figure 4.39 Registers 120–122 (0x078–0x07A) S/P DIF Channel Buffer Read Address [19:0] Reg. 120 S/P DIF Channel Buffer Read Address [7:0] Read Only S/P DIF Channel Buffer Read Address [15:8] Reg. 121 Read Only Reg. 122 S/P DIF Channel Buffer Read Address [19:16] Reserved Read Only These registers contain the current address of the S/P DIF (IEC958)
Page 113: Registers 128–130 (0X080–0X082 Picture Start Code Read Address [19:0]
Figure 4.41 Registers 128–130 (0x080–0x082) Picture Start Code Read Address [19:0] Reg. 128 Picture Start Code Read Address [7:0] Read Only Picture Start Code Read Address [15:8] Reg. 129 Read Only Reg. 130 Picture Start Code Read Address [19:16] Reserved Read Only These registers contain the address of the video channel read pointer captured at the time that a picture start code is decoded from the...
Page 114: Registers 134–136 (0X086–0X088 Video Es Channel Buffer Numitems [18:0]
Figure 4.43 Registers 134–136 (0x086–0x088) Video ES Channel Buffer Numitems [18:0] Reg. 134 Video ES Channel Buffer Numitems [7:0] Read Only Video ES Channel Buffer Numitems [15:8] Reg. 135 Read Only Video ES Channel Buffer Numitems Reg. 136 Reserved [18:16] Read Only These registers contain the number of items (64-bit words) remaining to be read in the Video ES channel buffer.
Page 115: Registers 137–139 (0X089–0X08B Audio Es Channel Buffer Numitems [18:0]
Figure 4.45 Registers 137–139 (0x089–0x08B) Audio ES Channel Buffer Numitems [18:0] Reg. 137 Audio ES Channel Buffer Numitems [7:0] Read Only Audio ES Channel Buffer Numitems [15:8] Reg. 138 Read Only Audio ES Channel Buffer Numitems Reg. 139 Reserved [18:16] Read Only These registers contain the number of items (64-bit words) remaining to be read from the Audio ES channel buffer to the selected Audio Decoder.
Page 116: Register 143 (0X08F)
Figure 4.47 Register 143 (0x08F) Audio Stream Select Enable [2:0] Audio Stream ID [4:0] Audio Stream ID [4:0] W [4:0] This ﬁeld is used to select a particular audio stream in the type enabled by the following Audio Stream Select Enable ﬁeld.
Page 117: Register 144 (0X090)
Figure 4.48 Register 144 (0x090) Transport Reserved Private Stream Audio Transport Private Stream Audio When this bit is cleared, MPEG audio is stored in the Audio ES channel buffer. Always clear this bit when writing to this register. Reserved [7:1] Figure 4.49 Register 145 (0x091) Video Stream Select Enable...
Page 118: Register 147 (0X093)
Video PES Header Enable [1:0] R/W [7:6] The coding of this ﬁeld determines which Video PES headers, if any, are stored and processed. Video PES Header Enable Description 0b00 Write no Video PES headers 0b01 Write one header if PTS or DTS. This mode is reset internally to mode 0b00 above after the successful completion of a write.
Page 119: Register 149 (0X094)
System Header Enable Description 0b00 Always discard 0b01 Write one header. This mode is reset internally back to mode 0b00 on successful completion of write. 0b10 Write all headers 0b11 Always discard Pack Header Enable [1:0] R/W [5:4] The host can conﬁgure these bits to have the L64105 store or not store pack headers as shown in the following table.
Page 120: Memory Interface Registers
Reserved [7:2] Figure 4.52 Registers 150 and 151 (0x096 and 0x097) Pictures in Video ES Channel Buffer Counter [15:0] Reg. 150 Pictures in Video ES Channel Buffer Counter [7:0] Read Only Reg. 151 Pictures in Video ES Channel Buffer Counter [15:8] Read Only These registers allow the host to read the number of pictures currently in the Video ES channel buffer.
Page 121: Register 193 (0X0C1)
Figure 4.54 Register 193 (0x0C1) Host SDRAM DMA Transfer Reserved Refresh Extend [1:0] Transfer Byte DMA Mode [1:0] Reserved Byte Ordering Ordering Reserved Clear this bit when writing to this register. DMA Mode [1:0] R/W [2:1] Deﬁnes the state of the DMA Transfer Request (DREQn) output signal per the following table.
Page 122 transferred to the internal 8 x 64 write FIFO. Note that separate counters and addresses are maintained for host and DMA write operations. The on-chip SDRAM controller continuously empties the write FIFO and transfers the data to the speciﬁed SDRAM target address.
Page 123: Register 194 (0X0C2) Host Sdram Read Data [7:0]
2 (default) 0b01 0b10 0b11 1 (Reserved for LSI Logic internal use only.) DMA SDRAM Transfer Byte Ordering Little Endian/Big Endian This bit must be set if the external DMA controller operates in big endian mode, i.e., with byte 0 in bits [63:56] and byte 7 in bits [7:0].
Page 124: Registers 196–198 (0X0C4–0X0C6 Host Sdram Target Address [18:0]
Figure 4.57 Registers 196–198 (0x0C4–0x0C6) Host SDRAM Target Address [18:0] Reg. 196 Host SDRAM Target Address [7:0] Host SDRAM Target Address [15:8] Reg. 197 Reg. 198 Host SDRAM Target Address [18:16] Reserved For a host write to SDRAM, the host must write the starting SDRAM address in this register.
Page 125: Registers 202 And 203 (0X0Ca And 0X0Cb Block Transfer Count [15:0]
Figure 4.59 Registers 202 and 203 (0x0CA and 0x0CB) Block Transfer Count [15:0] Reg. 202 Block Transfer Count [7:0] Reg. 203 Block Transfer Count [15:8] For an SDRAM block move, the host writes the number of 64-bit words to be moved in these registers. During the move, these registers contain the number of words left to transfer.
Page 126: Register 205 (0X0Cd)
Note that the delays are in units of del05, a delay of 0.5 ns at nominal conditions (nominal process factor, 25 ˚C, and V = + 3.3 V). Control for Programmable Delay Path 2 [1:0] R/W [7:6] This register controls the selection of delay cells on the incoming 81-MHz clock in scan test mode or bypass mode.
Page 127: Register 206 (0X0Ce)
Internal SDRAM State [2:0] R [5:3] Used to monitor the internal SDRAM state (diagnostics only). Bits [5:3] Description 0b000 Waiting for 2 clocks to reach synchronization 0b001 SDRAM initialization (precharge both banks) 0b010 SDRAM Initialization (ﬁrst 8 refreshes) 0b011 SDRAM Initialization (set mode register) 0b100 SDRAM Initialization (second 8 refreshes) 0b101...
Page 128: Registers 213–215 (0Xd5–0X0D7 Dma Sdram Target Address [18:0]
The PLL test interrupts the system clock and should not be attempted when the chip is running. Note: Registers 207 through 212 are included for LSI Logic’s testing purposes. Do not write to the registers without speciﬁc directions from LSI Logic.
Page 129: Register 219 (0X0Db) Dma Sdram Read Data [7:0]
Address should be updated by the host only when the DMA read FIFO is full, allowing a clean ﬂush of the read FIFO. When updating the DMA SDRAM Source Address, it should be written in MSB to LSB order. This triggers the reﬁll of the read FIFO at the new address.
Page 130: Microcontroller Registers
4.4 Microcontroller Registers Figure 4.70 Registers 224 and 225 (0x0E0 and 0x0E1) Anchor Luma Frame Store 1 Base Address [15:0] Reg. 224 Anchor Luma Frame Store 1 Base Address [7:0] Reg. 225 Anchor Luma Frame Store 1 Base Address [15:8] These registers contain the start address of the Anchor Luma Frame Store 1.
Page 131: Registers 230 And 231 (0X0E6 And 0X0E7 Anchor Chroma Frame Store 2 Base Address [15:0]
Figure 4.73 Registers 230 and 231 (0x0E6 and 0x0E7) Anchor Chroma Frame Store 2 Base Address [15:0] Reg. 230 Anchor Chroma Frame Store 2 Base Address [7:0] Reg. 231 Anchor Chroma Frame Store 2 Base Address [15:8] These registers contain the start address of the Anchor Chroma Frame Store 2.
Page 132: Register 236 (0X0Ec)
Figure 4.76 Register 236 (0x0EC) Video Video Skip Frame Read Reserved Continuous Status [1:0] Skip Status Video Video Skip Frame Write Reserved Continuous Mode [1:0] Skip Mode Video Skip Frame Status [1:0] R [1:0] In one-time skip mode (see the description of bit 2 in this register), the microcontroller clears these bits to let the host know that the skip has been completed.
Page 133: Register 237 (0X0Ed)
Video Continuous Skip Mode This bit controls the behavior of the video skip mode. If this bit is set, the video skip mode is continuous, i.e., the decoder continues to skip the selected picture types until the host resets the skip mode to 0b00 (normal play). If this bit is cleared by the host, then the skip is treated as one-time, that is, one picture of the selected type is skipped and the skip mode is reset back to 0b00 or...
Page 134: Register 238 (0X0Ee)
Video Continuous Repeat Frame Mode This bit controls the behavior of the video repeat frame function. When cleared, one frame is repeated and then the Video Repeat Frame Enable bit is cleared by the microcontroller. When this bit is set, frames are repeated continuously until the host clears the Video Repeat Frame Enable bit to end the operation.
Page 135 chroma on page 4-67). When Display Override Mode is active, the host must also specify the Override Picture Width (Register 283, bits [6:0], page 4-67). Pan and Scan from the bitstream must be disabled (bit 6 in Register 279 must be cleared, page 4-65) and pan-scan values (if any) must be supplied by the host.
Page 136: Register 239 (0X0Ef)
Current Decode Frame [1:0] R [5:4] These bits indicate which frame store is being used for reconstruction as shown in the following table. Current Display Frame Description 0b00 Anchor 1 0b01 Anchor 2 0b10 0b11 Reserved Reserved [7:6] Clear these bits when writing to this register. Figure 4.79 Register 239 (0x0EF) Ignore...
Page 137 reconstruction to the point where the picture starts tearing since reconstruction is not able to keep pace with the display. Eliminating the backward vectors reduces the demand made on the SDRAM bandwidth by reducing accesses to the reference anchor store in the SDRAM. This should alleviate any tearing problems.
Page 138: Register 240 (0X0F0)
Reserved Clear this bit when writing to this register. Figure 4.80 Register 240 (0x0F0) Host Next Read Reserved GOP/Seq Status Host Search Write Reserved Next GOP/Seq Command Host Next GOP/Seq Status Indicates the status of the bitstream search described for the following command.
Page 139: Register 242 (0X0F2) Q Table Entry [7:0]
Figure 4.82 Register 242 (0x0F2) Q Table Entry [7:0] Q Table Entry [7:0] Read Only The Q table entry addressed in the previous register is available to the host in this register. Figure 4.83 Register 243 and 244 (0x0F3 and 0x0F4) Microcontroller PC [11:0] Reg.
Page 140: Video Interface Registers
Register 247 (0x0F7) Reserved [7:0] Figure 4.86 Register 248 (0x0F8) Reduced Memory Mode (RMM) Bit Reduced Memory Reserved Mode (RMM) When set, this bit enables the Reduced Memory Mode (RMM) required for PAL resolution (720 x 576). This mode has the capability to use less than one frame store SDRAM memory space for B pictures provided some restrictions are met.
Page 141 Reserved Clear this bit when writing to this register. OSD Palette Counter Zero Flag This bit is set to inform the host that the OSD Palette Counter is cleared to zero. The host should check this bit before starting to write the OSD Palette. Clear OSD Palette Counter When this bit is set, the counter that controls access to the OSD palette is cleared.
Page 142: Registers 266–268 (0X10A And 0X10C Programmable Background Y/Cb/Cr [7:0]
Figure 4.88 Registers 266–268 (0x10A and 0x10C) Programmable Background Y/Cb/Cr [7:0] Programmable Background Y[7:0] Reg. 266 Programmable Background Cb[7:0] Reg. 267 Programmable Background Cr[7:0] Reg. 268 When the Force Video Background Mode (bits 6 and 7 in Register 265) is 0b10, the Y, Cb, and Cr values for the background are speciﬁed in Registers 266, 267, and 268 respectively.
Page 143: Registers 270–273 (0X10E–0X111 Osd Odd/Even Field Pointers [15:0]
Figure 4.90 Registers 270–273 (0x10E–0x111) OSD Odd/Even Field Pointers [15:0] Reg. 270 OSD Odd Field Pointer [7:0] Reg. 271 OSD Odd Field Pointer [15:8] Reg. 272 OSD Even Field Pointer [7:0] Reg. 273 OSD Even Field Pointer [15:8] The host can program the addresses of the OSD Odd/Even Field Pointers into these registers.
Page 144: Register 275 (0X113)
Figure 4.92 Register 275 (0x113) 3:2 Pull Down Top/Not Odd/Not Host Top Host Repeat First Field From Freeze Mode [1:0] Bottom Field Even Field Field First First Field Bitstream Freeze Mode [1:0] R/W [1:0] These bits select the Freeze Mode according to the following table.
Page 145: Register 276 (0X114)
Odd/Not Even Field The display controller sets this bit at the ﬁrst horizontal sync after a vertical sync during an odd ﬁeld. This bit is cleared at the ﬁrst horizontal sync after a vertical sync during an even ﬁeld. Top/Not Bottom Field This bit is set at the ﬁrst horizontal sync after a vertical sync when top-ﬁeld data is being displayed.
Page 146: Register 277 (0X115) Horizontal Filter Scale [7:0]
Table 4.1 Display Mode Selection Table Display Mode [3:0] Parameter 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 Field Structure Picture Frame Structure Picture 16:9 Aspect Ratio 4:3 Aspect Ratio SIF Res. (240/288 lines) Full Res. (480/576 lines) Field Sync Enable R/W 7 When this bit is set, the timing generator syncs to any...
Page 147: Register 278 (0X116)
Figure 4.95 Register 278 (0x116) Reserved Main Reads per Line [6:0] Main Reads per Line [6:0] R/W [6:0] This register is programmed with the number of reads required to construct a scan line for display. The value programmed is the number of pixels ÷ 8. Note that the number of display pixels may differ from main reads per line because of the horizontal interpolation ﬁlter.
Page 148: Register 280 (0X118) Horizontal Pan And Scan Luma/Chroma Word Offset [7:0]
Figure 4.97 Register 280 (0x118) Horizontal Pan and Scan Luma/Chroma Word Offset [7:0] Horizontal Pan and Scan Luma/Chroma Word Offset [7:0] The word number on each scan line on which the display begins. Since the Display Controller supports both positive and negative horizontal pan and scan, this register only needs to apply an offset of up to ±...
Page 149: Register 283 (0X11B)
Figure 4.100 Register 283 (0x11B) Reserved Override Picture Width [6:0] Override Picture Width [6:0] R/W [6:0] This ﬁeld contains the picture width of the override frame store in 8-pixel increments. In other words, this ﬁeld should be programmed with picture width in pixels ÷ 8. This ﬁeld is used only when the Display Override Mode bits (Register 265, bits 4 and 5, page...
Page 150: Registers 285–288 (0X11D–0X120) Display Override Luma/Chroma Frame Store Start Addresses [15:0]
CrCb 2’s Complement R/W 5 When this bit is set, the chroma components are converted to 2’s-complement values with the centers at 0 instead of 128. This is done by effectively inverting the MSB of the Cr and Cb values. VSYNC Input Type R/W 6 When this bit is set, the Vertical Sync pulse is an...
Page 151: Register 290 (0X122)
Number of Segments in RMM [5:0] R/W [6:1] This register can be programmed by the host for the number of memory segments available for B pictures in Reduced Memory Mode (RMM). Each segment can store 8 lines of the picture. The maximum number of segments allowed is 54.
Page 152: Registers 297–299 (0X129–0X12B) Main Start/End Rows [10:0]
Figure 4.105 Registers 297–299 (0x129–0x12B) Main Start/End Rows [10:0] Reg. 297 Main Start Row [7:0] Reg. 298 Main End Row [7:0] Reg. 299 Main End Row [10:8] Main Start Row [10:8] Reserved Reserved MSBs The host can write to these registers to program the start and end row numbers for the Main region on the display.
Page 153: Register 304 (0X130) Vcode Even [7:0]
Vcode Even [8] R/W 5 Most signiﬁcant bit of Vcode Even. See the description in Register 304. Vcode Even Plus 1 R/W 6 In the case of NTSC, the number of offset lines for the Vcode in the odd ﬁeld is one greater than the even ﬁeld. The host can program a one line difference by setting this bit.
Page 154: Audio Decoder Registers
Figure 4.110 Registers 306–308 (0x132–0x134) SAV/EAV Start Columns [10:0] Reg. 306 SAV Start Column [7:0] Reg. 307 EAV Start Column [7:0] Reg. 308 EAV Start Column [10:8] SAV Start Column [10:8] Reserved Reserved MSBs The host can write to these registers to deﬁne the start of SAV and EAV in terms of the number of system clocks from the horizontal sync.
Page 155: Mpeg Bitrate Index Table
Table 4.2 MPEG Bitrate Index Table bitrate_index Layer I Bitrate Layer II Bitrate Layer III Bitrate [3:0] (kbps) (kbps) (kbps) free Not used MPEG - protection_bit MPEG mode protection bit parsed from the bitstream. A 0 bit means that redundancy has been added in the bitstream to facilitate error detection and concealment.
Page 156: Register 337 (0X151)
MPEG - layer_code [1:0] R [6:5] MPEG mode bitstream layer parsed from the bitstream. Indicates the MPEG layer in the bitstream per the following table: layer_code Bits MPEG Layer 0b00 Reserved 0b01 Layer III 0b10 Layer II 0b11 Layer I MPEG - ID MPEG mode ID parsed from the bitstream.
Page 157 Subbands in Intensity mode_extension Bits Stereo 0b00 4 to 31, bound = 4 0b01 8 to 31, bound = 8 0b10 12 to 31, bound = 12 0b11 16 to 31, bound = 16 In Layer III, the mode_extension bits indicate which type of joint_stereo coding method is used per the following table.
Page 158: Register 338 (0X152)
MPEG - private_bit MPEG mode private_bit parsed from the bitstream. This bit is not used by ISO/IEC. MPEG - sampling_frequency [1:0] R [7:6] MPEG mode sampling_frequency parsed from the bitstream per the following table: sampling_ Sampling frequency Bits Frequency (kHz) 0b00 44.1 0b01...
Page 159: Register 351 (0X15F)
Figure 4.115 Register 351 (0x15F) PCM - audio_frm_num [4:0] PCM - num_of_audio_ch [2:0] PCM - num_of_audio_ch [2:0] R [2:0] PCM num_of_audio_ch parameter from Linear PCM bitstream. PCM - audio_frm_num [4:0] R [7:3] PCM audio_frm_num parameter from Linear PCM bitstream. Figure 4.116 Register 352 (0x160) PCM - PCM - Fs [1:0] PCM - quantization [1:0]...
Page 160: Register 354 (0X162)
PCM FIFO Near Full This bit is set when the PCM FIFO is near full, i.e., contains 25 bytes or more of unread data. PCM FIFO Full This bit is set when the PCM FIFO is full. Figure 4.118 Register 354 (0x162) MPEG Audio Multichannel...
Page 161: Register 355 (0X163)
MPEG Multichannel Extension Sync Word Missing This bit is set when the multichannel extension synchronization word can not be found during the decode process of the MPEG audio multichannel bitstream. Reading this bit clears it. Reserved [7:5] Clear these bits when writing to this register. Figure 4.119 Register 355 (0x163) Audio Audio Decoder Play Mode...
Page 162: Register 356 (0X164)
Audio Decoder Start/Stop R/W 7 When this bit is set, the selected audio decoder (MPEG or Linear PCM) starts decoding. Clearing this bit stops the decoder and ﬂushes the data from the Audio ES channel buffer. Figure 4.120 Register 356 (0x164) Audio Audio Formatter Play Mode Formatter...
Page 163: Register 357 (0X165)
Figure 4.121 Register 357 (0x165) Audio Decoder Mode Reserved Select [2:0] Reserved [4:0] Clear these bits when writing to this register. Audio Decoder Mode Select [2:0] R/W [7:5] These bits control the selection of modes that are allowable in the Audio Decoder according to Table 4.3.
Page 164: Register 358 (0X166)
Figure 4.122 Register 358 (0x166) Mute on Error User Mute Bit Reserved Audio Dual-Mono Mode [1:0] Reserved Reserved [1:0] Clear these bits when writing to this register. Audio Dual-Mono Mode [1:0] R/W [3:2] These bits select which audio channel (left/right) the dual-mono data is sent out.
Page 165: Register 359 (0X167) Pcm Fifo Data In [7:0]
Figure 4.123 Register 359 (0x167) PCM FIFO Data In [7:0] PCM FIFO Data In [7:0] The host should issue four consecutive write operations for each pair of PCM samples to be played at the output when the PCM FIFO Mode is enabled (see Audio Decoder Mode Select [2:0] on page 4-81).
Page 166: Register 362 (0X16A) Pcm Scale [7:0]
Figure 4.126 Register 362 (0x16A) PCM Scale [7:0] PCM Scale [7:0] This is an 8-bit, fractional, scale factor for scaling output PCM. PCM Scale = 0x00 mutes the audio output; PCM Scale = 0xFF keeps the output PCM scaled as decoded. Intermediate values (0x01, ..., 0xFE) scale the output PCM by factors of 2/256 to 255/256.The default value of this register is 0xFF.
Page 167: Register 364 (0X16C)
User R/W 6 The value of the User bit to be packed in the IEC958 (S/P DIF) output. The default is 0. Valid R/W 7 The data Valid bit to be packed in the IEC958 (S/P DIF) output. The bit is set when the S/P DIF output is from a formatter in the Audio Decoder and is cleared when the output is from one of the audio decoders.
Page 168: Aclk Divider Select [3:0] Code Deﬁnitions
♦ Case IIA: The Linear PCM bitstream with a sampling frequency of 96 kHz is selected and the external DAC supports 96-kHz sampling frequency. ACLK_48 at a multiple of 512 or 768 must be available and it must be selected. Use divider code 0x5 for ACLK = 768 * 48 or code 0x6 for ACLK = 512 * 48.
Page 169: Register 365 (0X16D)
Table 4.4 ACLK Divider Select [3:0] Code Deﬁnitions (Cont.) ACLK Divider ACLK Select [3:0] Input S/P DIF Interface BCLK DAC Interface BCLK DAC A_ACLK 128 * 32 = ACLK ÷ 6 64 * 32 = ACLK ÷ 12 256 * 32 = ACLK ÷ 3 512 * 48 128 * 32 = ACLK ÷...
Page 170: Register 366 (0X16E)
IEC - Overwrite Copyright R/W 7 When this bit is set, the value in bit 6 of this register is used instead of the copyright value in the bitstream. The default value of this bit is 0. Figure 4.130 Register 366 (0x16E) Formatter Skip Frame Size MPEG Overwrite...
Page 171: Register 367 (0X16F) Host Category [7:0]
Overwrite Quantization Enable R/W 3 When the host sets this bit, the value of the quantization parameter is speciﬁed by the Host Overwrite Quantization bits (bits 1 and 2 in this register]). When this bit is cleared (default), the quantization is as speciﬁed in the bitstream.
Page 172: Register 368 (0X170)
Figure 4.132 Register 368 (0x170) Host Pc Info Pd Selection Reserved Pd Data Valid Reserved Reserved Clear this bit when writing to this register. Pd Data Valid When the Pd Selection bits (3 and 4 in this register) are 0b10 (host force mode) and the host writes a Host Pd Value to Registers 369 and 370, this bit is set.
Page 173: Ram Test Registers
Figure 4.133 Registers 369 and 370 (0x171 and 0x172) Host Pd Value [15:0] Reg. 369 Host Pd Value [15:8] Reg. 370 Host Pd Value [7:0] When the Pd Selection bits (3 and 4 in Register 368) are 0b10 (host force mode), the host must write a Host Pd Value for the Pd ﬁeld in the preamble of the MPEG audio burst into these registers.
Page 174 Operational Mode [1:0] Description 0b00 Normal (no test) 0b01 Host-controlled testing of memories for a single address 0b10 Automated RAM test 0b11 Automated ROM test Report End of Test This bit is cleared by the L64105 at the conclusion of the memory test.
Page 175: Registers 387–392 (0X183–0X188) Memory Test Pass/Fail Status Bits
Figure 4.136 Registers 387–392 (0x183–0x188) Memory Test Pass/Fail Status Bits Reg. 387 MemTest08 MemTest07 MemTest06 MemTest05 MemTest04 MemTest03 MemTest02 MemTest01 Reg. 388 MemTest16 MemTest15 MemTest14 MemTest13 MemTest12 MemTest11 MemTest10 MemTest09 Reg. 389 MemTest24 MemTest23 MemTest22 MemTest21 MemTest20 MemTest19 MemTest18 MemTest17 Reg.
Page 176 4-94 Register Descriptions...
Page 177: Host Interface 5.1 Overview
Chapter 5 Host Interface This chapter describes the host’s interface to the L64105 chip and external SDRAM. Refer to Chapter 7 for a complete description of the interface between the L64105 and external SDRAM. This chapter includes the following sections: ♦...
Page 178: Interface Signals
Figure 5.1 Host Interface Block Diagram L64105 Host Interface Control, Status, and Interrupts To/From Buffer Start and Other End Addresses, Modules A[8:0] Read/Write Pointers SCSn Big/Little Endian D[7:0] SCASn 8-bit SRASn 1 M x 16 Transfer Registers Host SDRAM A[11:0] Write Control FIFO...
Page 179: Motorola Mode Write Timing
Table 5.1 Host Interface Signals (Cont.) Signal L64105 Direction Intel Mode Motorola Mode READ/READn Input READn READ DTACKn/RDYn Output (3-state) RDYn DTACKn WAITn/WTN Output (3-state) WAITn INTRn Output (open drain) INTRn INTRn DREQn Output DREQn DREQn PREQn Output PREQn PREQn Figure 5.2 shows the interface signal timing for a Motorola mode write cycle.
Page 180: Motorola Mode Read Timing
The cycle can be terminated by the L64105 setting DTACKn high or by the host deasserting CSn. When CSn is deasserted, the L64105 3-states its DTACKn output. The Motorola mode read timing is shown in Figure 5.3. The read timing is very similar to that for write.
Page 181: Register Access And Functions
Figure 5.4 Intel Mode Write Timing A[8:0] DTACKn D[7:0] WRITEn (On DSn pin) Figure 5.5 Intel Mode Read Timing A[8:0] DTACKn D[7:0] READn (On DSn pin) 5.3 Register Access and Functions The registers of the L64105 Decoder are accessed when the host places their address (0x000 through 0x1FF) on the A[8:0] input lines of the chip and starts a read or write operation.
Page 182: Scr Registers
When any of the interrupt bits in the ﬁrst few registers are set, the L64105 also asserts the INTRn output signal to the host. The INTRn signal alerts the host to read the interrupt registers to determine the reason for the interrupt and take the necessary action. Any of these interrupts can be masked to prevent the assertion of INTRn for that condition.
Page 183: Operation Of The Scr Counter
In the No Compare and Capture mode, the SCR counter can be read, paused, and loaded by the host through the SCR Value registers. The L64105 only keeps the LSB in Register 9 updated. When the host reads the LSB, the upper three bytes of the counter are captured and written to Registers 10, 11, and 12.
Page 184 In the Capture Mode, the host can select an event in the bitstream to use for capturing the value of the SCR counter. When the preparser in the chip detects the selected event, the SCR counter value is loaded into the SCR Compare/Capture registers.
Page 185: Interrupt Registers
5.3.3 Interrupt Registers In addition to the SCR Compare/Capture events, the L64105 uses other events (single cycle internal pulses occurring at a speciﬁc time) to tell the host when critical items have happened in the decoder. These events are needed in various systems to signal error conditions, channel buffer conditions, A/V sync information, and general data ﬂow through the decoder.
Page 186: Sdram Access
Note that, if an unmasked interrupt/status bit is still set at the time the Clear Interrupt Pin bit is set, INTRn deasserts for 1 clock cycle and then returns to its active state immediately, indicating pending events. The host must read all of the interrupt/status registers prior to setting the Clear Interrupt Pin bit.
Page 187 transfer the 8-byte data block through the registers in big or little endian order by setting or clearing the Host SDRAM Transfer Byte Ordering bit in Register 193 (page 4-39). The L64105 operates in big endian mode, i.e., byte 0 occupies the upper bits of the word and byte 8 occupies the lower bits.
Page 188 5.4.1.2 Host Write The host write operation proceeds similarly to the host read operation. The host begins an SDRAM write operation by setting or clearing the Host SDRAM Byte Ordering bit (if necessary) to change the endian mode and then writing the Host SDRAM Target Address, LSB last. The host can then begin to write bytes to the Host SDRAM Write Data register.
Page 189: Host Read/Write Flowchart
Figure 5.8 Host Read/Write Flowchart Begin Set Host Endian Mode (if needed) 193[3] = Host Endian Read Write Write SDRAM Source Address Write SDRAM Target Address 201[0:2] = [18:16] 198[0:2] = [18:16] 200 = [15:8] 197 = [15:8] 199 = [7:0] 196 = [7:0] (LSB must be set last) (LSB must be set last)
Page 190: Host Dma Sdram Transfers
5.4.2 Host DMA SDRAM Transfers Host DMA transfers to/from SDRAM through the L64105 are supported with the DMA Transfer Request (DREQn) output signal. This signal is asserted to the host during DMA reads when the DMA RdFIFO contains more than one 64-bit word and during DMA writes when the DMA WrFIFO has space left for more than one 64-bit word.
Page 191 5.4.2.1 DMA Read The system can use a dual-address DMA controller with a nonincrementing source address for DMA read operations. For a DMA read (refer to Figure 5.9), the host ﬁrst sets the DMA Mode to Idle to prevent DMA operation until everything is ready. This holds DREQn to the host deasserted.
Page 192 5.4.2.2 DMA Write The DMA SDRAM write operation is very similar to the DMA SDRAM read operation as shown in Figure 5.9. The host sets the DMA Mode to Idle, sets the endian mode if necessary, writes the SDRAM target address into the DMA SDRAM Target Address registers, and sets the DMA Mode to Write.
Page 193: Dma Sdram Read/Write Flowchart
Figure 5.9 DMA SDRAM Read/Write Flowchart Begin Set DMA Mode 193[2:1] = 0b00 Idle Set DMA Transfer Byte Ordering 193[6] = DMA Endian Read Write Write DMA SDRAM Source Address Write DMA SDRAM Target Address 218[2:0] = [18:16] 215[2:0] = [18:16] 217 = [15:8] 214 = [15:8] 216 = [7:0]...
Page 194: Sdram Block Move
5.4.2.3 DMA Bandwidth During DMA, the L64105 can support a bandwidth of a sustained rate of approximately 2.5 Mbytes/sec. During the transfer of data, the rate can increase for short periods of time. 5.4.3 SDRAM Block Move The SDRAM block move, ﬂowcharted in Figure 5.10, allows the host to specify a block of data to be copied from one SDRAM location to another...
Page 195: Block Move Flowchart
Figure 5.10 Block Move Flowchart Begin Set DMA Mode 193[2:1] = 0b00 Idle Write Block Transfer Count 202 = [7:0] / 203 = [15:8] Write DMA SDRAM Source Address 218[0:2] = [18:16] 217 = [15:8] 216 = [7:0] (LSB must be set last) Write DMA SDRAM Target Address 215[0:2] = [18:16] 214 = [15:8]...
Page 196 5-20 Host Interface...
Page 197: Channel Interface 6.1 Overview
Chapter 6 Channel Interface This chapter describes the processing of the system stream through the Channel Interface. It describes how the preparser operates on the input stream, demultiplexes the various components, and writes them to the appropriate buffers in SDRAM. Various methods of handling and recovering from input stream errors are also discussed.
Page 198: System Syntax
as a set of elementary streams that share the same system clock reference and therefore can be decoded synchronously. In MPEG-1, there are only two levels of hierarchy in the system syntax. In MPEG-2, there are four levels of hierarchy in the system syntax. The following table shows the system streams for MPEG-1 and MPEG-2 system syntax.
Page 199: Interface Signals Operation
Figure 6.1 Channel Interface Block Diagram L64105 Decoder Channel Interface CH_DATA[7:0] VREQn Channel Video Channel System AREQn Input Layer Write Preparser Synchronizer FIFO Synchronizer FIFO VVALIDn AVALIDn Buffer (≤ 9 MHz) Controller SYSCLK (27 MHz) D[15:0] 64-bit Data Bus A[11:0] Host 1 M x 16 Memory...
Page 200: Asynchronous Mode
6.2.1 Asynchronous Mode The timing for this mode is shown in Figure 6.2. The decoder asserts the AREQn or VREQn signal when it is ready for more audio or video data. Both the AREQn and VREQn requests are used for elementary streams and A/V PES streams from a transport decoder.
Page 201: Synchronous Validn Inputs
3. The system must respect the function of the AREQn/VREQn signals. The timing restriction above will allow enough space within the input channel FIFO to allow an external synchronizer on the AREQn/VREQn signals. This allows writing data beyond AREQn/VREQn rising edge by 1 byte. 4.
Page 202: Xvalidn Input Synchronization Circuits
Figure 6.3 xVALIDn Input Synchronization Circuits Audio Delayed Data Invert Channel Clock Bit Register 5 CH_DATA[7:0] SYSCLK VVALID_rise_pulse Internal Data AVALID_rise_pulse Pulldown Resistor AVALIDn VVALIDn audio_valid_rise_pulse video_valid_rise_pulse SYSCLK Figure 6.4 Synchronous Valid Signals Timing AVALIDn Int AVALIDn VVALIDn Int VVALIDn CH_DATA The constraints on synchronous valid signal mode are: 1.
Page 203: Synchronous A/Vreqn Outputs
2. It is recommended that the AVALIDn and VVALIDn outputs are registered on the rising edge of DCK (if DCK is in normal mode, i.e., not inverted mode.) 3. The minimum period of DCK must be ≥ 3 Tc (Tc = 1/27 MHz = 37 ns).
Page 204: Channel Bypass Mode
The internal request (int_req) signal is generated by the channel input FIFO controller on the L64105 and indicates available room in the on- chip buffers and the SDRAM channel buffers. The internal request signal is always registered by the L64105 SYSCLK. Normally, A/VREQn signals are asserted even when the channel is stopped to prevent upstream device overﬂow.
Page 205: Preparser
6.3 Preparser For A/V PES and program streams, the Preparser strips the packets of headers and writes the headers and packet data payloads into separate buffer areas in the off-chip SDRAM memory. The host writes the start and end addresses of each of the buffer areas into registers. The internal microcontroller transfers these addresses to the Buffer Controller.
Page 206: Audio Stream Select Enable Bits
Host Registers 143[4:0] store the audio stream ID. This is used in conjunction with the audio stream select enable (Register 143[7:5]) to select which audio stream IDs are selected for decoding. Table 6.3 illustrates the options available in selecting audio streams. Table 6.3 Audio Stream Select Enable Bits Audio Stream...
Page 207: Pack Header Enable Bits
Table 6.4 Pack Header Enable Bits Pack Header Enable Description 0b00 Write no headers. 0b01 Write one header. This mode is reset internally back to mode 0b00 above on successful completion of the write. 0b10 Write all headers. 0b11 Write no headers. The System Header Enable bits in Register 147 (page 4-36) determine...
Page 208: Elementary Streams
Table 6.6 Video PES Header Enable Bits Video PES Enable Description 0b00 Write no video PES headers. 0b01 Write one header if PTS or DTS is present. This mode is reset internally to mode 0b00 above after successful completion of the write.
Page 209: Elementary Stream Buffering
Figure 6.6 Elementary Stream Buffering L64105 SDRAM AREQn Audio ES Audio Channel Elementary Buffer Stream AVALIDn Preparser and Write FIFO VREQn Video Video ES Elementary Channel Stream Buffer VVALIDn The start and end addresses of each of the buffers are programmed by the host in the registers listed in Table 6.8.
Page 210: Pes Packet Structure
Table 6.9 Buffer Write and Read Pointer Registers in ES Mode Pointer Registers Page Ref. Video ES Channel Buffer Write Address 96–98 4-26 Audio ES Channel Buffer Write Address 99–101 4-26 Video ES Channel Buffer Read Address 108–110 4-27 Audio ES Channel Buffer Read Address 111–113 4-28 S/P DIF Channel Buffer Read Address...
Page 211: Pes Packet Structure
Packet Start Code is a string of 23 zeros followed by a logic one. The next byte, the Stream ID, identiﬁes the type of data that is in the packet. The Packet Length ﬁeld speciﬁes the number of bytes following to the end of the packet.
Page 212: Preparsing An Mpeg-1 System Stream
6.3.4 Preparsing an MPEG-1 System Stream In addition to audio and video channel buffers, a System Channel Buffer is allocated in SDRAM for MPEG-1 streams. This buffer is used to hold headers. When the decoder encounters any System Start Code, it synchronizes to that start code, if it is not already in sync.
Page 213: System Pes Channel Buffer Map For Mpeg-1 Streams
The host can subsequently use this value for system synchronization. The Preparser then moves the packet payload into the Audio ES Channel Buffer. The Preparser uses the Packet Length ﬁeld in the packet header to determine the end of the audio data payload. If the stream ID is a video stream, the Preparser skips any packet stufﬁng bytes and moves the remainder of the packet header into the System Channel Buffer.
Page 214: Preparsing A Program Stream
The only error that the Preparser can detect is a mismatch between the packet length ﬁeld and the next packet start code. If this occurs, the Preparser generates an interrupt and optionally clears the buffers. For a complete description of the MPEG-1 system stream syntax, the reader is referred to ISO/IEC 11172 .
Page 215: System Channel Buffer Map For Program Streams
The structure of a PES packet is shown in Figure 6.7. A description of MPEG-2 program syntax can be found in ISO/IEC 13818-1 . Figure 6.10 is the map of the System Channel Buffer for program streams. Stufﬁng bits are added to the end of the headers to round out the last word to 64 bits if necessary.
Page 216: Audio Es Channel Buffer Map For Linear Pcm Audio
The Audio ES Channel Buffer can contain any of the following audio streams: 1. Linear PCM audio 2. MPEG-1 audio 3. MPEG-2 audio Figure 6.11 shows the mapping of Linear PCM information in the Audio ES Channel Buffer. Figure 6.11 Audio ES Channel Buffer Map for Linear PCM Audio 64-bit Sync Code (4C 53 49 4C 4F 47 49 43) Length (16 bits) PCM Audio Data 1 (Includes audio frame information...
Page 217: Error Handling In Program Streams
Figure 6.12 Audio ES Channel Buffer Map for MPEG Audio ‘ MPEG-1 or MPEG-2 Audio ES Data 1 MPEG-1 or MPEG-2 Audio ES Data 2 MPEG-1 or MPEG-2 Audio ES Data 3 MPEG-1 or MPEG-2 Audio ES Data 4 Figure 6.13 shows the Video ES Channel Buffer.
Page 218 6.3.6.1 System Header Error Check Point: All header data (except the start code and packet length ﬁeld) Description: If the ERRORn signal is asserted during the processing of header data, the error data is stored as normal and the Preparser starts the search for the next start code.
Page 219 MPEG-2 – Error Check Point: After start code, zero packet length, and packet data Description: If the ERRORn signal is asserted during the start code, the whole packet is skipped and the Preparser resynchronizes to the next start code. If the ERRORn signal is asserted during packet data, the Packet Error Interrupt bit in Register 4 (page 4-9) is set, and INTRn is asserted if the...
Page 220: Preparsing A/V Pes Packets From A Transport Stream
6.3.6.5 Linear PCM Audio Stream Error Check Point: Packet data and packet length in the ﬁrst byte of packet data Description: If there are syntax errors in the packet length ﬁeld (zero packet length), the Preparser searches for the next start code and resynchronizes to it.
Page 221: Error Handling In A/V Pes Mode
The payloads of transport packets that contain PES data are presented over the parallel channel interface. The AVALIDn or VVALIDn strobe indicates the type of the elementary stream. For Audio PES streams, the Preparser stores the PES header in the Audio PES Header Channel Buffer, INTRn is asserted if not masked, and the Audio PES Data Ready Interrupt bit in Register 2 (page...
Page 222 6.3.8.1 Transport MPEG-1 Audio Error Check Point: Start codes, header data, and packet data Description: If the ERRORn signal is asserted during the start code, the Preparser skips the whole packet and resynchronizes to the next start code. If there are syntax errors during the header data, the Packet Error Interrupt bit is set, INTRn is asserted if the interrupt is not masked, and the remainder of the packet after the error is skipped.
Page 223: Channel Buffer Controller
6.3.8.4 Transport MPEG-2 Video Error Check Point: Start codes, zero packet length, and packet data Description: If the ERRORn signal is asserted during the start code, the whole packet is skipped and the Preparser resynchronizes to the next start code. If zero packet length is detected (transport mode is an exception), the packet data until the next start code is stored.
Page 224: Buffer Reset
6.4.1 Buffer Reset Each of the buffers can be reset on an individual basis, i.e., without affecting the other buffers. Resetting a buffer returns its read and write pointers to the buffer start address. A buffer is reset when the host sets the corresponding bit in Register 68 (page 4-20).
Page 225: In The Video Channel
In the case of audio, the host can select the read pointer for the Audio Decoder or the S/P DIF Formatter by setting the Enable Audio Read Compare bits in Register 69 so that synchronization can be maintained against either one. When the compare produces a match, INTRn is asserted if not masked and the DTS Audio Event Interrupt bit (page 4-6)
Page 226: Summary
6.5 Summary The operation of the Channel Interface is summarized in the ﬂowchart in Figure 6.15 for MPEG-1 streams and MPEG-2 program streams, and in Figure 6.16 for A/V PES streams from transport demultiplexers. Figure 6.15 MPEG-1/MPEG-2 Channel Interface Operation Start Search for Start Code Preﬁx Read Stream ID...
Page 227: A/V Pes Mode Channel Interface Operation
Figure 6.16 A/V PES Mode Channel Interface Operation Start Sync & Search Start Code Get Stream ID Stream ID = Stream Enable PES Enable Store if MPEG Video & ID Check Check Enable Skip Packet Private Read Stream 1? Substream ID LPCM Audio Linear...
Page 228 6-32 Channel Interface...
Page 229 ♦ Section 7.7, “Summary,” page 7-12 7.1 Overview The L64105 MPEG-2 Audio/Video Decoder has a dedicated memory interface which is used for buffering the input channel data stream, video frame storage during decode and display, and storing OSD graphics information. The interface includes a 16-bit data bus and a 12-bit multiplexed row/column address bus operating at 81 MHz to commodity SDRAMs.
Page 230: Sdram Conﬁgurations
The Memory Interface contains Byte Enable Logic and an Address Converter. The Byte Enable Logic converts the internal 8-byte words to 2-byte SDRAM words and vice versa. The Address Converter converts the 19-bit internal addresses to chip selects SCSn and SCS1n, and multiplexed, 12-bit, row/column addresses.
Page 231: Sdram Timing And Modes
♦ Page Break Penalty = 6 to 7 cycles (81 MHz) ♦ Memory capacity: 16 or 32 Mbit using one or two 1M x 16 bit chips Typical SDRAM devices are the Samsung KM416S1120A or NEC µPD4516161. The SDRAM interface uses a CAS latency of 3 and a burst length of 4. The 4-word burst provides high bandwidth transfer from the SDRAM 16-bit bus to the internal 64-bit bus.
Page 232: Sdram Timing Requirements For Reads
refresh modes. For exact timing, refer to the SDRAM vendor’s data sheet. Table 7.1 NEC’s 16 Mbit Synchronous DRAM (Burst Length = 2) Parameter act0 - act1 act - r/w pre - act act - pre ref - ref/act CAS Latency Time (ns) –...
Page 233: Sdram Refresh And Arbitration
The number of refreshes per macroblock is set by the Refresh Extend bits in Register 193 (page 4-40). The default setting of 2 refreshes per macroblock is sufﬁcient. More refreshes are excessive and the setting of 1 is for LSI Logic internal use only. SDRAM Refresh and Arbitration...
Page 234: Memory Channel Buffer Allocation
SDRAM arbitration is controlled by the internal microcontroller of the L64105. This microcontroller controls the functional units needed to decode MPEG video syntax. It is critical for the decoder to carefully control SDRAM access in order to ensure that the picture can be decoded in the available processing time.
Page 235 Table 7.2 Example NTSC SDRAM Allocation (Cont.) Item Size (bytes) System Header channel 3 Video Frame stores 1,555,200 OSD storage area optional The area consumed by the channel buffering is deﬁned in ISO/IEC 13818 . There are a number of items that affect the size of the channel buffering needed in a system.
Page 236: Channel Buffer Architectures
The third item requiring additional channel buffering is caused by the use of a slave mode pixel interface to the NTSC/PAL encoder. In this system conﬁguration, the decoder is locked to the external VSYNC and cannot start decoding at a channel start until the next VSYNC arrives. This results in a decode start delay of up to one ﬁeld time or 20 ms in a PAL system.
Page 237: Memory Frame Store Allocation
7.6 Memory Frame Store Allocation The SDRAM space allocated for video frame stores is dependent upon the operating mode of the device and the largest picture size expected in the bitstream. The size of the frame store cannot be altered while the video decoder is running.
Page 238: Normal Mode
number of chroma lines in 4:2:0 source data. Hence, the chroma frame store requires only half the area of the luma frame store. The three operating modes and the area consumed is described below. Figure 7.6 Chroma Frame Store Organization Word 0 Line 1 Word 1...
Page 239: Reduced Memory Mode (Rmm)
7.6.4 Reduced Memory Mode (RMM) This mode of operation is used in PAL systems and allows a partial frame store for decoding and displaying B frames. A complete description of this mode is given in Section 9.7, “Reduced Memory Mode.” This mode has some restrictions deﬁned in MPEG.
Page 240: Summary
Equation 7.5 With Chroma Field Repeat Display Mode × × Chroma Frame Store Memory Pixel Width Line Height 2 The following example shows the space consumed by the display B frame store in a PAL system. The example uses 44 segments with a Chroma Line Repeat Display mode.
Page 241 Table 7.4 Example NTSC SDRAM Allocation with Frame Store (720 x 480) (Cont.) Item Size (bytes) Anchor Chroma Frame Store 1 172,800 Anchor Luma Frame Store 2 345,600 Anchor Chroma Frame Store 2 172,800 B Luma Frame Store 345,600 B Chroma Frame Store 172,800 Decode Overﬂow + Other Usage Optional...
Page 242 7-14 Memory Interface...
Page 243 Chapter 8 Video Decoder Module This chapter describes the operation of the Video Decoder Module in the L64105. The chapter contains the following sections: ♦ Section 8.1, “Overview,” page 8-1 ♦ Section 8.2, “Postparser Operation,” page 8-4 ♦ Section 8.3, “Video Decoder Pacing,” page 8-24 ♦...
Page 244 A block diagram of the Video Decoder Module is shown in Figure 8.1. The module includes a Channel Read FIFO, Postparser, IDCT Pipeline, and the Auxiliary and User Data FIFOs and their controller. The microcontroller is also included since it decodes for the Postparser and controls most of the data transfers.
Page 245: Video Decoder Block Diagram
is also useful in the situation where channels are switched. The channel switch time can be decreased by increasing the number of sequence start codes in the bitstream. Figure 8.1 Video Decoder Block Diagram L64105 Decoder Video Decoder CH_DATA[7:0] MPEG Channel Table IDCT...
Page 246: Postparser Operation
8.2 Postparser Operation As mentioned, the Postparser separates the bitstream into its individual bits, ﬁelds, and picture blocks and steers them to other modules in the Video Decoder. Table 8.1 through Table 8.10 list all of the header parameters in a sequence, shows their format, and indicates their disposition by the Postparser.
Page 247 Table 8.1 Sequence Header Processing (Cont.) Parameter constrained_ bslbf parameters_ﬂag load_intra_ uimsbf quantizer_matrix if (load_intra_ quantizer_matrix) intra_quantizer_ 8 * 64 uimsbf matrix[64] load_non_intra_ uimsbf quantizer_matrix if (load_non_intra_ quantizer_matrix) non_intra_quantizer_ 8 * 64 uimsbf matrix[64] (Sheet 2 of 2) 1. bslbf = bit stream left bit ﬁrst; uimsbf = unsigned integer, most signiﬁcant bit ﬁrst 2.
Page 248: Sequence Extension
8.2.2 Sequence Extension Table 8.2 shows the actions the decoder takes for each of the parameters present in the Sequence Extension. Table 8.2 Sequence Extension Processing Parameter extension_start_code A[31:0] 32 bslbf (PscB5) extension_start_code_ B[3:0] uimsbf identiﬁer proﬁle_and_level_ C[7:0] uimsbf C7 C6 C5 C4 C1 C0 indication progressive_sequence...
Page 249: Sequence Display Extension
8.2.3 Sequence Display Extension Table 8.3 shows the actions the decoder takes for each of the parameters present in the Sequence Display Extension. Table 8.3 Sequence Display Extension Processing Parameter extension_start_code_ A[3:0] uimsbf identiﬁer (0x2) video_format B[2:0] uimsbf B1 B0 color_description C[0] uimsbf...
Page 250: Group Of Pictures Header
8.2.4 Group of Pictures Header Table 8.4 shows the actions the decoder takes for each of the parameters present in the Group of Pictures Header. Table 8.4 Group Of Pictures Header Processing Parameter group_start_code bslbf (PscB8) time_code A[24:0] 25 bslbf closed_gop uimsbf broken_link...
Page 251: Picture Header
8.2.5 Picture Header Table 8.5 shows the actions the decoder takes for each of the parameters present in the Picture Header. Table 8.5 Picture Header Processing Parameter picture_start_code bslbf (Psc00) temporal_reference A[9:0] uimsbf picture_coding_type B[2:0] uimsbf vbv_delay C[15:0] uimsbf C15 C14 C13 C12 C11 C10 C9 if (picture_coding_ type==2 || picture_coding_type...
Page 252 Table 8.5 Picture Header Processing (Cont.) Parameter while (nextbits() ==’1’) { extra_bit_picture /* 1*n uimsbf with the value 1 */ extra_information_ I[7:0] 8*n uimsbf picture extra_bit_picture /* uimsbf with the value 0 */ (Sheet 2 of 2) 1. bslbf = bit stream left bit ﬁrst; uimsbf = unsigned integer, most signiﬁcant bit ﬁrst 8-10 Video Decoder Module...
Page 253: Picture Coding Extension
8.2.6 Picture Coding Extension Table 8.6 shows the actions the decoder takes for each of the parameters present in the Picture Coding Extension. Table 8.6 Picture Coding Extension Processing Parameter extension_start_code bslbf (PscB5) extension_start_code_ A[3:0] uimsbf identiﬁer f_code[0][0] B[3:0] uimsbf B3 B2 f_code[0][1] C[3:0]...
Page 254 Table 8.6 Picture Coding Extension Processing (Cont.) Parameter composite_display_ﬂag uimsbf if (composite_display_ﬂag) v_axis uimsbf ﬁeld_sequence S[2:0] uimsbf sub_carrier uimsbf burst_amplitude U[6:0] uimsbf U6 U5 U4 U3 U2 sub_carrier_phase V[7:0] uimsbf V4 V3 V2 (Sheet 2 of 2) 1. bslbf = bit stream left bit ﬁrst; uimsbf = unsigned integer, most signiﬁcant bit ﬁrst 8-12 Video Decoder Module...
Page 255: Quant Matrix Extension
8.2.7 Quant Matrix Extension Table 8.7 shows the actions the decoder takes for each of the parameters present in the Quant Matrix Extension. Table 8.7 Quant Matrix Extension Processing Parameter extension_start_code_identiﬁer A[3:0] uimsbf (0x3) load_intra_quantizer_matrix uimsbf n if (load_intra_quantizer_matrix) intra_quantizer_matrix[64] 8 * 64 uimsbf n load_non_intra_quantizer_matrix uimsbf n...
Page 256: Host Access Of Q Table Entries
8.2.8 Host Access of Q Table Entries The host can read the intra and nonintra quant matrix values that are stored in the Q table in the L64105 for the current decode process. The quant matrix values may be the default values or they may have been provided by the bitstream in the sequence header or in the quant matrix extension.
Page 257: Picture Display Extension
8.2.9 Picture Display Extension Table 8.8 shows the actions the decoder takes for each of the parameters present in the Picture Display Extension. Table 8.8 Picture Display Extension Processing Parameter extension_start_ A[3:0] uimsbf code_identiﬁer (0x7) for (i=0; i<number_of_ frame_center_ offsets;i++) { frame_center_ B[15:0] 16 * n simsbf B15 B14 B13 B12 B11 B10...
Page 258: Number Of Frame Center Offsets
Table 8.9 Number of Frame Center Offsets Progressive Picture Top Field Repeat First Number of Frame Sequence Bit Structure First Bit Field Bit Display Order Center Offsets frame bottom ﬁeld, top ﬁeld frame bottom, top, bottom ﬁeld frame top, bottom ﬁeld frame top, bottom, top ﬁeld top ﬁeld...
Page 259: Copyright Extension
8.2.10 Copyright Extension Table 8.10 shows the actions the decoder takes for each of the parameters present in the Copyright Extension. Table 8.10 Copyright Extension Processing Parameter extension_ A[3:0] uimsbf start_code_ identiﬁer (0x4) copyright_ﬂag bslbf copyright_ C[7:0] uimsbf identiﬁer original_or_ bslbf copy reserved...
Page 260: User Data
8.2.11 User Data User data is written to the User Data FIFO, which is separate from the Auxiliary Data FIFO. The Group of Pictures (GOP) User Data Only bit in Register 239 (page 4-55) controls the user data processing. When this bit is cleared, user data of all layers is written to the User Data FIFO as shown in Table...
Page 261: Auxiliary Data Fifo Operation
8.2.14 Auxiliary Data FIFO Operation The Auxiliary Data FIFO is used to store certain header parameters required by the system controller or host. The FIFO operates as a 128-byte-deep circular buffer. The various registers associated with the Auxiliary Data FIFO are listed in Table 8.12 and described in the text following.
Page 262: Aux Data Fifo Status
Table 8.13 Aux Data FIFO Status Bits 64[1:0] Status 0b00 Empty 0b01 Data ready 0b10 Full 0b11 Overrun The status changes from empty to data ready as soon as the ﬁrst byte is written into the FIFO. Once overrun (0b11) occurs, the status remains at overrun until the host reads the register, and then changes to full until a byte is written in or read out.
Page 263: User Data Fifo Operation
When the ﬁrst data byte is written to the FIFO, it is placed in the Aux Data FIFO Output register. At the same time, the Postparser writes the layer ID of the data byte into the Auxiliary Data Layer ID ﬁeld of Register 64 (see Table 8.14).
Page 264: User Data Fifo Registers
Table 8.15 User Data FIFO Registers Register Bit(s) R/W Name Page Ref. Aux/User Data FIFO Ready Interrupt Aux/User Data FIFO Ready Mask First Slice Start Code Detect Interrupt First Slice Start Code Detect Mask Reset User Data FIFO 4-18 [1:0] User Data FIFO Status 4-18 [3:2]...
Page 265 The status changes from empty to data ready as soon as the ﬁrst byte is written into the FIFO. Once overrun (0b11) occurs, the status remains at overrun until the host reads the register, and then changes to full until a byte is written in or read out.
Page 266: Video Decoder Pacing
Table 8.17 User Data Layer ID Assignments User Data Layer ID [1:0] MPEG Layer 0b00 sequence 0b01 Group of pictures 0b10 Picture 0b11 Slice When the host writes a 1 to bit 0 of Register 65, the read and write pointers of the User Data FIFO are reset and the FIFO’s status goes to empty.
Page 267: Channel Start/Reset And Status Bits
The channel start command causes the Preparser to start accepting data from the external channel interface device. For details on how to control the location of the video channel in SDRAM memory and on selecting the proper stream ID, the reader is referred to Chapter 6, “Channel Interface,”...
Page 268: Video Decoder Start/Stop
8.3.2 Video Decoder Start/Stop The actual start of decoding should be delayed from the start of the channel. This is done to allow the Video ES Channel Buffer to ﬁll to a sufﬁcient level so that there is no underﬂow/overﬂow of the buffer while actually reconstructing pictures.
Page 269 As soon as the Video Decoder acknowledges the Decode Start Command, it starts parsing the payload data in the Video ES Channel Buffer and sets the Decode Status Interrupt bit in Register 0 (page 4-2). This causes the INTRn signal to the host to be asserted if it is not masked for this interrupt.
Page 270: Time Line For Frame Picture
Figure 8.2 Time Line for Frame Picture Reconstruction Display Channel Start Picture Start Code TIME Picture Start Code Picture Start Code Sequence Start Code Sequence Extension Picture 1 Start Code Picture 1 Extension Picture 1 Slice 1 Start Code DISPLAY START VSYNC BAV Interrupt HOST DECODE START...
Page 271: Time Line For Field Picture
Figure 8.3 Time Line for Field Picture Reconstruction Display Channel Start Picture Start Code TIME Picture Start Code Picture Start Code Sequence Start Code Sequence Extension Picture 1 Field 1 Start Code Picture 1 Field 1 Extension Picture 1 Field 1 Slice 1 Start Code DISPLAY START VSYNC BAV interrupt...
Page 272: Frame Store Modes
8.4 Frame Store Modes This section describes how frame stores are organized in the available modes. Frame stores are maintained in the external SDRAM. The Video Decoder decodes macroblocks from the Video ES Channel Buffer and writes them to the frame stores as reconstructed pictures. Depending on the bitstream, there are three store modes: ♦...
Page 273: Frame Store Organization In Normal Mode
Figure 8.4 Frame Store Organization in Normal Mode Frame Store A1 Frame Store A2 Frame Store A3 Luma Luma Luma Chroma Chroma Chroma TIME Decode (A1) (A2) (A3) (A3) (A1) (A3) (A3) (A2) P... Display (A1) (A3) (A3) (A2) (A3) (A3) (A1) (VSYNC pulses)
Page 274: Reduced Memory Mode
The start addresses of frame stores A1, A2, and A3 are programmed by the host using the registers listed in Table 8.18. Table 8.18 Frame Store Base Address Registers Frame Store Address Register Page Ref. Anchor Luma Frame Store 1 Base Address [7:0] 4-48 Anchor Luma Frame Store 1 Luma Base Address [15:8] Anchor Chroma Frame Store 1 Base Address [7:0]...
Page 275 Total Lines Min NumSegments ---------------------------- - Total Lines ≤ ≤ ---------------------------- - 1 Max Num Segments 54 – For a full-size PAL image, the minimum number of segments is 40. If sufﬁcient SDRAM memory is available, the recommended number of segments for adequate performance is 44.
Page 276: Two-Frame Store Mode
Display modes 4 and 5 above use Chroma Field Repeat. To achieve these modes, the chroma component of the B pictures should be allocated a full frame store even though the luma component uses less than a full frame store in RMM. Thus the chroma component effectively does not use reduced memory mode if the display mode is set to 4 or 5.
Page 277: Trick Modes
The Current Decode Frame bits are updated after the last ﬁeld of the currently displayed frame starts displaying. The Current Display Frame bits are updated at the ﬁrst vertical sync pulse indicating the start of display of the ﬁrst ﬁeld in the frame. Note: The Current Display Frame bits are not valid in the Display Override mode.
Page 278 the host clears either bits [1:0] or bit 2. If the host clears bit 2, one more frame is skipped and the internal microcontroller clears bits [1:0]. All three bits are read/write so the host can check the current skip mode status.
Page 279: Single Skip With And Without Display Freeze
Figure 8.5 Single Skip with and without Display Freeze Case 1: One-time skip B picture - no freeze Decode Skip Display VSYNC Case 2: One-time skip B picture causing display freeze Decode Skip Display VSYNC Note: ♦ F = First ﬁeld. ♦...
Page 280: Repeat Frame
8.5.2 Repeat Frame The repeat frame feature is controlled by two bits in Register 237 (page 4-51). When the host clears the Video Continuous Repeat Frame Mode bit (bit 1) and sets the Video Repeat Frame Enable bit (bit 0), the Video Encoder repeats the last ﬁeld of the frame currently being decoded twice.
Page 281: Frame Repeat Modes
Figure 8.6 Frame Repeat Modes Single Repeat Decode Host set repeat Repeat cleared by decoder Display VSYNC Continuous Repeat Decode Host set continuous repeat Host clear continuous repeat Display VSYNC Note: ♦ F = First ﬁeld. ♦ L = Last ﬁeld. Trick Modes 8-39...
Page 282: Channel Buffer Underﬂow Panic Repeat
8.5.3 Channel Buffer Underﬂow Panic Repeat When this feature is enabled and the decoder detects that the Video ES Channel Buffer is in danger of underﬂowing, it automatically freezes the display on the last ﬁeld of the currently displaying picture. The freeze is automatically removed when the channel buffer has ﬁlled to an adequate level.
Page 283 The Rip Forward Mode is intended to be used in applications where not every picture that is decoded needs to be displayed. The picture to be displayed is speciﬁed in separate registers. These registers are read by the Video Interface. See the Display Override Mode bits in Register 265 (page 4-59) and the Override Display Start Address in Registers 285, 286, 287, and 288...
Page 284: Setting Up Rip Forward/Display Override Command
Figure 8.7 Setting Up Rip Forward/Display Override Command Case 1: Normal Play Decode P1(A2) P2(A1) P3(A2) P4(A1) P5(A2) P6(A1) P7(A2) P8(A1) Display VSYNC Case 2: Display every other anchor picture P1(A2) P2(A1) P3(A2) P4(A1) P5(A2) P6(A1) P7(A2) Rip forward single step cleared by decoder Rip Forward Single Step Host set rip forward single step Rip Forward Enable...
Page 285: Force Broken Link
8.5.5 Force Broken Link The L64105 automatically skips all B pictures before the ﬁrst I picture in an open Group of Pictures (GOP) if the Broken Link bit in the bitstream is set. The host can force this feature in an open GOP regardless of the bitstream broken-link bit by setting the Host Force Broken Link Mode bit in Register 239 (page...
Page 286 display happen to coincide. When the decoder is set for Rip Forward Mode, the internal automatic rate control is turned off since the intention is to reconstruct pictures as fast as possible. Figure 8.8 shows examples when rate control is applied on B picture and on anchor picture reconstruction.
Page 287: Automatic Rate Control
Figure 8.8 Automatic Rate Control Case 1: Rate control on B picture decoding Decode (A1) (A2) (A3) (A3) (A1) (A3) (A3) (A2) Display (A1) (A3) (A3) (A2) (A3) (A3) (A1) VSYNC automatic_rate_control_on Case 2: Rate control on anchor picture decoding Decode (A1) (A2)
Page 288: Sequence End Processing
Figure 8.9 Using Force Rate Control in Rip Forward Mode P1(A2) P2(A1) P3(A2) P4(A1) P5(A2) P6(A1) P7(A2) Rip forward single step cleared by decoder Rip Forward Single Step Host set rip forward single step Rip Forward Mode Enable Display Override Enable I0(A1) P2(A1) P4(A1)
Page 289: Example Of Sequence End Processing
Figure 8.10 Example of Sequence End Processing Case 1: New sequence arrives right away Decode Seq End Display VSYNC Case 2: New sequence arrives late Decode Seq End Display VSYNC Case 3: Low rate single still picture Decode Seq End Seq End Seq End Display...
Page 290: Error Handling And Concealment
Frame I3 of the new sequence gets decoded but has to be kept in the frame store until the ﬁrst ﬁeld of frame P6 is decoded. So, the Video Decoder repeats frame P2. In case 2, the new sequence does not arrive until some time after the sequence end code, so frame P2 has to be repeated several times.
Page 291: Error Conditions Detected
8.6.1 Error Conditions Detected The following error conditions can be detected by the Video Decoder: 1. Variable Length Code (VLC) in error. 2. Context error, i.e., a parameter in the bitstream that is not consistent with the context or an illegal value in the bitstream. 3.
Page 292 8-50 Video Decoder Module...
Page 293 Chapter 9 Video Interface This chapter describes the operation of the Video Interface of the L64105 Decoder. It includes a description of how to program it for proper operation, and an overview of the operation of the Vertical and Horizontal Postprocessing Filters.
Page 294 9.1 Overview The Video Interface is shown in the block diagram of Figure 9.1. It includes postprocessing ﬁlters, mixers, and display control timing. The Video Interface relies on a two-ﬁeld display system operating with a 27-MHz pixel clock. The L64105 outputs 4:2:2 component video compatible with the ITU-R BT.601 format, allowing data to be time- division multiplexed onto an eight-bit bus.
Page 295: Video Interface Block Diagram
Figure 9.1 Video Interface Block Diagram L64105 Decoder Video Interface VS, HS, Timing Generator 27 MHz Video to Display NTSC/PAL Mixer Control Encoder Vertical Horizontal Horizontal Address Interpolation Letterbox Decimation Generator Filter Filter Filter CH_DATA[7:0] Video Channel Microcontroller ≤ 9 MHz Interface Decoder DCK (...
Page 296: Television Standard Select
9.2 Television Standard Select To simplify programming, a Television Standard Select ﬁeld in Register 290 (page 4-69) is provided. The ﬁeld can be coded by the host for the modes shown in Table 9.1 Table 9.1 Television Standard Select Field TV Standard Select Description 0b00 User Programmed (default)
Page 297: Display Areas
Table 9.2 Television Standard Select Default Values Parameter Register[Bits] NTSC Page Ref. Main Reads Per Line[6:0] 278[6:0] 4-65 Vline Count Init[2:0] 282[2:0] 4-66 Pixel State Reset Value [1:0] 284[4:3] 4-67 Main Start Row[10:0] 299[2:0], 297[7:0] 4-70 Main End Row[10:0] 299[6:4], 298[7:0] Main Start Column[10:0] 302[2:0], 300[7:0] 4-70...
Page 298: Display Areas Example
Figure 9.2 Display Areas Example VSYNC H_CNT HSYNC Line Active Display Area Main The Display Controller includes counters for counting the horizontal offset and the vertical offset from the new ﬁeld timing. The horizontal offset is measured in device clocks from the HS, while the vertical offset is measured as a line offset from the new ﬁeld timing.
Page 299: Vertical Timing
Therefore, the host must also program the required number of Main Reads per Line from the frame store in Register 278 (page 4-65). This value is the number of frame store pixels to be read divided by eight since there are eight luma bytes in an SDRAM burst. For example, if the source image is SIF resolution (352 pixels in width) and the target image is full resolution (720 pixels in width), the required main reads per line is equal to 352/8 = 44.
Page 300: Vertical Timing Vcodes And Fcodes For Ntsc
Figure 9.3 Vertical Timing Vcodes and Fcodes for NTSC FCODE: VCODE (verical blanking) LINE = 1 INIT = LINE 4 Blanking V = 1 VCODE ZERO = LINE 21 - [V = 0] MAIN START = LINE 23 - [V = 0] F = 0 Active Video (main)
Page 301: Vertical Timing Vcodes And Fcodes For Pal
Figure 9.4 Vertical Timing Vcodes and Fcodes for PAL FCODE: VCODE (vertical blanking) LINE = 1 - [V = 1] INIT = LINE 1 Blanking V = 1 VCODE ZERO = LINE 21 MAIN START = LINE 23 - [V = 0] F = 0 Active Video (main)
Page 302: Horizontal Timing
9.3.2 Horizontal Timing Figure 9.5 illustrates the timing of the horizontal and vertical sync inputs. The polarity of the VS and HS inputs on which the L64105 reacts is programmable with the Sync Active Low bit in Register 284 (page 4-67).
Page 303: Horizontal Input Timing
Figure 9.6 Horizontal Input Timing SYSCLK HCNT PEL State Horizontal Start Column The horizontal start column refers to the left edge of the display area. A start column and end column must be programmed for main video. Only a start column needs to be programmed for SAV and EAV codes. The L64105 should be programmed such that each start column coincides with a Cb pel state.
Page 304: Video Background Modes
Figure 9.7 Horizontal Timing for 8-Bit Digital Transmission for NTSC H = 1 H = 1 H = 0 H = 0 H = 1 Blanking Active Line (Cb, Y, Cr, Y) Blanking Next line 1440 MAIN START = 244 MAIN END = 1683 H = 1 COLUMN = 1...
Page 305: Still Image Display
When the Force Video Background bits are set to No Background, the active display area that is not occupied by the main display area assumes the color black (Y = 16, Cb = Cr = 128). Usually, the main display covers the entire active display area, except when displaying small images or during letterbox ﬁltering.
Page 306: Luma And Chroma Frame Store Format
Table 9.4 Override Display Registers Function/Parameter Register/Field Page Ref. DMA DRAM Target Address [18:0] 213–215 4-46 DMA DRAM Write Data [7:0] 4-47 DMA Mode [1:0] 193[2:1] 4-39 Display Override Luma Frame Store Start Address 285 and 286 4-68 [15:0] Display Override Chroma Frame Store Start 287 and 288 Address [15:0] Host Top Field First bit...
Page 307 Next, the host must set the Display Override Luma and Chroma Frame Store Start Addresses. These are the DMA SDRAM Target addresses the host used for the two stores or the Luma and Chroma Base Addresses for a decoded picture. In addition to the address pointers, the host must also program the width of the image using the Override Picture Width ﬁeld.
Page 308: Display Modes And Vertical Filtering
9.6 Display Modes and Vertical Filtering To fully understand the display modes and their effects on picture quality, the following terminology should be understood. ♦ A Progressive Frame is a frame in which all of the data represents one instance in time. This is based on the encoded bitstream, not the display system.
Page 309: Display Mode Selection Table
Table 9.5 Display Mode Selection Table Display Mode [3:0] Parameter 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB Field Structure Picture Frame Structure Picture 16:9 Aspect Ratio 4:3 Aspect Ratio SIF Resolution (240/288 lines) Full Resolution (480/576 lines) The following display modes are provided for vertically interpolating SIF resolution images to full resolution:...
Page 310 ♦ Display Mode 10 (0xA) - Interlaced Luma Repositioning/Interlaced Chroma Repositioning. Both the luma and chroma data is treated as interlaced. The odd lines of the frame store are used to interpolate the top ﬁeld, while the even lines of the frame store are used to interpolate the bottom ﬁeld.
Page 311: Reduced Memory Mode
♦ Display Mode 7 - Interlaced Luma/Interlaced Chroma with Repositioning. Both the luma data and chroma data are treated as interlaced. The chroma data is ﬁltered using the bilinear chroma ﬁlter to improve the chroma positioning. This display mode is suited for either ﬁeld- or frame-structured pictures.
Page 312: Horizontal Postprocessing Filters
Since the ﬁrst ﬁeld is not available after it has been displayed, RMM cannot fully support all of the freeze modes. In RMM, only Freeze Last Field is supported on B pictures because the second ﬁeld of data is overwritten in memory. In addition, when performing pulldown the second ﬁeld, instead of the ﬁrst ﬁeld, is repeated during the display of B-frames.
Page 313: Frequency Response A
Note that response A has a slightly higher cut-off frequency and provides a slightly sharper image. Response B has less ripple in the passband and provides more uniform brightness on complex patterns. Figure 9.9 Frequency Response A Frequency Response 0.025 0.05 0.075 0.15...
Page 314: Frequency Response B
Figure 9.11 Frequency Response B Frequency Response 0.025 0.05 0.075 0.125 3.14 Phase -3.14 Figure 9.12 Impulse Response B Impulse Response 0.05 -0.05 -0.1 The scale factor of the interpolator is the ratio between the widths of the source image and the target image in 1/256th of a pixel increments. The interpolator calculates the subpixel position to within 1/256th of a pixel and chooses one of the eight ﬁlter banks closest to the calculated location.
Page 315: On-Screen Display
where means to round the value x to the smallest integer larger than x. A value of zero in the Horizontal Filter Scale register (Register 277, page 4-64) is equivalent to an increment of 256. The raster mapper increment value is sampled at the new ﬁeld boundary to allow the host to change the scale factor between ﬁelds.
Page 316: Osd Modes
The OSD controller supports three basic image formats: ♦ Up to 720 x 576 pixels at 2 bits/pixel ♦ Up to 720 x 576 pixels at 4 bits/pixel ♦ Up to 720 x 576 pixels at 8 bits/pixel 9.9.1 OSD Modes The host can select the OSD mode by setting the OSD Mode bits in Register 265 (page...
Page 317: Osd Area Data Organization
Figure 9.13 OSD Area Data Organization SDRAM Word 0 SDRAM Word 1 SDRAM Word 2 SDRAM Word 3 OSDA STARTR ENDR OSDA STARTC OSDA ENDC Color 0 Color 1 Color 2 Color 3 Color 4 Color 5 Color 6 Color 7 Color 8 Color 9 Color 10...
Page 318: Osd Header Control Fields
9.9.2.2 Header Control Information The layout of the control information in the OSD header is shown in Figure 9.14. Figure 9.14 OSD Header Control Fields SDRAM Word 0 SDRAM Word 1 0 15 12 11 10 HIC[1] OSDA[5:0] STARTR[8:0] MIX[3:0] ENDR[8:0] SDRAM Word 2 SDRAM Word 3...
Page 319: Osd Header Color Fields
MIX[3:0] Mix Weight Word 1 [15:12] The value written into MIX[3:0] sets the mix ratio between the foreground (overlay) pixels and the background (reconstructed picture) pixels in increments of 1/16 of the pixel value. If Mix Weight is zero, the output pixel is weighted 100% reconstructed picture and 0% OSD.
Page 320 Reserved This bit should be cleared. Mix Enable If set, the Mix Weight ﬁeld applies to this color; otherwise, the output data is 100% OSD. Cb[3:0] Color Difference Y-B [7:4] Y-B color difference value with ITU-R BT.601 chromaticity. This value is multiplied by 16 before being used by the OSD controller.
Page 321: Osd Storage Formats
Figure 9.16 OSD Storage Formats Contiguous OSD OSD Odd Field Pointer OSD Even Field Pointer Header Header Bitmap Data Bitmap Data for Area 1 for Area 1 Frame 1 Frame 1 Header Header Bitmap Data Bitmap Data for Area 2 for Area 2 Frame 1 Frame 1...
Page 322 9.9.2.5 Bits/Pixel Modes The OSD Controller reads the OSD data from the SDRAM frame stores and displays it at a rate of one pixel every two L64105 clocks. Using 6 bits for Y, and 4 bits each for Cb and Cr, the OSD color palette can contain any of 16,384 colors including black and transparent.
Page 323: External Osd
9.9.2.7 OSD Requirements The following list of requirements must be met to program OSD areas: ♦ The OSD header MUST be word aligned in SDRAM. ♦ The OSD header should NOT include a row or column number that is out of range of the current display parameters, EXCEPT in the Termination Header.
Page 324: Pan And Scan Operation
Before switching to external OSD mode, the host loads the color palette information into the CLUT by ﬁrst setting the Clear OSD Palette Counter bit in Register 265 (page 4-58) to reset the CLUT address pointer and then writing 32 consecutive bytes to the OSD Palette Write register (Register 269, page 4-60).
Page 325: Host Controlled Pan And Scan
The pan and scan offset can either be controlled by the host or automatically with values extracted from the bitstream. The host can set or clear the Pan and Scan from Bitstream bit in Register 279 (page 4-65) to specify the source of the pan and scan controls. 9.10.1 Host Controlled Pan and Scan When the Pan and Scan from Bitstream bit is cleared, the host controls pan and scan and must program the registers listed in...
Page 326 The horizontal scale and main reads/line values are used for interpolating the horizontal display size up to the 720 pixels, and should be updated at the sequence boundary. The pan and scan offset values are used to display the desired portion of the reconstructed frame store. Unlike the pan and scan offset values embedded in the bitstream, an offset value of zero corresponds to the top-left pixel in the reconstructed frame store image, NOT the center of the image.
Page 327: Bitstream Controlled Pan And Scan
Figure 9.17 Horizontal Pan and Scan Calculation Display Image Reconstructed Image hps = (hs - hds)/2 - hor Note: ♦ hs = horizontal size extracted from sequence header. ♦ hds = horizontal display size extracted from sequence display extension. ♦ hor = horizontal picture offset extracted from picture display extension.
Page 328: Display Freeze
9.11 Display Freeze The host can write to the Freeze Mode bits of Register 275 (page 4-62) to select one of the three freeze modes listed in Table 9.10. Table 9.10 Freeze Modes Freeze Mode Bits Freeze Mode 0b00 Normal (no freeze) 0b01 Freeze Frame 0b10...
Page 329: Freeze Operation Timing
Figure 9.18 Freeze Operation Timing Odd/Even Normal Sequence Freeze Frame Freeze Last Field Freeze 1st Field & Hold Freeze Mode Normal Freeze Active Normal The Freeze Mode bits are sampled at the ﬁeld boundaries. However, only freeze requests issued before the ﬁrst ﬁeld in the frame are applied to the frame.
Page 330: Pulldown Operation
9.12 Pulldown Operation The 3:2 Pulldown from Bitstream bit in Register 275 (page 4-62) defaults to the set state at power-up or reset of the L64105. This causes the internal microcontroller to use the top ﬁeld ﬁrst and repeat ﬁrst ﬁeld bits in the picture coding extension of the bitstream.
Page 331: Video Output Format And Timing
Figure 9.19 Pulldown Operation Timing Odd/Even Normal Sequence 3:2 Pulldown Host Top Field First Host Repeat First Field 9.13 Video Output Format and Timing Output timing of video and control signals is shown in Figure 9.20. The Video Interface outputs 8-bit video compatible with 4:2:2 ITU-R BT.601 format.
Page 332: Display Controller Interrupts
Figure 9.20 Video and Control Output Timing SYSCLK PXL DATA 0x10 CREF BLANK 9.14 Display Controller Interrupts The Display Controller sets two interrupt bits in response to ﬁeld timing, the Begin Active Video Interrupt bit and Begin Vertical Blank Interrupt bit, both in Register 1 (page 4-4).
Page 333 Chapter 10 Audio Decoder Module This chapter describes the operation of the L64105 Audio Decoder. The Audio Decoder processes two different audio input bitstreams, Linear PCM and MPEG (MUSICAM). It also includes two output interfaces, a serial DAC interface, and a IEC958 S/P DIF interface. This chapter contains the following sections: ♦...
Page 334: Audio Decoder Overview
♦ Linear PCM Decoder – Decodes 1 or 2 channels. Higher channel data is discarded. – Sampling Frequencies (Fs) = 48 kHz or 96 kHz (96 kHz is decimated to 48 kHz for the IEC958 S/P DIF interface output). – Quantization accuracy: 16, 20, or 24 bits.
Page 335: Audio Decoder Modes
Table 10.1 Audio Decoder Modes Mode Bits [2:0] DAC Output S/P DIF (IEC958) Output 0b000 MPEG decoder MPEG decoder output PCM samples con- verted to IEC958 format 0b001 Reserved 0b010 MPEG Decoder MPEG Formatter 0b011 Reserved 0b100 Linear PCM Decoder Linear PCM Decoder NOTE: If the sample frequency in the Linear PCM bitstream is 96 kHz, then the IEC958...
Page 336: L64105 Audio Decoder Block Diagram
Figure 10.1 L64105 Audio Decoder Block Diagram L64105 Decoder CH_DATA[7:0] Channel Video Video Microcontroller Interface Decoder Interface DCK (27 MHz) 64-bit Data CD_ASDATA Host CD_BCLK Address Interface CD_LRCLK CD_ACLK Bypass Audio Decoder ASDATA BCLK LRCLK MPEG A_ACLK Decoder Interface Linear PCM Decoder BCLK From...
Page 337 Each audio frame in MPEG and Linear PCM streams starts with a sync word and contains a ﬁxed number of bytes. Once instructed to start, the audio decoder looks for the ﬁrst sync word and starts to decode immediately after detecting it. However, the decoder does not go into “in sync”...
Page 338: Decoding Flow Control
In the PCM FIFO mode, the host writes decoded PCM audio bytes into a FIFO through a register in the Host Interface. According to the mode selected, the outputs of the appropriate decoder and formatter and the PCM FIFO are steered through the two multiplexers to the DAC and S/P DIF interfaces.
Page 339: Audio Decoder Start/Stop
guarantee that the channel read pointer will stop at the end of a frame, decoder resynchronization is required when the mode is changed again. A prolonged audio pause will cause the Audio ES Channel Buffer to overﬂow and the system parser to deassert the channel request signals, stopping video as well as audio.
Page 340: Audio Formatter Play Mode
Once the decoder is stopped, the host should set the play mode bits to Pause Mode. On restart, the host should ﬁrst set the start bit, wait for some unread audio to accumulate in the channel buffer, and then change the play mode bits from pause to play.
Page 341: Autostart
10.3.5 Autostart The selected audio decoder and the formatter can be autostarted at a speciﬁed System Reference Clock (SCR) count. The registers associated with autostart are listed in Table 10.2. Table 10.2 Audio Autostart Registers Name Register/Bits Page Ref. SCR Compare/Capture Mode 17 bits 0 and 1 4-14 SCR Compare Audio...
Page 342: Mpeg Audio Decoder
10.4 MPEG Audio Decoder The L64105 MPEG Decoder supports Layer I and Layer II of the MPEG-1 audio compression and MPEG-2 low bit rate decoding. For MPEG-2 multichannel audio streams, the L64105 decodes the left and right channels and ignores the others. 10.4.1 MPEG Audio Syntax The basic MPEG audio bitstream syntax is shown in Figure...
Page 343: Mpeg Audio Bitstream Syntax
Figure 10.2 MPEG Audio Bitstream Syntax Frame Frame Frame Frame 384 Samples (Layer I), 1152 Samples (Layer II) Header Audio Data (4 bytes) (2 bytes) Sync word (12 bits) Layer I Data ID (1 bit) Layer (2 bits) Allocate 4 bits Scale factors, 6 bits Samples of 2 Protection (1 bit)
Page 344: Mpeg Audio Decoding
10.4.2 MPEG Audio Decoding MPEG audio encoding is performed by transforming the input signals from the time domain to the frequency domain and dividing them into 32 frequency subband samples. The subband samples are then quantized, normalized, and encoded using a variable length encoding scheme. For decoding, this process is reversed.
Page 345: Mpeg Audio Decoding Flow
Figure 10.3 MPEG Audio Decoding Flow Begin Bitstream Parsing Decoding of Bit Allocation Decoding of Scale Factors Reconstruction of Samples Synthesis Subband Filter Output PCM Samples MPEG Audio Decoder 10-13...
Page 346: Linear Pcm Audio Decoder
10.5 Linear PCM Audio Decoder Linear PCM is a high-ﬁdelity audio coding technique. Unlike MPEG, Linear PCM is not lossy compressed so that decoders can achieve high- quality audio reproduction. 10.5.1 Packet Header Syntax As shown in Figure 10.4, every Linear PCM pack contains a pack header, a packet header, a private data section, and audio data.
Page 347: Valid Linear Pcm Stream Permutations
Table 10.3 Valid Linear PCM Stream Permutations Number of Sampling Frequency Quantization Maximum Number of Data Size Channels (kHz) (Bits) Samples in One Pack (Bytes) 1 (mono) 48 / 96 1004 2008 48 / 96 2010 48 / 96 2010 2 (stereo) 48 / 96 2008...
Page 348: Synchronization
10.5.2 Synchronization The Preparser in the Channel Interface substitutes the original substream Linear PCM ID with an 8-byte sync word to mark the beginning of each Linear PCM packet. The Linear PCM Decoder searches for and synchronizes to the sync word. If the decoder loses synchronization, it sets the Audio Sync Error Interrupt bit in Register 4 (page 4-8), asserts INTRn to the host if the interrupt is not masked,...
Page 349 If the data in the Linear PCM bitstream does not agree with the options available, the decoder sets the Context Error Interrupt bit in Register 4 (page 4-8), asserts INTRn to the host if the interrupt is not masked, mutes the audio output, and searches for the next sync word. Dynamic Range Control is a compressed gain value that should be applied to all the samples in an audio frame.
Page 350: Other Host Controls And Status
10.5.3 Other Host Controls and Status The bitstream mute, emphasis, quantization, and sampling frequency information is written to Register 352 (page 4-77) for the host. The audio_frm_num and num_of_audio_ch are written to Register 351. When the mute bit in the audio packet is 1, PCM samples are muted by the output DAC and S/P DIF interface.
Page 351: Mpeg Formatter
Figure 10.6 Linear PCM Output Ports PCM port (96/48 kHz) Linear PCM Decoder DAC Interface (48 or 96 kHz) Decimation S/P DIF Interface Filter (48 kHz) S/P DIF port (48 kHz) 10.6 MPEG Formatter The L64105 MPEG Formatter formats the following audio bitstreams into IEC958 format: ♦...
Page 352: Syntax Of The Mpeg Data In Iec958 Format
Figure 10.7 Syntax of the MPEG Data in IEC958 Format IEC958 Data Burst Payload Padding Preamble MPEG Data Frames All 0s Note: Padding is all zeros until the end of each IEC958 frame. The preamble values for the MPEG formatter supported bitstream are given in Table 10.4.
Page 353: Number Of Iec958 Frames When Formatting Mpeg Data
10.6.1 Number of IEC958 Frames when Formatting MPEG Data The size of the IEC958 data burst differs according to the type of the incoming MPEG bitstream being fed to the MPEG Formatter. This is explained in detail in Table 10.5. Table 10.5 IEC958 Frame Sizes Supported in MPEG Audio Formatter...
Page 354: Pause Burst
The host can program the value of the Pd ﬁeld in the burst preamble by ﬁrst programming the Pd Selection bits in Register 368 (page 4-90). Table 10.6 shows the Pd Selection bit codes for this mode and two other modes.
Page 355: Inserting Pause Bursts In The Mpeg Formatter Output
Figure 10.9 Inserting Pause Bursts in the MPEG Formatter Output Burst A Burst A Burst B Burst B Pause Pause MPEG Data Continued MPEG Data Continued Burst A Burst B Burst C Pause Pause MPEG Data MPEG Data MPEG Data Discontinue Discontinue Burst A...
Page 356: Synchronization
10.6.4 Synchronization The MPEG Decoder and MPEG Formatter can run simultaneously. The formatter automatically detects when it is out of synchronization with the decoder and recovers by either waiting for the decoder or by skipping ahead of the currently processed data. The wait or skip operation is performed only at MPEG data frame boundaries.
Page 357: Mpeg Audio Formatter Error Handling
Table 10.8 MPEG Audio Formatter Error Handling Error Action Output Incorrect sync word Search for the next sync word. a_sync_error = 1 Pause with Pc bits 8–12 = 0x0.0001 Illegal table entry Search for the next sync word. a_illegal_bit = 1 Pause with Pc bits 8–12 = 0x0.0001 User pause Start Pause bursts and wait until user...
Page 358: Pcm Fifo Mode
10.7 PCM FIFO Mode The host can write four-byte, L-R PCM samples (two bytes for each channel) into the PCM FIFO and select these values to play through the Linear PCM Decoder. The registers associated with PCM FIFO mode are listed in Table 10.9.
Page 359: Dac Interface
10.8 DAC Interface The DAC Interface in the Audio Decoder converts the 16-, 20-, or 24-bit parallel PCM data received from the decoders into 32-bit, serial frames and transmits them to the external DAC. A demultiplexer controlled by the Audio Decoder Mode Select bits in Register 357 (page 4-81) selects the output of one of the three decoders or the PCM FIFO as the DAC...
Page 360: Dac Output Mode: Pcm Sample Precision = 20 Bit
Figure 10.11 DAC Output Mode: PCM Sample Precision = 20 Bit BCLK LRCLK (Invert LRCLK=0) Right PCM Left PCM Right PCM Left PCM LRCLK (Invert LRCLK=1) Right PCM Left PCM Right PCM Left PCM ASDATA S L19 S R19 R18 (Twelve sign extension bits) (Twelve sign extension bits) Note: S means sign-extension (0 for positive PCM values, 1 for negative PCM values).
Page 361 The ASDATA bits are clocked out on every BLCK falling edge. The A_ACLK is the DAC clock and is at 256 or 384 times the sample frequency depending on the DAC used. Note: Some DACs have an on-chip Phase-Locked Loop (PLL) to derive their operating clock from the incoming bit clock.
Page 362: Biphase Mark Coding
Section 10.9.2, “IEC958 Syntax.” The output demultiplexer selects either the output of the interface or the SPDIF_IN when the host selects the S/P DIF Bypass Mode. 10.9.1 Biphase Mark Coding To minimize the DC component on the transmission line, facilitate clock recovery from the bitstream, and make the interface insensitive to the polarity of connection, the bitstream is encoded in biphase marks.
Page 363: Iec958 Syntax
The layout of the subframes is also shown in Figure 10.14. Each subframe starts off with a 4-bit (8-state) preamble. The preamble is coded to mark the ﬁrst frame in a block, to differentiate between subframes in a frame, and to violate the biphase mark rule twice. This latter feature prevents other data in the stream from mimicking a preamble.
Page 364: Iec958 Channel Status
10.9.3 IEC958 Channel Status The L64105 uses the ﬁrst 32 C bits of each channel in each block to carry the four bytes of channel status information shown in Figure 10.15. The remaining C bits in the blocks are cleared to 0. The Copyright and Emphasis bits are from the incoming bitstream.
Page 365 32, 44.1, and 48 kHz sampling rates. The inputs to these must be the sampling rate times N, where N can be 256, 384, 512, or 768. The N value must be an integral multiple of the sample resolution (16, 20, or 24).
Page 366: Aclk Divider Select [3:0] Code Deﬁnitions
♦ Case IIB: The Linear PCM bitstream with a sampling frequency of 96 kHz is selected but the external DAC does not support 96-kHz sampling frequency. ACLK_48 must be available and it must be selected. Set the Audio Decoder Mode Select ﬁeld (Register 357, bit [7:5], page 4-81) to 0b101 to decimate the output samples to...
Page 367 Section 11.2, “AC Timing,” page 11-4 ♦ Section 11.3, “Pinouts and Packaging,” page 11-18 Note: All speciﬁcations are for the L64105 in LSI Logic’s 3.3-V, ® 0.25-micron G10 -p process technology and are subject to change. AC timing has been simulated and not characterized.
Page 368: Absolute Maximum Ratings
Table 11.1 Absolute Maximum Ratings Symbol Parameter Limits Unit − 0.3 to + 3.9 DC Supply − 1.0 to + 6.5 5 V Compatible Input Voltage ± 10 DC Input Current − 40 to + 125 Storage Temperature Range ˚C STGM 1.
Page 369: Dc Characteristics
Table 11.4 DC Characteristics Unit Symbol Parameter Condition Voltage Input Low – – CMOS – – 0.2 V Voltage Input High – – CMOS 0.7 V – – 5 V Compatible – Voltage Output Low 4-mA Output Buffers = 4.0 mA –...
Page 370: Ac Test Load And Waveform For Standard Outputs
11.2 AC Timing This section presents AC timing information for the L64105 MPEG-2 Audio/Video Decoder. The timing diagrams in this section illustrate the clock edges and speciﬁc signal edges from which the timing parameters are measured. These diagrams do not imply any other timing relationships.
Page 371: Ac Test Load And Waveform For 3-State Outputs
Figure 11.2 AC Test Load and Waveform for 3-State Outputs Test = 20 mA Point 2.4 V 2.4 V Output = 0.5 V 0.4 V 0.4 V 50 pF = −20 mA AC Timing is organized by interface and shown in the following tables and ﬁgures: ♦...
Page 372: Sdram Interface Ac Timing
Table 11.5 SDRAM Interface AC Timing Parameter Description Units SCSn Setup SCSn Hold SRASn Setup SRASn Hold SCASn Setup SCASn Hold SWEn Setup SWEn Hold Read Data Setup Read Data Hold Address Valid Address Hold SCLK Cycle Tc – SCLK Duty Cycle 0.45 Tc 0.55 Tc Write Data Setup...
Page 373: Sdram Read Cycle
Figure 11.3 SDRAM Read Cycle read0 act1 read1 pre0 81 MHz SCSn SRASn SCASn SWEn DQ(15:0) A(10:0) AC Timing 11-7...
Page 374: Sdram Write Cycle
Figure 11.4 SDRAM Write Cycle write0 act1 write1 pre0 81 MHz SCSn SRASn SCASn SWEn DQ(15:0) A(10:0) 11-8 Speciﬁcations...
Page 375: Host Interface Ac Timing (Motorola Mode)
Table 11.6 Host Interface AC Timing (Motorola Mode) Parameter Description Units Addr setup to ASn falling – Addr hold from ASn falling – ASn low pulse width 0.5 Tc – Data setup to DSn rising (Wr cycle) – Data hold from DSn rising (Wr cycle) –...
Page 376: Host Write Timing (Motorola Mode)
Figure 11.5 Host Write Timing (Motorola Mode) A[8:0] D[7:0] READ WAITn DTACKn 11-10 Speciﬁcations...
Page 377: Host Read Timing (Motorola Mode)
Figure 11.6 Host Read Timing (Motorola Mode) A[8:0] D[7:0] READ WAITn DTACKn AC Timing 11-11...
Page 378: Host Interface Ac Timing (Intel Mode)
Table 11.7 Host Interface AC Timing (Intel Mode) Parameter Description Units Addr setup to Write / Read falling – Addr hold from Write / Read falling – CSn setup to Write / Read falling – CSn hold from Write / Read rising –...
Page 379: Host Write Timing (Intel Mode)
Figure 11.7 Host Write Timing (Intel Mode) A[8:0] WRITE (on DSn pin) D[7:0] WAITn DTACKn Figure 11.8 Host Read Timing (Intel Mode) A[8:0] READ (on READ pin) D[7:0] WAITn DTACKn AC Timing 11-13...
Page 380: Asynchronous Channel Write Timing
Table 11.8 Asynchronous Channel Write AC Timing Parameter Description Units AVALIDn/VVALIDn low pulse width 0.5 Tc – Data setup to AVALIDn/VVALIDn rising – Data hold from AVALIDn/VVALIDn rising – AVALIDn/VVALIDn rise to AVALIDn/VVALIDn rise 3 Tc – 1. Tc = 1/27 MHz = 37 ns. Figure 11.9 Asynchronous Channel Write Timing AVALIDn/VVALIDn...
Page 381: Synchronous Avalidn/Vvalidn Signals Timing
Figure 11.10 Synchronous AVALIDn/VVALIDn Signals Timing CH_DATA[7:0] AVALIDn VVALIDn (int_AVALIDn) (Internal signal) int_VVALIDn) (Internal signal) Figure 11.11 Reset Timing SYSCLK 9 Tc RESETn Note: Tc = 1/27 MHz = 37 ns. AC Timing 11-15...
Page 382: Video Interface Timing
Table 11.10 Video Interface AC Timing Parameter Description Units HS/VS Hold Time – HS/VS Setup Time – HS/VS Minimum Pulse Width – SYSCLK HS/VS Maximum Cycle Time – 2047 SYSCLK SYSCLK to Pixel Data Out – SYSCLK to CREF Out –...
Page 383: Serial Pcm Data Out Timing
Table 11.11 Audio Interface AC Timing Parameter Description Units ASDATA change before BCLK rising – ASDATA change after BCLK rising – LRCLK change before BCLK rising – A_ACLK change after ACLK input PREQn change after SYSCLK Figure 11.13 Serial PCM Data Out Timing BCLK ASDATA LRCLK...
Page 384: Preqn Timing
Figure 11.15 PREQn Timing SYSCLK PREQn 11.3 Pinouts and Packaging The L64105 MPEG Audio/Video Decoder is available in a 160-pin Plastic Quad Flat Package (PQFP). Table 11.12 lists the L64105’s input/output signals in alphabetical order and includes: ♦ pin numbers ♦...
Page 385: Alphabetical Pin Summary
Following the table, Figure 11.16 Figure 11.17 are the pinout and outline drawings for the package. Table 11.12 Alphabetical Pin Summary Mnemonic Description Type Drive (mA) Register Address Bus TTL Input – A_ACLK Audio DAC Clock TTL Output ACLK_32 Audio Reference Clock TTL Input, pulldown –...
Page 386 Table 11.12 Alphabetical Pin Summary (Cont.) Mnemonic Description Type Drive (mA) CD_ASDATA CD Audio Serial Data TTL Input, pulldown – CD_BCLK CD DAC Serial Bit Clock TTL Input, pulldown – CD_LRCLK CD DAC Left/Right Clock TTL Input, pulldown – CH_DATA 0 Channel Data Bus TTL Input –...
Page 387 Table 11.12 Alphabetical Pin Summary (Cont.) Mnemonic Description Type Drive (mA) DTACKn/RDYn Data Acknowledge/Ready 3-State Output ERRORn Channel Data Error TTL Input, pullup – EXT_OSD 0 Palette Selection Bus TTL Input, pulldown – EXT_OSD 1 EXT_OSD 2 EXT_OSD 3 Horizontal Sync TTL Input –...
Page 388 Table 11.12 Alphabetical Pin Summary (Cont.) Mnemonic Description Type Drive (mA) SBA 0 SDRAM Address Bus TTL Output SBA 1 SBA 2 SBA 3 SBA 4 SBA 5 SBA 6 SBA 7 SBA 8 SBA 9 SBA 10 SBA 11 (Sheet 4 of 6) 11-22 Speciﬁcations...
Page 389 Table 11.12 Alphabetical Pin Summary (Cont.) Mnemonic Description Type Drive (mA) SBD 0 SDRAM Data Bus TTL Bidirectional SBD 1 SBD 2 SBD 3 SBD 4 SBD 5 SBD 6 SBD 7 SBD 8 SBD 9 SBD 10 SBD 11 SBD 12 SBD 13 SBD 14...
Page 390 Table 11.12 Alphabetical Pin Summary (Cont.) Mnemonic Description Type Drive (mA) SRASn DRAM Row Address Select TTL Output SWEn DRAM Write Enable TTL Output SYSCLK System Clock TTL Input – Test Mode 0 TTL Input – Test Mode 1 TTL Input –...
Page 391: Pin Package Pinout
Figure 11.16 160-Pin Package Pinout SBD 14 SBD 15 SBD 7 SBD 6 PREQn SBD 5 SCAN_TE SBD 4 ZTEST SBD 3 SBD 2 AUDIO_SYNC SBD 1 SPDIF_OUT SBD 0 CH_DATA 0 CH_DATA 1 ASDATA CH_DATA 2 LRCLK CH_DATA 3 BCLK CH_DATA 4 CH_DATA 5...
Page 392: Pin Pqfp (Pz) Mechanical Drawing (Sheet 1 Of 2)
Figure 11.17 160-Pin PQFP (PZ) Mechanical Drawing (Sheet 1 of 2) MD97.PZ-1 Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code PZ. 11-26 Speciﬁcations...
Page 393 MD97.PZ-2 Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code PZ. Pinouts and Packaging 11-27...
Page 394 11-28 Speciﬁcations...
Page 395 ﬂexible, but generally ﬁt the following criteria: ♦ Data rates are about 1 to 1.5 Mbit/s for MPEG-1 and up to 15 Mbit/s for MPEG-2. The L64105 MPEG-2 decoder is capable of supporting data rates up to 20 Mbit/s for either MPEG-1 or MPEG-2. ♦...
Page 396: Video Encoding
A.1.1 Video Encoding For a video signal to be compressed, it must be sampled, digitized, and converted to luminance and chrominance signals (Y, Cr, Cb). The MPEG standard stipulates that the brightness or luminance component (Y) be sampled with respect to the color difference or chrominance signals (Cr and Cb) by a ratio of 4:1.
Page 397: A.1 Mpeg Macroblock Structure
Figure A.1 MPEG Macroblock Structure Motion vectors deﬁne the displacement of the image in the current macroblock from its position in the previous picture. P pictures use motion compensation to exploit temporal redundancy in the video. When an encoder provides B pictures, it must reorder the picture sequence so that the decoder operates properly.
Page 398 The DCT coefﬁcient in the upper left location (0, 0) of the block represents the zero horizontal and zero vertical frequencies and is known as the DC coefﬁcient. The DC coefﬁcient is proportional to the average pixel value of the 8 x 8 block, and additional compression is provided through predictive coding because the difference in the average value of neighboring 8 x 8 blocks tends to be relatively small.
Page 399: Bitstream Syntax
A.1.2 Bitstream Syntax The MPEG standard speciﬁes the syntax for a compressed bitstream. The video syntax contains six layers, each of which supports either a signal processing or a system function. The layers and their functions are described in Table A.1.
Page 400: A.3 Typical Sequence Of Pictures In Bitstream Order
decoding the bitstream. For example, a typical sequence of pictures in display order might be as shown in Figure A.2. Figure A.2 Typical Sequence of Pictures in Display Order 10 11 12 13 14 15 16 17 18 In contrast, the bitstream order corresponding to the given display order would be as shown in Figure A.3.
Page 401: Video Decoding
A.1.3 Video Decoding Video decoding is the reverse of video encoding and is intended to reconstruct a moving picture sequence from a compressed, encoded bitstream. Decoding is simpler than encoding because there is no motion estimation performed and there are far fewer options. The data in the bitstream is decoded according to the syntax deﬁned in the MPEG-2 standard.
Page 402: Mpeg Audio Encoding
A.2.1 MPEG Audio Encoding MPEG audio encoding is intended to efﬁciently represent a digitized audio stream by removing redundant information. Because different applications have different performance goals, MPEG uses different encoding techniques. These techniques, called Layers , provide different trade-offs between compression and signal quality. The MPEG algorithm uses the two following processes for removing redundant audio information: ♦...
Page 403: A.5 Iso System Stream
Figure A.5 ISO System Stream Pack Pack . . . Pack System Packet More Packets Packet Layer Header (ﬁrst) (variable #) (last) 11172 Header Packet End Code Contains: Contains: Contains: Pack Start Code (32 bits), Various data, including Audio stream data system stream ID (in audio frames) System Clock Reference...
Page 404 A.2.1.1 Audio Packet Header An audio packet header contains the following: ♦ Packet Start Code Identiﬁes a packet as an audio packet. The Packet Start Code also contains a ﬁve-bit audio stream identiﬁer that lets the L64105 identify the audio channel. ♦...
Page 405: Audio Decoding
A.2.2 Audio Decoding Audio decoding is the reverse of audio encoding and is intended to reconstruct the compressed audio data. MPEG audio decoding involves: ♦ Identifying and removing a channel’s audio frames from the audio packets in the System Stream. ♦...
Page 406 A-12 Video/Audio Compression and Decompression Concepts...
Page 407 Appendix B Glossary of Terms and Abbreviations Numerics 3:2 Pulldown Film material digitized at 24 pictures per second forms an excellent source for the MPEG video bitstream. To display 24 frame-per-second video at the television frame rate of 30 frames-per-second, 3:2 pulldown is necessary. A single frame of 24 frames per second video is displayed three times at the television ﬁeld rate of 60 ﬁelds-per-second, followed by the next frame displayed...
Page 408 Cyclic Redundancy Check Bitstream error detection scheme. A check performed on data to see if an error has occurred in transmitting, reading, or writing the data. The result of a CRC is typically stored or transmitted with the checked data. The stored or transmitted result is then compared to a CRC calculated for the data to determine if an error has occurred.
Page 409 Decode Time Stamp Decoding times for presentation units extracted from the PES (Packetized Elementary Stream) headers. Used by the L64105 to start reading data from the video channel buffer and decoding it into frame stores. End of Active Video A CCIR656 timing code programmed into the output bitstream by the host to mark the end of the active display area.
Page 410 Frame In motion video, a single image. Frames can be presented at 25 frames per second (PAL standard) or at 30 frames per second (NTSC standard). Group of Frames A Linear PCM audio bitstream is divided in groups of audio frames. Each GOF includes several audio packs which, in turn, contain header data and audio frames.
Page 411 ITU-R BT.656 Recommendation for the generation of SAV/EAV (Start of Active Video/End of Active Video) timing codes in the bitstream. The SAV/EAV timing codes determine the vertical blanking interval and the location of the active display area. LPCM Linear PCM See PCM.
Page 412 NTSC National Television Standards Committee A committee which set the television standard used today in United States and Japan. The standard dictates a 720-pixel wide by 525-line high display in a 4:3 aspect ratio produced by two interlaced scans alternating at 60 scans per second;...
Page 413 Program Stream/Private Stream A Program Stream is a bitstream containing multiple streams related to a single audio/video programs. A Private Stream is a stream not further deﬁned by MPEG-2 but accommodated. Program Speciﬁc Information Presentation Time Stamp Presentation times of presentation units extracted from the PES (Packetized Elementary Stream) headers.
Page 414 S/P DIF Sony/Phillips Digital Interface A speciﬁcation for forming encoded or unencoded audio into bursts and coding the bits to reduce the DC component of the bitstream, facilitate clock recovery, and make the interface insensitive to the polarity of the connection.
Page 415 Video Buffering Veriﬁer An idealized model of a decoder deﬁned by MPEG. It is used to further deﬁne parameters of a ﬁxed bit rate stream to be sent to a decoder, such as bit rate, picture rate, video buffer size, and picture delay in the buffer. Video Compact Disk Voltage-Controlled Oscillator An oscillator whose output frequency is directly...
Page 416 B-10 Glossary of Terms and Abbreviations...
Page 417 Index Numerics asynchronous channel writes 11-14 test conditions 11-5 160-pin package outline drawing 11-25 accessing memory 1-3, 1-5, 5-10 160-pin package pinout 11-24 external SDRAM 6-27 16-bit checksum A-10 accessing trick modes 9-15 2:1 horizontal decimation 4-61 ACLK divider codes 4-86 filter 9-20...
Page 418 audio PES header/system channel size calculation 7-10 buffer end 4-25, size example 7-10 audio PES header/system channel anchor luma frame buffer start 4-25, store 1 base address bits 4-48 audio sync code 4-4, 4-31 store 2 base address bits 4-48 current read pointer anchor pictures 8-46...
Page 419 muted 4-82 S/P DIF output 4-30 packet detect bit signals PES header/system channel buffer starting 4-15, 4-16, 4-80, 5-8, 10-7 end addresses 4-25, status 4-78 PES header/system channel buffer stopping 4-80, 10-8 start addresses 4-25, synchronization 2-10 PES header/system channel buffer write 4-29 audio decoder mode select bits 4-81, 10-2...
Page 420 audio PES header/system channel buffer write address bits 4-29 B chroma frame store base address bits 4-49 audio reference clock See audio clock B frame stores 7-10 audio start on compare bit 4-15 B luma frame store base address bits 4-49 audio stream data B pictures A-2, A-5,...
Page 421 bitstream sample override 10-12, 10-16 setting up rip forward/display override 8-42 bitstream sample resolution 10-3 single skip display freeze 8-37 bitstream searches 4-56 system clock reference bitstream syntax MPEG compressed typical sequence of pictures in bitstream order black backgrounds 9-13, 9-28 typical sequence of pictures in display order blank output 2-8,...
Page 422 channel reset 4-20 SDRAM 2-7, current status multiplexed address 2-7, elementary streams 6-12 BUSMODE signal external memory 6-27 description external OSD 9-32 bypass mode 4-44, FIFO 1-3, 6-13 byte alignment 4-12 FIFO status 2-5, 4-38, 4-77 byte count matching 4-12 updating 5-12 byte enable logic 1-3,...
Page 423 CH_DATA [7:0] signal status bit 4-11 description storage 4-35 channel buffer controller 6-27 6-29 video ES overflow detection compare function 6-28, 8-40 write bypass enable 4-10 channel buffers channel data bus A/V ES end addresses 6-13, channel information 1-2, A/V ES start addresses 6-13, channel interface 6-31 architecture...
Page 424 chroma line repeat 9-17 compare mode (SCR) 4-13 defined 9-16 caution for use interlaced 9-18 overview 5-6, chrominance data See chroma data compare mode bits (SCR) 4-14 circular buffer 8-19, 8-21 compressed gain value 10-17 clear Interrupt pin bit 4-10 compression 10-10 clear OSD palette counter bit...
Page 425 current frame 4-53 channel constraints current picture 4-53 hardware sync controls and 2-10 input timing 9-10, 9-11 out-of-sync conditions 10-5 PCM data 10-16 D[7:0] signal timing 11-15 description synchronous recovery bit DC coefficient DAC clock 2-10, 10-6, 10-33 DCK input CD player data transfers synchronous and samples...
Page 426 digital data streams display override mode 8-41, 9-15 digital equipment 10-29 display parameters digital overwrite category 4-88 display rates 8-24, 9-30 digital transmission 8-bit timing 9-12 external OSD controller 9-32 digitized audio stream display start command bit 4-72 discrete cosine transform (DCT) display start override 4-59 display areas...
Page 427 MPEG-1 preparsing 6-18 DTS (Decode Time Stamp) 6-28 packet layer resynchronization 4-12 DTS audio address compare 4-29 packet syncronization 6-28 DTS audio event interrupt bit program streams 6-21 6-24 DTS register bits compare 6-28 recovery mechanism 8-49 DTS video event interrupt bit transmission A-11 DTS video read compare...
Page 428 Field vertical display 9-16 field inversion 4-65 first field bit 4-62 defined 9-37 first slice start code detect interrupt bit field mode (display override) 9-15 fixed packets 6-24 field picture time line 8-29 flushing audio channels 4-80 field structured pictures 9-18, 9-19 force broken link mode 4-54...
Page 429 override 4-67, 9-15 color fields 9-27 size 8-30 OSD storage formats 9-28, 9-29 starting addresses 8-32 pack enable 4-37, 6-11 status 8-30, 8-34 PCM data packets 6-20 video reads 9-6, 9-30 PES audio system enable 6-11 frame structured pictures 9-18, 9-19 system enable 4-36...
Page 430 host interface 5-19 frame stores 8-32, 8-34 AC timing broken link mode 8-43 Intel mode 11-12 force rate reconstruction 8-44 Motorola mode 11-9 repeat frame mode 8-38 address bus skip frame mode 8-35 address control testing 4-91 override picture width rip forward mode 8-41 audio decoding 10-3...
Page 431 idle states 4-39 resolution 1-5, 1-7, 9-16, 9-17 bitstream sample 10-3 IEC - host copyright bit 4-87 enhancing 9-23 IEC - host emphasis bits 4-87 raster mapper increments 9-22 IEC - overwrite copyright bit 4-88 reducing 9-20 IEC - overwrite emphasis bit 4-87 resolution enhancing 9-18...
Page 432 read/write strobe interrupt/status bits timing diagrams interrupts to 4-9, write timing diagram 11-13 clearing 4-10 intensity stereo 4-74, 4-75 display controller 9-40 interface signals generating host masking 5-6, 8-20, 8-23 summarized multiple priorities 5-10 miscellaneous and test 2-11 overflow interfaces audio ES channels host system clock...
Page 433 PCB layout connections resetting 4-12 LSI Logic LCBG10P specifications 11-1 specifications 11-1 luma L64105 data rates luma data filter 9-20 L64105 horizontal resolution luma data output 9-39 L64105 I/O signals block diagram horizontal timing 9-10 large images 9-19 luma frame store...
Page 434 SDRAM configurations mode signals 2-frame store 8-34 memory test address bits 4-91 3-frame store 8-30 memory test output select bit 4-92 mode select audio decoder bits 10-2 memory test pass/fail status bits 4-93 modes metastability active video at blanking 4-67, microcontroller asynchronous See also host interface...
Page 435 On-Screen Display 9-16 to 9-19, 9-24 MPEG bitstream error detection address override 4-59, 9-15 MPEG bitstream formats 4-12, 10-10, 10-11 data source select 4-58 audio multichannel 4-30 OSD internal/external IEC958 conversions 10-19, 10-21 panic preamble values 10-20 prediction enable 4-54 MPEG compressed bitstream syntax select bit 4-22...
Page 436 preparser errors 6-23 8-bit digital transmission timing 9-12 preparsing 6-16 6-18 formats system syntax SDRAM allocation MPEG-1 syntax and grammar references SDRAM allocation with frame store 7-12 MPEG-1 video sequences errors transport streams 6-26 vertical timing codes MPEG-2 audio NTSC/PAL code television standard select compression 10-10 NTSC/PAL encoder 1-4,...
Page 437 SDRAM writes 9-23 PCM samples 4-83, 10-12, 10-16, 10-19 start column 9-11, 9-27 reconstructed pictures start row 9-26 S/P DIF formatted 4-30 operation modes scaling 4-84, 10-17 operational mode for RAM test bits 4-91 synchronous transfers user data FIFO port 4-19 OSD chroma filter enable bit 4-61...
Page 438 packet length A-10 pause mode packet start code A-10 audio decoder 4-79, 10-6 packet syncronization errors 6-28 PCB layout connections Packetized Elementary Stream See PES packets emphasis bits 4-77 audio error status 4-37 Fs bits 4-77 See also PES packets mute_bit 4-77 video error status...
Page 439 PES packet header 6-18 state 9-10 PES packets 6-2, 6-14 to 6-15, A-7, reset value bits 4-67 A/V detection play mode bitstream formats 4-12 audio decoder 4-79, 10-6, 10-18 current audio write 4-29 audio formatter 4-80 data processing errors audio status 4-78 layer restart 4-12...
Page 440 PREQn signal RDYn signal description description timing 11-17 read pointers usage overview 10-26 audio DTS compare 4-29 Presentation Time Stamp A-10 audio ES channel buffer end address 10-7 presentation units synchronized audio ES channel reset 4-20 priority interrupts 4-11, 5-10 audio sync code address 4-31 private_2 stream packet data errors...
Page 441 user data FIFO port 4-19 report end of test bit 4-92 video items remaining 4-32 reposition display modes 9-16 real-time decode repositioning 9-18 reconstructed pictures 2-7, 2-12, 6-29, 8-24, 9-30, request signals B pictures 8-43, 9-19 requests chroma frame stores A/V channel transfers error detection 4-78...
Page 442 run length coding SAV/EAV column start 9-11 run length error interrupt bit SAV/EAV column start bits 4-72 SAV/EAV offset values 4-70, 4-71 SAV/EAV timing codes 4-4, 9-7, 9-39 SBA[11:0] signal S/P DIF description S/P DIF buffer read pointer reset 4-20 SBD[15:0] signal S/P DIF channel buffer numitems bits 4-33...
Page 443 SDQM signal underflow interrupts description video frame stores SDRAM 1-5, write enable accessing 1-3, write timing cycles address bus 2-7, writes 4-46, 4-47, 7-2, 9-23 addresses, incrementing 5-15 starting addresses 4-42 block moves 4-40, 4-43, 5-10, 5-14, 5-18 writes cycle timing diagram 11-8 caution 5-18...
Page 444 CH_DATA [7:0] memory interface CREF miscellaneous 2-11 test interface 2-11 D[7:0] vertical sync video interface DREQn single skip display freeze 8-37 single step command bit 4-53 DTACKn single step status 4-53 ERRORn single_channel mode 4-75 EXT_OSD[3:0] skip frame mode 4-50, 4-51, 8-35, 8-37 enable bits 8-35...
Page 445 internal clock synchronization 4-44 select bits 4-12 PCM FIFO buffer 4-77 system syntax play mode 4-78 video detection 4-35 RAM test 4-93 video select enable 4-35, repeat frame 4-51 video transfers 2-5, rip forward mode 4-52, 4-53 subband samples 10-10, 10-12 skip frame 4-50...
Page 446 current value 4-13 timing diagram incremental count pause 4-12 A_ACLK timing 11-17 load counter value asynchronous channel writes 11-14 overflow interrupt host read-Intel mode 11-13 sampling host read-Motorola mode 11-11 system header enable bits 4-36 host write-Intel mode 11-13 system header packet host write-Motorola mode 11-10 system PES header enable bits...
Page 447 unidirectional interface 10-29 vertical sync 4-63, 9-5, 9-10 unread audio data 10-7 rate 8-24 user bit 4-85 vertical sync signals 1-4, usage overview 10-31 active low enable 4-67 user data FIFO buffer 8-2, 8-18, 8-21 8-24 input type 4-68 layer ID assignments 8-24 vertical sync timing 9-10...
Page 448 read enable compare 4-21 underflow interrupt bit transfer request signal underflow preventing 8-24 transfer status 4-10 write address bits 4-26 valid input signal video ES channel buffer map 6-21 video decoder video interface AC timing 11-4 AC timing 11-16 autostarting 4-16, 5-8, 8-26 background modes 9-12...
Page 449 Vline count init bit 4-66 WRITEn signal usage overview 9-12 description voltage 11-3 writes output 11-4 asynchronous channel timing 11-14 VREQn signal audio PES header/system channel asynchronous transfers 6-4, buffer 6-10, 6-11, 6-12 channel bypass and channel bypass enable 4-10 description contiguous OSD storage 9-28...
Page 450 IX-34 Index...
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LSI L64105 MPEG-2 Technical Manual

Chapter 1 Introduction

Chapter 10 Audio Decoder Module

Chapter 5 Host Interface

Chapter 6 Channel Interface

Chapter 2 I/O Signal Descriptions

Chapter 3 Register Summary

Host Interface 5.1 Overview

Channel Interface 6.1 Overview

Chapter 7 Memory Interface

Chapter 8 Video Decoder Module

Chapter 9 Video Interface

Appendix A Video/Audio Compression and Decompression Concepts

Chapter 11 Specifications

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Summary of Contents for LSI L64105 MPEG-2