LSI L64005 Manuals

Manuals and User Guides for LSI L64005. We have 1 LSI L64005 manual available for free PDF download: Technical Manual

LSI L64005 Technical Manual

LSI L64005 Technical Manual (272 pages)

Enhanced MPEG-2 Audio/Video Decoder

Brand: LSI | Category: Media Converter | Size: 1 MB

Table of Contents

Table of Contents
9
Chapter 1 Introduction

21
- Video Compression and Decompression Concepts
  21
  - Video Encoding
    22
Appendix B Customer Feedback

23
- MPEG Macroblock Structure
  23
  - Bitstream Syntax
    25
- MPEG Compressed Bitstream Syntax
  25
- Typical Sequence of Frames in Bitstream Order
  26
  - Video Decoding
    27
- Typical Sequence of Frames in Display Order
  26
- Audio Compression and Decompression Concepts
  28
  - Audio Encoding Process (Simpliﬁed)
    29
  - MPEG Audio Encoding
    30
- MPEG Audio Packet Structure
  30
  - Audio Decoding
    31
  - Mpeg-1
    32
  - Video Decoding
    37
- System Overview
  37
  - Post Processing
    38
  - On-Screen Display
    38
  - PES Decoding
    39
  - Video Output
    42
- On-Screen Display
  44
  - 1.6.5.2 Audio Output
    45
  - System Controller Interface
    46
  - Channel Interface
    47
- Features
  48
- L64005 Register Map
  52
- Register Groups and Function
  52
  - Writing a Single Register
    64
- Address Indirection Register
  65
- Reading or Writing Multiple Registers in a Group
  65
Chapter 2 Registers

66
- Group 1 Status 0 Register
  66
- Status 0 Register
  66
- Group 2 Status 1 Register
  68
- Status 1 Register
  68
- Group 3 Interrupt Register 0
  69
- Group 3 Interrupt Register
  70
- Group 4 Interrupt Register
  71
- Group 5 Control Register
  72
- Group 6 Secondary Control Registers
  73
- User Data FIFO
  73
- VLD Parameters
  98
  - Group 7 DRAM Control
    101
  - Group 7 DRAM Address
    102
  - Group 7 DRAM Data
    103
  - Group 7 Horizontal Sync Width
    104
- Active Image Done Register
  105
  - Group 7 Horizontal Blank Pulse Width
    105
  - Group 7 Pre-Blank/Equalization
    106
- Scan Half Lines Register
  107
  - Group 7 Main/Serration Lines
    107
  - Group 7 Display Width
    108
  - Group 7 Reduced Memory Mode Control
    109
  - Group 7 Reserved Registers
    110
  - Group 7 Channel Buffer Read Address
    111
  - Group 7 Picture Start Code Read Address
    112
  - Group 7 DRAM Source Address Registers
    113
  - Group 7 Revision ID Register
    114
  - Group 7 System Clock Reference (SCR) Value
    116
  - User Interface
    117
- L64005 Logic Symbol
  118
- Channel Interface
  120
Chapter 3 Signals

120
- Parallel Channel Input Timing
  122
  - Parallel Channel Writes
    122
- Memory Interface
  123
  - Synchronous DRAM Signals
    124
Video Interface

125
- Audio Interface
  126
- Master Mode
  126
- PLL Interface
  127
- External Loop Filter
  128
- Channel Data Parsers
  129
Chapter 4 Video Data Flow

129
- Summary of the Bitstream Parsing Operations
  130
- Conceptual System Synchronization
  131
  - Pre-Parser Operation
    131
- Synchronization at the System Level
  132
  - Post-Parser Operation
    134
- Channel Buffer Operation
  138
  - User Data Buffer
    139
  - Auxiliary Data Buffer
    140
- Elementary Stream Decoding
  141
- Successful and Unsuccessful Frame Skips
  142
Chapter 5 External Memory Interface

143
- Overview
  143
- Memory Interface
  144
- Mapping of Physical Address Bus to BA[8:0]
  145
  - Synchronous DRAM Mode
    145
- Mapping of Physical Address Bus to SBA[11:0]
  146
  - DRAM Transfer Modes
    146
- Single Word Read Routine
  150
- Multiple Word Read Routine
  151
- 5.3.4.1 Regular DRAM Interface
  154
- Regular DRAM Read and Write Timing
  154
  - Read/Write
    154
  - Word Accesses Vs. 81Mhz Clock Cycles in Regular DRAM Mode
    155
- 5.3.4.2 Synchronous DRAM Interface
  156
- Word Accesses Vs. 81Mhz Clock Cycle in SDRAM Mode
  156
- Synchronous DRAM Read and Write Timing
  157
  - Refresh Cycles
    158
- Memory Map
  159
- Synchronous DRAM Refresh Timing
  159
- Memory Map of L64005
  160
  - Luma Frame Organization
    161
- Channel Buffer Architecture
  162
- Channel Buffer Organization in L64005
  163
  - Video PES Buffer
    163
  - Audio PES Buffer
    164
  - Video Output Features
    165
Chapter 6 On-Screen Display

165
- Composite Sync and Composite Blank
  166
  - Post-Processing 480- and 576-Line Images
    166
- Post-Processing Modes
  167
  - Post-Processing 240- and 288-Line Images
    168
  - Selecting the Post-Processing Mode
    169
- Effect of Vertical Resolution and Blanking
  170
- Video Resolution
  170
- Reduced Memory Mode
  171
- Horizontal Post-Processing Filter
  172
- Frequency and Phase Response a
  173
- Frequency and Phase Response B
  173
- Impulse Response a
  173
- Impulse Response B
  174
  - Setting the Filter Raster Mapper Increment
    174
- Raster Mapper Increment by Source Resolution
  175
  - Setting the Start Phase of the Filter
    175
- Video Timing
  176
  - Video Raster Timing (Master Mode
    176
- Video Timing Chain Nomenclature
  176
- Horizontal Sync Timing
  177
- Display Parameters
  178
- Vertical Timing of Common TV Systems
  181
  - Vcode Delay
    181
  - For Copy Protection
    182
- Display Trick Modes
  183
- Freeze Frame for One Frame Time
  185
- Freeze Frame for One Field Time
  186
- Pull-Down
  186
- Pull-Down Field Order
  187
- On-Screen Display
  188
- Pointers to Overlay Display Lists
  189
  - Operation of the OSD Controller
    189
- OSD File Organization
  191
- Region Attribute Bits
  192
- Color Fields
  193
- Color Attribute Bits
  194
- Color Extension Bits
  194
  - Alpha Blending
    196
- Conversion from 4:4:4
  197
  - Alignment of the Bitmap
    197
  - OSD Compatibility Mode
    198
  - Accessing the Overlay Bitmaps
    199
  - Audio Decoder
    201
Chapter 7 Audio Decoder

201
- Decoder Programming
  201
  - Starting, Stopping and Controlling the Rate of the Decoder
    202
  - Setting the DAC Interface Mode
    203
- Typical Values for NCO at 27 Mhz Fd
  205
  - Determining the Presentation Time
    206
- Location of Maskable Interrupts
  207
  - Output Control
    208
  - Parsing a Program Stream
    210
  - Parsing a Transport Stream
    212
  - System Parser Control Bits
    213
- DRAM Map of an MPEG-2 Packet Header Structure in the Elementary Stream with Write Pointer
  214
- MPEG-2 Transport Encoder
  215
- Audio and Video Sync Train
  216
- Audio and Video Dtss and Ptss
  218
- Interrupt at each Vertical Sync
  219
- L64005 MPEG-2 Audio/Video Decoder Technical Manual
  219
- Local Counter and Comparator Logic
  219
- Audio and Video Decode Interrupts
  220
  - L64005 Video Skip and Repeat Frame
    221
- Video Repeat
  222
- Video Skip
  222
- Decode to Display Delay
  223
  - Video Decoding and Presentation Schedule
    223
  - Audio Decoder Rate Control
    224
- Audio Input Clock Is 256 Fs
  225
  - Clock Recovery
    227
  - Creating Audio and Video PTS List
    228
- Buffer Organization in L64005 Memory
  229
- PES Header Structure
  230
- List of Pending Pus for Video and Audio
  231
- Picture Header Interrupt and AUX FIFO Interrupt
  231
- PTS Association with Presentation Unit
  232
- L64005 MPEG-2 Audio/Video Decoder Technical Manual
  233
- Picture Type Routine
  233
  - Vertical Sync Interrupt
    234
- AC Test Conditions
  240
- DRAM Read Cycle
  240
- DRAM Write Cycle
  240
- Host Read Timing
  240
- Host Write Timing
  240
- Parallel Channel Write Timing
  240
- Serial Data Input
  240
- AC Test Load and Waveform for 3-State Outputs
  241
- AC Test Load and Waveform for Standard Outputs
  241
- AC Timing Values
  242
- Absolute Maximum Ratings
  252
- Recommended Operating Conditions
  252
- DC Characteristics
  253
- Pin Description Summary
  254
- L64005 Ordering Information
  256
- Reset
  257
- L64005 Pinout Diagram for Regular DRAM 160-Pin PQFP
  259
- L64005 Pinout Diagram for Synchronous DRAM 160-Pin PQFP
  260
  - Mechanical Drawing
    261
  - Pin Copper Lead Frame PQFP Mechanical Drawing
    261
- DC Logic Levels
  264
Appendix A Interfacing the L64005 to 5-V Signals

265
- V-Compatible Input Buffers
  265
Chapter 9 Specifications

265
- A.12 DC Characteristics
  266
- Ibuf (3.3V Input), LVTTL AC Characteristics
  266
- Ibuff, LVTTL Input Buffer, Non-Inverting, 5V-Compatible
  266
- DC Characteristics
  268
  - Open Drain Outputs
    269

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