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MIPI D-PHY
Lattice MIPI D-PHY Manuals
Manuals and User Guides for Lattice MIPI D-PHY. We have
1
Lattice MIPI D-PHY manual available for free PDF download: User Manual
Lattice MIPI D-PHY User Manual (28 pages)
Bandwidth Matrix Table
Brand:
Lattice
| Category:
Server
| Size: 1 MB
Table of Contents
Table of Contents
2
Acronyms in this Document
4
1 Introduction
5
Figure 1.1. CMOS Sensor Bridge Model
5
2 Video Format
6
Figure 2.1. Interlaced Mode Video Frame Format
6
Video Resolution and Pixel Clock
7
Figure 2.2. most Common Display Resolutions
7
Color Depth
8
Table 2.1. Common Video Format
8
3 MIPI CSI-2/DSI Interfaces
9
Figure 3.1. Unidirectional Receive HS Mode and Bidirectional LP Mode Interface Implementation
9
Figure 3.2. Unidirectional Receive HS Mode Only Implementation
10
Figure 3.3. Unidirectional Transmit HS Mode and Bidirectional LP Mode Interface Implementation
11
Figure 3.4. Unidirectional Transmit HS Mode Only Implementation
12
4 Packetizing
13
Figure 4.1. an Example of RAW10 Transmissions on CSI-2 Bus
13
Xmulti-Lane
14
Table 4.1. CSI-2 Packet Size Constraints
14
5 Bandwidth and Data Rate
15
Bandwidth and Data Rate Calculation
15
Pixel Clock
15
Total Data Rate or Bandwidth
15
Data Rate Per Lane
15
Bit Clock
15
Examples
15
Example 1: 1920X1080P@60Hz, RAW10, 2-Lane
15
Example 2: 3840X2160@30Hz, RAW8, 4-Lane
15
6 Device Selection
16
Hardware Features
16
Table 6.1. MIPI Soft D-PHY RX/TX Hardware Comparison
16
7 MIPI Data Rate Calculation
18
FPGA Receiver Interface
18
Machxo2/Machxo3L
18
Figure 7.1. Machxo2/Machxo3L Maximum Data Rate
18
Latticeecp3
19
Figure 7.2. Latticeecp3 Maximum Data Rate
19
Ecp5/Ecp5-5G
20
Figure 7.3. ECP5/ECP5-5G Maximum Data Rate
20
Crosslink Soft D-PHY
21
SU /T HD Valid Window at Higher Data Rate
21
Figure 7.4. Crosslink Maximum Data Rate
21
Su Hd
21
FPGA Transmitter Interface
22
Machxo2/Machxo3L
22
Figure 7.5. Machxo2 Maximum Data Rate
22
Latticeecp3
23
Figure 7.6. Latticeecp3 Maximum Data Rate
23
Ecp5/Ecp5-5G
24
Tskew Window at Higher Data Rate
24
Figure 7.7. ECP5/ECP5-5G Maximum Data Rate
24
Table 7.2. Tskew Window for Higher Data Rate
24
MIPI D-PHY Lane Number Selection Matrix Table
25
Table 7.3. MIPI D-PHY Interface Lane Number and Line Rate Selection Example Matrix Table
25
Reference
27
Technical Support
27
Revision History
27
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