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Lattice MIPI D-PHY User Manual

Bandwidth matrix table
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MIPI D-PHY Bandwidth Matrix Table
User Guide
FPGA-UG-02041 Version 1.1
May 2018

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Summary of Contents for Lattice MIPI D-PHY

  • Page 1 MIPI D-PHY Bandwidth Matrix Table User Guide FPGA-UG-02041 Version 1.1 May 2018...

  • Page 2: Table Of Contents

    Revision History ................................27 © 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
  • Page 3 Table 7.3. MIPI D-PHY Interface Lane Number and Line Rate Selection Example Matrix Table........25 © 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 4: Acronyms In This Document

    Vertical Sync © 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 5: Introduction

    Figure 1.1. CMOS Sensor Bridge Model © 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 6: Video Format

    Start and Frame End) and Line Synchronization (that is Line Start and Line End). © 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 7: Video Resolution And Pixel Clock

    © 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 8: Color Depth

    RGB is defined as 30 bits per pixel, or 10 bits per color component. © 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 9: Mipi Csi-2/Dsi Interfaces

    MIPI D-PHY physical interface. MIPI D-PHY supports unidirectional HS (High Speed) mode and Bidirectional LP (Low Power) mode. For the application of CMOS sensor bridge, we will only need the MIPI D-PHY receiver (RX) on the FPGA receive interface, which allows the bridge to receive HS data on one clock lane and up to four data lanes.

  • Page 10: Figure 3.2. Unidirectional Receive Hs Mode Only Implementation

    Figure 3.2. Unidirectional Receive HS Mode Only Implementation © 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 11: Figure 3.3. Unidirectional Transmit Hs Mode And Bidirectional Lp Mode Interface Implementation

    Figure 3.3. Unidirectional Transmit HS Mode and Bidirectional LP Mode Interface Implementation © 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 12: Figure 3.4. Unidirectional Transmit Hs Mode Only Implementation

    Figure 3.4. Unidirectional Transmit HS Mode Only Implementation © 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 13: Packetizing

    Figure 4.1. An Example of RAW10 Transmissions on CSI-2 Bus © 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 14: Xmulti-Lane

    © 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 15: Bandwidth And Data Rate

    MIPI Bit Block Frequency = 594/2 = 297 MHz © 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 16: Device Selection

    1250 Mbps © 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
  • Page 17 CrossLink has two hardened MIPI IPs on the top side of the chip, and has dedicated IO associated with harded IP. Regard to MIPI D-PHY interface implementation, on the receiver side it has hardened IP offering as well as soft IP offering, but on the transmitter side it only offers hardened IP implemtation.

  • Page 18: Mipi Data Rate Calculation

    7. MIPI Data Rate Calculation This section shows the calculations of the maximum data rate that can be achieved on Lattice FPGA products. The values are based on data sheet specification of DDRX2/X4/X8 with clock and data center-aligned. These are MIPI Alliance Specification compliant with ±0.15 UI setup/hold window on the receiver at ≤1 Gbps and ±0.15 UI skew...

  • Page 19: Latticeecp3

    Figure 7.2. LatticeECP3 Maximum Data Rate © 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 20: Ecp5/Ecp5-5G

    Figure 7.3. ECP5/ECP5-5G Maximum Data Rate © 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 21: Crosslink Soft D-Phy

    0.20 UI © 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 22: Fpga Transmitter Interface

    Figure 7.5. MachXO2 Maximum Data Rate © 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 23: Latticeecp3

    Figure 7.6. LatticeECP3 Maximum Data Rate © 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 24: Ecp5/Ecp5-5G

    <= 0.150 UI © 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 25: Mipi D-Phy Lane Number Selection Matrix Table

    Table 7.3 lists the selection of MIPI D-PHY Lane number and Line rate versus the Total Data Rate required by each video format. For clarity, this Matrix table only chooses three common resolutions and the major color depths as examples. The lane number and line rate for other video formats can be calculated using the equations listed in Bandwidth and Data Rate section.
  • Page 26 Rx side is 0.24 UI (0.321 ns * 742.5 Mbps). © 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 27: Reference

    Initial release. © 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
  • Page 28 Floor, 111 SW 5 Avenue Portland, OR 97204, USA T 503.268.8000 www.latticesemi.com...

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