Freescale Semiconductor MPC5510 Manuals

Manuals and User Guides for Freescale Semiconductor MPC5510. We have 2 Freescale Semiconductor MPC5510 manuals available for free PDF download: Reference Manual

Freescale Semiconductor MPC5510 Reference Manual

Freescale Semiconductor MPC5510 Reference Manual (1021 pages)

Brand: Freescale Semiconductor | Category: Microcontrollers | Size: 4 MB

Table of Contents

MPC5510 Reference Manual Addendum, Rev
3
Rev.
4
Rev.
5
Appendix A Revision History

6
- Table of Contents
  10
- Introduction
  26
- Block Diagram
  27
- MPC5510 Family Comparison
  28
Chapter 1 Family Feature Set Scaling

30
- Chip-Level Features
  31
  - Low-Power Operation
    32
  - Introduction
    36
Chapter 2

47
- Power and Ground Supply Summary
  47
- Pinout – 144 LQFP
  49
- Pinout – 176 LQFP
  50
- Pinout – 208 BGA
  51
  - Port B Pins
    52
  - Port C Pins
    54
  - Port D Pins
    56
  - Port E Pins
    59
  - Port F Pins
    60
  - Port G Pins
    63
  - Port H Pins
    65
  - Port J Pins
    67
  - Port K Pins
    68
  - Power and Ground Pins
    69
  - Introduction
    72
Chapter 3

73
- External High-Frequency Crystal (XOSC)
  73
- External Low-Frequency Crystal (32Kxosc)
  74
- System Clock Architecture Block Diagram
  75
- Clock Dividers
  76
- Software-Controlled Power Management
  77
  - Halt Clock Gating
    78
- Alternate Module Clock Domains
  79
  - RTC Clock Domain
    80
    
    Introduction
    82
    
    Features
    83
  - Module Memory Map
    84
    
    Features
    86
    
    Functional Description
    92
- Resets
  99
Chapter 4

100
- PLL Loss-Of-Lock Reset
  100
  - Introduction
    102
  - Features
    104
- Memory Map and Registers
  105
  - Functional Description
    117
  - Low-Power Mode Entry
    118
  - Low-Power Operation
    119
  - Low-Power Wakeup
    125
  - Debug Mode
    128
- Real-Time Counter (RTC)
  129
  - RTC Functional Description
    130
  - Register Description
    132
- Power Supply Monitors
  133
  - Introduction
    136
  - Features
    137
  - Modes of Operation
    138
  - External Signal Description
    139
- Memory Map and Registers
  140
  - Register Descriptions
    146
  - Functional Description
    184
Chapter 6

185
- Reset Control
  185
- GPIO Operation
  186
- Introduction
  188
Chapter 7

189
- Reset (RESET)
  189
- Reset Sources
  190
- Reset Configuration
  191
- Introduction
  194
- Interrupt Vectors
  195
Chapter 8 Interrupts

196
- External Input: Software Vector Mode
  196
- Critical Input
  197
- Interrupt Sources
  198
  - Interrupt Operation
    212
  - Dynamic Priority Elevation
    213
    
    Introduction
    216
    
    Block Diagram
    217
    
    Modes of Operation
    219
- Signal Description
  220
  - Register Descriptions
    221
  - Functional Description
    230
Chapter 9

231
- Priority Management
  231
- Handshaking with Processor
  232
- Initialization/Application Information
  235
- ISR, RTOS, and Task Hierarchy
  237
- Priority Ceiling Protocol
  238
- Selecting Priorities According to Request Rates and Deadlines
  239
- Software Settable Interrupt Requests
  240
- Lowering Priority Within an ISR
  241
- Examining LIFO Contents
  242
- Introduction
  244
- Microarchitecture Summary
  245
Chapter 11

246
- Instruction Unit Features
  246
- Integer Unit Features
  247
- Core Registers and Programmer's Model
  248
- Interrupt Types
  266
- Bus Interface Unit (BIU)
  268
- Introduction
  270
- Microarchitecture Summary
  271
Chapter 10

272
- Instruction Unit Features
  272
- Load/Store Unit Features
  273
- Power Architecture Book E Registers
  276
- E200-Specific Special Purpose Registers
  278
- E200Z0 Core Complex Features Not Supported on the MPC5510
  280
- Bus Interface Unit (BIU)
  281
  - Introduction
    282
  - Features
    283
  - Modes of Operation
    284
  - Register Descriptions
    286
  - Register Descriptions
    288
  - Interrupt Requests
    289
  - Functional Description
    305
  - Edma Basic Data Flow
    307
- Initialization / Application Information
  310
  - DMA Programming Errors
    312
  - DMA Request Assignments
    313
  - DMA Transfer
    314
  - TCD Status
    317
  - Channel Linking
    318
  - Dynamic Programming
    319
  - Memory Map and Registers
    323
Chapter 13

331
- Always Enabled DMA Sources
  331
  - Initialization/Application Information
    332
  - Interrupts
    335
Chapter 14

336
- Terminology
  336
- Read Cycles
  338
Chapter 15

340
- Master Ports
  340
- Slave Port State Machine
  345
  - DMA Requests
    347
  - Introduction
    348
  - Memory Map and Registers
    349
  - Register Descriptions
    351
  - Functional Description
    364
Chapter 17

379
Chapter 16

379
Chapter 18 Semaphore Usage

394
- Initialization Information
  395
- DMA Requests
  396
  - Introduction
    398
  - Features
    399
  - External Signal Description
    401
Chapter 19

402
- Device Identification Register
  402
- IEEE 1149.1-2001 (JTAG) Test Access Port
  403
- JTAGC Instructions
  405
- Boundary Scan
  407
- E200Z0 and E200Z1 Once Controllers
  408
  - E200Z0 Once Controller Register Descriptions
    409
    
    Initialization/Application Information
    411
    
    Introduction
    412
Chapter 33

413
- Block Diagram
  413
  - Features
    414
  - Modes of Operation
    415
Chapter 28

417
- External Signal Description
  417
- Register Descriptions
  418
- Debug Mode
  422
- Functional Description
  427
  - Configuring the NDI for Nexus Messaging
    428
  - Switching Ownership of Nexus2+
    429
  - Nexus Messaging
    430
  - Nexus Reset Control
    433
    
    Introduction
    434
    
    Features
    435
  - Modes of Operation
    436
  - Register Descriptions
    437
Chapter 21

438
- Reset Operation
  438
- Example Code
  439
- Introduction
  440
Chapter 29 Block Diagram

441
- Features
  442
- Memory Map and Registers
  443
  - Register Descriptions
    444
  - Functional Description
    457
  - Read While Write (RWW)
    458
  - Flash Erase
    461
  - Flash Shadow Block
    464
  - Flash Stop Mode
    465
- Interrupt Requests
  466
  - Introduction
    468
  - Features
    469
  - Features
    470
  - Modes of Operation
    471
  - Register Descriptions
    472
  - Functional Description
    496
  - Modes of Operation
    497
Chapter 23

498
- Start and Stop of DSPI Transfers
  498
- Serial Peripheral Interface (SPI) Configuration
  499
- Deserial Serial Interface (DSI) Configuration
  502
- Combined Serial Interface (CSI) Configuration
  508
- Buffered SPI Operation
  511
- Transfer Formats
  514
- Continuous Serial Communications Clock
  520
- Peripheral Chip Select Expansion and Deglitching
  521
- DMA and Interrupt Conditions
  522
- Power Saving Features
  523
- Initialization/Application Information
  524
  - Baud Rate Settings
    525
  - Delay Settings
    526
  - Calculation of FIFO Pointer Addresses
    527
- Introduction
  530
  - Features
    531
  - Module Memory Map
    532
- Functional Description
  545
Chapter 24

546
- Data Format
  546
- Baud Rate Generation
  547
- Transmitter
  548
- Receiver
  552
- Single-Wire Operation
  558
- Loop Operation
  559
- Interrupt Operation
  560
- Using the LIN Hardware
  563
Chapter 32

568
- Introduction
  568
Chapter 22

569
- Features
  569
- Modes of Operation
  570
- External Signal Description
  571
Chapter 25

573
- Message Buffer Structure
  573
- Rx FIFO Structure
  576
- Register Descriptions
  578
- Functional Description
  595
  - Transmit Process
    596
  - Receive Process
    597
  - Matching Process
    598
  - Data Coherence
    600
  - Rx FIFO
    602
  - CAN Protocol Related Features
    603
  - Modes of Operation Details
    606
  - Interrupts
    608
  - Flexcan Initialization Sequence
    609
Chapter 20

610
- Introduction
  610
  - Features
    611
  - Modes of Operation
    612
  - External Signal Description
    613
    
    Output Disable Input — Emios200 Output Disable Input Signal
    614
    
    Register Descriptions
    615
Chapter 26

617
- Emios200 Global FLAG Register (EMIOS_GFR)
  617
- Emios200 Disable Channel (EMIOSUCDIS)
  618
- Emios200 B Register (Emios_Cbdr[N])
  619
- Emios200 Counter Register (Emios_Ccntr[N])
  620
- Emios200 Status Register (Emios_Csr[N])
  625
- IP Bus Interface Unit (BIU)
  652
- Interrupts
  653
- Coherent Accesses
  654
- I-Bus Protocol
  666
- Interrupts
  670
- Initialization/Application Information
  671
- DMA Application Information
  675
- Example Configuration
  690
  - Introduction
    692
  - Features
    693
  - Modes of Operation
    694
- Signal Description
  696
  - Signal Function and Direction by Mode
    698
  - Signal Pad Configuration by Mode
    699
    
    Register Descriptions
    700
    
    Functional Description
    707
  - External Bus Operations
    713
  - Initialization/Application Information
    739
  - Connecting an MCU to Multiple Memories
    741
  - Dual-MCU Operation with Reduced Pinout Mcus
    742
  - Introduction
    744
Chapter 30 Flexray Communication Controller (FLEXRAY)

745
- Color Coding
  745
  - Features
    747
  - Modes of Operation
    748
  - External Signal Description
    749
- Controller Host Interface Clocking
  750
  - Oscillator Clocking
    751
    
    Register Descriptions
    754
    
    Functional Description
    821
  - Message Buffer Types
    822
  - Flexray Memory Layout
    827
  - Physical Message Buffer Description
    829
  - Individual Message Buffer Functional Description
    838
  - Individual Message Buffer Search
    862
  - Individual Message Buffer Reconfiguration
    865
  - Receive FIFO
    866
  - Channel Device Modes
    870
  - External Clock Synchronization
    872
  - MTS Generation
    875
  - Sync Frame and Startup Frame Transmission
    876
  - Sync Frame Filtering
    877
  - Strobe Signal Support
    878
  - Timer Support
    879
  - Slot Status Monitoring
    880
  - Interrupt Support
    883
  - Lower Bit Rate Support
    887
- Application Information
  888
  - Shut down Sequence
    889
  - Protocol Control Command Execution
    890
  - Protocol Reset Command
    891
  - Message Buffer Search on Simple Message Buffer Configuration
    892
  - Introduction
    896
- Block Diagram
  897
  - Features
    898
  - Modes of Operation
    899
  - External Signal Description
    900
  - Module Memory Map
    901
  - Register Descriptions
    904
Chapter 31

920
- On-Chip ADC Registers
  920
- Functional Description
  926
- Data Flow in the Eqadc
  927
- Command/Result Queues
  936
- Result Fifos
  951
- On-Chip ADC Configuration and Control
  954
- Internal/External Multiplexing
  960
- Eqadc Edma/Interrupt Request
  965
- Analog Submodule
  966
- Initialization/Application Information
  969
- Eqadc/Edma Controller Interface
  972
- Sending Immediate Command Setup Example
  973
- Modifying Queues
  974
- Command Queue and Result Queue Usage
  975
- ADC Result Calibration
  976
- Softmlb Interface Logic Description
  1012
- Softmlb Interface Logic Signal Description
  1013
- A.1 Changes between Revisions 0 and 1
  1018

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Freescale Semiconductor MPC5510 Reference Manual

Freescale Semiconductor MPC5510 Reference Manual (1014 pages)

Brand: Freescale Semiconductor | Category: Microcontrollers | Size: 6 MB

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