Diodes PI7C9X2G304SL Manuals

Manuals and User Guides for Diodes PI7C9X2G304SL. We have 1 Diodes PI7C9X2G304SL manual available for free PDF download: Manual

Diodes PI7C9X2G304SL Manual (89 pages)

PCI EXPRESS GEN 2 PACKET SWITCH 3-Port, 4-Lane, SlimPacket PCIe 2.0 Packet Switch

Brand: Diodes | Category: Switch | Size: 1 MB

Table of Contents
4
Features
9
General Description
10
Pin Description
12
Pci Express Interface Signals
12
Port Configuration Signals
13
Miscellaneous Signals
13
Jtag Boundary Scan Signals
14
Pow er Pins
15
Pin Assignments
16
Pin List of 129-Pin Lqfp
16
Functional Description
17
Physical Layer Circuit
17
Receiver Detection
17
Receiver Signal Detection
18
Receiver Equalization
18
Transmitter Swing
18
Drive Amplitude and De-Emphasis Settings
18
Drive Amplitude
19
Drive De-Emphasis
20
Transmitter Electrical Idle Latency
20
Data Link Layer (Dll)
20
Transaction Layer Receive Block (Tlp Decapsulation)
21
Routing
21
Tc/VC Mapping
21
Queue
21
Nphd
22
Cplh
22
Cpld
22
Transaction Ordering
22
Port Arbitration
23
VC Arbitration
23
Flow Control
23
Transation Layer Transmit Block (Tlp Encapsulation)
24
Access Control Service
24
Eeprom Interface and System Management Bus
25
Eeprom Interface
25
Auto Mode Eerpom Access
25
Eeprom Mode at Reset
25
Eeprom Space Address Map
25
Mapping Eeprom Contents to Configuration Registers
27
Smbus INTERFACE
35
Register Description
36
Register Types
36
Transparent Mode Configuration Registers
36
VENDOR ID REGISTER - OFFSET 00H
38
DEVICE ID REGISTER - OFFSET 00H
38
COMMAND REGISTER - OFFSET 04H
38
PRIMARY STATUS REGISTER - OFFSET 04H
39
REVISION ID REGISTER - OFFSET 08H
40
CLASS CODE REGISTER - OFFSET 08H
40
CACHE LINE REGISTER - OFFSET 0Ch
40
PRIMARY LATENCY TIMER REGISTER - OFFSET 0Ch
40
HEADER TYPE REGISTER - OFFSET 0Ch
40
PRIMARY BUS NUMBER REGISTER - OFFSET 18H
40
SECONDARY BUS NUMBER REGISTER - OFFSET 18H
40
SUBORDINATE BUS NUMBER REGISTER - OFFSET 18H
41
SECONDARY LATENCY TIMER REGISTER - OFFSET 18H
41
I/O BASE ADDRESS REGISTER - OFFSET 1Ch
41
I/O LIMIT ADDRESS REGISTER - OFFSET 1Ch
41
SECONDARY STATUS REGISTER - OFFSET 1Ch
41
MEMORY BASE ADDRESS REGISTER - OFFSET 20H
42
MEMORY LIMIT ADDRESS REGISTER - OFFSET 20H
42
PREFETCHABLE MEMORY BASE ADDRESS REGISTER - OFFSET 24H
42
PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER - OFFSET 24H
42
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER - OFFSET 28H
43
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER - OFFSET 2Ch
43
I/O BASE ADDRESS UPPER 16-BITS REGISTER - OFFSET 30H
43
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER - OFFSET 30H
43
CAPABILITY POINTER REGISTER - OFFSET 34H
43
INTERRUPT LINE REGISTER - OFFSET 3Ch
44
INTERRUPT PIN REGISTER - OFFSET 3Ch
44
BRIDGE CONTROL REGISTER - OFFSET 3Ch
44
POWER MANAGEMENT CAPABILITY REGISTER - OFFSET 40H
45
POWER MANAGEMENT DATA REGISTER - OFFSET 44H
45
PPB SUPPORT EXTENSIONS - OFFSET 44H
46
DATA REGISTER - OFFSET 44H
46
MSI CAPABILITY REGISTER - OFFSET 4Ch (Downstream Port Only)
46
MESSAGE CONTROL REGISTER - OFFSET 4Ch (Downstream Port Only)
46
MESSAGE ADDRESS REGISTER - OFFSET 50H (Downstream Port Only)
46
MESSAGE UPPER ADDRESS REGISTER - OFFSET 54H (Downstream Port Only)
47
MESSAGE DATA REGISTER - OFFSET 58H (Downstream Port Only)
47
VPD CAPABILITY REGISTER - OFFSET 5Ch (Upstream Port Only)
47
VPD DATA REGISTER - OFFSET 60H (Upstream Port Only)
47
VENDOR SPECIFIC CAPABILITY REGISTER - OFFSET 64H
47
XPIP CSR0 - OFFSET 68H (Test Purpose Only)
48
XPIP CSR1 - OFFSET 6Ch (Test Purpose Only)
48
REPLAY TIME-OUT COUNTER - OFFSET 70H
48
ACKNOWLEDGE LATENCY TIMER - OFFSET 70H
48
SWITCH OPERATION MODE - OFFSET 74H (Upstream Port)
49
SWITCH OPERATION MODE - OFFSET 74H (Downstream Port)
50
XPIP_CSR2 - OFFSET 78H
50
PHY PARAMETER 1 - OFFSET 78H
50
PHY PARAMETER 2 - OFFSET 7Ch
51
XPIP_CSR3 - OFFSET 80H
51
XPIP_CSR4 - OFFSET 84H
51
XPIP_CSR5 - OFFSET 88H
52
TL_CSR - OFFSET 8Ch
52
PHY PARAMETER 3 - OFFSET 90H
53
PHY PARAMETER 4 - OFFSET 94H
53
OPERATION MODE -OFFSET 98H
53
SSID/SSVID CAPABILITY REGISTER - OFFSET B0H
53
SUBSYSTEM ID REGISTER - OFFSET B4H
54
GPIO CONTROL REGISTER - OFFSET B8H (Upstream Port Only)
54
EEPROM CONTROL REGISTER - OFFSET Bch (Upstream Port Only)
55
EEPROM ADDRESS REGISTER - OFFSET Bch (Upstream Port Only)
56
EEPROM DATA REGISTER - OFFSET Bch (Upstream Port Only)
56
PCI EXPRESS CAPABILITY REGISTER - OFFSET C0H
56
DEVICE CAPABILITIES REGISTER - OFFSET C4H
57
DEVICE CONTROL REGISTER - OFFSET C8H
57
DEVICE STATUS REGISTER - OFFSET C8H
58
LINK CAPABILITIES REGISTER - OFFSET Cch
59
LINK CONTROL REGISTER - OFFSET D0H
60
LINK STATUS REGISTER - OFFSET D0H
60
SLOT CAPABILITIES REGISTER (Downstream Port Only) - OFFSET D4H
61
SLOT CONTROL REGISTER (Downstream Port Only) - OFFSET D8H
62
SLOT STATUS REGISTER (Downstream Port Only) - OFFSET D8H
63
DEVICE CAPABILITIES REGISTER 2 - OFFSET E4H
63
DEVICE CONTROL REGISTER 2 - OFFSET E8H
63
DEVIDE STATUS REGISTER 2 - OFFSET E8H
64
LINK CAPABILITIES REGISTER 2 - OFFSET Ech
64
LINK CONTROL REGISTER 2 - OFFSET F0H
64
LINK STATUS REGISTER 2 - OFFSET F0H
64
SLOT CAPABILITIES REGISTER 2 - OFFSET F4H
64
SLOT CONTORL REGISTER 2 - OFFSET F8H
64
SLOT STATUS REGISTER 2 - OFFSET F8H
65
PCI EXPRESS ADVANCED ERROR REPORTING CAPABILITY REGISTER - OFFSET 100H
65
UNCORRECTABLE ERROR STATUS REGISTER - OFFSET 104H
65
UNCORRECTABLE ERROR MASK REGISTER - OFFSET 108H
66
UNCORRECTABLE ERROR SEVERITY REGISTER - OFFSET 10Ch
66
CORRECTABLE ERROR STATUS REGISTER - OFFSET 110 H
67
CORRECTABLE ERROR MASK REGISTER - OFFSET 114 H
68
ADVANCE ERROR CAPABILITIES and CONTROL REGISTER - OFFSET 118H
68
HEADER LOG REGISTER - OFFSET from 11Ch to 128H
69
PCI EXPRESS VIRTUAL CHANNEL CAPABILITY REGISTER - OFFSET 140H
69
PORT VC CAPABILITY REGISTER 1 - OFFSET 144H
69
PORT VC CAPABILITY REGISTER 2 - OFFSET 148H
69
PORT VC CONTROL REGISTER - OFFSET 14Ch
70
PORT VC STATUS REGISTER - OFFSET 14Ch
70
VC RESOURCE CAPABILITY REGISTER (0) - OFFSET 150H
70
VC RESOURCE CONTROL REGISTER (0) - OFFSET 154H
71
VC RESOURCE STATUS REGISTER (0) - OFFSET 158H
71
VC RESOURCE CAPABILITY REGISTER (1) - OFFSET 15Ch
72
VC RESOURCE CONTROL REGISTER (1) - OFFSET 160H
72
100 VC RESOURCE STATUS REGISTER (1) - OFFSET 164H
73
101 VC ARBITRATION TABLE REGISTER - OFFSET 170H
73
102 PORT ARBITRATION TABLE REGISTER (0) and (1) - OFFSET 180H and 1C0H
73
103 PCI EXPRESS POWER BUDGETING CAPABILITY REGISTER - OFFSET 20Ch
74
104 DATA SELECT REGISTER - OFFSET 210H
74
105 POWER BUDGETING DATA REGISTER - OFFSET 214H
74
106 POWER BUDGET C APABILITY REGISTER - OFFSET 218H
75
107 ACS EXTENDED CAPABILITY HEADER - OFFSET 220H (Downstream Port Only)
75
108 ACS CAPABILITY REGISTER - OFFSET 224H (Downstream Port Only)
75
109 EGRESS con TROL VEC TOR - OFFSET 228H (Downstream Port Only)
76
110 LTR EXTEN DED CAPABILITY HEADER - OFFSET 230H (Upstream Port Only)
76
111 MAX SNOOP LATENCY REGISTER - OFFSET 234H (Upstream Port Only)
76
112 MAX NO-SNOOP LATENCY REGISTER - OFFSET 234H (Upstream Port Only)
76
Clock Scheme
78
Ieee 1149.1 Compatible Jtag Controller
79
Instruction Register
79
Bypass Register
79
Device ID Register
79
Boundary Scan Register
80
Jtag Boundary Scan Register Order
80
Power Management
82
Power Sequence
83
Electrical and Timing Specifications
84
Absolute Maximum Ratings
84
DC Specifications
84
Ac Specifications
84
Operating Ambient Temperature
86
Power Consumption
86
Pi7C9X2G304Sl
87
Package Information
87
Ordering Information
88

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