Diodes PI7C9X2G304SL Manual
  1. Manuals
  2. Brands
  3. Diodes Manuals
  4. Switch
  5. PI7C9X2G304SL
  6. Manual

Diodes PI7C9X2G304SL Manual

Pci express gen 2 packet switch 3-port, 4-lane, slimpacket pcie 2.0 packet switch
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
PI7C9X2G304SL
PCI EXPRESS GEN 2 PACKET SWITCH
3-Port, 4-Lane, SlimPacket PCIe 2.0 Packet Switch
DATASHEET
REVISION 2-2
September 2017
1545 Barber Lane Milpitas, CA 95035
Telephone: 408-232-9100
FAX: 408-434-1040
Internet:
http://www.diodes.com
Document Number DS39933 Rev 2-2

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the PI7C9X2G304SL and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Diodes PI7C9X2G304SL

Summary of Contents for Diodes PI7C9X2G304SL

  • Page 1 PI7C9X2G304SL PCI EXPRESS GEN 2 PACKET SWITCH 3-Port, 4-Lane, SlimPacket PCIe 2.0 Packet Switch DATASHEET REVISION 2-2 September 2017 1545 Barber Lane Milpitas, CA 95035 Telephone: 408-232-9100 FAX: 408-434-1040 Internet: http://www.diodes.com Document Number DS39933 Rev 2-2...
  • Page 2 LIFE SUPPORT Diodes Incorporated products are speci f ically not authorized for use as critical components in life support devi c es or systems w ithout the express written approval of the Chief Executive Officer of Diodes Incorporated. As used herein: A.
  • Page 3 Updated Table 12-2 DC Electrical Characteristics Added Section 12.4 Operating Ambient Temperature Added Section 12.5 Power Consumption Revision numbering system changed to whole number PI7C9X2G304SL Page 4 of 88 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 4: Table Of Contents

    MAPPIN G EEPROM CONTENTS TO C ONFIGURATION REGISTERS ..........28 INTERFA CE ..............................36 REGISTER DES CRIPTION ................................ 37 REGISTER TYPES................................. 37 TRANSPA RENT MODE CONFIGURATION REGISTERS ................37 PI7C9X2G304SL Page 5 of 88 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...
  • Page 5 TL_CSR – OFFSET 8Ch ...........................53 7.2.54 PHY PARAMETER 3 – OFFSET 90h ......................54 7.2.55 PHY PARAMETER 4 - OFFSET 94h......................54 7.2.56 OPERATION MODE –OFFSET 98h ......................54 PI7C9X2G304SL Page 6 of 88 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...
  • Page 6 7.2.110 LTR EXTEN DED CAPABILITY HEADER – OFFSET 230h (Upstream Port Only) ......77 7.2.111 MAX SNOOP LATENCY REGISTER – OFFSET 234h (Upstream Port Only)........77 7.2.112 MAX NO-SNOOP LATENCY REGISTER – OFFSET 234h (Upstream Port Only) .......77 PI7C9X2G304SL Page 7 of 88 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...
  • Page 7 AC SPECIFICATIONS ..............................85 12.4 OPERATING AM BIENT TEMPERATURE......................87 12.5 POW ER CONSUMPTION............................87 13 PACKAGE INFORMATION............................... 88 14 ORDERING INFORMATION ..............................89 PI7C9X2G304SL Page 8 of 88 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...
  • Page 8 PI7C9X2G304SL TABLE OF FIGURES 5-1 D ............................. 20 IGURE RIVER UTPUT AVEFORM 6-1 SMB PI7C9X2G304SL............... 36 IGURE RCHIT ECTURE MPLEMENTATION ON 11-1 I ..........................84 IGURE NIT IAL OWER EQUENCE 13-1 P ........................... 88 IGURE ACKAGE OUT LINE DRAWING LIST OF TABLES 5-1 R ......................

  • Page 9: Features

    • Low Power Dissipation: 650 mW typical in L0 normal mode • Industrial Temperature Range -40 to 85 • 128-pin LQFP 14mm x 14mm package PI7C9X2G304SL Page 10 of 9 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 10: General Description

    The built-in Integrated Reference Clock Buffer of the PCI Exp ress Switch supports three reference clock outputs. The clock buffer is fro m a single 100MHz clock input, and distributes the clock source to three outputs, which can be PI7C9X2G304SL Page 11 of 10 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...
  • Page 11 PI7C9X2G304SL used by the downstream PCI Express end devices. The clock buffer feature can be enabled and disabled by strapping pin setting. PI7C9X2G304SL Page 12 of 11 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 12: Pin Description

    However, if pin is connected to a board trace and not driven, it is recommended that an external 330-ohm pull-down resistor be used. PI7C9X2G304SL Page 13 of 12 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 13: Port Configuration Signals

    SM Bus Clock: System management Bus Clock. This pin requires an external 5.1K-ohm pull-up resistor. SMBDAT A SM Bus Data: Bi-Directional System Management Bus Data. This pin requires an external 5.1K-ohm pull-up resistor. PI7C9X2G304SL Page 14 of 13 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 14: Jtag Boundary Scan Signals

    When JTAG boundary scan function is not implemented, this pin should be pulled low through a 330-Ohm pull-down resistor. PI7C9X2G304SL Page 15 of 14 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 15: Pow Er Pins

    2, 4, 11, 12, 30, VSS Ground: Used as ground pins. 32, 34, 41, 50, 56, 61, 63, 66, 87, 90, 95, 104, 120, 126,129 PI7C9X2G304SL Page 16 of 15 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 16: Pin Assignments

    SMBDAT A VDDC PET N[0] PWR_SAV CLKBUF_PD T MS PET P[0] VDDC T DI AVDD VDDC T RST _L VDDC PERN[0] VDDR VDDR PERP[0] E_PAD PI7C9X2G304SL Page 17 of 16 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 17: Functional Description

    Thre shold 1.0 us 2.0 us 4.0 us (Recommended) 5.0 us 10 us 20 us 40 us 50 us Multiple lanes could share the PLL. PI7C9X2G304SL Page 18 of 17 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 18: Receiver Signal Detection

    The driver output waveform is the synthesis of amplitude and de-emphasis. The driver amplitude without de-emphasis is specified as a peak differential voltage level (mVpd), and the driver de-emphasis modifies the driver amplitude. PI7C9X2G304SL Page 19 of 18 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 19: Drive Amplitude

    3. At higher amplitudes, actual swings will be less than the theoretical value due to process variations and environment factors, such as voltage overhead compression, package losses, board losses, and other effects. PI7C9X2G304SL Page 20 of 19 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 20: Drive De-Emphasis

    ACK wou ld be flushed out from the buffer. If a NA CK is received or no ACK/NA CK is returned fro m the link partner after the replay timer expires, then a replay mechanism built in DLL transmitter is PI7C9X2G304SL Page 21 of 20 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 21: Transaction Layer Receive Block (Tlp Decapsulation)

    DW, it can be merged with the corresponding NPH into a co mmon queue named NPHD. Except NPHD, each virtual channel (VC0 or VC1) has its own corresponding packet header and data queue. When only VC0 is PI7C9X2G304SL Page 22 of 21 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 22: Nphd

    Table 5-9 Summary of PCI Express Ordering Rules Row Pass Column Posted Re ad Non-posted Write Re ad Non-posted Write Re quest Re quest Re quest Completion Completion Posted Request Yes/No PI7C9X2G304SL Page 23 of 22 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 23: Port Arbitration

    The data lin k layer co mpares the current PI7C9X2G304SL Page 24 of 23 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 24: Transation Layer Transmit Block (Tlp Encapsulation)

    Endpoint, validating every Request transaction between two downstream components and enabling direct routing of peer-to-peer Memory Requests whose addresses have been Translated when ATS system is being used. PI7C9X2G304SL Page 25 of 24 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 25: Eeprom Interface And System Management Bus

    Global XPIP_CSR6[7:5] for Port 0~2 MAC_CT R / Global PHY Parameter 3 for Port 0~2 NFT S / Scramble / XPIP_CSR2 / Deskew mde select for Port 0 PI7C9X2G304SL Page 26 of 25 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...
  • Page 26 XPIP_CSR5[30:24] for Port 1 PM Control Para/Rx Polarity for Port 1 XPIP_CSR5[30:24] for Port 2 PM Control Para/Rx Polarity for Port 2 Reserved Reserved Reserved Reserved Reserved PI7C9X2G304SL Page 27 of 26 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 27: Mapping Eeprom Contents To Configuration Registers

    ADDRESS PCI CFG O FFSET DESCRIPTIO N EEPRO M signature – 1516h 00h ~ 01h Ve ndor ID 02h ~ 03h De vice ID PI7C9X2G304SL Page 28 of 27 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...
  • Page 28 O BFF Capability Enable for Port 0~2 E4h: Bit [18] Bit [15] : enable OBFF capability  74h (Port 0~2) PHY Parameter 0 for Port 0~2 PI7C9X2G304SL Page 29 of 28 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...
  • Page 29 De skew Mode Select for Port 1 68h: Bit [14:13] Bit [9:8]: deskew mode select  78h (Port 1) Scrambler Control for Port 1 PI7C9X2G304SL Page 30 of 29 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...
  • Page 30 F0h: Bit [6] Bit [12]: Selectable De-emphasis  78h (Port 2) Compliance to Detect for Port 2 78h: Bit [11] Bit [13]: compliance to detect  PI7C9X2G304SL Page 31 of 30 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...
  • Page 31 VC0 TC/VC Map for Port 0 154h: Bit [7:1] Bit [15:9]: When set, it indicates the corresponding T C is mapped  into VC0 PI7C9X2G304SL Page 32 of 31 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...
  • Page 32 VGA De code Enable for Port 0 70h: Bit [31] Bit [7]: Enable VGA decode  88h (Port 0) XPIP_CSR5[31:24] for Port 0 88h: Bit [31:24] Bit[15:8]: XPIP_CSR5[31:24] PI7C9X2G304SL Page 33 of 32 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...
  • Page 33 Bit [30:16]: Acknowledge Latency Timer  70h (Port 2) Acknowledge Latency Timer for Port 2 70h: Bit [30:16] Bit [30:16]: Acknowledge Latency Timer  PI7C9X2G304SL Page 34 of 33 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...
  • Page 34 160h (Port 2) TC/VC Map for Port 2 160h: Bit [7:0] Bit [15:8]: When set, it indicates the corresponding T C is mapped  into VC1 PI7C9X2G304SL Page 35 of 34 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 35: Smbus Interface

    The PI7C9X2G304SL p rovides the System Management Bus (SMBus), a two-wire interface through which a simp le device can co mmunicate with the rest of the system. The SM Bus interface on the PI7C9X2G304SL is a bi-d irectional slave interface. It can receive data fro m the SMBus master or send data to the master. The interface allows full access to the configuration registers.

  • Page 36: Register Description

    Replay T ime-out Counter PHY Parameter 0 Switch Modes PHY Parameter 1 XPIP_CSR2 PHY Parameter 2 XPIP_CSR3 XPIP_CSR4 XPIP_CSR5 XPIP_CSR7 XPIP_CSR6 T L_CSR PHY parameter 3 PI7C9X2G304SL Page 37 of 36 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...
  • Page 37 Port Arbitration T able with 128 Phases for VC1 1C0h – 1FCh Reserved 200h – 20Bh Next Capability Offset=220/230h Cap. PCI Express Extended Capability ID=0004h 20Ch Version PI7C9X2G304SL Page 38 of 37 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 38: Vendor Id Register - Offset 00H

    0b: Switch may ignore any parity errors that it detects and continue normal Parity Error operation Response Enable 1b: Switch must take its normal action when a parity error is detected PI7C9X2G304SL Page 39 of 38 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 39: Primary Status Register - Offset 04H

    Set to 1 whenever the primary side of the port in a Switch receives a Poisoned T LP. Detected Parity Error Reset to 0b. PI7C9X2G304SL Page 40 of 39 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 40: Revision Id Register - Offset 08H

    Indicates the number of the PCI bus to which the secondary interface is Secondary Bus connected. T he value is set in software during configuration. 15:8 Number Reset to 00h. PI7C9X2G304SL Page 41 of 40 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 41: Subordinate Bus Number Register - Offset 18H

    Does not apply to PCI Express. Must be hardwired to 0b. Signaled T arget Set to 1 (by a completer) whenever completing a request in the secondary side Abort using Completer Abort Completion Status. PI7C9X2G304SL Page 42 of 41 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 42: Memory Base Address Register - Offset 20H

    7.2.20 PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h FUNCTIO N TYPE DESCRIPTIO N 19:16 64-bit addressing Read as 0001b to indicate 64-bit addressing. PI7C9X2G304SL Page 43 of 42 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 43: Prefetchable Memory Base Address Upper 32-Bits Register - Offset 28H

    CAPABILITY POINTER REGISTER – OFFSET 34h FUNCTIO N TYPE DESCRIPTIO N Pointer points to the PCI power management registers. Capability Pointer Reset to 40h. PI7C9X2G304SL Page 44 of 43 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 44: Interrupt Line Register - Offset 3Ch

    Does not apply to PCI Express. Must be hardwired to 0b. T imeout Master T imeout Does not apply to PCI Express. Must be hardwired to 0b. PI7C9X2G304SL Page 45 of 44 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 45: Power Management Capability Register - Offset 40H

    12:9 Data Select Reset to 0h. 14:13 Data Scale Reset to 00b. PME status Read as 0b as the PME# message is not implemented. PI7C9X2G304SL Page 46 of 45 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 46: Ppb Support Extensions - Offset 44H

    If the message enable bit is set, the contents of this register specify the DWORD aligned address for MSI memory write transaction. 31:2 Message Address Reset to 0000_0000h. PI7C9X2G304SL Page 47 of 46 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 47: Message Upper Address Register - Offset 54H (Downstream Port Only)

    VENDOR SPECIFIC CAPABILITY REGISTER – OFFSET 64h FUNCTIO N TYPE DESCRIPTIO N Enhanced Read as 09h to indicate that these are vendor specific capability registers. Capabilities ID PI7C9X2G304SL Page 48 of 47 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 48: Xpip Csr0 - Offset 68H (Test Purpose Only)

    SMBus or auto-loading from EEPROM. Latency Reset to 0b. Enable the VGA range decode. VGA Decode Enable Reset to 1b. PI7C9X2G304SL Page 49 of 48 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 49: Switch Operation Mode - Offset 74H (Upstream Port)

    C_DRV_LVL_3P5_ EEPROM. 20:16 Reset to 1_0011b. T he default value may be changed by SMBus or auto-loading from C_DRV_LVL_6P0_ EEPROM. 25:21 Reset to 1_0011b. PI7C9X2G304SL Page 50 of 49 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 50: Switch Operation Mode - Offset 74H (Downstream Port)

    T he default value may be changed by SMBus or auto-loading from EEPROM. C_EMP_POST _ 30:26 GEN2_6P0_NOM Reset to 1_1101b. Reserved RsvdP Not Support. PI7C9X2G304SL Page 51 of 50 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 51: Phy Parameter 2 - Offset 7Ch

    XPIP_CSR4 – OFFSET 84h FUNCTIO N TYPE DESCRIPTIO N T he default value may be changed by SMBus or auto-loading from EEPROM. 31:0 XPIP_CSR4 Reset to 0000_0000h. PI7C9X2G304SL Page 52 of 51 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 52: Xpip_Csr5 - Offset 88H

    RsvdP Not Support. XPIP_CSR6 Value. T he default value may be changed by SMBus or auto- loading from EEPROM. 23:16 XPIP_CSR6 Reset to 79h. PI7C9X2G304SL Page 53 of 52 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 53: Phy Parameter 3 - Offset 90H

    SSID/SSVID CAPABILITY REGISTER – OFFSET B0h FUNCTIO N TYPE DESCRIPTIO N SSID/SSVID Read as 0Dh to indicate that these are SSID/SSVID capability registers. Capabilities ID PI7C9X2G304SL Page 54 of 53 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 54: Subsystem Id Register - Offset B4H

    Value of this bit will be output to GPIO [3] pin if GPIO [3] is configured as GPIO [3] Output an output pin. Register Reset to 0b. Reserved RsvdP Not Support. GPIO [4] Input State of GPIO [4] pin. PI7C9X2G304SL Page 55 of 54 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 55: Eeprom Control Register - Offset Bch (Upstream Port Only)

    1b: EEPROM autoload occurred successfully after PREST . Configuration EEPROM Autoload registers were loaded with values stored in the EEPROM Status Reset to 0b. PI7C9X2G304SL Page 56 of 55 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 56: Eeprom Address Register - Offset Bch (Upstream Port Only)

    Reset to the status of SLOT_IMP strapped pin. Interrupt Message Read as 0b. No MSI messages are generated in the transparent mode. 29:25 Number 31:30 Reserved RsvdP Not Support. PI7C9X2G304SL Page 57 of 56 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 57: Device Capabilities Register - Offset C4H

    1b: Enable Non-Fatal Error Reporting Reporting Enable Reset to 0b. 0b: Disable Fatal Error Reporting Fatal Error Reporting 1b: Enable Fatal Error Reporting Enable Reset to 0b. PI7C9X2G304SL Page 58 of 57 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 58: Device Status Register - Offset C8H

    RW1C Control register. Request Detected Reset to 0b. Asserted when the AUX power is detected by the Switch AUX Power Detected Reset to 1b. PI7C9X2G304SL Page 59 of 58 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 59: Link Capabilities Register - Offset Cch

    SMBus or auto-loading from EEPROM. 31:24 Port Number Reset to 00h for Port 0. Reset to 01h for Port 1. Reset to 02h for Port 2. PI7C9X2G304SL Page 60 of 59 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 60: Link Control Register - Offset D0H

    T his bit is cleared by hardware upon successful training of the link to the L0 T raining Error link state. Reset to 0b. PI7C9X2G304SL Page 61 of 60 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 61: Slot Capabilities Register (Downstream Port Only) - Offset D4H

    Power Limit Value. Writes to this register also cause the Port to send the Slot Power Limit Set_Slot_Power_Limit message. T he default value may be changed by 16:15 Scale SMBus or auto-loading from EEPROM. Reset to 00b. PI7C9X2G304SL Page 62 of 61 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 62: Slot Control Register (Downstream Port Only) - Offset D8H

    Data Link Layer Link Active State Changed field is changed. Enable Reset to 0b. 15:13 Reserved RsvdP Not Support. PI7C9X2G304SL Page 63 of 62 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 63: Slot Status Register (Downstream Port Only) - Offset D8H

    Device Control 2 Reset to 000h. Enable LT R Mechanism. LT R Mechanism Enable Reset to 0b. 12:11 Device Control 2 Reset to 00b. PI7C9X2G304SL Page 64 of 63 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 64: Devide Status Register 2 - Offset E8H

    Slot Capabilities 2 Reset to 0000_0000h. 7.2.80 SLOT CONTORL REGISTER 2 – OFFSET F8h FUNCTIO N TYPE DESCRIPTIO N 15:0 Slot Control 2 Reset to 0000h. PI7C9X2G304SL Page 65 of 64 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 65: Slot Status Register 2 - Offset F8H

    Reset to 0b. When set, indicates that an ACS Violation event has occurred ACS Violation RW1CS Status Reset to 0b. 31:21 Reserved RsvdP Not Support. PI7C9X2G304SL Page 66 of 65 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 66: Uncorrectable Error Mask Register - Offset 108H

    T raining Error 1b: Fatal Severity Reset to 1b. Reserved RsvdP Not Support. 0b: Non-Fatal Data Link Protocol 1b: Fatal Error Severity Reset to 1b. PI7C9X2G304SL Page 67 of 66 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 67: Correctable Error Status Register - Offset 110 H

    11:9 Reserved RsvdP Not Support. When set, the Replay Timer Timeout event is detected. Replay T imer RW1CS T imeout Status Reset to 0b. PI7C9X2G304SL Page 68 of 67 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 68: Correctable Error Mask Register - Offset 114 H

    Capable Reset to 1b. When set, the function of checking ECRC is enabled. ECRC Check Enable Reset to 0b. 31:9 Reserved RsvdP Not Support. PI7C9X2G304SL Page 69 of 68 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 69: Header Log Register - Offset From 11Ch To 128H

    Robin arbitration with 32 phases in LPVC. Capability Reset to 03h if offset 144h.bit[0]=1. Reset to 00h if offset 144h.bit[0]=0. 23:8 Reserved RsvdP Not Support. PI7C9X2G304SL Page 70 of 69 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 70: Port Vc Control Register - Offset 14Ch

    Isochronous traffic. The default value may be changed by auto-loading from Maximum T ime 22:16 EEPROM. Slots Reset to 7Fh. Reserved RsvdP Not Support. PI7C9X2G304SL Page 71 of 70 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 71: Vc Resource Control Register (0) - Offset 154H

    When set, it indicates that the VC resource is still in the process of VC Negotiation negotiation. This bit is cleared after the VC negotiation is complete. Pending Reset to 0b. 31:18 Reserved RsvdP Not Support. PI7C9X2G304SL Page 72 of 71 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 72: Vc Resource Capability Register (1) - Offset 15Ch

    Reset to 000b if offset 144h.bit[0]=0. 30:27 Reserved RsvdP Not Support 0b: disables this Virtual Channel 1b: enables this Virtual Channel VC Enable Reset to 0b. PI7C9X2G304SL Page 73 of 72 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 73: 100 Vc Resource Status Register (1) - Offset 164H

    [95:94] [93:92] [91:90] [89:88] [87:86] [85:84] [83:82] [81:80] Phase Phase Phase Phase Phase Phase Phase Phase [111:110] [109:108] [107:106] [105:104] [103:102] [101:100] [99:98] [97:96] PI7C9X2G304SL Page 74 of 73 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 74: 103 Pci Express Power Budgeting Capability Register - Offset 20Ch

    Reset to 111b. It specifies the power rail of the given operation condition. 20:18 Power Rail Reset to 010b. 31:21 Reserved RsvdP Not Support. PI7C9X2G304SL Page 75 of 74 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 75: 106 Power Budget C Apability Register - Offset 218H

    Enable ACS T ranslation Blocking. ACS T ranslation Blocking Enable Reset to 0b. Enable ACS P2P Request Redirect. ACS P2P Request Redirect Reset to 0b. PI7C9X2G304SL Page 76 of 75 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 76: 109 Egress Con Trol Vec Tor - Offset 228H (Downstream Port Only)

    FUNCTIO N TYPE DESCRIPTIO N .Specifies the maximum no-snoop latency that a device is permitted to request Max No-Snoop 25:16 Latency Value Reset to 000h. PI7C9X2G304SL Page 77 of 76 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...
  • Page 77 T his register provides a scale for the value contained within the Maximum Max No-Snoop No-Snoop Latency Value field 28:26 Latency Scale Reset to 000b 31:29 Reserved RsvdP Not Support. PI7C9X2G304SL Page 78 of 77 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 78: Clock Scheme

    When CLKBUF_PD p in is asserted high, the clock buffer is in power down mode and disabled. The 100M Hz Reference Clock Output Pairs are disabled, and The PI7C9X2G304SL requires 100M Hz d ifferential clock inputs through REFCLKP and REFCLKN Pins as shown in the following table.

  • Page 79: Ieee 1149.1 Compatible Jtag Controller

    An IEEE 1149.1 co mpatib le Test Access Port (TAP) controller and associated TAP pins are provided to support boundary scan in PI7C9X2G304SL for board-level continuity test and diagnostics. The TAP pins assigned are TCK, TDI, TDO, TMS and TRST_L. All digital input, output, input/output pins are tested except TAP pins.

  • Page 80: Boundary Scan Register

    The boundary scan register has a set of serial shift-register cells. A chain of boundary scan cells is formed by connected the internal signal of the PI7C9X2G304SL package pins. The VDD, VSS, and JTA G pins are not in the boundary scan chain.
  • Page 81 Re giste r Numbe r Pin Name Ball Location Type Tri-state Control Ce ll Internal Control Internal CLKBUF_PD Birdir Internal Internal Internal EECLK Output2 EEPD Birdir Control PI7C9X2G304SL Page 82 of 81 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 82: Power Management

    VDDCAUX and VA UX with the au xiliary power supplies to maintain all necessary informat ion to be restored to the full power D0 state. PI7C9X2G304SL has been designed to have sticky registers that are powered by au xiliary power supplies.

  • Page 83: Power Sequence

    Aux and Main power rails. Figure 11-1 Initial Power-Up Sequence Power-down sequence is the reverse of power-up sequence PI7C9X2G304SL Page 84 of 83 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 84: Electrical And Timing Specifications

    Table 12-3 PCI Express Interface - Differential Transmitter (TX) Output (5.0 Gbps) Characteristics Parameter Symbol Unit Unit Interval 199.94 200.0 200.06 Differential p-p TX voltage swing TX-DIFF-P-P Low power differential p-p TX voltage TX-DIFF-P-P-LOW PI7C9X2G304SL Page 85 of 84 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...
  • Page 85 Differential RX Peak-to-Peak Voltage 1200 RX-DIFF-PP-CC T otal jitter tolerance 0.68 Receiver DC common mode impedance Ω RX-DC RX AC Common Mode Voltage RX-CM-AC-P PI7C9X2G304SL Page 86 of 85 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 86: Operating Ambient Temperature

    - Ambient T emperature at 25 - Power consumption in the table is a reference, be affected by various environments, bus traffic and power supply etc. PI7C9X2G304SL Page 87 of 86 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...

  • Page 87: Pi7C9X2G304Sl

    PI7C9X2G304SL PACKAGE INFORMATION The package of PI7C9X2G304SL is a 14mm x 14mm LQFP (128 Pin) package. The fo llowing are the package information and mechanical dimension: Figure 13-1 Package outline drawing PI7C9X2G304SL Page 88 of 87 September 2017 www.diodes.com Document Number DS39933 Rev 2-2...

  • Page 88: Ordering Information

    14mm x 14mm PI 7C 9X2G304SL FD E X Tape & Reel Pb-Free and Green Package Code Blank=Standard =Revision Device Type Device Number Family Pericom PI7C9X2G304SL Page 89 of 88 September 2017 www.diodes.com Document Number DS39933 Rev 2-2 © Diodes Incorporated...
  • Page 89 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Diodes Incorporated PI7C9X2G304SLAFDE PI7C9X2G304SLAFDEX PI7C9X2G304SLBFDEX PI7C9X2G304SLBFDE PI7C9X2G304SLBQFDE PI7C9X2G304SLBQFDEX...

Table of Contents