Dialog Semiconductor DA6021 Manuals

Manuals and User Guides for Dialog Semiconductor DA6021. We have 1 Dialog Semiconductor DA6021 manual available for free PDF download: Manual

Dialog Semiconductor DA6021 Manual (225 pages)

HIGHLY INTEGRATED POWER MANAGEMENT IC FOR INTEL ATOM Z3000 PROCESSOR

Brand: Dialog Semiconductor | Category: Network Hardware | Size: 4 MB

Table of Contents
3
Figure 1: Overview Diagram
17
Figure 2: Detailed Block Diagram
18
Table 1: DA6021 Absolute Maximum Ratings
19
Table 2: DA6021 Recommended Operating Conditions
19
Figure 3: Maximum Allowed Peak Power
20
Table 3: Abbreviations of Validation Status
20
Table 4: Pin Description
25
Table 5: Pin Type Definition
25
Sdmmc3_Pwr_En_B
28
Modem_Off_B
28
Sdwn_B
28
Usbrst_B
28
Gpios
28
Burst Control Unit
29
Pwm[2:0]
29
Display
29
Adc
29
DA6021 Power States
30
Figure 4: DA6021 Power States
30
Figure 5: VSYS Areas
31
Table 6 : G3 State Transition
31
Table 7: SOC_G3 State Transition
31
Soc Power States
32
SOC_S0 State
32
Figure 6: Soc Power States
32
SOC S0Ix State
33
Table 8:SOC S0 State Transition
33
SOC S3 State
34
Table 9: SOC S0Ix State Transition
34
Table 10: SOC S3 State Transition
34
SOC S4 State
35
Truth Table of Sleep Signals and DA6021 Final Power States
35
Table 11: SOC S4 State Transition
35
Table 12: Truth Table of Sleep Signals and DA6021 Final Power States
35
DA6021 Power State Transitions and Sleep Signals
36
Table 13: DA6021 State Transition and Sleep Signals
36
Register File and Address Range
37
Slave ID Versus DA6021
37
Figure 7: Address Range and Pages
37
Table 14: Slave ID Versus DA6021 Storage Page
37
10. Power Controller State Machine
38
Overview
38
Power State Transitions
38
Figure 8: State Transitions
38
Sequencing
39
Table 15:U2 & D2 Event Generation Table
39
DA6021 Power Sequences
40
Cold Boot
41
Table 16: Cold Boot Triggers
42
Table 17: Truth Table of Cold Boot Triggers
42
Figure 9: Cold Boot Power Sequencing Diagram, Valid Battery Insertion
43
Table 18: Cold Boot Timings
45
Warm Reset Sequence
46
Enter SOC S0Ix Mode
46
Figure 10: Enter S0Ix Sequencing Diagram (VCCAPWROKCFG=1)
47
Figure 11: Enter S0Ix Sequencing Diagram (VCCAPWROKCFG=0)
48
Exit SOC S0Ix Mode
49
Table 19: Enter S0Ix Timing
49
Figure 12: Exit S0Ix Sequencing Diagram (VCCAPWROKCFG=1)
50
Figure 13: Exit S0Ix Sequencing Diagram (VCCAPWROKCFG=0)
51
Enter SOC S3 Mode
52
Table 20: Exit S0Ix Timing
52
Figure 14: Enter S3 Sequencing Diagram
53
Exit SOC S3 Mode
54
Figure 15: Exit S3 Sequencing Diagram
54
Enter SOC S4 Mode
55
Figure 16: Enter S4 Sequencing Diagram
55
Exit SOC S4 Mode
56
Figure 17: Exit S4 Sequencing Diagram
56
Cold off
57
Table 21: Cold off Triggers
57
Figure 18: Cold off Power Sequencing Diagram (SUSPWRDNACKCFG=1)
58
Table 22: Cold off Sequencing Timing
61
Figure 19: Power Button Forced Cold off
62
Figure 20: Catastrophic Event (Except VSYSOVP) Shutdown Sequence
63
Figure 21: VSYSOVP Shutdown Sequence
63
Table 23: Catastrophic Event (Except VSYSOVP) Shutdown Sequence
63
Table 24: VSYSOVP Shutdown Timing
63
Modem Reset Sequence
64
Figure 22: Modem Reset Sequencing Diagram
64
Table 25: Modem Reset Timing Intervals
64
PMIC Resets
65
Wake Events
65
Table 26 : PMIC Reset Sources
65
11. Platform Power Domains
66
Power Domains Summary
66
Table 27: Power Domains
67
Voltage Rail ON/OFF on Various Power States
68
PMIC Current Consumption in Various States
68
Table 28: Status Power Domains
68
Table 29: PMIC Current Consumption
68
Voltage Rail Control Mechanism
69
SVID Interface
69
SVID DC Electrical Parameters
69
Table 30: VCC & VNN Addresses
69
Table 31: SVID DC Electrical Characteristics
69
VCLK Timing Parameters
70
Figure 23: Definition of VHYS
70
Table 32: SVID Buffer AC Electrical Parameters
70
Table 33: VCLK AC Timing Parameters
70
Data Sampling and Timing
71
Figure 24: Measurement Points for VCLK
71
Figure 25: Soc Driving Timing Definition
72
Figure 26: DA6021 Driving Timing Definition
72
SVID Command Set
73
Table 34: SVID Supported Commands
73
SVID Register Set
74
Table 35: SVID Supported Registers
75
VID DAC Table
78
Table 36: VID Values
78
Low Power State Control Signals
79
Power Supplies
79
DC/DC Buck Regulator VCC
79
Figure 27: VCC Block Diagram
79
Figure 28: VCC Timings
80
Figure 29: VCC Efficiency
81
Table 37: Electrical Parameters for BUCK_VCC
81
DC/DC Buck Regulator VNN
82
Figure 30: Buck VNN Block Diagram
82
Figure 31: VNN Efficiency
83
Table 38: Electrical Parameters for BUCK_VNN
83
DC/DC Buck Regulator V1P0A
84
Figure 32: V1P0A Power Rail Block Diagram
84
Table 39: Electrical Parameter for BUCK_V1P0A
85
Figure 33: V1P0A Efficiency
86
Table 40: V1P0A Truth Table
87
Table 41: V1P0S_EN Truth Table
87
Table 42: V1P0SX_EN Truth Table
88
DC/DC Buck Regulator V1P05S
89
Figure 34: Buck V1P05S Block Diagram
89
Table 43: VDDQ_VTT Truth Table
89
Table 44: Electrical Parameter for VDDQ_VTT
89
Table 45: Electrical Parameter for BUCK_V1P05S
90
Figure 35: V1P05S Efficiency
91
DC/DC Buck Regulator V1P8_A
92
Figure 36: Buck V1P8A Power Rail Block Diagram
92
Table 46: V1P05S Truth Table
92
Figure 37: V1P8A Efficiency
93
Table 47: Electrical Parameter for BUCK_V1P8A
93
Table 48: V1P8A Truth Table
94
Table 49: V1P8U_EN_B Truth Table
95
Table 50: V1P8S Power Switch Specification
95
Table 51: V1P8S Truth Table
95
Table 52: V1P8S Power Switch Specification
96
Table 53: V1P8SX Truth Table
96
Table 54: Electrical Parameter for V1P2A
97
DC/DC Buck Regulator VDDQ
98
Figure 38: VDDQ Power Domain Block Diagram
98
Table 55: Electrical Parameter for VREFDQ1/2
98
Table 56: Electrical Parameter for BUCK_VDDQ
99
Figure 39: VDDQ Efficiency
100
Table 57: VDDQ Truth Table
101
Table 58: V1P2S Power Switch Specification
101
Table 59: Electrical Parameter for V1P2S LDO
101
Table 60: V1P2S Truth Table
102
Table 61: V1P2SX Power Switch Specification
102
Power Rail VSYSU
103
Table 62: V1P2SX Truth Table
103
Table 63: VSYSU_EN_B Truth Table
103
Power Rail VSYS_SX
104
Table 64: VSYSSX_EN_B Truth Table
104
Power Rail VSYS_S
105
Buck Boost Regulator V2P85S
105
Figure 40: Buck Boost V2P85S Power Domain Block Diagram
105
Table 65: VSYS_S Power Switch Specification
105
Table 66: VSYS_S Truth Table
105
Table 67: Electrical Parameter for BUCKBOOST_V2P85S
106
Figure 41: V2P85S Efficiency
107
Table 68: V2P85S Truth Table
107
Table 69: V2P85SX Power Switch Specification
108
Table 70: V2P85SX Truth Table
108
Buck Boost Regulator V3P3A
109
Figure 42:V3P3A Power Domain Block Diagram
109
Figure 43:V3P3A Efficiency
110
Table 71: Electrical Parameter for BUCKBOOST_V3P3A
110
Table 72: V3P3A Truth Table
111
Table 73: V3P3U_EN_B Truth Table
111
Table 74: V3P3S_EN_B Truth Table
112
Table 75: VUSBPHY Power Switch Specification
112
Boost Regulator V5P0S
113
Figure 44:V5P0S Power Domain Block Diagram
113
Table 76: VSDIO Power Switch Specification
113
Table 77: VSDIO Output Voltage Selection
113
Figure 45:V5P0S Efficiency
114
Table 78: Electrical Parameter for BOOST_V5P0S
114
Table 79: V5P0S Truth Table
115
Table 80: VHOST_EN Truth Table
116
Table 81: VHOST External Power Switch Driver Capability
116
Table 82: VBUS_EN Truth Table
116
Table 83: VBUS External Switch Driver Capability
116
VLP Low Power Regulator
117
Table 84: VHDMI Power Switch Specification
117
Table 85: VHDMI Truth Table
117
Current Monitor
118
Figure 46: Current Measurement Tolerance Boundary
118
Table 86: Electrical Parameter for LDO_LP
118
Table 87: Current Measurement Resolution
118
VCC/VNN Current Vs ADC Data
119
Figure 47: VCC/VNN ADC Current Coding
119
Figure 48: Typical VCC Current Sensing Error
119
Figure 49: Typical VNN Current Sensing Error
119
V1P0A Current Vs ADC Data
120
Figure 50: V1P0A ADC Current Coding
120
Figure 51: Typical V1P0A Current Sensing Error
120
V1P5S Current Vs ADC Data
121
Figure 52: V1P05S ADC Current Coding
121
Figure 53: Typical V1P05S Current Sensing Error
121
VDDQ Current Vs ADC Data
122
Figure 54: VDDQ ADC Current Coding
122
Figure 55: Typical VDDQ Current Sensing Error
122
12. I2C Interface
123
Overview
123
Slave Addresses
123
Protocol
123
Figure 56: I2C Fast Speed Write
123
Table 88: I2C Slave Addresses
123
Electrical Requirements
124
Figure 57: I2C Fast Speed Read
124
Figure 58: High Speed Write
124
Figure 59: High Speed Read
124
Table 89: I2C Signal Electrical Specification
124
13. External EEPROM Controller
125
Overview
125
Electrical Characteristics
125
Functions
125
Table 90: EEPROM Signal Electrical Specifications
125
14. Power Source Detection
126
Overview
126
VBAT Power Source Detection
126
Battery Voltage Monitor & Removal / Insertion Detection
126
Figure 60: VBAT Input Detection
126
Battery Pack Interface
127
Figure 61: Battery Single Wire Block Diagram for Analog Sensing, Digital Communication
127
Table 91: BATID Comparator Threshold
127
Table 92: VBAT Removal Comparator Threshold
127
Battery Presence Detection
128
BSI Sensing
128
Digital Battery Communications
128
Table 93: BATID Electrical Specification
128
Table 94: Digital Battery Interface Specification
128
System Voltage Monitor
129
VBUS Power Source Detection
129
Figure 62: VSYS Valid Input Power Detection
129
Figure 63: USB Detection
129
Table 95: VSYSREF Definition
129
VDCIN Power Source Detection Comparators
130
Figure 64: DCIN Detection
130
Table 96: VBUS Detection, Analog Electrical Parameters
130
BATLOW Definition
131
Figure 65: Valid Battery Thresholds
131
Table 97: VDCIN Detection, Analog Electrical Parameters
131
Power Source Detection Events
132
Wake-Up Logic
132
Table 98: System Wake-Up Condition
132
DA6021 Catastrophic and Critical Events
133
Power Source Registers
134
15. Analog-To-Digital Converter
139
Electrical Characteristics
139
Analog Overview
140
Table 99: ADC Electrical Charakteristics
140
ADC Measurement Support
141
Preamplifier
141
Table 100: ADC Channel Overview
141
ADC Sequencer
142
Manual Measurements
142
Table 101: ADC Channel Data Format
142
Reference Source
145
Event and Status Generation
145
Result Register
146
CH0: Battery Pack Voltage
146
CH1: Battery ID Resistance
146
CH2: die Temperature
146
CH3-4: Battery Pack Temperature
146
CH5-7: System Temperature Thermistor
147
CH8-12: VR Current Measurement
147
CH8: VSYS Voltage Measurements
147
ADC Registers
148
16. System Voltage & Temperature Monitoring
153
Overview
153
SVTM Block Diagram
158
Functional Description
158
VSYS Input Trip Points for ADC Measurement
158
Figure 66: SVTM Block Diagram
158
VSYS Related Output Control
160
Figure 67: BCU Warning Flag Generation
161
Figure 68: VSYS Trip Points Flag Logic
164
Under- & Over- Voltage Condition
165
Permanent Temperature Monitoring
165
Table 102: VSYS Event Table
165
Temperature Monitoring Via ADC
166
Critical Thermal Events
175
System Temperature
175
Battery Critical Temperature
176
DA6021 die Temperature
176
Thermal Monitoring Event Table
177
Backup Battery Management
177
Table 103: Thermal Monitoring Events
177
Backup Battery Charger
178
Power Consumption
178
17. General Purpose Ios
179
Overview
179
Analog Block, Control & Data Signals
179
Figure 69 : GPIO Block Diagram
179
GPIO Digital Features
180
Bouncing
180
Status Register
180
Interrupt Functionality
180
Analogue Mode
180
Alternative Functions
180
Table 104: GPIO Direction Configuration
180
Table 105: GPIO Pull-Up/Pull-Down Configuration
180
Defining an Output Value
181
Supported Alternate Functions
181
Gpio0P0 - Batidin
181
Gpio0P1 - Batidout
181
Gpio0P2 - Gpio0P7-Pcsmcnt
181
Gpio1P0 - Uibtn_B
181
Gpio1P1 - Clk32Out
181
Gpio1P2 - Trig1
181
Gpio1P3 - Trig2
181
Gpio1P4 - Wake1
181
Electrical Characteristics
182
GPIO Registers
182
Table 106: GPIO 1.8V Electrical Specification
182
Table 107: GPIO 3.3V Electrical Specification
182
18. External Battery Charger Control
188
Overview
188
Charger Current Limit
188
External Charger Control Signals
188
Table 108: External Charger Current Limits
188
Table 109: Charger Control Pins
188
Battery Charger Registers
189
19. Interrupt Controller
190
Overview
190
First Level Interrupt
190
Second Level Interrupt
190
Figure 70: 1St Level Interrupts
190
Critical Race Condition (Set Vs. Clear)
193
Interrupt Controller Registers
193
Table 110: Second Level Interrupts
193
20. Power Button & Utility Button
195
Overview
195
Power/Utility Button Block Diagram
195
PWRBTNIN_B Electrical Parameters
195
Figure 71 : Power/Utility Button Detection Logic
195
Power Button
196
Power Button Cold Boot Flow Diagram
196
Figure 72: Power Button Boot Flow Diagram
196
Force a Cold off Sequence
197
Force Cold off Flow Diagram
197
Uibtn_B
197
Figure 73: Power Button Cold off Flow Diagram
197
Power Button Registers
198
21. Pulse Width Modulation Generation
200
Overview
200
Functional Description
200
PWM Output Signals
200
PWM Registers
200
Table 111: PWM Output Signals
200
22. Panel Control
203
Overview
203
Functional Description
203
Debug Ports
204
SVID Debug Port
204
Figure 74: SVID Debug Port Bus Diagram
204
Table 112: SVID Debug Port Truth Table
204
I2C Debug Port
205
Figure 75: I2C Debug Port Bus Diagram
205
Table 113: I2C Debug Port Truth Table
206
24. Register Map
207
Table 114: DA6021 Register Map
209
25. Package Information
210
DA6021 Package Details
210
Pin Description, Pin out
210
Ball Order
210
DA6021 325 Pin FCBGA Package
218
Component Marking
219
Package Outline
219
Soldering Profile
220
Figure 76: Package Outline Drawing and Dimensions
220

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