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Dialog Semiconductor DA6021 Manual

Highly integrated power management ic for intel atom z3000 processor
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DA6021
HIGHLY INTEGRATED POWER MANAGEMENT IC FOR
INTEL® ATOM™ Z3000 PROCESSOR
1. General Description
The DA6021 PMIC is a monolithic single chip power management IC for Intel® Atom™ Z3000 processor. It
provides all power supplies for tablet PC's and can also be used in multiple embedded applications as well as
Netbooks and Nettops. It is designed to support platforms based on Intel's Z3000 Atom processor series,
including DDR3 memory and various peripherals.
Integrated power management
Dialog Semiconductor's new DA6021 uses a single supply voltage at a wide range of input voltage and provides
low noise supplies to all SoC voltage domains, DDR3 memory and many peripherals.
The DA6021 integrates 6 high performance low dropout (LDO) voltage regulators using Dialog's patented Smart
Mirror™ technology for very low quiescent current. It includes 11 internal power switches and the control logic for
9 external switching devices. These include in-rush current control for platform power distribution simplification.
Six fully integrated high efficiency DC-DC buck converters provide current to Intel Atom platform's various low
voltage domains as well as to the memory and the peripherals. Two buck-boost and one boost converter also
supply energy for the platform. All nine regulators are designed to support external component height of 1mm.
Ultra flexible power sequencer
The ultra-flexible power sequencer takes care of the complete platform start-up, state-transitioning and power-
down procedure. The DA6021 operates autonomously and reduces the power consumption when entering
stand-by or power down mode. The DA6021 is fully programmable and allows adaption to all Intel Atom
processor Z3000 and platform sequences. The OTP programmed power sequence is copied into operational
registers during power-up. Those registers can be overwritten by EEPROM after initial OTP copy routine or via
operational processor.
Auxiliary function
An analogue to digital converter (ADC) with 10-bit resolution combined with a multi-channel input multiplexer
allows measurement of the input supply voltage, battery ID, PMIC die temperature as well as 5 battery pack &
system temperatures. The number of external components is significantly reduced due to the integration of 16
GPIO's, 3 channel PWM output signal generators, a multi-input detector with a charger control as well as a
programmable IRQ controller.
2. Key Features
■
Two high efficiency buck converters with
integrated SVID interface running IMVP-7
protocol. These two quad phase DC/DC
regulators generate the voltages for CPU and
graphic cores
■
One dual phase buck regulator for memory
supply supporting DDR3-L and -LP memory types
■
3 single phase buck regulators supplying 1.0V,
1.05V and 1.8V towards the platform
■
2 buck-boost converters generating 2.85V and
3.3V for the platform even if the input supply is
down to 2.7V
■
Boost converter providing 5V for the USB
components
■
3 LDOs with fixed output voltage
■
2 LDO with programmable output voltage
■
1 push-pull LDO used for DDR3 address line
termination
■
11 integrated power rail switching devices
■
9 external power rail switching devices
Data Sheet
© 2014 Dialog Semiconductor GmbH
■
Ultra flexible power sequencer programmable via
OTP/ EEPROM and register
■
I2C communication interface for SoC access
■
EEPROM interface for optional OTP over-writing
■
16 general purpose I/Os with alternate functions
■
16 channel 10-bit ADC including conditioning
circuits and programmable flexible sequencing for
automatic and manual measurements
■
System voltage and temperature monitoring,
supervising
■
Programmable IRQ controller
■
1-wire digital battery interface including 2-wire
conversion
■
3 channel PWM signal generation, flexible
frequency and duty cycle programmable
■
Input power source detection, included with
charger control
Version 3.A - Final
1 of 224
Company Confidential
31-Jan-14
www.dialog-semiconductor.com

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Summary of Contents for Dialog Semiconductor DA6021

  • Page 1 DDR3 memory and various peripherals. Integrated power management Dialog Semiconductor’s new DA6021 uses a single supply voltage at a wide range of input voltage and provides low noise supplies to all SoC voltage domains, DDR3 memory and many peripherals.
  • Page 2 COREPWROK ....................... 27 9.1.23 SUSPWRDNOK ......................27 9.1.24 BATLOW_B........................27 9.1.25 SUSCLK ......................... 28 9.1.26 THERMTRIP_B ......................28 9.1.27 PROCHOT_B ......................... 28 9.1.28 SDMMC3_1P8_EN ......................28 Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 2 of 224 www.dialog-semiconductor.com...

  • Page 3: Table Of Contents

    SOC S3 State......................... 34 9.3.4 SOC S4 State......................... 35 9.3.5 Truth Table of Sleep Signals and DA6021 Final Power States ........35 9.3.6 DA6021 Power State Transitions and Sleep Signals ............ 36 Register File and Address Range ....................37 9.4.1 Slave ID versus DA6021 Pages ..................
  • Page 4 VDCIN Power Source Detection Comparators ................ 130 14.5 BATLOW Definition ........................131 14.6 Power Source Detection Events ....................132 14.7 Wake-Up Logic ......................... 132 Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 4 of 224 www.dialog-semiconductor.com...
  • Page 5 DA6021 Company Confidential HIGHLY INTEGRATED POWER MANAGEMENT IC FOR INTEL® ATOM™ Z3000 PROCESSOR 14.8 DA6021 Catastrophic and Critical Events ................133 14.9 Power Source Registers ......................134 15. Analog–to–Digital Converter ......................139 15.1 Electrical Characteristics ......................139 15.2 Analog Overview ........................140 15.2.1...
  • Page 6 22. Panel Control ............................ 203 22.1 Overview ..........................203 22.2 Functional Description ......................203 23. Debug Ports ............................204 23.1 SVID Debug port ........................204 Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 6 of 224 www.dialog-semiconductor.com...
  • Page 7 DA6021 Package Details ......................210 25.1.1 Pin Description, Pin Out ....................210 25.1.2 Ball Order ........................210 25.2 DA6021 325 Pin FCBGA Package ................... 218 25.3 Component Marking ......................... 219 25.4 Package Outline ........................219 25.5 Soldering Profile ........................220 Data Sheet Version 3.A - Final...
  • Page 8 Figure 23: Definition of VHYS ........................70 Figure 24: Measurement Points for VCLK ....................71 Figure 25: SoC Driving Timing Definition ....................72 Figure 26: DA6021 Driving Timing Definition ..................... 72 Figure 27: VCC Block Diagram ........................79 Figure 28: VCC Timings ..........................80 Figure 29: VCC Efficiency...........................
  • Page 9 Figure 74: SVID Debug Port Bus Diagram ....................204 Figure 75: I2C Debug Port Bus Diagram ....................205 Figure 76: Package Outline Drawing and Dimensions ................220 Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 9 of 224 www.dialog-semiconductor.com...
  • Page 10 Table 10: SOC S3 State Transition ......................34 Table 11: SOC S4 State Transition ......................35 Table 12: Truth Table of Sleep Signals and DA6021 Final Power States ..........35 Table 13: DA6021 State Transition and Sleep Signals ................36 Table 14: Slave ID versus DA6021 Storage Page ..................
  • Page 11 Table 110: Second Level Interrupts ......................193 Table 111: PWM Output Signals ......................200 Table 112: SVID Debug Port Truth Table ....................204 Table 113: I2C Debug Port Truth Table ....................206 Table 114: DA6021 Register Map ......................209 Data Sheet Version 3.A - Final 31-Jan-14 ©...
  • Page 12 DA6021 Company Confidential HIGHLY INTEGRATED POWER MANAGEMENT IC FOR INTEL® ATOM™ Z3000 PROCESSOR Table 115: DA6021 Ball Order ......................... 217 Table 116: Soldering Profile ........................221 Table 117: DA6021 BOM Proposal ......................223 Data Sheet Version 3.A - Final 31-Jan-14 ©...
  • Page 13 Removed SVID registers 0x07 and 0x0A Added SVID registers 0x14, 0x15, 0x1D, 0x1E, 0x1F, 0x20, 0x2D, 0x2E and 0x2F Updated chapter 10.3 “DA6021 Power Sequences”, included timing diagrams and tables Added efficiency curves for all DC/DC regulators Updated descriptions of internal and external switches...
  • Page 14 Changed “new Intel Atom processor” into “Intel Atom processor Z3000” 2013.12.13 Updated the BOM Updated figure 11: Enter S0iX Sequencing Diagram (VCCAPWROKCFG=0) 2013.12.17 Added note regarding behaviour V2P85S chapter 11.6.10 Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 14 of 224 www.dialog-semiconductor.com...
  • Page 15 Version after receiving Intel’s PRQ statement 2013.01.27 Editorial changes in the register descriptions Corrected typo in VHDMI_CTRL register Updated BOM, cost and size optimized Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 15 of 224 www.dialog-semiconductor.com...
  • Page 16 It introduces a level shifting between the SoC and the main battery  OTP & EEPROM Interface: DA6021 will read its parameters from integrated OTP during power on reset. Optionally those OTP parameter settings can be overwritten by an external EEPROM for back-up solution, debugging or development.

  • Page 17: Figure 1: Overview Diagram

    GPIOs VSYSU GPIO1 V3P3U V1P8U VBATBKUP External V1P0S power DEBUG_CS V1P0SX switches Misc/Debug DEBUG_SVID V3P3S DEBUG_CS VHOST DEBUG_I2C VBUS VSYSSX Figure 1: Overview Diagram Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 17 of 224 www.dialog-semiconductor.com...

  • Page 18: Figure 2: Detailed Block Diagram

    1.9A BUCK_V1P0A 0.47µH VBATBKUP Backup Battery Charger V1P0A_GND V1P0S_EN EXT_SW_V1P0S V1P0S_SENSE V1P0SX_EN EXT_SW_V1P0SX V1P0SX_SENSE VDDQ_VTT_VIN VDDQ_VTT_R LDO_VDDQ_VTT VDDQ_VTT VDDQ_VTT_GND Figure 2: Detailed Block Diagram Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 18 of 224 www.dialog-semiconductor.com...

  • Page 19: Table 1: Da6021 Absolute Maximum Ratings

    All parameters are valid over the full operating temperature range and power supply range unless otherwise noted. Please note that the power dissipation must be limited to avoid overheating of DA6021. The maximum power dissipation should not be reached with maximum ambient temperature.

  • Page 20: Figure 3: Maximum Allowed Peak Power

    Part Package Name Package description Package Outline Number DA6021 FCBGA 325 pin, FCBGA 11x6mm, 0.4mm pitch Figure 76 Current OTP variant: -08 (Intel approved) Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 20 of 224 www.dialog-semiconductor.com...
  • Page 21 V1P8A feedback positive V1P8A_FBP V1P8A sense V1P8A feedback negative V1P8A_FBN V1P8A sense V3P3A V3P3A buck boost input V3P3A_VIN VSYS supply V3P3A_GND V3P3A buck boost ground Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 21 of 224 www.dialog-semiconductor.com...
  • Page 22 Input signal to enable ULPI_VBUS_EN VSYS VBUS VHDMI VHDMI_VIN VHDMI VHDMI input voltage VHDMI VHDMI VHDMI output voltage V2P85SX V2P85SX_VIN V2P85S V2P85SX input voltage Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 22 of 224 www.dialog-semiconductor.com...
  • Page 23 0=enter S3 1=exit S3 Sleep S4 trigger SLP_S4_B V1P8A 0=enter S4 1=exit S4 Resume reset to SoC, de- RSMRST_B V3P3A assertion (=1) after V3P3A Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 23 of 224 www.dialog-semiconductor.com...
  • Page 24 Battery temperature input BPTHERM0 of pack 0 Battery temperature input BPTHERM1 of pack 1 BATID Battery identification VBATSENSE VBAT battery sense voltage Test PMICTEST Test pin Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 24 of 224 www.dialog-semiconductor.com...

  • Page 25: Table 4: Pin Description

    I2C data debug channel Table 4: Pin Description Pin Type Description Pin Type Description Input Digital Output Power Analog Table 5: Pin Type Definition Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 25 of 224 www.dialog-semiconductor.com...
  • Page 26 9.1.14 PWRBTN_B DA6021 passes the power button input information via the PWRBTN_B output signal to the SOC. PWRBTN_B is a level shifted copy of PWRBTNIN_B after the 30ms de-bouncer. PWRBTN_B is valid when RSMRST_B=1 (de- asserted).
  • Page 27 BATLOW_B is an active low dedicated output signal to the SOC indicating that the battery voltage is not sufficiently high to boot the SoC. Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 27 of 224 www.dialog-semiconductor.com...

  • Page 28: Sdmmc3_Pwr_En_B

    SUSCLK SUSCLK is the 32.768kHz RTC clock that is supplied from the SoC. It is available to DA6021 about 100ms after RSMRST_B is de-asserted and continue to be available in S0, S0iX, S3 and S4 state. It is not available if the platform will be in G3 mode when the suspend voltage rails are disable.

  • Page 29: Burst Control Unit

    9.1.36.2 PANEL_EN Output signal to enable the display 9.1.37 9.1.37.1 SYSTHERM[2:0] System temperature thermistor input signal to be multiplexed to DA6021 ADC 9.1.37.2 BPTHERM[1:0] Battery pack temperature input signal to be multiplexed to DA6021 ADC 9.1.37.3 BATID Battery identification from the battery for battery presence detection and battery size indication 9.1.37.4...

  • Page 30: Da6021 Power States

    DA6021. When VSYS reaches the 2.0 Volt (point B) the POR will happen and DA6021 will go to reset. All the registers will be initialized with default values. Only registers supplied from RTC will retain their value. POR will be released Data Sheet Version 3.A - Final...

  • Page 31: Figure 5: Vsys Areas

    OTP content. In this case the device again in G3 is waiting for the VSYS to become valid, VSYS > VSYSREF = 3.0. DA6021 will go then to SOC_G3 state waiting for wakeup condition to be met. In order to have valid VSYS de-bouncing of 100ms will be needed.

  • Page 32: Soc Power States

    9.3.1 SOC_S0 State In the “SOC S0 State”, DA6021 completed the bring-up of the platform, and released the SOC from reset. In this state, the DA6021 state machines may be modified and controlled by the SOC, through commands issued over the I2C and SVID interfaces.

  • Page 33: Soc S0Ix State

    Each of these three sub-states has its own entry task list, required because of the different states of power rails in each. The entering and exiting of the SOC S0IX state is controlled by a signal which is delivered to DA6021 by the SOC via a dedicated physical pin SLP_S0IX_B.

  • Page 34: Soc S3 State

    Event Trigger Conditions (all Next state Note mandatory) Input power Source removal and VSYS < VMIN DA6021 loses states, except Main Battery Removal/Depletion VBATBKUP>VMIN RTC powered registers Restart with default values except RTC powered registers VSYS < VMIN DA6021 loses states, RTC VBATBKUP<VMIN...

  • Page 35: Soc S4 State

    SOC_S4 Note 5 SOC_S3 Note 6 SOC_S0iX Note 7 SOC_S0 Note 7 Table 12: Truth Table of Sleep Signals and DA6021 Final Power States Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 35 of 224 www.dialog-semiconductor.com...

  • Page 36: Da6021 Power State Transitions And Sleep Signals

    6. 6. Normally SLP_S0IX_B =0 when SLP_S3_B=0. SUSPWRDNACK=1 in this power state. 7. 7. Normally SUSPWRDNACK=1 in this power state. 9.3.6 DA6021 Power State Transitions and Sleep Signals The table below summarizes how DA6021 transitions from one power state to the next based on sleep signals and SUCPWRDNACK. SUSPWDNA SUSPWRDN...

  • Page 37: Register File And Address Range

    Semiconductor if you need changes in the sequencing. Such updates can be made in 2 ways, via new OTP, This would mean producing a new DA6021 variant, or via an external EEPROM. Page 1 includes all the registers to control the ADC functions, GPIO’s, PWM controller, controllable voltage domains and further functions described in the document below.

  • Page 38: 10. Power Controller State Machine

    Overview The power controller state machine is the main state machine of DA6021. It is comprises a first phase related to the power up sequence where all the condition for a safe boot are evaluated and the parameter are taken from the OTP/EEPROM, and a second phase related to the SoC power sequence where all the power rails for the SoC and platform are turned on according to certain sequencing rules.

  • Page 39: Sequencing

    HIGHLY INTEGRATED POWER MANAGEMENT IC FOR INTEL® ATOM™ Z3000 PROCESSOR The figure above represents DA6021 power state transitions. There are several events and condition for these transitions to occur. Following is the list of conditions used in the figure. ...

  • Page 40: Da6021 Power Sequences

    INTEL® ATOM™ Z3000 PROCESSOR 10.3 DA6021 Power Sequences There are 10 power state transitions to be performed in DA6021. These are:  Cold Boot: A cold boot sequence begins at the “SOC G3” state, and terminates at the “SOC S0” state.

  • Page 41: Cold Boot

    All the triggers listed in the table below will cause DA6021 bringing up the SUS rails. After that, signals from the SOC (SLP_S4_B, SLP_S3_B) are needed for DA6021 completing the cold boot sequence. Battery insertion is used as an illustration of Cold Boot power sequence due to one of triggers.

  • Page 42: Table 16: Cold Boot Triggers

    AC/DC adapter insertion but without a battery can only occur when all these conditions are met: SVDCINDET=1 (AC/DC adapter insertion), ADPWAKEEN=1, BATLOW_B=1 (which means DCBOOT=1), BATRMPDEN=0. Without a battery, USB power source insertion cannot cause the system to boot. Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 42 of 224 www.dialog-semiconductor.com...

  • Page 43: Figure 9: Cold Boot Power Sequencing Diagram, Valid Battery Insertion

    V1P05S V1P8S V1P2S V3P3S V2P85S SLP_S0iX_B VDDQ_VTT V1P2SX V1P0SX VCCAPWROK COREPWROK PLTRST_B MODEM_OFF_B SDWN_B Figure 9: Cold Boot Power Sequencing Diagram, Valid Battery Insertion Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 43 of 224 www.dialog-semiconductor.com...
  • Page 44 T2_V1P0S Ramp-Up time from 10% to 90% voltage 0,08 1,00 2,00 0,062 T3_V1P0S- Rail to Subsequent Rail Turn-On Delay 0,10 1,00 2,05 0,109 V1P05S Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 44 of 224 www.dialog-semiconductor.com...

  • Page 45: Table 18: Cold Boot Timings

    The delay time for “Core rails valid to VCCAPWEROK and COREPWROK assertion” is programmable by the following register. The configuration bit for VCCAPWROK and SUSPWRDNOK are also included in the PWRSEQCFG register (page 0), as defined below. Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 45 of 224 www.dialog-semiconductor.com...

  • Page 46: Warm Reset Sequence

    During a warm reset the SoC will toggle the PLTRST_B pin for a certain amount of time. This sequence can only happen while in SOC_S0 state. DA6021 captures this event in order to disable/idle the I2C interface and SVID interface. All voltage rails remain in regulation, except VCC and VNN, as those will be re-programmed to VBOOT voltage.

  • Page 47: Figure 10: Enter S0Ix Sequencing Diagram (Vccapwrokcfg=1)

    V1P05SVSEL_S0iX V1P05S V1P0S V5P0S SUSPWRDNACK SLP_S4_B DRAMPWROK VREFDQ1/2 VDDQ, VSYS_U, V3P3_U V1P8U SUS Rails RSMRST_B SDWN_B MODEM_OFF_B Figure 10: Enter S0iX Sequencing Diagram (VCCAPWROKCFG=1) Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 47 of 224 www.dialog-semiconductor.com...

  • Page 48: Figure 11: Enter S0Ix Sequencing Diagram (Vccapwrokcfg=0)

    V1P05SVSEL_S0iX V1P05S V1P0S V5P0S SUSPWRDNACK SLP_S4_B DRAMPWROK VREFDQ1/2 VDDQ, VSYS_U, V3P3_U V1P8U SUS Rails RSMRST_B SDWN_B MODEM_OFF_B Figure 11: Enter S0iX Sequencing Diagram (VCCAPWROKCFG=0) Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 48 of 224 www.dialog-semiconductor.com...

  • Page 49: Exit Soc S0Ix Mode

    The VCC rail will be turned on by SVID commands (not by SLP_S0IX). The rest of the rails will come out of power save mode. The rail sequencing is shown in the figure below: Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 49 of 224 www.dialog-semiconductor.com...

  • Page 50: Figure 12: Exit S0Ix Sequencing Diagram (Vccapwrokcfg=1)

    V1P05SVSEL V1P05SVSEL_S0iX V1P0S V1P05S V1P8S V1P2S V3P3S V2P85S SLP_S0iX_B VDDQ_VTT V1P2SX V1P0SX VCCAPWROK COREPWROK PLTRST_B MODEM_OFF_B SDWN_B Figure 12: Exit S0iX Sequencing Diagram (VCCAPWROKCFG=1) Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 50 of 224 www.dialog-semiconductor.com...

  • Page 51: Figure 13: Exit S0Ix Sequencing Diagram (Vccapwrokcfg=0)

    V1P05SVSEL V1P05SVSEL_S0iX V1P0S V1P05S V1P8S V1P2S V3P3S V2P85S SLP_S0iX_B VDDQ_VTT V1P2SX V1P0SX VCCAPWROK COREPWROK PLTRST_B MODEM_OFF_B SDWN_B Figure 13: Exit S0iX Sequencing Diagram (VCCAPWROKCFG=0) Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 51 of 224 www.dialog-semiconductor.com...

  • Page 52: Enter Soc S3 Mode

    The S3 state is entered when the SOC asserts the SLP_S3_B pin (LOW). VRs that remain on enter into power saving mode. The rail sequencing is shown in the figure below. Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 52 of 224 www.dialog-semiconductor.com...

  • Page 53: Figure 14: Enter S3 Sequencing Diagram

    V1P2S V1P8S V1P05S V1P0S V5P0S SUSPWRDNACK SLP_S4_B DRAMPWROK VREFDQ1/2 VDDQ, VSYS_U, V3P3_U V1P8U SUS Rails RSMRST_B SDWN_B MODEM_OFF_B Figure 14: Enter S3 Sequencing Diagram Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 53 of 224 www.dialog-semiconductor.com...

  • Page 54: Exit Soc S3 Mode

    DRAMPWROK SLP_S3_B V5P0S V1P0S V1P05S V1P8S V1P2S V3P3S V2P85S SLP_S0iX_B VDDQ_VTT V1P2SX V1P0SX VCCAPWROK COREPWROK PLTRST_B MODEM_OFF_B SDWN_B Figure 15: Exit S3 Sequencing Diagram Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 54 of 224 www.dialog-semiconductor.com...

  • Page 55: Enter Soc S4 Mode

    V1P2S V1P8S V1P05S V1P0S V5P0S SUSPWRDNACK SLP_S4_B DRAMPWROK VREFDQ1/2 VDDQ, VSYS_U, V3P3_U V1P8U SUS Rails RSMRST_B SDWN_B MODEM_OFF_B Figure 16: Enter S4 Sequencing Diagram Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 55 of 224 www.dialog-semiconductor.com...

  • Page 56: Exit Soc S4 Mode

    DRAMPWROK SLP_S3_B V5P0S V1P0S V1P05S V1P8S V1P2S V3P3S V2P85S SLP_S0iX_B VDDQ_VTT V1P2SX V1P0SX VCCAPWROK COREPWROK PLTRST_B MODEM_OFF_B SDWN_B Figure 17: Exit S4 Sequencing Diagram Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 56 of 224 www.dialog-semiconductor.com...

  • Page 57: Cold Off

    Cold Off A Cold Off, either through a SOC request or a system event, requests DA6021 in the ‘Mechanical Off’ (SOC G3, G3 for battery removal with no external power source) state. The system remains in this state until it receives a wake-up event, or until platform power sources are removed.

  • Page 58: Figure 18: Cold Off Power Sequencing Diagram (Suspwrdnackcfg=1)

    V5P0S SUSPWRDNACK SLP_S4_B DRAMPWROK VREFDQ1/2 VDDQ, VSYS_U, V3P3_U V1P8U RSMRST_B V3P3A V1P2A V1P8A V1P0A SDWN_B MODEM_OFF_B Figure 18: Cold Off Power Sequencing Diagram (SUSPWRDNACKCFG=1) Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 58 of 224 www.dialog-semiconductor.com...
  • Page 59 INTEL® ATOM™ Z3000 PROCESSOR For SOC initiated Cold Off, there is a configuration bit in the RTC domain supplied registers called SUSPWRDNACKCFG. This bit decides whether DA6021 enters SOC G3 state or stops at SOC S4 state:  When RSMRST_B=1, SLP_S4_B=0 and SUSPWRDNACKCFG=1, DA6021 enters SOC G3 state if SUSPWRDNACK=1 ...
  • Page 60 0,024 0,032 0,098 RSMRST_B assertion to V3P3A starts to turn 0,000 0,024 0,032 0,036 T3_V3P3A Ramp-down Time from 90% to 10% 1,00 2,00 0,951 Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 60 of 224 www.dialog-semiconductor.com...

  • Page 61: Table 22: Cold Off Sequencing Timing

    0,538 SLP_S4_B assertion to SDWN_B assertion 0,000 0,024 0,032 0,003 SDWN_B assertion to MODEM_OFF_B 0,40 0,80 0,608 assertion Table 22: Cold Off Sequencing Timing Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 61 of 224 www.dialog-semiconductor.com...

  • Page 62: Figure 19: Power Button Forced Cold Off

    V1P8S V1P05S V1P0S V5P0S DRAMPWROK VREFDQ1/2 VDDQ, VSYS_U, V3P3_U V1P8U RSMRST_B V3P3A V1P2A V1P8A V1P0A SDWN_B MODEM_OFF_B Figure 19: Power Button forced Cold Off Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 62 of 224 www.dialog-semiconductor.com...

  • Page 63: Figure 20: Catastrophic Event (Except Vsysovp) Shutdown Sequence

    DA6021 output signals to SOC MODEM_OFF_B Figure 21: VSYSOVP Shutdown Sequence Parameter Description [µs] [µs] [µs] VSYSOVP debounce time Table 24: VSYSOVP Shutdown Timing Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 63 of 224 www.dialog-semiconductor.com...

  • Page 64: Modem Reset Sequence

    10.3.10 Modem Reset Sequence The sequence is initiated by the SoC while setting the MODEMRSTSEQ bit. During a modem reset sequence DA6021 will toggle the SDWN_B and MODEM_OFF_B pins. For detail refer to the following diagram. SDWN_B MODEM_OFF_B Figure 22: Modem Reset Sequencing Diagram...

  • Page 65: Pmic Resets

    DA6021 Company Confidential HIGHLY INTEGRATED POWER MANAGEMENT IC FOR INTEL® ATOM™ Z3000 PROCESSOR 10.4 PMIC Resets The following table summarizes the reset sources for DA6021 Reset Source Reset trigger Reset Type/Sequence SoC Request PLTRST_B Warm Reset External Button PWRBTN_B held longer than...

  • Page 66: 11. Platform Power Domains

    DA6021 Company Confidential HIGHLY INTEGRATED POWER MANAGEMENT IC FOR INTEL® ATOM™ Z3000 PROCESSOR 11. Platform Power Domains 11.1 Power Domains Summary The power supply part of DA6021 consists of various power supplies modules: DA6021 Power Supply Supplied Supplied Supplied Notes...

  • Page 67: Table 27: Power Domains

    V5P0S 900mA External switched power domain supplied by V5P0S EFS_VBUS VBUS V5P0S 900mA External switched power domain supplied by V5P0S Table 27: Power Domains Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 67 of 224 www.dialog-semiconductor.com...

  • Page 68: Voltage Rail On/Off On Various Power States

    Ta = 25°C, VSYS = 3.7V, no load Power State Typ. [mA] SOC_S0 2.089 SOC_S0iX 1.793 SOC_S3 1.022 SOC_S4 0.789 SOC_G3 0.069 0.056 Table 29: PMIC Current Consumption Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 68 of 224 www.dialog-semiconductor.com...

  • Page 69: Voltage Rail Control Mechanism

    SOC communicates with the DA6021 via the SVID interface. SVID‘s commands composed of 9 bits – 4 MSBs determine the address and 5 LSBs are the command bits. DA6021 supports 2 SVID voltage regulators – VCC & VNN. The address for each of the voltage regulator is indicated in the table below:...

  • Page 70: Vclk Timing Parameters

    % of 0.5 Tperiod Trise VCLK rise time @VR 0.25 Tfall VCLK fall time @VR 0.25 Duty cycle Table 33: VCLK AC Timing Parameters NOTES: Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 70 of 224 www.dialog-semiconductor.com...

  • Page 71: Data Sampling And Timing

    Following SVID Bus platform timings have to be fulfilled  Tco_max_VR clock to data delay = 12ns  Tco_min_VR clock to data delay = 4ns  Tsu_VR VDIO setup time at DA6021 = 7ns  Thld_VR VDIO hold time at DA6021 = 14ns  Tfly_min 0.3ns ...

  • Page 72: Figure 25: Soc Driving Timing Definition

    DA6021 Company Confidential HIGHLY INTEGRATED POWER MANAGEMENT IC FOR INTEL® ATOM™ Z3000 PROCESSOR Figure 25: SoC Driving Timing Definition Figure 26: DA6021 Driving Timing Definition Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 72 of 224...

  • Page 73: Svid Command Set

    The majority of the VR monitoring data is accessed NAK all call through the GetReg command. address) Table 34: SVID Supported Commands Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 73 of 224 www.dialog-semiconductor.com...

  • Page 74: Svid Register Set

    11.5.5 SVID Register Set Register Description Access Note 0x00 Vendor ID The vendor ID is defined by Intel . DA6021 Read only returns the assigned vendor ID 0x01 Product ID Identifies the DA6021 with its specific number Read only 0x02...

  • Page 75: Table 35: Svid Supported Registers

    Read Page 2/3 0x00 VendorID[7:0] VendorID[7:0] 0x2B identifies Dialog Semiconductor Register Name PRODUCT_ID Address 0x01 Read Page 2/3 0x00 ProductID[7:0] ProductID[7:0] Identifies the product Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 75 of 224 www.dialog-semiconductor.com...
  • Page 76 Current monitoring supported ICCmax alert is issued from DA6021 to the SOC via the ALERT_B line of the SVID interface if the output current of VCC or VNN is considered to exceed the Imax threshold.When VCC and VNN are active,DA6021 measures and averages the output current and compares it with the alert threshold which is programmed to approximately 10% above Imax.
  • Page 77 0x00 normal mode 0x01 light load 0x02 very light load 0x03 ultra light mode 0x04 .. 0xFF not supported, error message is sent out Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 77 of 224 www.dialog-semiconductor.com...

  • Page 78: Vid Dac Table

    +/- 5mV 1.00V +/- 0.5% VID 1.01V +/- 0.5% VID 1.19V +/- 0.5% VID 1.20V +/- 0.5% VID 1.21V >1.21V Table 36: VID Values Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 78 of 224 www.dialog-semiconductor.com...

  • Page 79: Low Power State Control Signals

    Power States PS0 – active state: DA6021 VCC voltage rail can handle up to 8A peak current for a duration of several seconds before it reaches the maximum operational temperature of DA6021. The regulator automatically switches between synchronous PWM and asynchronous PFM mode depending on the load.

  • Page 80: Figure 28: Vcc Timings

    INTEL® ATOM™ Z3000 PROCESSOR PS3 – C6 at S0ix The SoC sends a SVID command SetVID_decay with 0V to enter the PS3 mode. DA6021 switches off all unnecessary functional blocks minimizing the quiescent current. When detecting an exit from S0ix state, the SoC sends SetVID_fast/slow and DA6021 recovers VCC to the operating voltage level.

  • Page 81: Figure 29: Vcc Efficiency

    VCC Efficiency vs. output current, Vin = 3.7V, Vout = 1.00V, Auto Mode Vin = 3.7V 10,0 Output Current [A] Figure 29: VCC Efficiency Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 81 of 224 www.dialog-semiconductor.com...

  • Page 82: Dc/Dc Buck Regulator Vnn

    Power States Active state: DA6021 VNN voltage rail can handle up to 8A peak current for duration of several seconds until it would reach the maximum operational temperature of DA6021. The regulator automatically switches between synchronous PWM and asynchronous PFM mode depending on the load.

  • Page 83: Figure 31: Vnn Efficiency

    Output Current [A] Figure 31: VNN Efficiency Including DC accuracy, ripple and load regulation Including DC accuracy, ripple and load regulation RDSON measurement on ATE Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 83 of 224 www.dialog-semiconductor.com...

  • Page 84: Dc/Dc Buck Regulator V1P0A

    Power States Active State: DA6021 V1P0A voltage rail can handle up to 1.9A. Even though the average current is in the range of 50mA to 350mA. Optimized efficiency is achieved from 50mA to 500mA. Automatically switching from PWM to PFM mode achieves the best power efficiency.

  • Page 85: Table 39: Electrical Parameter For Buck_V1P0A

    Table 39: Electrical Parameter for BUCK_V1P0A Including DC accuracy, ripple and load regulation Including DC accuracy, ripple and load regulation RDSON measurement on ATE Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 85 of 224 www.dialog-semiconductor.com...

  • Page 86: Figure 33: V1P0A Efficiency

    V1P0A active state or S0iX state is determined by SLP_S0iX_B V1P0A only operate at active state, no S0iX, regardless of SLP_S0iX_B V1P0A_VSEL 0.900V 0.950V 1.000V 1.010V 1.020V 1.030V 1.050V 1.100V Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 86 of 224 www.dialog-semiconductor.com...

  • Page 87: Table 40: V1P0A Truth Table

    This voltage rail powers the SoC display & DDR3 I/O, PCIe and further functions. The current requirement of this voltage rail is 916mA and requests an external switch providing this power rail to the SoC. DA6021 provides a control signal named V1P0SX_EN supplied by V5P0S.When this signal is asserted (high), the slew rate is controlled in order to limit the inrush current drawn via the external N-channel FET.

  • Page 88: Table 42: V1P0Sx_En Truth Table

    VDDQ_VTT controlled by SLP_S0iX_B according to sequencing VDDQ_VTT controlled by VDDQ_VTT_CTRL.VDDQ_VTT_EN bit Regardless of VDDQ_VTT_EN and VDDQ_VTT_SEL, VDDQ_VTT is disabled when SLP_S3_B is asserted, means low Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 88 of 224 www.dialog-semiconductor.com...

  • Page 89: Dc/Dc Buck Regulator V1P05S

    The maximum output current of the 1P05S buck regulator is 474mA V1P05S_FBN V1P05S_FBP V1P05S_VIN 1.05V 0.5A V1P05S bus BUCK_V1P05S 0.47µH V1P05S_GND Figure 34: Buck V1P05S Block Diagram Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 89 of 224 www.dialog-semiconductor.com...

  • Page 90: Table 45: Electrical Parameter For Buck_V1P05S

    Power States Active state: DA6021 V1P05S voltage rail can handle up to 474mA max current. Its usual average current workload is at 1mA to 50mA, but thermally able to handle 474mA in peaks. Optimized efficiency is achieved from 1mA to 50mA.

  • Page 91: Figure 35: V1P05S Efficiency

    V1P05S active, regardless of SLP_S0iX_B V1P05SVSEL_S0iX Output voltage in S0iX mode 0.60V 0.65V 0.70V Nominal voltage (1.05V) V1P05S_VSEL 0.945V 0.998V 1.020V 1.030V 1.040V 1.050V 1.103V 1.115V Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 91 of 224 www.dialog-semiconductor.com...

  • Page 92: Dc/Dc Buck Regulator V1P8_A

    Figure 36: Buck V1P8A Power Rail Block Diagram S0ix State: When the SoC enters the S0ix state, SLP_S0ix is held low. DA6021 turns the V1P8A buck regulator into low power mode and disables all un-necessary blocks, reducing the power requirements. DA6021 exits this power saving mode within 5µs after SoC asserts the SLP_S0ix signal to high.

  • Page 93: Figure 37: V1P8A Efficiency

    Output Current [A] Figure 37: V1P8A Efficiency Including DC accuracy, ripple and load regulation Including DC accuracy, ripple and load regulation RDSON measurement on ATE Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 93 of 224 www.dialog-semiconductor.com...

  • Page 94: Table 48: V1P8A Truth Table

    V1P8A Subsystems V1P8U: This power rail is primarily to supply LPDDR2 or LPDDR3 RAMs. DA6021 provides a control signal V1P8U_EN_B supplied by VSYS and derived from SLP_S4_B sent out by the SoC. When V1P8U_EN_B is asserted low, the signal slew rate is controlled to limit the inrush current when the external P-channel FET is turned on.

  • Page 95: Table 49: V1P8U_En_B Truth Table

    100-465pF V1P8S: The maximum current of this power rail is defined to 145mA, sourcing the SoC, USB PHY, UICC SIM … DA6021 controls this power rail while deriving the information from SoC SLP_S3_B signal and switching the rail internally. The typical RDSon value of this internal switch is 170mΩ...

  • Page 96: Table 52: V1P8S Power Switch Specification

    This power rail is used to source platform devices such as eMMC, camera, audio codecs … The maximum allowed output current is defined to 240mA. DA6021 controls this power rail while deriving the information from SoC SLP_S0ix_B signal and switching the rail internally. The typical R of this internal switch is 100mΩ.

  • Page 97: Table 54: Electrical Parameter For V1P2A

    SLP_S4_B is asserted, means low VREFDQVSEL[4:0] 00000 0.600V 00001 0.620V 00010 0.640V 00011 0.660V … … 11100 1.160V 11101 1.180V 11110 1.200V 11111 1.220V Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 97 of 224 www.dialog-semiconductor.com...

  • Page 98: Dc/Dc Buck Regulator Vddq

    Power States Active State: DA6021 VDDQ voltage rail can handle up to 2800mA max current. The usual average current is at 50mA to 500mA, but thermally able to handle 2800mA in peaks.. Optimized efficiency is achieved from 50mA to 500mA.

  • Page 99: Table 56: Electrical Parameter For Buck_Vddq

    INTEL® ATOM™ Z3000 PROCESSOR S0ix State: When the SoC enters the S0ix state, SLP_S0ix is held low. DA6021 turns the VDDQ buck regulator into low power mode and disables all un-necessary blocks, reducing the power requirements. DA6021 exits this power saving mode within 5µs after the SoC asserts the SLP_S0ix signal to high.

  • Page 100: Figure 39: Vddq Efficiency

    VDDQ active determined by SLP_S0iX_B VDDQ active, regardless of SLP_S0iX_B VDDQ_VSEL 1.080V 1.140V 1.200V 1.240V nominal voltage DDR3LP 1.350V DDR3L 1.390V 1.418V 1.500V DDR3 Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 100 of 224 www.dialog-semiconductor.com...

  • Page 101: Table 57: Vddq Truth Table

    Power supply Noise = 0.1Vpp, 1- rejection ratio 10kHz, ½ Iout-DC Vnoise Output noise µVRMS 10-100kHz, ½ Iout-DC Table 59: Electrical Parameter for V1P2S LDO Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 101 of 224 www.dialog-semiconductor.com...

  • Page 102: Table 60: V1P2S Truth Table

    Regardless of V1P2SX_EN and V1P2SX_SEL, V1P2SX is disable when SLP_S3_B is asserted, means low The maximum current is defined to 155mA, switched internally and controlled via the SoC SLP_S0iX_B signal. Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 102 of 224 www.dialog-semiconductor.com...

  • Page 103: Power Rail Vsysu

    The external power switch is generated via a P-channel FET. DA6021 provides an enable signal VSYSU_EN_B supplied by VSYS, driving the gate of the external FET. DA6021 provides also a feedback input signal VSYSU_FB to control the slew rate and limit the inrush current Register Name...

  • Page 104: Power Rail Vsys_Sx

    The external power switch is generated via a P-channel FET. DA6021 provides an enable signal VSYSSX_EN_B, supplied by VSYS, driving the gate of the external FET. DA6021 provides also a feedback input signal VSYSSX_FB to control the slew rate and limit the inrush current Register Name...

  • Page 105: Power Rail Vsys_S

    Company Confidential HIGHLY INTEGRATED POWER MANAGEMENT IC FOR INTEL® ATOM™ Z3000 PROCESSOR 11.6.9 Power Rail VSYS_S VSYS_S is a voltage rail that is supplied by VSYS through an internal DA6021 power switch with a R DSon 900mΩ. Description Value [max, mΩ] Input, output rails wirebond &...

  • Page 106: Table 67: Electrical Parameter For Buckboost_V2P85S

    Table 67: Electrical Parameter for BUCKBOOST_V2P85S Including DC accuracy, ripple and load regulation Including DC accuracy, ripple and load regulation RDSON meansurement on ATE Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 106 of 224 www.dialog-semiconductor.com...

  • Page 107: Figure 41: V2P85S Efficiency

    Note: If V2P85S is disabled when system in S0-mode, after exiting S0iX-mode, the regulator will be enabled automatically V2P85S_CTRL. SLP_S3_B V2P85S V2P85S_SEL V2P85S_EN Table 68: V2P85S Truth Table Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 107 of 224 www.dialog-semiconductor.com...

  • Page 108: Table 69: V2P85Sx Power Switch Specification

    Regardless of V2P85SX_EN and V2P85SX_SEL, V2P85SX is high when SLP_S3_B is asserted, means low V2P85SX_CTRL. SLP_S3_B V2P85SX V2P85SX_SEL V2P85SX_EN Table 70: V2P85SX Truth Table Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 108 of 224 www.dialog-semiconductor.com...

  • Page 109: Buck Boost Regulator V3P3A

    11.6.11 Buck Boost Regulator V3P3A DA6021 integrates a buck/boost converter supplying 3.3V into the system towards the SoC, V3P3U, V3P3S, VUSBPHY and VSDIO. The output voltage is set to 3.333V. The maximum output current of V3P3A buck regulator is 1600mA...

  • Page 110: Figure 43:V3P3A Efficiency

    V3P3A controlled by SUSPWRDNACK according to sequencing V3P3A controlled by V3P3A_CTRL.V3P3A_EN bit Regardless of V3P3A_EN and V3P3A_SEL, V3P3A is disable when SUSPWRDNACK is de-asserted, means high Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 110 of 224 www.dialog-semiconductor.com...

  • Page 111: Table 72: V3P3A Truth Table

    V3P3U is the voltage rail which is sourced by V3P3A and switched by an external P-channel FET. This voltage rail is foreseen to supply mainly WIFI and BT. DA6021 provides a control signal V3P3_U_EN supplied by V3P3A and derived from SoC’s SLP_S4_B signal. The maximum current for this power rail is 700mA...

  • Page 112: Table 74: V3P3S_En_B Truth Table

    V1P8_A buck converter or by V3P3_A. In case of a 3.3V supply, the internal switch has a R of 200mΩ, in DSon case of 1.8V the R is 80mΩ. The maximum current is defined to 200mA. DSon Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 112 of 224 www.dialog-semiconductor.com...

  • Page 113: Boost Regulator V5P0S

    1.8V Table 77: VSDIO Output Voltage Selection 11.6.12 Boost Regulator V5P0S DA6021 integrates a boost converter supplying 5V into the platform towards HDMI, USB3, VBUS & USB2/3 OTG. The maximum output current of V5P0_S boost converter is 955mA V5P0S_FBN V5P0S_FBP V5P0S_LX 5.048V...

  • Page 114: Figure 45:V5P0S Efficiency

    Output Current [A] Figure 45:V5P0S Efficiency Including DC accuracy, ripple and load regulation Including DC accuracy, ripple and load regulation RDSON measurement on ATE Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 114 of 224 www.dialog-semiconductor.com...

  • Page 115: Table 79: V5P0S Truth Table

    Regardless of VHOST_EN and VHOST_SEL, VHOST_EN is low when SLP_S3_B is asserted, means low The maximum current of this power domain is defined to 900mA Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 115 of 224 www.dialog-semiconductor.com...

  • Page 116: Table 80: Vhost_En Truth Table

    VBUS_EN high High high Table 82: VBUS_EN Truth Table Parameter Value V_IL >0.66V V_IH <1.1V I_EN >0.5µA Table 83: VBUS External Switch Driver Capability Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 116 of 224 www.dialog-semiconductor.com...

  • Page 117: Vlp Low Power Regulator

    The LDO_LP will be used for running the internal sequencer. It is supplied by the system supply voltage VSYS. This allows a power up prior the system power domains. This LDO acts as the supply for the bias, reference, OTP and DA6021 registers. Electrical Characteristics (Ta = -40 to +85 ºC) VSUP = 2.7 to 4.5V...

  • Page 118: Current Monitor

    Figure 46: Current Measurement Tolerance Boundary Voltage Rail Resolution Tolerance 20mA/LSB ±5% 20mA/LSB ±5% V1P0A 5mA/LSB ±5% V1P05S 2.5mA/LSB ±5% VDDQ 5mA/LSB ±5% Table 87: Current Measurement Resolution Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 118 of 224 www.dialog-semiconductor.com...

  • Page 119: Vcc/Vnn Current Vs Adc Data

    VNN current sensing error Current set (A) 5,0% 4,0% 3,0% 2,0% 1,0% 0,0% -1,0% -2,0% -3,0% -4,0% -5,0% Typical Error Figure 49: Typical VNN Current Sensing Error Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 119 of 224 www.dialog-semiconductor.com...

  • Page 120: V1P0A Current Vs Adc Data

    V1P0A current sensing error Current set (A) 5,0% 4,0% 3,0% 2,0% 1,0% 0,0% -1,0% -2,0% -3,0% -4,0% -5,0% Typical Error Figure 51: Typical V1P0A Current Sensing Error Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 120 of 224 www.dialog-semiconductor.com...

  • Page 121: V1P5S Current Vs Adc Data

    0,55 0,65 0,75 0,85 5,0% 4,0% 3,0% 2,0% 1,0% 0,0% -1,0% -2,0% -3,0% -4,0% -5,0% Typical error Figure 53: Typical V1P05S Current Sensing Error Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 121 of 224 www.dialog-semiconductor.com...

  • Page 122: Vddq Current Vs Adc Data

    VDDQ current sensing error Current set (A) 5,0% 4,0% 3,0% 2,0% 1,0% 0,0% -1,0% -2,0% -3,0% -4,0% -5,0% Typical Error Figure 55: Typical VDDQ Current Sensing Error Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 122 of 224 www.dialog-semiconductor.com...

  • Page 123: 12. I2C Interface

    12.1 Overview DA6021 is a slave-only device that is mastered by the SoC. It resides off the SoC’s I2C. The slave device implemented on DA6021 side is an asynchronous implementation and will support the high speed mode (3.4MHz). Some of the main features for the I2C slave are: ...

  • Page 124: Electrical Requirements

    At pin 0.3*VDD 0.7*VDD Vhys 0.2*VDD Cpin Tfall_hs 3.33 Mb/s Operation Tfall_fs 400 Kb/s Operation Tr/Tf Measurement Points Table 89: I2C Signal Electrical Specification Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 124 of 224 www.dialog-semiconductor.com...

  • Page 125: 13. External Eeprom Controller

    EEPROM. Therefore the EEPROM has to be supplied from a dedicated external power rail or directly from the main battery. If no valid signature is read, DA6021 operates with the register setting based on the OTP registers.

  • Page 126: 14. Power Source Detection

    14.1 Overview There are three input supply sources that can be detected by DA6021: VBAT, VDCIN_SENSE and VBUS_SENSE referring respectively to the battery, AC adapter and USB connector. For all power sources dedicated comparators are used for the power detection. All detectors include de-bounce logic with a nominal time period of 100ms which can be disabled by software.

  • Page 127: Battery Pack Interface

    Figure 61: Battery Single Wire Block Diagram for Analog sensing, Digital communication Parameter Units Notes Digital D, E Frequency 3.268 communication Voltage 1.71 1.89 0.35 Vhys 0.05 Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 127 of 224 www.dialog-semiconductor.com...

  • Page 128: Battery Presence Detection

    30KΩ to 200KΩ. When this occurs, DA6021 detects that the battery is being removed (if configured). The integrated 100ms de-bounce logic ensures there are no false removal alerts. Depending on the DA6021 setting either a complete Cold Off sequence will be performed or an interrupt to the SOC will be sent.

  • Page 129: System Voltage Monitor

    100ms de-bounce time before the SVBUSDET bit in the SPWRSRCIRQ register is set, indicating charger connection. If VBUSDBEN is cleared, SVBUSDET is set immediately upon VBUS becoming valid. Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 129 of 224 www.dialog-semiconductor.com...

  • Page 130: Vdcin Power Source Detection Comparators

    100ms de-bounce time before the SDCINDET bit in the SPWRSRCIRQ register is set, indicating adapter connection. If VDCINDBEN is cleared, SDCINDET is set immediately upon VDCIN becoming valid. Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 130 of 224 www.dialog-semiconductor.com...

  • Page 131: Batlow Definition

    PMIC will assert the BATLOW pin, the processor will then take action. All thresholds are preprogrammed in OTP and can be overwritten by software. Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 131 of 224 www.dialog-semiconductor.com...

  • Page 132: Power Source Detection Events

    AC/DC. Battery still not charged DCBOOT = 0 enough.  Wakeup immediately DCBOOT = 1  BSTRMDETRN = 0 Table 98: System Wake-Up Condition Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 132 of 224 www.dialog-semiconductor.com...

  • Page 133: Da6021 Catastrophic And Critical Events

    INTEL® ATOM™ Z3000 PROCESSOR It is assumed that DA6021 is in SOC_G3 and VSYS is valid. Such wake-up event will be generated even if the system is in SOC_S4, SOC_S3 and SOC_SX. Wake-up is completely under the control of the processor.

  • Page 134: Power Source Registers

    Critical events are:  IDBATRM – DA6021 detects that a battery was removed from the system by BATID presence comparator when the bit BATRMSRC in the PSDETCTRL register is set (=1). All VRs are shut down in sequenced order but without waiting for SLP_S*_B from SOC. If BATRMPDEN is cleared, the PMIC may operate without detecting a valid battery is present ONLY if an AC/DC adapter (SDCINDET_B=1), therefore no Cold Off in this case.
  • Page 135 DCP, if CHGDET=1 then perform a Cold off Enable, perform a cold off BATRMSRC VBAT comparator BATID presence comparator DBIEN Digital battery interface communication disable Digital battery interface communication enable Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 135 of 224 www.dialog-semiconductor.com...
  • Page 136 AD/DC adapter is plugged in System boot enable with AD/DC adaptor alone, no battery required Register Name LOWBATDET1 Address 0x24 Read/Write Page 1 Reset Value 0x8A LOWBATDCP LOWBATSDP Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 136 of 224 www.dialog-semiconductor.com...
  • Page 137 System won’t wake up when AC/DC adapter insertion is detected ADPWAKEEN System wakes up when AC/DC adapter insertion is detected and boot conditions are met Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 137 of 224 www.dialog-semiconductor.com...
  • Page 138 Wake-up triggered by power button WAKEBAT Wake-up triggered by battery insertion WABEUSB Wake-up triggered by USB charger insertion WAKEADP Wake-up triggered by AC/DC adapter insertion Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 138 of 224 www.dialog-semiconductor.com...

  • Page 139: 15. Analog-To-Digital Converter

    ~7τ = 7 x (RS + Acquisition Time RINT) x CINT VSYS Voltage Range ADC=[(VSYS-2.5) x / channel A0 / 0.5] x 1023 Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 139 of 224 www.dialog-semiconductor.com...

  • Page 140: Analog Overview

    1ms prior to BPTHERM1) ADC measurement. System Temp 0 Vin/VREF 0.0V .. (Pin: ADCIN4 T*1023 SYSTHERM0) System Temp 1 0.0V .. Vin/VREF ADCIN5 (Pin: T*1023 Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 140 of 224 www.dialog-semiconductor.com...

  • Page 141: Adc Measurement Support

    Table 100: ADC Channel Overview The ADC is used for temperature, current and voltage measurements. It is managed by the DA6021 ADC state machine. The state machine performs ADC operations are, like regular readings of temperatures, current and voltage, programmed in registers and may be modified by the SOC after boot and initialization. The ADC state machine is an independent hardware engine which prevents the management of lengthy ADC transactions from blocking time-critical power sequencing tasks.

  • Page 142: Adc Sequencer

    Initiates manual conversion of PMICTEMP, clears after conversion BPTHERM0 Initiates manual conversion of BPTHERM0, clears after conversion BPTHERM1 Initiates manual conversion of BPTHERM1, clears after conversion Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 142 of 224 www.dialog-semiconductor.com...
  • Page 143 Conversion request for PMICTEMP complete, clear by writing “1” BPTHERM0 Conversion request for BPTHERM0 complete, clear by writing “1” BPTHERM1 Conversion request for BPTHERM1 complete, clear by writing “1” Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 143 of 224 www.dialog-semiconductor.com...
  • Page 144 3 event BPTHERM1 mask channel 4 event SYSTHERM0 mask channel 5 event SYSTHERM1 mask channel 6 event SYSTHERM2 mask channel 7 event Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 144 of 224 www.dialog-semiconductor.com...

  • Page 145: Reference Source

    The SOC needs to write a ‘1’ to the event register to serve and clear the event. This clears the interrupt line, too if there is not another interrupt request pending. As with all event registers in the DA6021 device, a Mask bit to disable the event and interrupt generation exists. Data Sheet Version 3.A - Final...

  • Page 146: Result Register

    15.3.7 CH2: Die Temperature The DA6021 die temperature thermistor has an alert event register EPMICALRT that flag an interrupt when the according temperature threshold PMICALRT is exceeded. In case temperature exceeds one of the thresholds, the status register SPMICALRT and the event register EPMICALRT are set and an Interrupt is generated to the SOC.

  • Page 147: Ch5-7: System Temperature Thermistor

    15.3.10 CH8-12: VR Current Measurement DA6021 is capable to monitor the output current of the VCC, VNN, V1P0A, V1P05S and VDDQ buck regulator. The results are stored in the corresponding result registers. Usually the current of the buck regulators is monitored when the system is in S0 state. The current is averaged and measured per default every 1ms.

  • Page 148: Adc Registers

    Upper bits of temperature alert threshold for SYS2TEMP SYS2_THRM_RSLTL 0x79 Register Name Address Read Page 1 Reset Value 0x00 SYS2TEMP SYS2TEMP[7:0] 0..255 Lower bits of temperature alert threshold for SYS2TEMP Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 148 of 224 www.dialog-semiconductor.com...
  • Page 149 Upper bits of temperature alert threshold for PMICTEMP Register Name PMIC_THRM_RSLTL Address 0x7F Read Page 1 Reset Value 0x00 PMICTEMP PMICTEMP[7:0] 0..255 Lower bits of temperature alert threshold for PMICTEMP Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 149 of 224 www.dialog-semiconductor.com...
  • Page 150 Upper bits of VCC current measurement IVCCRSLTL 0x85 Register Name Address Read Page 1 Reset Value 0x00 IVCC IVCC[7:0] 0..255 Lower bits of VCC current measurement Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 150 of 224 www.dialog-semiconductor.com...
  • Page 151 Upper bits of V1P05S current measurement Register Name IV1P05SRSLTL Address 0x8B Read Page 1 Reset Value 0x00 IV1P0A IV1P05S[7:0] 0..255 Lower bits of V1P05S current measurement Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 151 of 224 www.dialog-semiconductor.com...
  • Page 152 Upper bits of VDDQ current measurement IVDDQRSLTL 0x8D Register Name Address Read Page 1 Reset Value 0x00 IVDDQ IVDDQ[7:0] 0..255 Lower bits of VDDQ current measurement Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 152 of 224 www.dialog-semiconductor.com...

  • Page 153: 16. System Voltage & Temperature Monitoring

    In reaction to either threshold crosses or a flag coming from several comparators the SVTM will drive several pins on DA6021 for use by the processor and to other platform components. According to the condition it can generate warnings, and or interrupts and can generate a shutdown event.
  • Page 154 Alert1 thermal status passed platform thermistor 1 BAT0_A1_ST Alert1 thermal status passed battery thermistor0 BAT1_A1_ST Alert1 thermal status passed battery thermistor1 PMIC_A1_ST Alert1 thermal status passed PMIC thermistor Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 154 of 224 www.dialog-semiconductor.com...
  • Page 155 Reset Value 0x00 reserved PMIC SYS2 SYS1 SYS0 CRIT CRIT CRIT CRIT SYS0CRIT Set by thermal state machine when system thermistor 0 thermal critical event occurs Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 155 of 224 www.dialog-semiconductor.com...
  • Page 156 No mask Interrupt masked MSYS0ALRT1 No mask Interrupt masked MSYS1ALRT1 No mask Interrupt masked MSYS2ALRT1 No mask Interrupt masked MPMICALRT1 No mask Interrupt masked Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 156 of 224 www.dialog-semiconductor.com...
  • Page 157 No mask Interrupt masked BAT0ALRT1 No mask Interrupt masked BAT1ALRT1 No mask Interrupt masked BAT0CRIT No mask Interrupt masked BAT1CRIT No mask Interrupt masked Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 157 of 224 www.dialog-semiconductor.com...

  • Page 158: Svtm Block Diagram

    All the settings can be programmed via the configuration registers. It is assumed that these thresholds are programmed as VWARNA > VWARNB > VCRIT. VSYS monitoring will only be executed while being in SoC_S0 state. Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 158 of 224 www.dialog-semiconductor.com...
  • Page 159 7 fast clock cycles 0110 10 fast clock cycles 0111 20 fast clock cycles 1000 30 fast clock cycles … … 1111 100 fast clock cycles Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 159 of 224 www.dialog-semiconductor.com...

  • Page 160: Vsys Related Output Control

    20 fast clock cycles 16.3.2 VSYS Related Output Control The DA6021 outputs DISA, DISB, DISCRIT are directly derived from the current platform status and the register settings. The PROCCHOT_B signal is derived from a several input criterias as DA6021 on-die, battery and system temperature as well as battery voltage drop.

  • Page 161: Figure 67: Bcu Warning Flag Generation

    Reset Value 0x07 reserved MVCRIT MVWARNB MVWARNB MVWARNB Interrupt not masked Interrupt masked MVWARNA Interrupt not masked Interrupt masked MVCRIT Interrupt not masked Interrupt masked Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 161 of 224 www.dialog-semiconductor.com...
  • Page 162 BCU DISCRIT function signal enable DISCRIT_POL BCU DISCRIT pin active low BCU DISCRIT pin active high DISCRIT_STICKY 0 = signal assertion not sticky 1= signal assertion is sticky Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 162 of 224 www.dialog-semiconductor.com...
  • Page 163 SPROTHOT_B PROTHOT_B not asserted PROTHOT_B asserted DISCRIT DISCRIT not asserted DISCRIT asserted SDISB DISB not asserted DISB asserted SDISA DISA not asserted DISA asserted Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 163 of 224 www.dialog-semiconductor.com...

  • Page 164: Figure 68: Vsys Trip Points Flag Logic

    SOC with BCUIRQ (if enabled as such) Clears BCUIRQ and Warning Zone B and VWARNBIRQ VWARNB interrupt bits. bits... Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 164 of 224 www.dialog-semiconductor.com...

  • Page 165: Under- & Over- Voltage Condition

    In the case of the under-voltage condition the VSYS is too low being considered valid and the analog circuitry cannot work properly. DA6021 will initiate a system shut down regardless of the SoC state and will end up in G3 state.

  • Page 166: Temperature Monitoring Via Adc

    Assert PROCHOT_B at VWARNB PROCHOT_B_ST 0 = low status indication 1= high status indication 16.3.5 Temperature Monitoring via ADC DA6021 has the capability to monitor six miscellaneous temperatures and stores the measurement results in the corresponding registers  SYSTHERM0: System temperature 0 ...
  • Page 167 Each ALERT has a 4-bit hysteresis and 4 STATUS bits (A0_ST, A1_ST, CRIT_ST) and for all the ALERT0 a policy register (A0P_EN) is defined in order to allow actions upon crossing thresholds. Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 167 of 224 www.dialog-semiconductor.com...
  • Page 168 0001 thermal event … 1110 1111 A1EN Disable Enable SYS0_THRMALRT1L 0x97 Register Name Address Read/Write Page 1 Reset Value 0x00 ALERT1LSB ALERT1LSB [7:0] 0..255 Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 168 of 224 www.dialog-semiconductor.com...
  • Page 169 Alert1 threshold MSBs ALERT1_HYST[0:3] 0000 SYSTEMP0 must be above ALERT1 + ALERT1_HYS to clear a 0001 thermal event … 1110 1111 A1EN Disable Enable Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 169 of 224 www.dialog-semiconductor.com...
  • Page 170 ALERT0LSB ALERT0LSB [7:0] 0..255 SYS2THERMAL2 0xA0 Register Name Address Read/Write Page 1 Reset Value 0x00 reserved A1EN ALERT1_HYST ALERT1MSB ALERT1MSB[1:0] 00..11 Alert1 threshold MSBs Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 170 of 224 www.dialog-semiconductor.com...
  • Page 171 Disable Enable A0PEN Policy action disable Policy action enable Register Name BAT0THERMAL1 Address 0xA4 Read/Write Page 1 Reset Value 0x00 ALERT0LSB ALERT0LSB [7:0] 0..255 Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 171 of 224 www.dialog-semiconductor.com...
  • Page 172 BPTHERM0 Register Name BAT1THERMAL0 Address 0xA9 Read/Write Page 1 Reset Value 0x00 A0PEN A0EN ALERT0_HYST ALERT0MSB ALERT0MSB[1:0] 00..11 Alert0 threshold MSBs Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 172 of 224 www.dialog-semiconductor.com...
  • Page 173 Reset Value 0x00 ALERT1LSB ALERT1LSB [7:0] 0..255 Register Name BAT1THERMCRITH Address 0xAD Read/Write Page 1 Reset Value 0x00 reserved TCRIT[9:8] TCRIT [9:8] 0..3 MSBs Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 173 of 224 www.dialog-semiconductor.com...
  • Page 174 Alert1 threshold MSBs ALERT1_HYST[0:3] 0000 SYSTEMP0 must be above ALERT1 + ALERT1_HYS to clear a 0001 thermal event … 1110 1111 A1EN Disable Enable Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 174 of 224 www.dialog-semiconductor.com...

  • Page 175: Critical Thermal Events

    16.4 Critical Thermal Events Unlike alerts, which are pre-emptive warnings, ―critical thermal events occur when the system or battery pack(s) or DA6021 die temperature exceed design thresholds, immediate action must be taken to resolve this thermal issue. 16.4.1 System Temperature...

  • Page 176: Battery Critical Temperature

    DA6021 sets the RBATTEMP bit in the RESETSRC0 register to indicate the reason for shutdown.  DA6021 sets BATCRIT in THRMIRQ2 to interrupt the SOC. However, the SOC may not have time to respond before the system is shut down.

  • Page 177: Thermal Monitoring Event Table

    Backup Battery Management Configuration and status registers of DA6021, and timekeeping logic (powered by a platform voltage rail VRTC) in the SOC are backed-up by a super capacitor or coin cell battery in case of SOC power loss (e.g., main battery changed).

  • Page 178: Backup Battery Charger

    Not charging Charging ongoing CHG_DONE_ST Not fully charged Back-up charging completed 16.5.2 Power Consumption The DA6021 logic supplied by the RTC domain will consume <5µA. Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 178 of 224 www.dialog-semiconductor.com...

  • Page 179: 17. General Purpose Ios

    17.1 Overview DA6021 provides 16 GPIO pins for general purpose IOs under the control of the SoC. The majority of these GPIO pins have a default configuration as CMOS inputs with weak (50 KOhm) pull downs enabled. The GPIO buffers support operation as open-drain or push pull outputs. They are split into 2 groups, each with a different fixed supply: ...

  • Page 180: Gpio Digital Features

    GPIO PAD cell. Interrupts can be generated on rising and/or falling edges of GPIO inputs. DA6021 provides includes an internal interrupt interface collecting all events from various modules to generate the interrupt signal to the SOC. The interrupt options are defined in GPIOx_IRQCFG register.

  • Page 181: Defining An Output Value

    GPIO1P4 can be used as an additional wakeup input forcing the PCSM to switch to S0 state GPIO1P5 – WAKE2 17.7.9 GPIO1P5 can be used as an additional wakeup input forcing the PCSM to switch to S0 state. Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 181 of 224 www.dialog-semiconductor.com...

  • Page 182: Electrical Characteristics

    Reset Value 0x14 reserved PULL_EN PULL_LVL PULL_DIR DOUT DOUT Low output High output (CMOS or high-Z OD) PULL_DIR Pull down Pull up 2kΩ PULL_LVL 50kΩ Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 182 of 224 www.dialog-semiconductor.com...
  • Page 183 Pull up 2kΩ PULL_LVL 50kΩ PULL_EN No pull-up or pull-down Pull-up/-down enable CMOS Open Drain Input Output Normal GPIO port GPIO used with alternative function Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 183 of 224 www.dialog-semiconductor.com...
  • Page 184 GPIO0P4_IRQ No pending Interrupt Interrupt pending GPIO0P5_IRQ No pending Interrupt Interrupt pending GPIO0P6_IRQ No pending Interrupt Interrupt pending GPIO0P7_IRQ No pending Interrupt Interrupt pending Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 184 of 224 www.dialog-semiconductor.com...
  • Page 185 IRQ unmasked IRQ masked MGPIO0P4_IRQ IRQ unmasked IRQ masked MGPIO0P5_IRQ IRQ unmasked IRQ masked MGPIO0P6_IRQ IRQ unmasked IRQ masked MGPIO0P7_IRQ IRQ unmasked IRQ masked Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 185 of 224 www.dialog-semiconductor.com...
  • Page 186 IRQ unmasked IRQ masked MGPIO0P4_IRQ IRQ unmasked IRQ masked MGPIO0P5_IRQ IRQ unmasked IRQ masked MGPIO0P6_IRQ IRQ unmasked IRQ masked MGPIO0P7_IRQ IRQ unmasked IRQ masked Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 186 of 224 www.dialog-semiconductor.com...
  • Page 187 IRQ unmasked IRQ masked MGPIO1P4_IRQ IRQ unmasked IRQ masked MGPIO1P5_IRQ IRQ unmasked IRQ masked MGPIO1P6_IRQ IRQ unmasked IRQ masked MGPIO1P7_IRQ IRQ unmasked IRQ masked Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 187 of 224 www.dialog-semiconductor.com...

  • Page 188: 18. External Battery Charger Control

    USB charger detected. ILIM0 and ILIM1 pins of DA6021 will output signals to the charger to set the charger input current limit. The external charger is capable of interrupt which will be forwarded to the SoC via DA6021. This interrupt will come from the CHGRINT_B pin.

  • Page 189: Battery Charger Registers

    Charger IRQ unmasked Charger IRQ masked Register Name MCHRG_IRQ Address 0x18 Read/Write Page 1 Reset Value 0x01 Reserved MCHRG_ CHRG_IRQ Charger IRQ unmasked Charger IRQ masked Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 189 of 224 www.dialog-semiconductor.com...

  • Page 190: 19. Interrupt Controller

    The interrupt control unit maintains the state of the First Level IRQ tree and is responsible for asserting and de- asserting the DA6021’s IRQ to the application SoC. It contains status bits for interrupts from all the second-level sub-blocks. If unmasked, the second-level interrupts will propagate to the appropriate first-level interrupt bit, as assigned below.
  • Page 191 2 critical Unit temperature event occurs Thermal Set by the thermal state machine when PMICCRIT THRMIRQ1 THRM Control a PMIC die critical temperature event Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 191 of 224 www.dialog-semiconductor.com...
  • Page 192 Unit generated. Each GPIO pin can be configured as GPIOxPx GPIOIRQ GPIO GPIO DINxPx input with programmable interrupt edge Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 192 of 224 www.dialog-semiconductor.com...

  • Page 193: Critical Race Condition (Set Vs. Clear)

    CHRG CHRG IRQ not asserted CHRG IRQ asserted GPIO GPIO IRQ not asserted GPIO IRQ asserted HDMI HDMI IRQ not asserted HDMI IRQ asserted Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 193 of 224 www.dialog-semiconductor.com...
  • Page 194 ADC IRQ masked MCHRG CHRG IRQ unmasked CHRG IRQ masked MGPIO GPIO IRQ unmasked GPIO IRQ masked MHDMI HDMI IRQ unmasked HDMI IRQ masked Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 194 of 224 www.dialog-semiconductor.com...

  • Page 195: 20. Power Button & Utility Button

    The table below provides the PWRBTNIN_B pad thresholds: L->H H->L Vhyst Vth, high Vth, low [mV] [mV] [mV] 672.5 577.5 927.5 732.5 1158.5 860.5 Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 195 of 224 www.dialog-semiconductor.com...

  • Page 196: Power Button

    PWRBTN_B signal is only valid when RSMRST=1. If the system is in SOC_G3 state and the power button is pressed more than 100ms, the DA6021 switches on all suspend (*_A) rails, de-asserts RSMRST_B after the power button is released and passes the power button information towards the SoC.

  • Page 197: Force A Cold Off Sequence

    DA6021 triggers a “Cold Off” sequence when the power button is hold for more than in register PBCONFIG specified time (default is 4sec). In the event of such a “Cold Off” sequence, DA6021 sets the RFCO (Reset due to Forced Cold Off) in register RESETSRCCRIT and clears the timer PBHT bits in the power button status register PBSTATUS.

  • Page 198: Power Button Registers

    PBLVL PWR button pressed PWR button released PBDT Power button disable timer, clears when expired not disabled (0s) 30s disabled 60s disabled 120s disabled Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 198 of 224 www.dialog-semiconductor.com...
  • Page 199 PBHT[3:0] Time that UI button has been held down 00000 00001 0.5s 00010 … … 11111 15.5s UBLVL UI button pressed UI button released Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 199 of 224 www.dialog-semiconductor.com...

  • Page 200: 21. Pulse Width Modulation Generation

    Each of the PWM outputs is able to generate output frequencies from ~23.44 KHz down to ~183Hz in 128 steps.  f= (6MHz/256) / (FREQ+1) The duty cycle can be selected between 1/256 to 256/256 (always high). 21.3 PWM Output Signals There are 3 PWM output signals (PWM[2:0]) on DA6021 Name Voltage Pin Level Internal Level...
  • Page 201 Page 1 Reset Value 0x00 DUTY DUTY[7:0] High for 1/256 PWM period High for 2/256 PWM period … High for 255/256 PWM period Always high Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 201 of 224 www.dialog-semiconductor.com...
  • Page 202 Page 1 Reset Value 0x00 DUTY DUTY[7:0] High for 1/256 PWM period High for 2/256 PWM period … High for 255/256 PWM period Always high Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 202 of 224 www.dialog-semiconductor.com...

  • Page 203: 22. Panel Control

    22.1 Overview The DA6021 provides two pins for display panel control, BACKLIGHT_EN to enable the display backlight circuit and PANEL_EN to enable the display panel electronics. The buffers driving these pins are slew-rate controlled push-pull output buffers similar to the GPIOs, each capable of high-voltage (3.3V) operation.

  • Page 204: Debug Ports

    _CLK _DATA _ALERT# “H” (VSYS) DATA ALERT# Disabled Disabled Disabled “L” (0V) Disabled Disabled Disabled DATA ALERT# Table 112: SVID Debug Port Truth Table Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 204 of 224 www.dialog-semiconductor.com...

  • Page 205: I2C Debug Port

    I2C Debug port This addresses I2C in a way similar to the SVID. The intent is to disable DA6021 I2C buffers connected to the SOC when in debug mode and redirect communication to an external bus master using a secondary set of pins.

  • Page 206: Table 113: I2C Debug Port Truth Table

    I2C channel select pin (DEBUG_CS) as shown in the figure above. When DEBUG_CS is tied to VSYS, DA6021 directs the internal channel to external channel 0 and disables the I/O of external channel 1. When DEBUG_CS is tied to ground, DA6021 enables communication between External Channel 1 and the internal channel, with External Channel 0 I/O disabled.

  • Page 207: 24. Register Map

    LOWBATSDP PSDETCFG 0x25 DBIEN BATRMSRC BATRMDE BATDBEN VDCINDBEN VBUSDBEN PBCONFIG 0x26 PBDBCNT UIBTNDISA CLRUIBHT FCOT PBSTATUS 0x27 PBDT PBLVL PBHT UBSTATUS 0x28 UBLVL UBHT Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 207 of 224 www.dialog-semiconductor.com...
  • Page 208 0x8C IVDDQ IVDDQRSLTL 0x8D IVDDQ THRMMONCTL0 0x8E SYSFRQS BATFRQS SYSFRQA BATFRQA THRMEN THRMMONCTL1 0c8F PMICFRQS PMICFRQA TS_ENABLE 0x90 PMICEN BAT1EN BAT0EN SYS2EN SYS1EN SYS0EN Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 208 of 224 www.dialog-semiconductor.com...

  • Page 209: Table 114: Da6021 Register Map

    TS_CRIT_ST 0xBD PMICST BAT1ST BAT0ST SYS2ST SYS1ST SYS0ST reserved 0xBE. .0xC5 VREFDQ1_CTRL 0xC6 VREFDQVSEL VREFDQ_SEL VREFDQ_EN reserved 0xC7. .0xFF Table 114: DA6021 Register Map Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 209 of 224 www.dialog-semiconductor.com...

  • Page 210: 25. Package Information

    INTEL® ATOM™ Z3000 PROCESSOR 25. Package Information 25.1 DA6021 Package Details 25.1.1 Pin Description, Pin Out Below is the pin description list of DA6021. In the type column the following abbreviations have been used  PS, VSS Power Supply  DI, DO, DIO Digital Input, Output, Input/Output ...
  • Page 211 Ground VDDQ_GND2B Ground V2P85S_GNDA Ground V2P85S_GNDB Ground interrupt output signal PWM1 PWM1 output signal PWM0 PWM0 output signal PWM2 PWM2 output signal PWM_GND Ground Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 211 of 224 www.dialog-semiconductor.com...
  • Page 212 SLP_S4_B input signal SLP_S0IX_B SLP_S0iX_B input signal SLP_S3_B SLP_S3_B input signal SDMMC3_PWR_EN_B SDMMC-card power enable SDMMC3_1P8_EN SDMMC-card power select PWRBTN_B Power button signal towards SoC Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 212 of 224 www.dialog-semiconductor.com...
  • Page 213 SVID clock signal DEBUG_SVID_ALERT_B debug SVID alert signal GPIO0P6 ADIO low voltage GPIO 6 DGND35 Ground DGND36 Ground DGND37 Ground DGND38 Ground DGND39 Ground Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 213 of 224 www.dialog-semiconductor.com...
  • Page 214 V3P3A LX node 2 V3P3A_A buck boost V3P3A output voltage DGND16 Ground DGND17 Ground VCC_GND1A Ground GPIO1P7 ADIO high voltage GPIO 7 Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 214 of 224 www.dialog-semiconductor.com...
  • Page 215 GPIO 2 GPIO1P1 ADIO high voltage GPIO 1 GPIO1P0_UIBTN_B ADIO high voltage GPIO 0 PROCHOT_B DA6021 high temperature indication VREFT Reference thermistor output voltage VREFB Reference voltage battery ID measurement PWRBTNIN_B power detection input signal VDCIN_SENSE DC input voltage detection...
  • Page 216 V1P0S_FB V1P0S sense line V1P0SX_EN V1P0SX external FET control line VREF12_GND Ground PMICTEST test signal V5P0S_LXA V5P0S buck boost LX node 1 Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 216 of 224 www.dialog-semiconductor.com...
  • Page 217 B BCUDISCRIT system voltage in critical range I2CM_SDA EEPROM data signal VSYS21 system power supply VSYS22 system power supply Table 115: DA6021 Ball Order Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 217 of 224 www.dialog-semiconductor.com...

  • Page 218: Da6021 325 Pin Fcbga Package

    DA6021 Company Confidential HIGHLY INTEGRATED POWER MANAGEMENT IC FOR INTEL® ATOM™ Z3000 PROCESSOR 25.2 DA6021 325 Pin FCBGA Package Map of ball allocations as seen from above the package. Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 218 of 224 www.dialog-semiconductor.com...

  • Page 219: Component Marking

    25.3 Component Marking Every component will be marked according to the following:  Product code – DA6021, as referred to in the relevant purchase order.  Dialog logo.  Date of manufacture, in a four digit code of the form WWYY (e.g. 3504) or other codes as agreed upon.

  • Page 220: Soldering Profile

    • Board finish Referring to IPC/JEDEC J-STD-20D.a the figure and table below show the recommended reflow profile condition for 3Sn/37Pb and lead free solder. Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 220 of 224 www.dialog-semiconductor.com...
  • Page 221 DA6021 Company Confidential HIGHLY INTEGRATED POWER MANAGEMENT IC FOR INTEL® ATOM™ Z3000 PROCESSOR Table 116: Soldering Profile Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 221 of 224 www.dialog-semiconductor.com...
  • Page 222 V1P8A 1µF ±20% 6.3V 0201 Output stabilization capacitor GPIO0_VDD 100nF ±10% 0201 Supply voltage filter capacitor GPIO1_VDD 100nF ±10% 0201 Supply voltage filter capacitor Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 222 of 224 www.dialog-semiconductor.com...
  • Page 223 330pF ±5% 0201 optional VBUS_SENSE 10nF ±20% 0201 Optional VBAT_SENSE 10nF ±20% 0201 optional VDCIN_SENSE 10nF ±20% 0201 optional Table 117: DA6021 BOM Proposal Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 223 of 224 www.dialog-semiconductor.com...
  • Page 224 Dialog Semiconductor excludes all liability in this respect. Customer notes that nothing in this document may be construed as a license for customer to use the Dialog Semiconductor products, software and applications referred to in this document. Such license must be separately sought by customer with Dialog Semiconductor.
  • Page 225 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.

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