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CYP15G0101DXB
Cypress Semiconductor CYP15G0101DXB Manuals
Manuals and User Guides for Cypress Semiconductor CYP15G0101DXB. We have
1
Cypress Semiconductor CYP15G0101DXB manual available for free PDF download: User Manual
Cypress Semiconductor CYP15G0101DXB User Manual (41 pages)
Brand:
Cypress Semiconductor
| Category:
Motherboard
| Size: 1 MB
Table of Contents
Table of Contents
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1 Overview
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2 Kit Contents
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3 Features of the CYP15G0101DXB
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4 Functional Description of CYP15G0101DXB
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Figure 1. CYP15G0101DXB Transmitter Section Block Diagram
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Figure 2. CYP15G0101DXB Hotlink II™ Block Diagram
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Figure 3. CYP15G0101DXB Receiver Section Block Diagram
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5 Board Layout, Photograph and Pin Descriptions
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Figure 4. CYP15G0101DXB-EVAL Skeletal View
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Figure 5. Pin Description of CYP15G0101DXB-EVAL
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Table 1. Description of Connectors of the CYP15G0101DXB Evaluation Board
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Table 2. Description of Control Pins in JT7
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6 Test Modes
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Figure 6. the bist Mode Operation
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Adjusting Settings on the Board
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Figure 7. Control Switches for Test Set-Up
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Figure 8. Controlling REFCLK Settings
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BIST Test Set-Up
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BIST Internal Loopback Mode
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Equipment Required
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Figure 9. Controlling SWT1 Dip Switches Settings
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Figure 10. Controlling JT7 Pins Settings
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Table 3. the High, MID, and Low Levels on JT32
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Test Equipment Set-Up
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Test Set-Up
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Figure 11. Pictorial Representation of the Internal bist Set-Up
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Table 4. the Levels of Different Static Signals on JT7 for bist Mode
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Figure 12. Signal on RXST1 When bist Is Successful
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Table 5. Channel Enabling Controls
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BIST External Loopback Mode
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Equipment Required
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Test Set-Up
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Figure 13. the Eye Diagram through the Signal Analyzer
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Figure 14. Coaxial Cable Connection for External bist Mode
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Parallel Data in - Parallel Data out Mode
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Encoded Mode
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Equipment Required
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Test Set-Up
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Figure 15. Generated Clock, Data and Control Signal from DG2020
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Result Verification
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Unencoded Mode (Parallel-In - Parallel-Out)
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Equipment Required
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Test Set-Up
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Table 6. the Levels of Static Signals on JT32 for Parallel In-Parallel out Mode (Encoded)
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Table 7. the Levels of Static Signals on JT32 for Parallel In-Parallel out Mode (Unencoded)
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Table 8. Output Register Bit Assignments
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Table 9. Input Register Bit Assignments
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Result Verification
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Operational Variations for Parallel-In-Parallel-Out Mode
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Equipment Required
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Test Set-Up and Result Verification
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Figure 16. Adding Two Framing Characters to Data Stream
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7 Schematic Diagram, PCB Layout, and Bill of Materials (BOM)
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Table 10.Operation Specification of CYP15G0101DXB Eval Board
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Appendix A. Schematic Diagram of CYP15G0101DXB Evaluation Board
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Figure 17. CYP15G0101DXB-EVAL Top Level Schematics
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Figure 18. CYP15G0101DXB-EVAL Terminated Transmitter & Receiver Blocks
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Figure 19. CYP15G0101DXB-EVAL Terminated Control Signals Block
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Figure 20. CYP15G0101DXB-EVAL Transmit and Receive Clock Schematics
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Figure 21. CYP15G0101DXB-EVAL Input Power Schematics
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Appendix B. PCB Layout for CYP15G0101DXB Evaluation Board
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Figure 22. CYP15G0101DXB-EVAL Top Layout
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Figure 23. CYP15G0101DXB-EVAL Bottom Layout
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Figure 24. CYP15G0101DXB-EVAL Top Layer Silk Layout
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Figure 25. CYP15G0101DXB-EVAL Bottom Layer Silk Layout
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Figure 26. CYP15G0101DXB-EVAL Top Layer Solder Mask Layout
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Figure 27. CYP15G0101DXB-EVAL Bottom Layer Solder Mask Layout
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Figure 28. CYP15G0101DXB-EVAL Power Plane Layout
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Figure 29. CYP15G0101DXB-EVAL Ground Plane Layout
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Appendix C. Bill of Materials (BOM) CYP15G0101DXB Evaluation Board
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Table 11.CYP15G0101DXB Eval Board Bill of Materials
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