Bouffalo Lab BL706 Development Board Manuals

Manuals and User Guides for Bouffalo Lab BL706 Development Board. We have 1 Bouffalo Lab BL706 Development Board manual available for free PDF download: Reference Manual

Bouffalo Lab BL706 Reference Manual

Bouffalo Lab BL706 Reference Manual (375 pages)

Brand: Bouffalo Lab | Category: Microcontrollers | Size: 4 MB

Table of Contents

Table of Contents

2
List of Figures

18
- Function Description
  22
- Introduction
  22
- Main Features
  22
- System and Memory Overview
  22
- Bus Connection
  23
- Memory Map
  23
- Interrupt Source
  24
- Memory Map
  24
- Interrupt Source
  25
- Introduction
  26
- Reset and Clock
  26
- Reset Source
  26
- Clock Source
  27
- Reset Source
  27
- Clock Architecture
  28
- Clock Management
  29
- Function Description
  29
- Glb
  29
- Introduction
  29
- Reset Management
  29
- Software Reset Function Table
  30
- Bus Management
  31
- GPIO Main Features
  31
- GPIO Overview
  31
- Memory Management
  31
- Basic Block Diagram of GPIO
  32
- GPIO Function Description
  32
- GPIO Function Setting
  33
- GPIO Function Table
  33
- GPIO Function Table
  34
- GPIO Function Table
  35
- GPIO Function Table
  36
- GPIO Input Settings
  37
- GPIO Optional Function Settings
  37
- GPIO Output Settings
  37
- GPIO Interrupt Settings
  38
- Register Description
  38
- Clk_Cfg0
  40
- Clk_Cfg1
  41
- Clk_Cfg2
  42
- Clk_Cfg3
  43
- Swrst_Cfg0
  43
- Swrst_Cfg1
  44
- Swrst_Cfg2
  45
- Cgen_Cfg0
  46
- Cgen_Cfg1
  46
- Bmx_Cfg1
  47
- Bmx_Cfg2
  48
- Bmx_Err_Addr
  48
- Cpu_Clk_Cfg
  49
- Seam_Misc
  49
- Dig32K_Wakeup_Ctrl
  50
- Gpadc_32M_Src_Ctrl
  50
- Uart_Sig_Sel_0
  51
- Gpio_Cfgctl0
  53
- Gpio_Cfgctl1
  54
- Gpio_Cfgctl2
  55
- Gpio_Cfgctl3
  56
- Gpio_Cfgctl4
  57
- Gpio_Cfgctl5
  58
- Gpio_Cfgctl6
  59
- Gpio_Cfgctl7
  60
- Gpio_Cfgctl8
  61
- Gpio_Cfgctl9
  62
- Gpio_Cfgctl10
  63
- Gpio_Cfgctl11
  64
- Gpio_Cfgctl12
  65
- Gpio_Cfgctl13
  66
- Gpio_Cfgctl14
  67
- Gpio_Cfgctl15
  68
- Gpio_Cfgctl16
  69
- Gpio_Cfgctl17
  69
- Gpio_Cfgctl18
  70
- Gpio_Cfgctl30
  71
- Gpio_Cfgctl32
  72
- Gpio_Cfgctl34
  74
- Gpio_Cfgctl35
  76
- Gpio_Int_Mask1
  77
- ADC Block Diagram
  91
- ADC External Pins
  92
- ADC Internal Signals
  92
- ADC Clock
  93
- ADC Conversion Result Format
  95
- Nec
  99
- DAC Basic Block Diagram
  112
- Internal Reference Voltage
  113
- DMA Architecture
  121
- LLI Architecture
  124
- L1C Architecture
  158
- Waydisable Settings
  159
- Cache Architecture
  160
- Nec Logical
  164
- Rc5 Logical
  164
- SPI Clock
  179
- SPI Ignore Waveform
  180
- UART Data
  190
- UART Clock
  191
- UART Sampling Waveform
  192
- UART Fixed Character Mode Waveform
  193
- UART Flow Control
  194
- Pin Lists
  207
- I2C Data Transmission Format
  208
- I2C Stop/Start Condition
  208
- Master Rx and Slave Tx
  209
- Master Tx and Slave Rx
  209
- Tx and Rx Together
  210
- PWM Waveform
  223
- Duty Cycle Parameters
  224
- Timer Block Diagram
  240
- Watchdog Timer Block Diagram
  241
- Timer Preload
  242
- Watchdog Timing
  243
- Watchdog Alarm Mechanism
  244
- QDEC Functional Block Diagram
  264
- I2S Pin List
  281
- EMAC Architecture
  291
- Transmission Signal
  292
- Transmission Signal
  293
- USB Interrupt Trigger Mode
  310
- USB Communication Method
  313
- Register Configuration
  314
- Register Configuration
  315
- Low Power Mode
  349
- Power Mode
  351
- Document Revision History
  375

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