1. Manuals
  2. Brands
  3. Bouffalo Lab Manuals
  4. Microcontrollers
  5. BL702
  6. Reference manual

Bouffalo Lab BL702 Reference Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

BL702/704/706
Reference Manual
version：1.2
copyright @ 2021
www.bouffalolab.com

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the BL702 and is the answer not in the manual?

Questions and answers

Summary of Contents for Bouffalo Lab BL702

  • Page 1 BL702/704/706 Reference Manual version：1.2 copyright @ 2021 www.bouffalolab.com...

  • Page 2: Table Of Contents

    ........3.3.2 2/ 375 @2021 Bouffalo Lab BL702/704/706 Reference Manual...
  • Page 3 BL702/704/706 Reference Manual clk_cfg2 ........
  • Page 4 BL702/704/706 Reference Manual GPIO_INT_STAT1 ....... . 3.3.42 GPIO_INT_CLR1 ....... .
  • Page 5 BL702/704/706 Reference Manual gpadc_reg_scn_neg2 ......4.4.9 gpadc_reg_status ....... .
  • Page 6 BL702/704/706 Reference Manual DMA_EnbldChns ....... . 6.5.8 DMA_SoftBReq ....... . .
  • Page 7 BL702/704/706 Reference Manual DMA_C6LLI ........6.5.47 DMA_C6Control .
  • Page 8 BL702/704/706 Reference Manual irtx_swm_pw_3 ....... . . 8.4.10 irtx_swm_pw_4 ....... . .
  • Page 9 BL702/704/706 Reference Manual 10.2 UART main features ........
  • Page 10 BL702/704/706 Reference Manual 11.5 I2C configuration process ....... Configuration item ....... .
  • Page 11 BL702/704/706 Reference Manual pwm0_config ........12.4.6 pwm0_interrupt ....... . .
  • Page 12 BL702/704/706 Reference Manual TMR2_2 ........
  • Page 13 BL702/704/706 Reference Manual qdec0_ctrl1 ........14.4.2 qdec0_value .
  • Page 14 BL702/704/706 Reference Manual i2s_fifo_config_0 ....... . 16.4.4 i2s_fifo_config_1 ....... .
  • Page 15 BL702/704/706 Reference Manual 18.3 USB function description ..............
  • Page 16 BL702/704/706 Reference Manual 18.4.34 ep4_fifo_status ....... . . 18.4.35 ep4_tx_fifo_wdata ....... .
  • Page 17 BL702/704/706 Reference Manual ........19.5.2 PDS_TIME1 PDS_INT ........
  • Page 18 11.1 I2C stop/start condition ......... . . 18/ 375 @2021 Bouffalo Lab BL702/704/706 Reference Manual...
  • Page 19 BL702/704/706 Reference Manual 11.2 I2C data transmission format ........
  • Page 20 18.1 Register configuration 1 ......... . . 20/ 375 @2021 Bouffalo Lab BL702/704/706 Reference Manual...
  • Page 21 BL702/704/706 Reference Manual 18.2 Register configuration 2 ......... . .

  • Page 22: System And Memory Overview

    • Off-chip memory Flash 1.3 Function description The BL702/704/706 bus connection and address access are summarized as follows: The bus master includes CPU, Ethernet, DMA, encryption engine, debugging interface. The bus slave includes memory, peripherals, and Zigbee/BLE. Except for Ethernet and encryption engine which can only access memory, all other bus masters can access all bus slaves.

  • Page 23: Bus Connection

    BL702/704/706 Reference Manual Table 1.1: Bus connection Ethernet Encryption Debug Slave/Master engine interface memory Peripheral Zigbee/BLE The address access mainly distinguishes ”memory” or ”peripheral” by [27:24], and the [31:28] bits can be ignored. The memory space is consecutive addresses 0x2010000~0x202FFFF (128KB SRAM)，the read-only memory address is 0x1000000，...

  • Page 24: Memory Map

    BL702/704/706 Reference Manual Table 1.2: Memory Map Base Address Size Description Module eFuse 0x40007000 eFuse memory control 0x40004000 Security engine GPIP 0x40002000 General purpose DAC/ADC/ACOMP interface control 0x40001000 Mixed signal register 0x40000000 Global control register pSRAM 0x24000000 pSRAM memory 0x23000000...

  • Page 25: Interrupt Source

    BL702/704/706 Reference Manual Table 1.3: Interrupt source Signal source uart0_irq spi_int efuse_int adc_int flash_int emac_int usb_int 19~20 ir_remote_int i2s_int dma_int 9~14 sec_eng_int err_int rf_int err_int BL702/704/706 Reference Manual 25/ 375 @2021 Bouffalo Lab...

  • Page 26: Reset And Clock

    – Software system reset (reg_ctrl_sys_reset): Trigger the rising edge of this register by software, retain neces- sary logic processing such as power management unit, and reset the chip part of the system – Software module reset: Set software reset according to the needs of specific modules 26/ 375 @2021 Bouffalo Lab BL702/704/706 Reference Manual...

  • Page 27: Clock Source

    BL702/704/706 Reference Manual EXT _RST _N ana_pwrst_n ana_powb ~pds_misc_rst wdt _rst_src_ ana_ext_pwr_rst_n Sync pwronrst_n reg_ctrl _pwron _rst reg_ctrl _cpu_reset cpu_porst_n Sync cpu_rst_n efuse_cpu_rst_dis ~pds_cpu_rst efuse_autoload_done ~pds_soc_rst Sync hreset_n reg_ctrl _sys_reset cpu_sys_rstreq_ Sync nwdt_hreset_n Fig. 2.1: Reset source 2.3 Clock source The clock source includes: •...

  • Page 28: Clock Architecture

    BL702/704/706 Reference Manual 11bit f32k_clk XTAL32K RC32K f32k_sel qdec clk(1MHz) general adc clk 5bit 6bit kys clk(1MHz) AUPLL i2s clk(~2MHz) kys clk(128KHz) 24.576MHz 32.768MHz gpdac clk 32MHz (~512KHz) xtal_clk xclk pwm clk RC32M 16bit root_clk_sel[0] ir clk i2c clk (~2MHz)

  • Page 29: Glb

    • System reset: All peripherals and CPU will be reset, but related registers in the AON domain will not be reset • Power-on reset: the entire system including the related registers of the AON domain will be reset The application can choose to use the corresponding reset method as needed. 29/ 375 @2021 Bouffalo Lab BL702/704/706 Reference Manual...

  • Page 30: Software Reset Function Table

    BL702/704/706 Reference Manual Table 3.1: Software reset function table BL702 RST_PIN/HBN/WDT SW.Reset CPU/PDS/SYS PDS/CPU /POWER ON ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ swrst_s1[0] ✓ ✓ ✓ ✓ ✓ ✓ gpip swrst_s1[2] ✓...

  • Page 31: Bus Management

    BL702/704/706 Reference Manual 3.2.3 Bus management Provide bus arbitration settings and bus error settings, you can set whether to generate an interrupt when a bus error occurs, and provide error bus address information to facilitate user debugging. 3.2.4 Memory management...

  • Page 32: Gpio Function Description

    BL702/704/706 Reference Manual 3.2.7 GPIO function description Each GPIO can be configured by software as: • Multiple functions: I2S, SPI, I2C, UART, PWM, USB, SWGPIO... up to 24 functions • InputEnable/OutputEnable: input, output, high impedance (ie=0, oe=0) • PullUp/PullDown: pull up, pull down, float (pu=0, pd=0) •...

  • Page 33: Gpio Function Setting

    BL702/704/706 Reference Manual 3.2.8 GPIO function setting The function of GPIO is set through the GPIO_CFGCTL register group. The main setting items include: • func_sel: select GPIO function • pu: Choose whether to pull up • pd: Choose whether to drop down •...

  • Page 34: Gpio Function Table

    BL702/704/706 Reference Manual Table 3.2: GPIO function table 1 CLK_OUT Flash_PSRAM SPI0 UART GPIO GPIO6 clk_out[0] DIO/DO SIG6/SIG2 PWM[1] GPIO7 clk_out[1] RCLK_O/DI SCLK SIG7/SIG3 PWM[2] GPIO8 clk_out[0] BCLK MISO/MOSI SIG0/SIG4 PWM[3] GPIO9 clk_out[1] MOSI/MISO SIG1/SIG5 PWM[4] GPIO10 clk_out[0] DIO/DO SIG2/SIG6...

  • Page 35: Gpio Function Table

    BL702/704/706 Reference Manual Table 3.3: GPIO function table 2 Analog SWGPIO JTAG Ether_Mac QDEC GPIO GPIO0 GPIO[0] TMS/TCK MII_REF_CLK GPIO1 GPIO[1] TDI/TDO MII_TXD[0] GPIO2 GPIO[2] TCK/TMS MII_TXD[1] GPIO3 GPIO[3] TDO/TDI GPIO4 GPIO[4] TMS/TCK GPIO5 GPIO[5] TDI/TDO GPIO6 GPIO[6] TCK/TMS GPIO7...

  • Page 36: Gpio Function Table

    BL702/704/706 Reference Manual Table 3.3: GPIO function table 2 Analog SWGPIO JTAG Ether_Mac QDEC GPIO GPIO31 GPIO[31] TDO/TDI Table 3.4: GPIO function table 3 SWGPIO GPIO GPIO SWGPIO GPIO17 pad_irrx_i,irrxgpsl=1 GPIO18 pad_irrx_i,irrxgpsl=2 GPIO19 pad_irrx_i,irrxgpsl=3 GPIO20 pad_irrx_i,irrxgpsl=4 GPIO21 pad_irrx_i,irrxgpsl=5 GPIO22 pad_irrx_i,irrxgpsl=6...

  • Page 37: Gpio Output Settings

    BL702/704/706 Reference Manual • 1 : UART0_CTS • 2 : UART0_TXD • 3 : UART0_RXD • 4 : UART1_RTS • 5 : UART1_CTS • 6 : UART1_TXD • 7 : UART1_RXD Take GPIO0 as an example, when fun_sel selects UART, GPIO0 selects UART_SIG0. By default, the value of UART_- SIG0_SEL is 0, which is UART0_RTS, that is, GPIO is UART0_RTS function.

  • Page 38: Gpio Interrupt Settings

    BL702/704/706 Reference Manual affect the function. But as the input direction, IE must be set and the configuration of OE does not affect the function; when used as swgpio, both IE and OE need to be configured correctly. 3.2.12 GPIO interrupt settings To use the interrupt function of GPIO, you need to set GPIO to input mode first, and the interrupt trigger mode is set through the GPIO_INT_MODE_SET register group.
  • Page 39 BL702/704/706 Reference Manual Description Name DIG32K_WAKEUP_CTRL DIG32K wakeup control UART_SIG_SEL_0 UART Signal Select GPIO_CFGCTL0 GPIO0, GPIO1 configuration GPIO_CFGCTL1 GPIO2, GPIO3 configuration GPIO_CFGCTL2 GPIO4, GPIO5 configuration GPIO_CFGCTL3 GPIO6, GPIO7 configuration GPIO_CFGCTL4 GPIO8, GPIO9 configuration GPIO_CFGCTL5 GPIO10, GPIO11 configuration GPIO_CFGCTL6 GPIO12, GPIO13 configuration...

  • Page 40: Clk_Cfg0

    BL702/704/706 Reference Manual Description Name GPIO_INT_MODE_SET2 GPIO interrupt mode set2 GPIO_INT_MODE_SET3 GPIO interrupt mode set3 GPIO_INT_MODE_SET4 GPIO interrupt mode set4 GPIO_INT2_MASK1 GPIO interrupt2 mask1 GPIO_INT2_STAT1 GPIO interrupt2 state1 GPIO_INT2_CLR1 GPIO interrupt2 clear1 GPIO_INT2_MODE_SET1 GPIO interrupt 2 mode set1 GPIO_INT2_MODE_SET2 GPIO interrupt 2 mode set2...

  • Page 41: Clk_Cfg1

    BL702/704/706 Reference Manual Name Type Reset Description Bits PLLSEL pll clock selection 0: 57.6MHz 1: 96MHz 2: 144MHz 3: 120MHz (Clock Freq will be changes with Audio PLL, not sugges use this CLK) BLCKEN bclk force on HCLKEN hclk force on...

  • Page 42: Clk_Cfg2

    BL702/704/706 Reference Manual Name Type Reset Description Bits QDECCSEL QDEC Clock Source Select. 0:xclk 1:f32k (PDS mode) RSVD QDECCDIV 5’d31 QDEC Clock Divider qdec_clk_sel/(N+1), default 1MHz 3.3.3 clk_cfg2 Address：0x40000008 DMAEN IRCL RSVD IRCLDIV SFSEL2 SFSEL SFEN SFDIV RSVD UART RSVD...

  • Page 43: Clk_Cfg3

    BL702/704/706 Reference Manual 3.3.4 clk_cfg3 Address：0x4000000c CCO1S CCO0S RSVD I2CDIV RSVD IRFT SREF SPIDIV Name Type Reset Description Bits 31:30 CCO1S 2’b0 clk_out_1 selection (0: no chip clock out, 1: i2s_ref_clk out, 2: audio_pll_clk out, 3: clk_xtal_soc_32M) 29:28 CCO0S 2’b0...

  • Page 44: Swrst_Cfg1

    BL702/704/706 Reference Manual Name Type Reset Description Bits 31:9 RSVD SRS30 software reset BLE RSVD SRS20 software reset M154 RSVD 3.3.6 swrst_cfg1 Address：0x40000014 RSVD RSVD S1AC S1AA S1A9 S1A8 S1A7 S1A6 S1A5 S1A4 S1A3 S1A2 S1A1 S1A0 RSVD RSVD Name...

  • Page 45: Swrst_Cfg2

    BL702/704/706 Reference Manual Name Type Reset Description Bits SRS1D software reset EMAC SRS1C software reset DMA SRS1B software reset SF RSVD SRS19 software reset L1C SRS18 software reset CCI SRS17 software reset eFuse SRS16 software reset TZ2 SRS15 software reset TZ1...

  • Page 46: Cgen_Cfg0

    BL702/704/706 Reference Manual Name Type Reset Description Bits CPURST cpu reset, see the software reset table for details PWORST power on reset, see the software reset table for details 3.3.8 cgen_cfg0 Address：0x40000020 RSVD RSVD CGENM Name Type Reset Description Bits...

  • Page 47: Bmx_Cfg1

    BL702/704/706 Reference Manual Name Type Reset Description Bits 31:16 CGENS1A 16’h9B23 [0] uart0 clock ungate enable [1] uart1 clock ungate enable [2] spi clock ungate enable [3] i2c clock ungate enable [4] pwm clock ungate enable [5] timer clock ungate enable...

  • Page 48: Bmx_Cfg2

    BL702/704/706 Reference Manual Name Type Reset Description Bits 3.3.11 bmx_cfg2 Address：0x40000054 RSVD RSVD RSVD ADDR Name Type Reset Description Bits 31:6 RSVD ERRTZ Bus trustzone decode error ERRDEC Bus addr decode error RSVD ADDRDIS Bus addr error monitor disable 3.3.12 bmx_err_addr Address：0x40000058...

  • Page 49: Seam_Misc

    BL702/704/706 Reference Manual 3.3.13 seam_misc Address：0x4000007c RSVD RSVD EMSEL Name Type Reset Description Bits 31:4 RSVD EMSEL 4’h3 em/ocram share memory em select 0x0: 0KB ; 0x3:8KB ; 0xF:16KB 3.3.14 CPU_CLK_CFG Address：0x40000090 RSVD RSVD RTCDIV Name Type Reset Description Bits...

  • Page 50: Gpadc_32M_Src_Ctrl

    BL702/704/706 Reference Manual 3.3.15 GPADC_32M_SRC_CTRL Address：0x400000a4 RSVD RSVD GADC GADC RSVD GADCDIV Name Type Reset Description Bits 31:9 RSVD GADCDIV GPADC 32M Clock Dvider Enable GADCSEL GPADC Clock Source Select. 0: Audio PLL, 1: xclk RSVD GADCDIV 6’d2 GPADC 32M Clock Divider (gpadc clock)/(N+1) 3.3.16 DIG32K_WAKEUP_CTRL...

  • Page 51: Uart_Sig_Sel_0

    BL702/704/706 Reference Manual Name Type Reset Description Bits 15:14 RSVD 32KCOMP Compensation => Duty of dig_32k_out = dig_32k_div : (dig_32k_div+1) 32KEN Enable dig_32k_out RSVD 10:0 32KDIV 11’d1000 (PLL 32MHz or xclk) / dig_32k_div Ex: Set 750 for 24MHz ; Set 1000 for 32MHz ; Set 1200 for 38.4MHz ;...
  • Page 52 BL702/704/706 Reference Manual Name Type Reset Description Bits 23:20 SIG5SEL 4’d5 UART Signal5 Select : 0 : UART0_RTS 1 : UART0_CTS 2 : UART0_TXD 3 : UART0_RXD 4 : UART1_RTS 5 : UART1_CTS 6 : UART1_TXD 7 : UART1_RXD 19:16 SIG4SEL 4’d4...

  • Page 53: Gpio_Cfgctl0

    BL702/704/706 Reference Manual Name Type Reset Description Bits SIG1SEL 4’d1 UART Signal1 Select : 0 : UART0_RTS 1 : UART0_CTS 2 : UART0_TXD 3 : UART0_RXD 4 : UART1_RTS 5 : UART1_CTS 6 : UART1_TXD 7 : UART1_RXD SIG0SEL UART Signal0 Select :...

  • Page 54: Gpio_Cfgctl1

    BL702/704/706 Reference Manual Name Type Reset Description Bits GP1IE GPIO Input Enable 15:13 RSVD 12:8 GP0FUNC 5’hE GPIO Function Select (Default : JTAG) RSVD GP0PD GPIO Pull Down Control GP0PU GPIO Pull Up Control GP0DRV GPIO Driving Control GP0SMT GPIO SMT Control...

  • Page 55: Gpio_Cfgctl2

    BL702/704/706 Reference Manual Name Type Reset Description Bits GP2PU GPIO Pull Up Control GP2DRV GPIO Driving Control GP2SMT GPIO SMT Control GP2IE GPIO Input Enable 3.3.20 GPIO_CFGCTL2 Address：0x40000108 RSVD GP5FUNC RSVD GP5DRV RSVD GP4FUNC RSVD GP4DRV Name Type Reset Description...

  • Page 56: Gpio_Cfgctl3

    BL702/704/706 Reference Manual 3.3.21 GPIO_CFGCTL3 Address：0x4000010c RSVD GP7FUNC RSVD GP7DRV RSVD GP6FUNC RSVD GP6DRV Name Type Reset Description Bits 31:29 RSVD 28:24 GP7FUNC 5’hB GPIO Function Select (Default : SWGPIO) 23:22 RSVD GP7PD GPIO Pull Down Control GP7PU GPIO Pull Up Control...

  • Page 57: Gpio_Cfgctl4

    BL702/704/706 Reference Manual 3.3.22 GPIO_CFGCTL4 Address：0x40000110 RSVD GP9FUNC RSVD GP9DRV RSVD GP8FUNC RSVD GP8DRV Name Type Reset Description Bits 31:29 RSVD 28:24 GP9FUNC 5’hE GPIO Function Select (Default : JTAG ) 23:22 RSVD GP9PD GPIO Pull Down Control (Use this bit if reg_en_hw_pu_pd...

  • Page 58: Gpio_Cfgctl5

    BL702/704/706 Reference Manual 3.3.23 GPIO_CFGCTL5 Address：0x40000114 RSVD GP11FUNC RSVD GP11 GP11 GP11DRV GP11 GP11 RSVD GP10FUNC RSVD GP10 GP10 GP10DRV GP10 GP10 Name Type Reset Description Bits 31:29 RSVD 28:24 GP11FUNC 5’hB GPIO Function Select (Default : SWGPIO ) 23:22...

  • Page 59: Gpio_Cfgctl6

    BL702/704/706 Reference Manual 3.3.24 GPIO_CFGCTL6 Address：0x40000118 RSVD GP13FUNC RSVD GP13 GP13 GP13DRV GP13 GP13 RSVD GP12FUNC RSVD GP12 GP12 GP12DRV GP12 GP12 Name Type Reset Description Bits 31:29 RSVD 28:24 GP13FUNC 5’hB GPIO Function Select (Default : SWGPIO ) 23:22...

  • Page 60: Gpio_Cfgctl7

    BL702/704/706 Reference Manual 3.3.25 GPIO_CFGCTL7 Address：0x4000011c RSVD GP15FUNC RSVD GP15 GP15 GP15DRV GP15 GP15 RSVD GP14FUNC RSVD GP14 GP14 GP14DRV GP14 GP14 Name Type Reset Description Bits 31:29 RSVD 28:24 GP15FUNC 5’hB GPIO Function Select (Default : SWGPIO ) 23:22...

  • Page 61: Gpio_Cfgctl8

    BL702/704/706 Reference Manual 3.3.26 GPIO_CFGCTL8 Address：0x40000120 RSVD GP17FUNC RSVD GP17 GP17 GP17DRV GP17 GP17 RSVD GP16FUNC RSVD GP16 GP16 GP16DRV GP16 GP16 Name Type Reset Description Bits 31:29 RSVD 28:24 GP17FUNC 5’hB GPIO Function Select (Default : SWGPIO ) 23:22...

  • Page 62: Gpio_Cfgctl9

    BL702/704/706 Reference Manual 3.3.27 GPIO_CFGCTL9 Address：0x40000124 RSVD GP19FUNC RSVD GP19 GP19 GP19DRV GP19 GP19 RSVD GP18FUNC RSVD GP18 GP18 GP18DRV GP18 GP18 Name Type Reset Description Bits 31:29 RSVD 28:24 GP19FUNC 5’hB GPIO Function Select (Default : SWGPIO ) 23:22...

  • Page 63: Gpio_Cfgctl10

    BL702/704/706 Reference Manual 3.3.28 GPIO_CFGCTL10 Address：0x40000128 RSVD GP21FUNC RSVD GP21 GP21 GP21DRV GP21 GP21 RSVD GP20FUNC RSVD GP20 GP20 GP20DRV GP20 GP20 Name Type Reset Description Bits 31:29 RSVD 28:24 GP21FUNC 5’hB GPIO Function Select (Default : SWGPIO ) 23:22...

  • Page 64: Gpio_Cfgctl11

    BL702/704/706 Reference Manual 3.3.29 GPIO_CFGCTL11 Address：0x4000012c RSVD GP23FUNC RSVD GP23 GP23 GP23DRV GP23 GP23 RSVD GP22FUNC RSVD GP22 GP22 GP22DRV GP22 GP22 Name Type Reset Description Bits 31:29 RSVD 28:24 GP23FUNC 5’hB GPIO Function Select (Default : SWGPIO ) 23:22...

  • Page 65: Gpio_Cfgctl12

    BL702/704/706 Reference Manual 3.3.30 GPIO_CFGCTL12 Address：0x40000130 RSVD GP25FUNC RSVD GP25 GP25 GP25DRV GP25 GP25 RSVD GP24FUNC RSVD GP24 GP24 GP24DRV GP24 GP24 Name Type Reset Description Bits 31:29 RSVD 28:24 GP25FUNC 5’hB GPIO Function Select (Default : SWGPIO ) 23:22...

  • Page 66: Gpio_Cfgctl13

    BL702/704/706 Reference Manual 3.3.31 GPIO_CFGCTL13 Address：0x40000134 RSVD GP27FUNC RSVD GP27 GP27 GP27DRV GP27 GP27 RSVD GP26FUNC RSVD GP26 GP26 GP26DRV GP26 GP26 Name Type Reset Description Bits 31:29 RSVD 28:24 GP27FUNC 5’hB GPIO Function Select (Default : SWGPIO ) 23:22...

  • Page 67: Gpio_Cfgctl14

    BL702/704/706 Reference Manual 3.3.32 GPIO_CFGCTL14 Address：0x40000138 RSVD GP29FUNC RSVD GP29 GP29 GP29DRV GP29 GP29 RSVD GP28FUNC RSVD GP28 GP28 GP28DRV GP28 GP28 Name Type Reset Description Bits 31:29 RSVD 28:24 GP29FUNC 5’hB GPIO Function Select (Default : SWGPIO ) 23:22...

  • Page 68: Gpio_Cfgctl15

    BL702/704/706 Reference Manual 3.3.33 GPIO_CFGCTL15 Address：0x4000013c RSVD GP31FUNC RSVD GP31 GP31 GP31DRV GP31 GP31 RSVD GP30FUNC RSVD GP30 GP30 GP30DRV GP30 GP30 Name Type Reset Description Bits 31:29 RSVD 28:24 GP31FUNC 5’hB GPIO Function Select (Default : SWGPIO ) 23:22...

  • Page 69: Gpio_Cfgctl16

    BL702/704/706 Reference Manual 3.3.34 GPIO_CFGCTL16 Address：0x40000140 RSVD GP33 GP33 GP33DRV GP33 GP33 RSVD GP32 GP32 GP32DRV GP32 GP32 Name Type Reset Description Bits 31:22 RSVD GP33PD GPIO Pull Down Control GP33PU GPIO Pull Up Control 19:18 GP33DRV GPIO Driving Control...

  • Page 70: Gpio_Cfgctl18

    BL702/704/706 Reference Manual Name Type Reset Description Bits GP35PD GPIO Pull Down Control GP35PU GPIO Pull Up Control 19:18 GP35DRV GPIO Driving Control GP35SMT GPIO SMT Control GP35IE GPIO Input Enable 15:6 RSVD GP34PD GPIO Pull Down Control GP34PU GPIO Pull Up Control...

  • Page 71: Gpio_Cfgctl30

    BL702/704/706 Reference Manual Name Type Reset Description Bits GP36SMT GPIO SMT Control GP36IE GPIO Input Enable 3.3.37 GPIO_CFGCTL30 Address：0x40000180 GP31 GP30 GP29 GP28 GP27 GP26 GP25 GP24 GP23 GP22 GP21 GP20 GP19 GP18 GP17 GP16 GP15 GP14 GP13 GP12 GP11...

  • Page 72: Gpio_Cfgctl32

    BL702/704/706 Reference Manual Name Type Reset Description Bits GP12I Register Controlled GPIO Input value GP11I Register Controlled GPIO Input value GP10I Register Controlled GPIO Input value GP9I Register Controlled GPIO Input value GP8I Register Controlled GPIO Input value GP7I Register Controlled GPIO Input value...
  • Page 73 BL702/704/706 Reference Manual Name Type Reset Description Bits GP23O Register Controlled GPIO Output Value GP22O Register Controlled GPIO Output Value GP21O Register Controlled GPIO Output Value GP20O Register Controlled GPIO Output Value GP19O Register Controlled GPIO Output Value GP18O Register Controlled GPIO Output Value...

  • Page 74: Gpio_Cfgctl34

    BL702/704/706 Reference Manual 3.3.39 GPIO_CFGCTL34 Address：0x40000190 GP31 GP30 GP29 GP28 GP27 GP26 GP25 GP24 GP23 GP22 GP21 GP20 GP19 GP18 GP17 GP16 GP15 GP14 GP13 GP12 GP11 GP10 Name Type Reset Description Bits GP31OE Register Controlled GPIO Output Enable (Used when GPIO...
  • Page 75 BL702/704/706 Reference Manual Name Type Reset Description Bits GP17OE Register Controlled GPIO Output Enable (Used when GPIO Function select to Register Control GPIO) GP16OE Register Controlled GPIO Output Enable (Used when GPIO Function select to Register Control GPIO) GP15OE Register Controlled GPIO Output Enable (Used when GPIO...

  • Page 76: Gpio_Cfgctl35

    BL702/704/706 Reference Manual 3.3.40 GPIO_CFGCTL35 Address：0x40000194 RSVD RSVD GP40 GP39 GP38 GP37 GP36 GP35 GP34 GP33 GP32 Name Type Reset Description Bits 31:9 RSVD GP40OE Register Controlled GPIO Output Enable (Used when GPIO Function select to Register Control GPIO) GP39OE...

  • Page 77: Gpio_Int_Mask1

    BL702/704/706 Reference Manual 3.3.41 GPIO_INT_MASK1 Address：0x400001a0 GPITMS1 GPITMS1 Name Type Reset Description Bits 31:0 GPITMS1 32’hFFFFFFFF reg_gpio_int_mask[31:0] 3.3.42 GPIO_INT_STAT1 Address：0x400001a8 GPITSTA1 GPITSTA1 Name Type Reset Description Bits 31:0 GPITSTA1 gpio_int_stat[31:0] 3.3.43 GPIO_INT_CLR1 Address：0x400001b0 GPITCLR1 GPITCLR1 Name Type Reset Description Bits...
  • Page 78 BL702/704/706 Reference Manual 3.3.44 GPIO_INT_MODE_SET1 Address：0x400001c0 RSVD GPITMS1 GPITMS1 Name Type Reset Description Bits 31:30 RSVD 29:0 GPITMS1 [2:0] : GPIO 0 Interrupt Mode Control[2:0] [5:3] : GPIO 1 Interrupt Mode Control[2:0] [8:6] : GPIO 2 Interrupt Mode Control[2:0] [11:9] : GPIO 3 Interrupt Mode Control[2:0]...
  • Page 79 BL702/704/706 Reference Manual Name Type Reset Description Bits 31:30 RSVD 29:0 GPITMS2 [2:0] : GPIO 10 Interrupt Mode Control[2:0] [5:3] : GPIO 11 Interrupt Mode Control[2:0] [8:6] : GPIO 12 Interrupt Mode Control[2:0] [11:9] : GPIO 13 Interrupt Mode Control[2:0]...
  • Page 80 BL702/704/706 Reference Manual Name Type Reset Description Bits 29:0 GPITMS3 [2:0] : GPIO 20 Interrupt Mode Control[2:0] [5:3] : GPIO 21 Interrupt Mode Control[2:0] [8:6] : GPIO 22 Interrupt Mode Control[2:0] [11:9] : GPIO 23 Interrupt Mode Control[2:0] [14:12] : GPIO 24 Interrupt Mode Control[2:0]...
  • Page 81 BL702/704/706 Reference Manual Name Type Reset Description Bits GPITMS4 [2:0] : GPIO 30 Interrupt Mode Control[2:0] [5:3] : GPIO 31 Interrupt Mode Control[2:0] [8:6] : GPIO 32 Interrupt Mode Control[2:0] [11:9] : GPIO 33 Interrupt Mode Control[2:0] [14:12] : GPIO 34 Interrupt Mode Control[2:0]...
  • Page 82 BL702/704/706 Reference Manual 3.3.49 GPIO_INT2_STAT1 Address：0x400001d4 GPIT2ST1 GPIT2ST1 Name Type Reset Description Bits 31:0 GPIT2ST1 gpio_int2_stat[31:0] 3.3.50 GPIO_INT2_CLR1 Address：0x400001d8 GPIT2CL1 GPIT2CL1 Name Type Reset Description Bits 31:0 GPIT2CL1 reg_gpio_int2_clr[31:0] 3.3.51 GPIO_INT2_MODE_SET1 Address：0x400001dc RSVD GPIT2MS1 GPIT2MS1 Name Type Reset Description Bits...
  • Page 83 BL702/704/706 Reference Manual Name Type Reset Description Bits 29:0 GPIT2MS1 [2:0] : GPIO 0 Interrupt Mode Control[2:0] [5:3] : GPIO 1 Interrupt Mode Control[2:0] [8:6] : GPIO 2 Interrupt Mode Control[2:0] [11:9] : GPIO 3 Interrupt Mode Control[2:0] [14:12] : GPIO 4 Interrupt Mode Control[2:0]...
  • Page 84 BL702/704/706 Reference Manual Name Type Reset Description Bits 29:0 GPIT2MS2 [2:0] : GPIO 10 Interrupt Mode Control[2:0] [5:3] : GPIO 11 Interrupt Mode Control[2:0] [8:6] : GPIO 12 Interrupt Mode Control[2:0] [11:9] : GPIO 13 Interrupt Mode Control[2:0] [14:12] : GPIO 14 Interrupt Mode Control[2:0]...
  • Page 85 BL702/704/706 Reference Manual Name Type Reset Description Bits 29:0 GPIT2MS3 [2:0] : GPIO 20 Interrupt Mode Control[2:0] [5:3] : GPIO 21 Interrupt Mode Control[2:0] [8:6] : GPIO 22 Interrupt Mode Control[2:0] [11:9] : GPIO 23 Interrupt Mode Control[2:0] [14:12] : GPIO 24 Interrupt Mode Control[2:0]...
  • Page 86 BL702/704/706 Reference Manual Name Type Reset Description Bits GPIT2MS4 [2:0] : GPIO 30 Interrupt Mode Control[2:0] [5:3] : GPIO 31 Interrupt Mode Control[2:0] [8:6] : GPIO 32 Interrupt Mode Control[2:0] [11:9] : GPIO 33 Interrupt Mode Control[2:0] [14:12] : GPIO 34 Interrupt Mode Control[2:0]...
  • Page 87 BL702/704/706 Reference Manual Name Type Reset Description Bits 11:8 IRRXGPSL 4’h0 0 : disable ir_rx select gpio 1 15 :select gpio 19 33 as ir_rx (GPIO need to set as SWG- PIO mode) LDRVIBIA 4’h8 ir led drive strength, [7:4]*8mA RSVD 3.3.56 usb_xcvr...
  • Page 88 BL702/704/706 Reference Manual Name Type Reset Description Bits OEBREG 1’b1 Leave it as the default OEBSEL 1’b0 0: usb_oeb; 1: usb_oeb_reg Leave it as the default RSVD 10:8 ROUTPMOS 3’h3 Leave it as the default RSVD ROUTNMOS 3’h3 Leave it as the default PUIDO 1’b0...
  • Page 89 BL702/704/706 Reference Manual Name Type Reset Description Bits RSVD 14:12 PUTUNE 3’h2 pull up resistor tuning Leave it as the default USECTRL 1’b1 1: USB XCVR use on-chip usb controller ; 0: USB XCVR usb off-chip usb controller Leave it as the default...
  • Page 90 – Two input modes: single-ended and differential – Support jitter compensation – User can set conversion result offset value • Analog channels – 12 external analog channels 90/ 375 @2021 Bouffalo Lab BL702/704/706 Reference Manual...

  • Page 91: Adc Block Diagram

    BL702/704/706 Reference Manual – 2 DAC internal channels – 1 VBAT / 2 channel – 1 TSEN channel 4.3 ADC functional description The basic block diagram of the ADC is shown below. VDD33(1.7~3.6V) IVBIAS Pga_gain REF_gen Pos/neg_sel Diff/single Scan Data_final[25:0]...

  • Page 92: Adc Internal Signals

    BL702/704/706 Reference Manual pushed into the FIFO. 4.3.1 ADC pins and internal signals Table 4.1: ADC internal signals Internal Signal type Description signals VBAT/2 Input Voltage signal divided from the power pin TSEN Input Internal temperature sensor output voltage VREF...

  • Page 93: Adc Clock

    BL702/704/706 Reference Manual • ADC CH8 • ADC CH9 • ADC CH10 • ADC CH11 • VSSA • DAC OUTA • DAC OUTB • VBAT/2 • TSEN • VREF • GND It should be noted that if VBAT/2 or TSEN is selected as the input signal to be acquired, gpadc_vbat_en or gpadc_- ts_en needs to be set.
  • Page 94 BL702/704/706 Reference Manual Inside the ADC module, a clock divider is provided, which can divide the input clock by 1/4/8/12/16/20/24/32. Users can adjust the ADC clock source and various frequency division coefficients according to actual sampling require- ments. Note that the maximum input clock of ADC is 2MHZ.

  • Page 95: Adc Conversion Result Format

    BL702/704/706 Reference Manual implement multiple sampling conversions on a channel. ADC conversion results are generally placed in the FIFO. The ADC module does not provide conversion completion interrupts. Users need to set the FIFO receive data threshold interrupt based on the actual number of conversion channels.
  • Page 96 BL702/704/706 Reference Manual In single-ended mode, there is no sign bit, that is, when 12 bits are selected, bit15-bit4 is the conversion result and bit15 is the MSB. In actual use, the results of the ADC are generally placed in the FIFO, which is particularly important in the multi- channel scan mode.
  • Page 97 BL702/704/706 Reference Manual Using the threshold interrupt of the FIFO, when the interrupt is generated and the number of ADC data reaches the threshold, the CPU can read the length of the ADC FIFO in the interrupt service function and read it all.
  • Page 98 BL702/704/706 Reference Manual 4.3.9 VBAT measurement The VBAT/2 measurement is the voltage of the chip VDD33, not the voltage of an external battery such as a lithium battery. If you need to measure the voltage of a power supply head such as a lithium battery, you can divide the voltage and then input it to the ADC’s GPIO analog channel.

  • Page 99: Nec

    BL702/704/706 Reference Manual 4.4 Register description Description Name gpadc_config GPADC configuration gpadc_dma_rdata GPADC DMA read data gpadc_reg_cmd GPADC register configuration 0 gpadc_reg_config1 GPADC register configuration 1 gpadc_reg_config2 GPADC register configuration 2 gpadc_reg_scn_pos1 adc converation sequence 1 gpadc_reg_scn_pos2 adc converation sequence 2...
  • Page 100 BL702/704/706 Reference Manual Name Type Reset Description Bits 21:16 FIFODACN 6’d0 fifo data number FIFORDYM 1’b1 write 1 mask FURM 1’b0 write 1 mask FORM 1’b0 write 1 mask RDYM 1’b0 write 1 mask RSVD URCL 1’b0 Write 1 to clear flag ORCL 1’b0...
  • Page 101 BL702/704/706 Reference Manual 4.4.3 gpadc_reg_cmd Address：0x4000f90c RSVD SENT SENSEL CSEN RSVD MB32 MP2G M1DF M2DF RSVD MBBP MPEN MBEN NGGR POSSEL NEGSEL SFRS CVST GBEN Name Type Reset Description Bits RSVD SENTEN 1’b0 enable sensor dc test mux 29:28 SENSEL 2’h0...
  • Page 102 BL702/704/706 Reference Manual Name Type Reset Description Bits MBBP 1’b0 micboost amp bypass 1’b0: not bypass 1’b1: bypass MPEN 1’b0 micpga enable 1’b0: micpga disable 1’b1: miapga enable MBEN 1’b0 enable micbias 1’b0: micbias power down 1’b1: miabias power on NGGR 1’b0...
  • Page 103 BL702/704/706 Reference Manual Name Type Reset Description Bits NEGSEL 5’hf select adc negative input in none-scan mode 5’h0 gpip_ch[0] 5’h1 gpip_ch[1] 5’h2 gpip_ch[2] 5‘h3 gpip_ch[3] 5’h4 gpip_ch[4] 5’h5 gpip_ch[5] 5’h6 gpip_ch[6] 5’h7 gpip_ch[7] 5’h8 gpip_ch[8] 5’h9 gpip_ch[9] 5’h10 gpip_ch[10] 5’h11 gpip_ch[11] 5’h12 daca...
  • Page 104 BL702/704/706 Reference Manual Name Type Reset Description Bits SCEN 1’h0 select scan mode enable: 0: select gpadc_pos/neg_sel;1: select : select gpadc_scan_pos_x and gpadc_scan_neg_x 24:21 SCLEN 4’h0 select scan mode length 4’b0000 : select gpadc_scan_pos_0 and gpadc_scan_- neg_0 4’b0001 : select gpadc_scan_pos_1 and gpadc_scan_- neg_1 4’b0010 : select gpadc_scan_pos_2 and gpadc_scan_-...
  • Page 105 BL702/704/706 Reference Manual Name Type Reset Description Bits SELEN 1’b0 pga vcm selected when lowv_det_en is enable RSVD RESSEL 3’h0 adc resolution/over-sample rate select 3’b000 12bit 2MS/s, OSR=1 3’b001 14bit 125kS/s, OSR=16 3’b010 14bit 31.25kS/s, OSR=64 3’b011 16bit 15.625KS/s, OSR=128 (voice mode16KS/s) 3’b100 16bit 7.8125KS/s, OSR=256 (voice mode 8KS/s)
  • Page 106 BL702/704/706 Reference Manual Name Type Reset Description Bits 24:22 PGA2GAIN 3’h0 3’h0: disable 3’h1: gain=1 3’h2: gain=2 3’h3: gain=4 3’h4: gain=8 3’h5: gain=16 3’h6: gain=32 3’h7: gain=32 21:19 TESTSEL 3’h0 select test point 0 7 TESTEN 1’b0 Analog test enable.
  • Page 107 BL702/704/706 Reference Manual 4.4.6 gpadc_reg_scn_pos1 Address：0x4000f918 RSVD SCP5 SCP4 SCP3 SCP3 SCP2 SCP1 SCP0 Name Type Reset Description Bits 31:30 RSVD 29:25 SCP5 5’hf definition is the same as adc_reg_cmd.adc_pos_sel 24:20 SCP4 5’hf definition is the same as adc_reg_cmd.adc_pos_sel 19:15 SCP3 5’hf...
  • Page 108 BL702/704/706 Reference Manual 4.4.8 gpadc_reg_scn_neg1 Address：0x4000f920 RSVD SCN5 SCN4 SCN3 SCN3 SCN2 SCN1 SCN0 Name Type Reset Description Bits 31:30 RSVD 29:25 SCN5 5’hf definition is the same as adc_reg_cmd.adc_neg_sel 24:20 SCN4 5’hf definition is the same as adc_reg_cmd.adc_neg_sel 19:15 SCN3 5’hf...
  • Page 109 BL702/704/706 Reference Manual 4.4.10 gpadc_reg_status Address：0x4000f928 RSVD RSVD DARD Name Type Reset Description Bits 31:1 RSVD DARD 1’b0 ADC final conversion data ready 4.4.11 gpadc_reg_isr Address：0x4000f92c RSVD RSVD RSVD RSVD Name Type Reset Description Bits 31:10 RSVD 1’h0 write 1 mask 1’h0...
  • Page 110 BL702/704/706 Reference Manual 4.4.12 gpadc_reg_raw_result Address：0x4000f934 RSVD RSVD RAWDA Name Type Reset Description Bits 31:12 RSVD 11:0 RAWDA 12’h0 ADC Raw data 4.4.13 gpadc_reg_define Address：0x4000f938 RSVD OSCALDA Name Type Reset Description Bits 31:16 RSVD 15:0 OSCALDA 16’h0 User defined or self calculated offset data 16-bit signed...
  • Page 111 • The output pin of DAC is fixed to ChannelA as GPIO11, ChannelB as GPIO17 • DAC reference voltage can be selected internally 5.3 DAC function description The basic block diagram of the DAC module is shown in the figure. 111/ 375 @2021 Bouffalo Lab BL702/704/706 Reference Manual...

  • Page 112: Dac Basic Block Diagram

    BL702/704/706 Reference Manual Fig. 5.1: DAC basic block diagram The DAC module contains two DAC modulation circuits and a power supply circuit related to modulating analog signals. The user can use Ref_Sel to select whether the DAC reference voltage is external/internal, and Ref_Rng to select the internal reference voltage source.

  • Page 113: Internal Reference Voltage

    BL702/704/706 Reference Manual sequence, and the modulation order is {A0},{A1},{A2},... If gpdac_dma_format is 1, the high 16 bits of the data transferred into gpdac_dma_wdata by DMA are modulated in Channel B, and the low 16 bits are modulated in Channel A. The modulation sequence is {B0,A0},{B1,A1},{B2,A2},..
  • Page 114 BL702/704/706 Reference Manual 5.4.1 gpdac_config Address：0x40002040 RSVD CHBSEL CHASEL RSVD MODE RSVD DSMMODE RSVD Name Type Reset Description Bits 31:24 RSVD 23:20 CHBSEL Channel B Source Select 0: Reg 1: DMA 2: DMA + Filter 3: Sin Gen 4: A (The same as channel A)
  • Page 115 BL702/704/706 Reference Manual 5.4.2 gpdac_dma_config Address：0x40002044 RSVD RSVD DMAFM RSVD TXEN Name Type Reset Description Bits 31:6 RSVD DMAFM DMA TX format (Data 12-bit) 0: A0, A1, A2… 1: B0,A0, B1,A1, B2,A2… 2: A1,A0, A3,A2, A5,A4… (Note: 20’h0,[11:0] or 4’h0,[27:16],4’h0,[11:0])
  • Page 116 BL702/704/706 Reference Manual 5.4.4 gpdac_ctrl Address：0x40000308 RSVD RSVD TSEN RSVD Name Type Reset Description Bits 31:9 RSVD REFSEL 1’h0 Reference select 1’h0 Internal reference 1’h1 External reference TSEN 1’h0 Test enable 1’h0 analog test disabled (ATEST is set in Hi-Z state) 1’h1 analog test point enabled to ATEST...
  • Page 117 BL702/704/706 Reference Manual Name Type Reset Description Bits IOAEN 1’h0 Channel A conversion output to pad enable 1’h0 Disable channel A conversion result to GPIO 1’h1 Enable channel A conversion result to GPIO 1’h0 Channel A enable/disable signal 1’h0 Disable channel A conversion.
  • Page 118 BL702/704/706 Reference Manual 5.4.7 gpdac_data Address：0x40000314 RSVD ADATA RSVD BDATA Name Type Reset Description Bits 31:26 RSVD 25:16 ADATA 10’h0 Channel A Data input 15:10 RSVD BDATA 10’h0 Channel B Data input BL702/704/706 Reference Manual 118/ 375 @2021 Bouffalo Lab...
  • Page 119 – DMA flow control, source memory, target peripheral – DMA flow control, source peripheral, target memory – DMA flow control, source peripheral, target peripheral • Support LLI linked list function to improve DMA efficiency 119/ 375 @2021 Bouffalo Lab BL702/704/706 Reference Manual...
  • Page 120 BL702/704/706 Reference Manual 6.3 DMA functional description 6.3.1 Working principle When a device attempts to transfer data (usually a large amount of data) directly to another device via the bus, it will first send a DMA request signal to the CPU. The peripheral device makes a bus request to the CPU to take over the bus control right through the DMA.

  • Page 121: Dma Architecture

    BL702/704/706 Reference Manual DMA Controller DMA_Channel0 REQ0 REQ1 «« FIFO «« REQ31 DMA_Channel1 REQ0 REQ1 «« FIFO «« REQ31 AHB Master ・ ・ ・ DMA_Channe7 REQ0 REQ1 «« FIFO AHB slave «« AHB Slave Programming REQ31 Fig. 6.1: DMA architecture The DMA includes a set of AHB Master interfaces and a set of AHB Slave interfaces.
  • Page 122 BL702/704/706 Reference Manual 6.3.2 DMA channel configuration DMA supports 8 channels in total, each channel does not interfere with each other and can run at the same time. The following is the configuration process of DMA channel x: 1. Set 32-bit source address in DMA_C0SrcAddr register 2.
  • Page 123 BL702/704/706 Reference Manual 2. Set the value of the DMA_C0Config [DSTPH] bit to 10, that is, set the Destination peripheral to SPI_RX ADC uses DMA to transfer data The configuration is as follows: 1. Set the value of the DMA_C0Config [SRCPH] bit to 22, that is, set the Source peripheral to GPADC...

  • Page 124: Lli Architecture

    BL702/704/706 Reference Manual IDLE channel enable Source Address Dest Address Next LLI IntTCEnable= DMA Control Source Address Dest Address Next LLI IntTCEnable= DMA Control IntTCEnable= · · · IntTCEnable= Source Address Dest Address Next LLI DMA Control Fig. 6.2: LLI architecture 6.3.5 DMA interrupt...
  • Page 125 BL702/704/706 Reference Manual 6.4 Transmission mode 6.4.1 Memory to memory After this mode is started, the DMA will move the data from the source address to the destination address according to the set transfer size. After the transfer, the DMA controller will automatically return to the idle state and wait for the next transfer.
  • Page 126 BL702/704/706 Reference Manual 6.4.3 Peripheral to memory In this working mode, when the source peripheral request is triggered, the source configuration is burst to the buffer until the set number of moves reaches the stop. On the other hand, when the internal cache is enough for the target...
  • Page 127 BL702/704/706 Reference Manual 6.5 Register description Description Name DMA_IntStatus Interrupt status DMA_IntTCStatus Interrupt terminal count request status DMA_IntTCClear Terminal count request clear DMA_IntErrorStatus Interrupt error status DMA_IntErrClr Interrupt error clear DMA_RawIntTCStatus Status of the terminal count interrupt prior to masking...
  • Page 128 BL702/704/706 Reference Manual Description Name DMA_C2Config Channel DMA configuration DMA_C3SrcAddr Channel DMA source address DMA_C3DstAddr Channel DMA Destination address DMA_C3LLI Channel DMA link list DMA_C3Control Channel DMA bus control DMA_C3Config Channel DMA configuration DMA_C4SrcAddr Channel DMA source address DMA_C4DstAddr Channel DMA Destination address...
  • Page 129 BL702/704/706 Reference Manual 6.5.1 DMA_IntStatus Address：0x4000c000 RSVD RSVD INTSTA Name Type Reset Description Bits 31:8 RSVD INTSTA Status of the DMA interrupts after masking 6.5.2 DMA_IntTCStatus Address：0x4000c004 RSVD RSVD INTTCSTA Name Type Reset Description Bits 31:8 RSVD INTTCSTA Interrupt terminal count request status 6.5.3 DMA_IntTCClear...
  • Page 130 BL702/704/706 Reference Manual Name Type Reset Description Bits 6.5.4 DMA_IntErrorStatus Address：0x4000c00c RSVD RSVD Name Type Reset Description Bits 31:8 RSVD Interrupt error status 6.5.5 DMA_IntErrClr Address：0x4000c010 RSVD RSVD Name Type Reset Description Bits 31:8 RSVD Interrupt error clear 6.5.6 DMA_RawIntTCStatus Address：0x4000c014...
  • Page 131 BL702/704/706 Reference Manual Name Type Reset Description Bits 31:8 RSVD SOTCIPTM Status of the terminal count interrupt prior to masking 6.5.7 DMA_RawIntErrorStatus Address：0x4000c018 RSVD RSVD SOTEIPTM Name Type Reset Description Bits 31:8 RSVD SOTEIPTM Status of the error interrupt prior to masking 6.5.8 DMA_EnbldChns...
  • Page 132 BL702/704/706 Reference Manual 6.5.9 DMA_SoftBReq Address：0x4000c020 Name Type Reset Description Bits 31:0 Software burst request 6.5.10 DMA_SoftSReq Address：0x4000c024 Name Type Reset Description Bits 31:0 Software single request 6.5.11 DMA_SoftLBReq Address：0x4000c028 SLBR SLBR Name Type Reset Description Bits 31:0 SLBR Software last burst request...
  • Page 133 BL702/704/706 Reference Manual 6.5.12 DMA_SoftLSReq Address：0x4000c02c SLSR SLSR Name Type Reset Description Bits 31:0 SLSR Software last single request 6.5.13 DMA_Config Address：0x4000c030 RSVD RSVD SDMA Name Type Reset Description Bits 31:2 RSVD AHBMEC AHB Master endianness configuration: 0 = little-endian, 1...
  • Page 134 BL702/704/706 Reference Manual Name Type Reset Description Bits 31:0 DSLFDRS DMA synchronization logic for DMA request signals: 0 = enable, 1 = disable 6.5.15 DMA_C0SrcAddr Address：0x4000c100 DMASA DMASA Name Type Reset Description Bits 31:0 DMASA DMA source address 6.5.16 DMA_C0DstAddr Address：0x4000c104...
  • Page 135 BL702/704/706 Reference Manual Name Type Reset Description Bits 31:0 FLLI First linked list item. Bits [1:0] must be 0. 6.5.18 DMA_C0Control Address：0x4000c10c PROTECT RSVD FIXCNT RSVD MODE MODE Name Type Reset Description Bits TCIEN Terminal count interrupt enable bit. It controls whether the current LLI is expected to trigger the terminal count inter- rupt.
  • Page 136 BL702/704/706 Reference Manual 6.5.19 DMA_C0Config Address：0x4000c110 RSVD LLICOUNT RSVD HALT LOCK TIVE TCIM FLOWCTRL DSTPH SRCPH CHEN Name Type Reset Description Bits 31:30 RSVD 29:20 LLICOUNT LLI counter. Increased 1 each LLI run. Cleared 0 when config Control. RSVD HALT Halt: 0 = enable DMA requests, 1 = ignore subsequent source DMA requests.
  • Page 137 BL702/704/706 Reference Manual Name Type Reset Description Bits CHEN Channel enable. 6.5.20 DMA_C1SrcAddr Address：0x4000c200 DMASA DMASA Name Type Reset Description Bits 31:0 DMASA DMA source address 6.5.21 DMA_C1DstAddr Address：0x4000c204 DMADA DMADA Name Type Reset Description Bits 31:0 DMADA DMA Destination address 6.5.22 DMA_C1LLI...
  • Page 138 BL702/704/706 Reference Manual Name Type Reset Description Bits 31:2 FLLI First linked list item. Bits [1:0] must be 0. RSVD 6.5.23 DMA_C1Control Address：0x4000c20c PROTECT RSVD FIXCNT MODE MODE Name Type Reset Description Bits TCIEN Terminal count interrupt enable bit. It controls whether the current LLI is expected to trigger the terminal count inter- rupt.
  • Page 139 BL702/704/706 Reference Manual 6.5.24 DMA_C1Config Address：0x4000c210 RSVD HALT LOCK TIVE TCIM FLOWCTRL DSTPH SRCPH CHEN Name Type Reset Description Bits 31:19 RSVD HALT Halt: 0 = enable DMA requests, 1 = ignore subsequent source DMA requests. ACTIVE Active: 0 = no data in FIFO of the channel, 1 = FIFO of the channel has data.
  • Page 140 BL702/704/706 Reference Manual 6.5.25 DMA_C2SrcAddr Address：0x4000c300 DMASA DMASA Name Type Reset Description Bits 31:0 DMASA DMA source address 6.5.26 DMA_C2DstAddr Address：0x4000c304 DMADA DMADA Name Type Reset Description Bits 31:0 DMADA DMA Destination address 6.5.27 DMA_C2LLI Address：0x4000c308 FLLI FLLI RSVD Name...
  • Page 141 BL702/704/706 Reference Manual 6.5.28 DMA_C2Control Address：0x4000c30c PROTECT RSVD FIXCNT MODE MODE Name Type Reset Description Bits TCIEN Terminal count interrupt enable bit. It controls whether the current LLI is expected to trigger the terminal count inter- rupt. 30:28 PROTECT Protection.
  • Page 142 BL702/704/706 Reference Manual 6.5.29 DMA_C2Config Address：0x4000c310 RSVD HALT LOCK TIVE TCIM FLOWCTRL DSTPH SRCPH CHEN Name Type Reset Description Bits 31:19 RSVD HALT Halt: 0 = enable DMA requests, 1 = ignore subsequent source DMA requests. ACTIVE Active: 0 = no data in FIFO of the channel, 1 = FIFO of the channel has data.
  • Page 143 BL702/704/706 Reference Manual 6.5.30 DMA_C3SrcAddr Address：0x4000c400 DMASA DMASA Name Type Reset Description Bits 31:0 DMASA DMA source address 6.5.31 DMA_C3DstAddr Address：0x4000c404 DMADA DMADA Name Type Reset Description Bits 31:0 DMADA DMA Destination address 6.5.32 DMA_C3LLI Address：0x4000c408 FLLI FLLI RSVD Name...
  • Page 144 BL702/704/706 Reference Manual 6.5.33 DMA_C3Control Address：0x4000c40c PROTECT RSVD FIXCNT MODE MODE Name Type Reset Description Bits TCIEN Terminal count interrupt enable bit. It controls whether the current LLI is expected to trigger the terminal count inter- rupt. 30:28 PROTECT Protection.
  • Page 145 BL702/704/706 Reference Manual 6.5.34 DMA_C3Config Address：0x4000c410 RSVD HALT LOCK TIVE TCIM FLOWCTRL DSTPH SRCPH CHEN Name Type Reset Description Bits 31:19 RSVD HALT Halt: 0 = enable DMA requests, 1 = ignore subsequent source DMA requests. ACTIVE Active: 0 = no data in FIFO of the channel, 1 = FIFO of the channel has data.
  • Page 146 BL702/704/706 Reference Manual 6.5.35 DMA_C4SrcAddr Address：0x4000c500 DMASA DMASA Name Type Reset Description Bits 31:0 DMASA DMA source address 6.5.36 DMA_C4DstAddr Address：0x4000c504 DMADA DMADA Name Type Reset Description Bits 31:0 DMADA DMA Destination address 6.5.37 DMA_C4LLI Address：0x4000c508 FLLI FLLI RSVD Name...
  • Page 147 BL702/704/706 Reference Manual 6.5.38 DMA_C4Control Address：0x4000c50c PROTECT RSVD FIXCNT MODE MODE Name Type Reset Description Bits TCIEN Terminal count interrupt enable bit. It controls whether the current LLI is expected to trigger the terminal count inter- rupt. 30:28 PROTECT Protection.
  • Page 148 BL702/704/706 Reference Manual 6.5.39 DMA_C4Config Address：0x4000c510 RSVD HALT LOCK TIVE TCIM FLOWCTRL DSTPH SRCPH CHEN Name Type Reset Description Bits 31:19 RSVD HALT Halt: 0 = enable DMA requests, 1 = ignore subsequent source DMA requests. ACTIVE Active: 0 = no data in FIFO of the channel, 1 = FIFO of the channel has data.
  • Page 149 BL702/704/706 Reference Manual 6.5.40 DMA_C5SrcAddr Address：0x4000c600 DMASA DMASA Name Type Reset Description Bits 31:0 DMASA DMA source address 6.5.41 DMA_C5DstAddr Address：0x4000c604 DMADA DMADA Name Type Reset Description Bits 31:0 DMADA DMA Destination address 6.5.42 DMA_C5LLI Address：0x4000c608 FLLI FLLI RSVD Name...
  • Page 150 BL702/704/706 Reference Manual 6.5.43 DMA_C5Control Address：0x4000c60c PROTECT RSVD FIXCNT MODE MODE Name Type Reset Description Bits TCIEN Terminal count interrupt enable bit. It controls whether the current LLI is expected to trigger the terminal count inter- rupt. 30:28 PROTECT Protection.
  • Page 151 BL702/704/706 Reference Manual 6.5.44 DMA_C5Config Address：0x4000c610 RSVD HALT LOCK TIVE TCIM FLOWCTRL DSTPH SRCPH CHEN Name Type Reset Description Bits 31:19 RSVD HALT Halt: 0 = enable DMA requests, 1 = ignore subsequent source DMA requests. ACTIVE Active: 0 = no data in FIFO of the channel, 1 = FIFO of the channel has data.
  • Page 152 BL702/704/706 Reference Manual 6.5.45 DMA_C6SrcAddr Address：0x4000c700 DMASA DMASA Name Type Reset Description Bits 31:0 DMASA DMA source address 6.5.46 DMA_C6DstAddr Address：0x4000c704 DMADA DMADA Name Type Reset Description Bits 31:0 DMADA DMA Destination address 6.5.47 DMA_C6LLI Address：0x4000c708 FLLI FLLI RSVD Name...
  • Page 153 BL702/704/706 Reference Manual 6.5.48 DMA_C6Control Address：0x4000c70c PROTECT RSVD FIXCNT MODE MODE Name Type Reset Description Bits TCIEN Terminal count interrupt enable bit. It controls whether the current LLI is expected to trigger the terminal count inter- rupt. 30:28 PROTECT Protection.
  • Page 154 BL702/704/706 Reference Manual 6.5.49 DMA_C6Config Address：0x4000c710 RSVD HALT LOCK TIVE TCIM FLOWCTRL DSTPH SRCPH CHEN Name Type Reset Description Bits 31:19 RSVD HALT Halt: 0 = enable DMA requests, 1 = ignore subsequent source DMA requests. ACTIVE Active: 0 = no data in FIFO of the channel, 1 = FIFO of the channel has data.
  • Page 155 BL702/704/706 Reference Manual 6.5.50 DMA_C7SrcAddr Address：0x4000c800 DMASA DMASA Name Type Reset Description Bits 31:0 DMASA DMA source address 6.5.51 DMA_C7DstAddr Address：0x4000c804 DMADA DMADA Name Type Reset Description Bits 31:0 DMADA DMA Destination address 6.5.52 DMA_C7LLI Address：0x4000c808 FLLI FLLI RSVD Name...
  • Page 156 BL702/704/706 Reference Manual 6.5.53 DMA_C7Control Address：0x4000c80c PROTECT RSVD FIXCNT MODE MODE Name Type Reset Description Bits TCIEN Terminal count interrupt enable bit. It controls whether the current LLI is expected to trigger the terminal count inter- rupt. 30:28 PROTECT Protection.
  • Page 157 BL702/704/706 Reference Manual 6.5.54 DMA_C7Config Address：0x4000c810 RSVD HALT LOCK TIVE TCIM FLOWCTRL DSTPH SRCPH CHEN Name Type Reset Description Bits 31:19 RSVD HALT Halt: 0 = enable DMA requests, 1 = ignore subsequent source DMA requests. ACTIVE Active: 0 = no data in FIFO of the channel, 1 = FIFO of the channel has data.

  • Page 158: L1C Architecture

    Flash, the less time wasted, the higher the efficiency. The L1C cache can be used as a lubricating role between the processor and the Flash to improve the efficiency of the processor. 158/ 375 @2021 Bouffalo Lab BL702/704/706 Reference Manual...

  • Page 159: Waydisable Settings

    BL702/704/706 Reference Manual 7.2 L1C main features • 4-way Set-Associative mapping • Variable cache size • Connect to TCM address space, can easily configure L1C space as TCM space • Support cache performance statistics 7.3 L1C function description 7.3.1 Mutual conversion between TCM and Cache RAM resources In order to increase memory usage efficiency, it is supported to adjust all or part of the Cache’s 16K RAM to TCM...

  • Page 160: Cache Architecture

    BL702/704/706 Reference Manual index offset valid Word 3 Word 2 Word 1 Word 0 Fig. 7.2: Cache architecture Each set of associative mapping caches contains two parts, the first is a tag, which contains the valid value and the address mapping relationship. The second part is data storage. When the processor accesses the cache, the cache processor compares the relationship between the address and the tag.
  • Page 161 BL702/704/706 Reference Manual 7.4.1 l1c_config Address：0x40009000 RSVD RSVD WAYDIS RSVD ABLE Name Type Reset Description Bits 31:12 RSVD 11:8 WAYDIS 4’b1111 Disable part of cache ways & used as ITCM RSVD CNTEN CACABLE 7.4.2 hit_cnt_lsb Address：0x40009004 CNTLSB CNTLSB Name Type...
  • Page 162 BL702/704/706 Reference Manual Name Type Reset Description Bits 31:0 CNTMSB total hit count = hit_cnt_msb*23̂ 2 + hit_cnt_lsb 7.4.4 miss_cnt Address：0x4000900c MISSCNT MISSCNT Name Type Reset Description Bits 31:0 MISSCNT BL702/704/706 Reference Manual 162/ 375 @2021 Bouffalo Lab...
  • Page 163 8.3.1 Fixed receiving protocol IR receiver supports two fixed protocols, NEC protocol and RC-5 protocol. • NEC protocol The logic 1 and logic 0 waveforms of the NEC protocol are shown in the following figure: 163/ 375 @2021 Bouffalo Lab BL702/704/706 Reference Manual...

  • Page 164: Nec Logical

    BL702/704/706 Reference Manual Logical”1” Logical”0” 560us 560us 560us 2.25ms 1.12ms Fig. 8.1: nec logical Logic 1 is 2.25ms, pulse time is 560us; logic 0 bit is 1.12ms, pulse time is 560us. The specific format of the NEC protocol is shown in the following figure: 9ms 4.5...
  • Page 165 BL702/704/706 Reference Manual bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit9 bit10 bit11 bit12 bit13 bit14 “1” “1” “0” “0” “1” “0” “1” “1” “1” “0” “1” “0” “1” “0” Address Command Start bits always“1” Fig. 8.4: rc5 The first two bits are the start bit, fixed to logic 1, and the third bit is the flip bit. When a key value is issued and then pressed, the bit will be inverted.
  • Page 166 BL702/704/706 Reference Manual 8.3.5 Carrier modulation Setting the upper 16 bits of the IRTX_PULSE_WIDTH register can generate carriers with different frequencies and duty cycles. The <TXMPH1W> bit in this register sets the width of carrier phase 1, and the <TXMPH0W> bit sets the width of carrier phase 0.
  • Page 167 BL702/704/706 Reference Manual Description Name irrx_data_word0 IR RX data word0 irrx_data_word1 IR RX data word1 irrx_swm_fifo_config_0 IR RX FIFO configuration irrx_swm_fifo_rdata IR RX software mode pulse width data 8.4.1 irtx_config Address：0x4000a600 RSVD TXDATANU TXDATANU TPHL TXTP RSVD TXL1 TXL0 TXDA...
  • Page 168 BL702/704/706 Reference Manual Name Type Reset Description Bits TXMDEN 1’b0 Enable signal of output modulation TXOEN 1’b0 Output inverse signal 1’b0: Output stays at Low during idle state 1’b1: Output stays at High during idle state TXEN 1’b0 Enable signal of IRTX function...
  • Page 169 BL702/704/706 Reference Manual 8.4.3 irtx_data_word0 Address：0x4000a608 TXDW0 TXDW0 Name Type Reset Description Bits 31:0 TXDW0 32’h0 TX data word 0 (Don’t care if SWM is enabled) 8.4.4 irtx_data_word1 Address：0x4000a60c TXDW1 TXDW1 Name Type Reset Description Bits 31:0 TXDW1 32’h0 TX data word 1 (Don’t care if SWM is enabled) 8.4.5 irtx_pulse_width...
  • Page 170 BL702/704/706 Reference Manual Name Type Reset Description Bits 8.4.6 irtx_pw Address：0x4000a614 TXTPH1W TXTPH0W TXHPH1W TXHPH0W TXL1PH1W TXL1PH0W TXL0PH1W TXL0PH0WS Name Type Reset Description Bits 31:28 TXTPH1W 4’d0 Pulse width of tail pulse phase 1 (Don’t care if SWM is en-...
  • Page 171 BL702/704/706 Reference Manual Name Type Reset Description Bits 31:0 TXSWPW0 32’h0 IRTX Software Mode pulse width data #0 #7, each pulse is represented by 4-bit ([3:0] is the 1st pulse, [7:4] is the 2nd pulse, [11:8] is the 3rd pulse, etc) 8.4.8 irtx_swm_pw_1...
  • Page 172 BL702/704/706 Reference Manual 8.4.10 irtx_swm_pw_3 Address：0x4000a64c TXSWPW3 TXSWPW3 Name Type Reset Description Bits 31:0 TXSWPW3 32’h0 IRTX Software Mode pulse width data #24 #31, each pulse is represented by 4-bit ([3:0] is the 1st pulse, [7:4] is the 2nd pulse, [11:8] is the 3rd pulse, etc) 8.4.11 irtx_swm_pw_4...
  • Page 173 BL702/704/706 Reference Manual Name Type Reset Description Bits 31:0 TXSWPW5 32’h0 IRTX Software Mode pulse width data #40 #47, each pulse is represented by 4-bit ([3:0] is the 1st pulse, [7:4] is the 2nd pulse, [11:8] is the 3rd pulse, etc) 8.4.13 irtx_swm_pw_6...
  • Page 174 BL702/704/706 Reference Manual 8.4.15 irrx_config Address：0x4000a680 RSVD RSVD RXDEGCNT RSVD RXDG RXMODE RXIN RXEN Name Type Reset Description Bits 31:12 RSVD 11:8 RXDEGCNT 4’d0 De-glitch function cycle count RSVD RXDGEN 1’b0 Enable signal of IRRX input de-glitch function RXMODE 2’d0...
  • Page 175 BL702/704/706 Reference Manual Name Type Reset Description Bits 23:17 RSVD RXECLR 1’b0 Interrupt clear of irrx_end_int 15:9 RSVD RXEMASK 1’b1 Interrupt mask of irrx_end_int RSVD RXEINT 1’b0 IRRX transfer end interrupt 8.4.17 irrx_pw_config Address：0x4000a688 RXETH RXDATH Name Type Reset Description...
  • Page 176 BL702/704/706 Reference Manual 8.4.19 irrx_data_word0 Address：0x4000a694 RXDAW0 RXDAW0 Name Type Reset Description Bits 31:0 RXDAW0 32’h0 RX data word 0 8.4.20 irrx_data_word1 Address：0x4000a698 RXDAW1 RXDAW1 Name Type Reset Description Bits 31:0 RXDAW1 32’h0 RX data word 1 8.4.21 irrx_swm_fifo_config_0 Address：0x4000a6c0...
  • Page 177 BL702/704/706 Reference Manual Name Type Reset Description Bits RXFOF 1’b0 Overflow flag of RX FIFO, can be cleared by rx_fifo_clr RSVD RXFCLR 1’b0 Clear signal of RX FIFO 8.4.22 irrx_swm_fifo_rdata Address：0x4000a6c4 RSVD RXFRDA Name Type Reset Description Bits 31:16 RSVD...
  • Page 178 • Both master and slave devices support 1/2/3/4 byte transmission mode • Flexible clock configuration, support up to 40M clock • Configurable MSB/LSB priority transmission • Acceptance filtering function • Timeout mechanism under the slave • Support DMA transfer mode 178/ 375 @2021 Bouffalo Lab BL702/704/706 Reference Manual...

  • Page 179: Spi Clock

    BL702/704/706 Reference Manual 9.3 SPI function description 9.3.1 Clock control According to different clock phases and polarity settings, the SPI clock has four modes, which can be set by bit4 (CPOL) and bit5 (CPHA) of the SPI_CONFIG register. CPOL is used to determine the level of the SCK clock signal when idle, CPOL = 0 means the idle level is low, and CPOL = 1 means the idle level is high.

  • Page 180: Spi Ignore Waveform

    BL702/704/706 Reference Manual 9.3.3 Acceptance filtering function By setting the start and end bits that need to be filtered out, the SPI discards the corresponding data segment in the received data. As shown below: Address Opcode Dummy Byte High-Impedance State Fig.
  • Page 181 BL702/704/706 Reference Manual 9.3.7 DMA transfer mode SPI supports DMA transfer mode. The use of this mode requires the TX and RX FIFO thresholds to be set separately. When this mode is enabled, the UART will check the TX / RX FIFO. Once the TX / RX FIFO available count value is greater than its set threshold, a DMA request will be initiated , DMA will move data to TX FIFO or out of RX FIFO according to the setting.
  • Page 182 BL702/704/706 Reference Manual Description Name spi_fifo_config_0 SPI FIFO configuration register0 spi_fifo_config_1 SPI FIFO configuration register1 spi_fifo_wdata SPI FIFO write data spi_fifo_rdata SPI FIFO read data 9.4.1 spi_config Address：0x4000a200 RSVD DEGCNT RSVD MCEN IGNR BYTE SCLK SCLK FSIZE Name Type Reset...
  • Page 183 BL702/704/706 Reference Manual Name Type Reset Description Bits SCLKPOL 1’b0 SCLK polarity 0: SCLK output LOW at IDLE state 1: SCLK output HIGH at IDLE state FSIZE 2’d0 SPI frame size (also the valid width for each FIFO entry) 2’d0: 8-bit 2’d1: 16-bit...
  • Page 184 BL702/704/706 Reference Manual Name Type Reset Description Bits 18:17 RSVD ENDCLR 1’b0 Interrupt clear of spi_end_int 15:14 RSVD FERMASK 1’b1 Interrupt mask of spi_fer_int TXUMASK 1’b1 Interrupt mask of spi_txu_int STOMASK 1’b1 Interrupt mask of spi_sto_int RXFMASK 1’b1 Interrupt mask of spi_rxv_int TXFMASK 1’b1...
  • Page 185 BL702/704/706 Reference Manual Name Type Reset Description Bits 31:1 RSVD BUSBUSY 1’b0 Indicator of SPI bus busy 9.4.4 spi_prd_0 Address：0x4000a210 PRDPH1 PRDPH0 PRDP PRDS Name Type Reset Description Bits 31:24 PRDPH1 8’d15 Length of DATA phase 1 (please refer to ”Timing” tab)
  • Page 186 BL702/704/706 Reference Manual 9.4.6 spi_rxd_ignr Address：0x4000a218 RSVD RXDIGS RSVD RXDIGP Name Type Reset Description Bits 31:21 RSVD 20:16 RXDIGS 5’d0 Starting point of RX data ignore function 15:5 RSVD RXDIGP 5’d0 Stopping point of RX data ignore function 9.4.7 spi_sto_value Address：0x4000a21c...
  • Page 187 BL702/704/706 Reference Manual Name Type Reset Description Bits 31:8 RSVD RFUF 1’b0 Underflow flag of RX FIFO, can be cleared by rx_fifo_clr RFOF 1’b0 Overflow flag of RX FIFO, can be cleared by rx_fifo_clr TFUF 1’b0 Underflow flag of TX FIFO, can be cleared by tx_fifo_clr TFOF 1’b0...
  • Page 188 BL702/704/706 Reference Manual 9.4.10 spi_fifo_wdata Address：0x4000a288 FWDATA FWDATA Name Type Reset Description Bits 31:0 FWDATA SPI FIFO write data 9.4.11 spi_fifo_rdata Address：0x4000a28c FRDATA FRDATA Name Type Reset Description Bits 31:0 FRDATA 32’h0 SPI FIFO read data BL702/704/706 Reference Manual 188/ 375...
  • Page 189 • Convenient baud rate programming • Configurable MSB / LSB priority transmission • Normal / fixed character automatic baud rate detection • 32-byte transmit / receive FIFO • Support DMA transfer mode 189/ 375 @2021 Bouffalo Lab BL702/704/706 Reference Manual...

  • Page 190: Uart Data

    10.3.1 Data format description Normal UART communication data is composed of a start bit, a data bit, a parity bit, and a stop bit. The BL702’s UART supports configurable data bits, parity bits, and stop bits, all of which are set in the UTX_CONFIG and URX_CONFIG registers.

  • Page 191: Uart Clock

    BL702/704/706 Reference Manual FCLK hbn_uart_clk_sel Fig. 10.2: UART clock 10.3.3 Baud rate setting he user can generate the required baud rate by setting the register UART_BIT_PRD. The upper 16 bits and lower 16 bits of this register correspond to RX and TX respectively, that is, the baud rates of RX and TX can be set independently.

  • Page 192: Uart Sampling Waveform

    BL702/704/706 Reference Manual UART Clock Stop Start Baud rate 115200 = 96M/833 Sampling Time 5000 10000 10000 Start 10000 Baud rate 9600 = 96M/10000 Fig. 10.3: UART sampling waveform 10.3.4 Transmitter The transmitter contains a 128-byte transmit FIFO to store the data to be transmitted. Software can write TX FIFO through APB bus, and can also move data into TX FIFO through DMA.

  • Page 193: Uart Fixed Character Mode Waveform

    BL702/704/706 Reference Manual 10.3.6 Automatic baud rate detection The UART module supports automatic baud rate detection. The detection is divided into two types, one is general mode and the other is fixed character mode. The two detection modes will be enabled every time the bit <ABREN>...

  • Page 194: Uart Flow Control

    BL702/704/706 Reference Manual 10.3.7 Hardware flow control The UART supports hardware flow control in CTS / RTS mode to prevent data in the FIFO from being lost because it is too late to process. The hardware flow control connection is shown in the following figure:...
  • Page 195 BL702/704/706 Reference Manual 10.3.9 DMA transfer mode UART supports DMA transfer mode. To use this mode, you need to set the thresholds of TX and RX FIFO through the bits <TFITH> and <RFITH> of the register UART_FIFO_CONFIG_1. When this mode is enabled, the UART will check the TX/RX FIFO.
  • Page 196 BL702/704/706 Reference Manual 10.4 Register description Description Name utx_config UART TX configuration register urx_config UART RX configuration register uart_bit_prd UART period control register data_config UART data configuration register utx_ir_position UART TX ir position control register urx_ir_position UART RX ir position control register...
  • Page 197 BL702/704/706 Reference Manual Name Type Reset Description Bits 31:16 TXLEN 16’d0 Length of UART TX data transfer (Unit: character/byte) (Don’t-care if cr_utx_frm_en is enabled) 15:13 TXBCNTP 3’d4 UART TX BREAK bit count (for LIN protocol) Note: Additional 8 bit times will be added since LIN Break...
  • Page 198 BL702/704/706 Reference Manual Name Type Reset Description Bits DEGEN 1’b0 Enable signal of RXD input de-glitch function 10:8 RXBCNTD 3’d7 UART RX DATA bit count for each character IRRXINV 1’b0 Inverse signal of UART RX input in IR mode IRRXEN 1’b0...
  • Page 199 BL702/704/706 Reference Manual 10.4.4 data_config Address：0x4000a00c RSVD RSVD Name Type Reset Description Bits 31:1 RSVD BITINV 1’b0 Bit-inverse signal for each data byte 0: Each byte is sent out LSB-first 1: Each byte is sent out MSB-first 10.4.5 utx_ir_position Address：0x4000a010...
  • Page 200 BL702/704/706 Reference Manual Name Type Reset Description Bits 31:16 RSVD 15:0 RXIRPS 16’d111 START position of UART RXD pulse recovered from IR sig- 10.4.7 urx_rto_timer Address：0x4000a018 RSVD RSVD RXRTOVA Name Type Reset Description Bits 31:8 RSVD RXRTOVA 8’d15 Time-out value for triggering RTO interrupt (unit: bit time) 10.4.8 uart_sw_mode...
  • Page 201 BL702/704/706 Reference Manual 10.4.9 uart_int_sts Address：0x4000a020 RSVD RSVD RLSE RFER TFIN RPCE RRTO RFIN TFIN REIN TEIN Name Type Reset Description Bits 31:9 RSVD RLSEINT 1’b0 UART RX LIN mode sync field error interrupt RFERINT 1’b0 UART RX FIFO error interrupt, auto-cleared when FIFO...
  • Page 202 BL702/704/706 Reference Manual Name Type Reset Description Bits 31:9 RSVD RLSEMASK 1’b1 Interrupt mask of urx_lse_int RFERMASK 1’b1 Interrupt mask of urx_fer_int TFERMASK 1’b1 Interrupt mask of utx_fer_int RPCEMASK 1’b1 Interrupt mask of urx_pce_int RRTOMASK 1’b1 Interrupt mask of urx_rto_int RFMS 1’b1...
  • Page 203 BL702/704/706 Reference Manual 10.4.12 uart_int_en Address：0x4000a02c RSVD RSVD RLSE RFER TFER RPCE RRTO RFIF TFIF REND TEND Name Type Reset Description Bits 31:9 RSVD RLSE 1’b1 Interrupt enable of urx_lse_int RFER 1’b1 Interrupt enable of urx_fer_int TFER 1’b1 Interrupt enable of utx_fer_int RPCE 1’b1...
  • Page 204 BL702/704/706 Reference Manual 10.4.14 sts_urx_abr_prd Address：0x4000a034 ABRPRD ABRPRDS Name Type Reset Description Bits 31:16 ABRPRD 16’d0 Bit period of Auto Baud Rate detection using codeword 0x55 15:0 ABRPRDS 16’d0 Bit period of Auto Baud Rate detection using START bit 10.4.15 uart_fifo_config_0 Address：0x4000a080...
  • Page 205 BL702/704/706 Reference Manual 10.4.16 uart_fifo_config_1 Address：0x4000a084 RSVD RFITH RSVD TFITH RFICNT TFICNT Name Type Reset Description Bits RSVD 30:24 RFITH 7’d0 RX FIFO threshold, dma_rx_req will not be asserted if tx_- fifo_cnt is less than this value RSVD 22:16 TFITH 7’d0...
  • Page 206 BL702/704/706 Reference Manual 10.4.18 uart_fifo_rdata Address：0x4000a08c RSVD RSVD UFIRD Name Type Reset Description Bits 31:8 RSVD UFIRD 8’h0 UART FIFO read data BL702/704/706 Reference Manual 206/ 375 @2021 Bouffalo Lab...

  • Page 207: Pin Lists

    If two or more hosts are initialized at the same time, data transmission can prevent data from being destroyed through collision detection and arbitration. BL702 includes an I2C controller host, which can be flexibly configured with slaveAddr, subAddr, and data transmission to facilitate communication with slave devices. It provides 2 word depth fifo and provides interrupt functions. It can be used with DMA to improve efficiency and flexibly adjust clock frequency.

  • Page 208: I2C Stop/Start Condition

    BL702/704/706 Reference Manual 11.3.1 Start and stop conditions All transfers begin with a START condition and end with a STOP condition. The start and stop conditions are generally generated by the master. The bus is considered to be in a busy state after the start condition, and is considered to be in an idle state for a period of time after the stop condition.

  • Page 209: Master Tx And Slave Rx

    BL702/704/706 Reference Manual SLAVE ADDRESS DATA A/A DATA data transferred '0'(write) (n bytes + acknowledge) A = acknowledge(SDA LOW) from master to slave A = not acknowledge(SDA HIGH) S = START condition from slave to master P = STOP condition Fig.

  • Page 210: Tx And Rx Together

    BL702/704/706 Reference Manual master 1 loses arbitration DATA 1 ≠ SDA DATA1 DATA2 Fig. 11.5: Tx and Rx together 11.4 I2C clock setting The I2C clock is derived from bclk (bus clock), which can be divided based on the bclk clock.
  • Page 211 BL702/704/706 Reference Manual • Enable signal 11.5.2 Read and write flags I2C supports two working states: sending and receiving. Register PKTDIR indicates the sending or receiving status. When it is set to 0, it indicates the sending state, and when it is set to 1, it indicates the receiving state.
  • Page 212 BL702/704/706 Reference Manual 11.5.8 Enable signal After the above configurations are completed, write the enable signal register MEN to 1 to automatically start the I2C transmission process. When the read-write flag is set to 0, I2C sends data, and the host sends the process: 1.
  • Page 213 BL702/704/706 Reference Manual • TX FIFO underflow: When the size of the data filled in the TX FIFO does not meet the configured I2C data length PKTLEN, and there is no new data to be filled into the TX FIFO, the register TFIU will be set;...
  • Page 214 BL702/704/706 Reference Manual 11.7.2 DMA receiving process 1. Configure the read-write flag i2c_config[PKTDIR] to 1 2. Configure the slave device address i2c_config[SLVADDR] 3. Configure slave device register address i2c_sub_addr, slave device register address length i2c_config[SABC], configure slave device register address enable bit i2c_config[SAEN] to 1 4.
  • Page 215 BL702/704/706 Reference Manual Description Name i2c_bus_busy I2C bus busy control register i2c_prd_start I2C length of start phase i2c_prd_stop I2C length of stop phase i2c_prd_data I2C length of data phase i2c_fifo_config_0 I2C FIFO configuration register0 i2c_fifo_config_1 I2C FIFO configuration register1 i2c_fifo_wdata...
  • Page 216 BL702/704/706 Reference Manual Name Type Reset Description Bits DEGEN 1’b0 Enable signal of I2C input de-glitch function (for all input pins) PKTDIR 1’b1 Transfer direction of the packet 1’b0: Write; 1’b1: Read 1’b0 Enable signal of I2C Master function Asserting this bit will trigger the transaction, and should be de-asserted after finish 11.9.2 i2c_int_sts...
  • Page 217 BL702/704/706 Reference Manual Name Type Reset Description Bits NAKMASK 1’b1 Interrupt mask of i2c_nak_int RXFMASK 1’b1 Interrupt mask of i2c_rxf_int TXFMASK 1’b1 Interrupt mask of i2c_txf_int ENDMASK 1’b1 Interrupt mask of i2c_end_int RSVD FERINT 1’b0 I2C TX/RX FIFO error interrupt, auto-cleared when FIFO...
  • Page 218 BL702/704/706 Reference Manual 11.9.4 i2c_bus_busy Address：0x4000a30c RSVD RSVD BUSY BUSY Name Type Reset Description Bits 31:2 RSVD BUSYCLR 1’b0 Clear signal of bus_busy status, not for normal usage (in case I2C bus hangs) BUSY 1’b0 Indicator of I2C bus busy 11.9.5 i2c_prd_start...
  • Page 219 BL702/704/706 Reference Manual 11.9.6 i2c_prd_stop Address：0x4000a314 PRDPPH3 PRDPPH2 PRDPPH1 PRDPPH0 Name Type Reset Description Bits 31:24 PRDPPH3 8’d15 Length of STOP condition phase 3 23:16 PRDPPH2 8’d15 Length of STOP condition phase 2 15:8 PRDPPH1 8’d15 Length of STOP condition phase 1 PRDPPH0 8’d15...
  • Page 220 BL702/704/706 Reference Manual 11.9.8 i2c_fifo_config_0 Address：0x4000a380 RSVD RSVD RFIU RFIO TFIU TFIO DREN DTEN Name Type Reset Description Bits 31:8 RSVD RFIU 1’b0 Underflow flag of RX FIFO, can be cleared by rx_fifo_clr RFIO 1’b0 Overflow flag of RX FIFO, can be cleared by rx_fifo_clr TFIU 1’b0...
  • Page 221 BL702/704/706 Reference Manual Name Type Reset Description Bits 15:10 RSVD RFICNT 2’d0 RX FIFO available count RSVD TFICNT 2’d2 TX FIFO available count 11.9.10 i2c_fifo_wdata Address：0x4000a388 FIWD FIWD Name Type Reset Description Bits 31:0 FIWD I2C FIFO write data 11.9.11 i2c_fifo_rdata Address：0x4000a38c...
  • Page 222 Each counter has its own 16-bit frequency divider. The PWM counter will use the divided clock as the counting cycle unit, and perform one action every time a counting cycle passes . 222/ 375 @2021 Bouffalo Lab BL702/704/706 Reference Manual...

  • Page 223: Pwm Waveform

    BL702/704/706 Reference Manual 12.3.2 Pulse generation principle There is a counter in the PWM. When the counter is in the middle of two settable thresholds, the PWM output is 1, otherwise when the counter is outside the two set thresholds, the PWM output is 0. As shown below:...

  • Page 224: Duty Cycle Parameters

    BL702/704/706 Reference Manual 12.3.3 PWM interrupt For each PWM channel, you can set the cycle count value. When the cycle number of the PWM output reaches this count value, a PWM interrupt will be generated. Table 12.1: Duty Cycle Parameters Freq/MHz Supported duty cycle(n is an integer,and 2 <= n <= 65535^2)
  • Page 225 BL702/704/706 Reference Manual Description Name pwm1_thre2 PWM1 sencond counter threshold configuration register pwm1_period PWM1 period setting register pwm1_config PWM1 configuration register pwm1_interrupt PWM1 interrupt register pwm2_clkdiv PWM2 clock division configuration register pwm2_thre1 PWM2 first counter threshold configuration register pwm2_thre2 PWM2 sencond counter threshold configuration register...
  • Page 226 BL702/704/706 Reference Manual 12.4.1 pwm_int_config Address：0x4000a400 RSVD RSVD INTCLR RSVD INTSTS Name Type Reset Description Bits 31:14 RSVD 13:8 INTCLR 6’d0 PWM channel interrupt clear RSVD INTSTS 6’d0 PWM channel interrupt status 12.4.2 pwm0_clkdiv Address：0x4000a420 RSVD CLKDIV Name Type Reset...
  • Page 227 BL702/704/706 Reference Manual Name Type Reset Description Bits 31:16 RSVD 15:0 THRE1 16’b0 PWM first counter threshold, can’t be larger that pwm_thre2 12.4.4 pwm0_thre2 Address：0x4000a428 RSVD THRE2 Name Type Reset Description Bits 31:16 RSVD 15:0 THRE2 16’d0 PWM sencond counter threshold, can’t be smaller that pwm_thre1 12.4.5 pwm0_period...
  • Page 228 BL702/704/706 Reference Manual 12.4.6 pwm0_config Address：0x4000a430 RSVD RSVD STOP STOP STOP CLKSEL MODE FVAL MODE Name Type Reset Description Bits 31:8 RSVD STOPSTA 1’b0 PWM stop status STOPEN 1’b0 PWM stop enable SWMODE 1’b0 PWM SW Mode setting SWFVAL 1’b0...
  • Page 229 BL702/704/706 Reference Manual 12.4.8 pwm1_clkdiv Address：0x4000a440 RSVD CLKDIV Name Type Reset Description Bits 31:16 RSVD 15:0 CLKDIV 16’b0 PWM clock division 12.4.9 pwm1_thre1 Address：0x4000a444 RSVD THRE1 Name Type Reset Description Bits 31:16 RSVD 15:0 THRE1 16’b0 PWM first counter threshold, can’t be larger that pwm_thre2 12.4.10 pwm1_thre2...
  • Page 230 BL702/704/706 Reference Manual Name Type Reset Description Bits 15:0 THRE2 16’d0 PWM sencond counter threshold, can’t be smaller that pwm_thre1 12.4.11 pwm1_period Address：0x4000a44c RSVD PERIOD Name Type Reset Description Bits 31:16 RSVD 15:0 PERIOD 16’d0 PWM period setting 12.4.12 pwm1_config Address：0x4000a450...
  • Page 231 BL702/704/706 Reference Manual Name Type Reset Description Bits 12.4.13 pwm1_interrupt Address：0x4000a454 RSVD INTPECN Name Type Reset Description Bits 31:17 RSVD INTEN 1’b0 PWM interrupt enable 15:0 INTPECN 16’d0 PWM interrupt period counter threshold 12.4.14 pwm2_clkdiv Address：0x4000a460 RSVD CLKDIV Name Type...
  • Page 232 BL702/704/706 Reference Manual 12.4.15 pwm2_thre1 Address：0x4000a464 RSVD THRE1 Name Type Reset Description Bits 31:16 RSVD 15:0 THRE1 16’b0 PWM first counter threshold, can’t be larger that pwm_thre2 12.4.16 pwm2_thre2 Address：0x4000a468 RSVD THRE2 Name Type Reset Description Bits 31:16 RSVD 15:0 THRE2 16’d0...
  • Page 233 BL702/704/706 Reference Manual Name Type Reset Description Bits 15:0 PERIOD 16’d0 PWM period setting 12.4.18 pwm2_config Address：0x4000a470 RSVD RSVD STOP STOP STOP CLKSEL MODE FVAL MODE Name Type Reset Description Bits 31:8 RSVD STOPSTA 1’b0 PWM stop status STOPEN 1’b0...
  • Page 234 BL702/704/706 Reference Manual Name Type Reset Description Bits 15:0 INTPECN 16’d0 PWM interrupt period counter threshold 12.4.20 pwm3_clkdiv Address：0x4000a480 RSVD CLKDIV Name Type Reset Description Bits 31:16 RSVD 15:0 CLKDIV 16’b0 PWM clock division 12.4.21 pwm3_thre1 Address：0x4000a484 RSVD THRE1 Name...
  • Page 235 BL702/704/706 Reference Manual 12.4.22 pwm3_thre2 Address：0x4000a488 RSVD THRE2 Name Type Reset Description Bits 31:16 RSVD 15:0 THRE2 16’d0 PWM sencond counter threshold, can’t be smaller that pwm_thre1 12.4.23 pwm3_period Address：0x4000a48c RSVD PERIOD Name Type Reset Description Bits 31:16 RSVD 15:0 PERIOD 16’d0...
  • Page 236 BL702/704/706 Reference Manual Name Type Reset Description Bits 31:8 RSVD STOPSTA 1’b0 PWM stop status STOPEN 1’b0 PWM stop enable SWMODE 1’b0 PWM SW Mode setting SWFVAL 1’b0 PWM SW Mode force value STOPMODE 1’b1 PWM stop mode, 1’b1 - graceful ; 1’b0 - abrupt OUTINV 1’b0...
  • Page 237 BL702/704/706 Reference Manual Name Type Reset Description Bits 31:16 RSVD 15:0 CLKDIV 16’b0 PWM clock division 12.4.27 pwm4_thre1 Address：0x4000a4a4 RSVD THRE1 Name Type Reset Description Bits 31:16 RSVD 15:0 THRE1 16’b0 PWM first counter threshold, can’t be larger that pwm_thre2 12.4.28 pwm4_thre2...
  • Page 238 BL702/704/706 Reference Manual 12.4.29 pwm4_period Address：0x4000a4ac RSVD PERIOD Name Type Reset Description Bits 31:16 RSVD 15:0 PERIOD 16’d0 PWM period setting 12.4.30 pwm4_config Address：0x4000a4b0 RSVD RSVD STOP STOP STOP CLKSEL MODE FVAL MODE Name Type Reset Description Bits 31:8 RSVD STOPSTA 1’b0...
  • Page 239 BL702/704/706 Reference Manual 12.4.31 pwm4_interrupt Address：0x4000a4b4 RSVD INTPECN Name Type Reset Description Bits 31:17 RSVD INTEN 1’b0 PWM interrupt enable 15:0 INTPECN 16’d0 PWM interrupt period counter threshold BL702/704/706 Reference Manual 239/ 375 @2021 Bouffalo Lab...

  • Page 240: Timer Block Diagram

    Timer, which can trigger interrupt or system reset according to the setting. BL_TIMER 32-bit timer fclk xtal_ clk_mux clk_div timer_cnt timer_irq f32k _ Fig. 13.1: Timer block diagram 240/ 375 @2021 Bouffalo Lab BL702/704/706 Reference Manual...

  • Page 241: Watchdog Timer Block Diagram

    BL702/704/706 Reference Manual BL_WDT watch-dog timer fclk wdt_ir q xtal_ clk_mux clk_div wdt_cnt f32k_ Fig. 13.2: Watchdog timer block diagram 13.2 TIMER main features • Multiple clock source options • 8-bit clock divider with a division factor of 1-256. • Two 32-bit timers •...

  • Page 242: Timer Preload

    BL702/704/706 Reference Manual • Fclk--System master clock • 32K--32K clock • 1K--1K clock（32K frequency division） • Xtal--External crystal Each counter has its own 8-bit frequency divider. The selected clock can be divided by 1-256 through APB. Specifically, when it is set to 0, it means no frequency division, and when it is set to 1, it divides it by 2. The maximum frequency division coefficient is 256, the counter will use the divided clock as the unit of the counting cycle, each time a counting cycle is increased by one.

  • Page 243: Watchdog Timing

    BL702/704/706 Reference Manual In FreeRun mode, the timer working sequence is basically the same as PreLoad, the difference is that the counter will start to accumulate from 0 to the maximum value. The mechanism of the generated compare flags and compare interrupts is the same as in PreLoad mode.

  • Page 244: Watchdog Alarm Mechanism

    BL702/704/706 Reference Manual 13.3.5 Watchdog alarm A comparison value can be set for each counter. When the software fails to reset the watchdog counter to zero due to a system error, which causes the watchdog counter to exceed the comparison value, a watchdog alarm is triggered.
  • Page 245 BL702/704/706 Reference Manual Description Name TMR3_0 Timer3 match register 0 TMR3_1 Timer3 match register 1 TMR3_2 Timer3 match register 2 TCR2 Timer2 counter register TCR3 Timer3 counter register TMSR2 Timer2 match register status TMSR3 Timer3 match register status TIER2 Timer2 match interrupt enable register...
  • Page 246 BL702/704/706 Reference Manual Description Name TCVSYN2 Timer2 synchronous value of counter register TCVSYN3 Timer3 synchronous value of counter register TCDR WDT/Timer clock division register 13.4.1 TCCR Address：0x4000a500 RSVD RSVD CSWDT RSVD RSVD RSVD Name Type Reset Description Bits 31:10 RSVD CSWDT 2’d0...
  • Page 247 BL702/704/706 Reference Manual 13.4.2 TMR2_0 Address：0x4000a510 TMR20 TMR20 Name Type Reset Description Bits 31:0 TMR20 32’hffffffff Timer2 match register 0 13.4.3 TMR2_1 Address：0x4000a514 TMR21 TMR21 Name Type Reset Description Bits 31:0 TMR21 32’hffffffff Timer2 match register 1 13.4.4 TMR2_2 Address：0x4000a518...
  • Page 248 BL702/704/706 Reference Manual 13.4.5 TMR3_0 Address：0x4000a51c TMR30 TMR30 Name Type Reset Description Bits 31:0 TMR30 32’hffffffff Timer3 match register 0 13.4.6 TMR3_1 Address：0x4000a520 TMR31 TMR31 Name Type Reset Description Bits 31:0 TMR31 32’hffffffff Timer3 match register 1 13.4.7 TMR3_2 Address：0x4000a524...
  • Page 249 BL702/704/706 Reference Manual 13.4.8 TCR2 Address：0x4000a52c TCR2COUT TCR2COUT Name Type Reset Description Bits 31:0 TCR2COUT 32’h0 Timer2 counter register 13.4.9 TCR3 Address：0x4000a530 TCR3COUT TCR3COUT Name Type Reset Description Bits 31:0 TCR3COUT 32’h0 Timer3 counter register 13.4.10 TMSR2 Address：0x4000a538 RSVD RSVD...
  • Page 250 BL702/704/706 Reference Manual Name Type Reset Description Bits T2MR1S 1’b0 Timer2 match register 1 status/Clear interrupt would also clear this bit T2MR0S 1’b0 Timer2 match register 0 status/Clear interrupt would also clear this bit 13.4.11 TMSR3 Address：0x4000a53c RSVD RSVD Name...
  • Page 251 BL702/704/706 Reference Manual Name Type Reset Description Bits TIER21 1’b0 Timer2 match register 1 interrupt enable register TIER20 1’b0 Timer2 match register 0 interrupt enable register 13.4.13 TIER3 Address：0x4000a548 RSVD RSVD TIER TIER31 TIER30 Name Type Reset Description Bits 31:3...
  • Page 252 BL702/704/706 Reference Manual 13.4.15 TPLVR3 Address：0x4000a554 TPLVR3 TPLVR3 Name Type Reset Description Bits 31:0 TPLVR3 32’h0 Timer3 pre-load value register 13.4.16 TPLCR2 Address：0x4000a55c RSVD RSVD TPLCR2 Name Type Reset Description Bits 31:2 RSVD TPLCR2 2’h0 Timer2 pre-load control register 2’d0 - No pre-load 2’d1 - Pre-load with match comparator 0...
  • Page 253 BL702/704/706 Reference Manual Name Type Reset Description Bits 31:2 RSVD TPLCR3 2’h0 Timer3 pre-load control register 2’d0 - No pre-load 2’d1 - Pre-load with match comparator 0 2’d2 - Pre-load with match comparator 1 2’d3 - Pre-load with match comparator 2 13.4.18 WMER...
  • Page 254 BL702/704/706 Reference Manual 13.4.20 WVR Address：0x4000a56c RSVD Name Type Reset Description Bits 31:16 RSVD 15:0 16’h0 WDT counter value register 13.4.21 WSR Address：0x4000a570 RSVD RSVD Name Type Reset Description Bits 31:1 RSVD 1’b0 WDT timer reset indication, Indicates that reset was caused by the WDT.
  • Page 255 BL702/704/706 Reference Manual 13.4.22 TICR2 Address：0x4000a578 RSVD RSVD TCLR TCLR TCLR Name Type Reset Description Bits 31:3 RSVD TCLR22 1’b0 Timer2 Interrupt clear for match comparator 2 TCLR21 1’b0 Timer2 Interrupt clear for match comparator 1 TCLR20 1’b0 Timer2 Interrupt clear for match comparator 0 13.4.23 TICR3...
  • Page 256 BL702/704/706 Reference Manual 13.4.24 WICR Address：0x4000a580 RSVD RSVD Name Type Reset Description Bits 31:1 RSVD WICLR 1’b0 WDT Interrupt clear register 13.4.25 TCER Address：0x4000a584 RSVD RSVD TIM3 TIM2 RSVD Name Type Reset Description Bits 31:3 RSVD TIM3EN 1’b0 Timer3 count enable TIM2EN 1’b0...
  • Page 257 BL702/704/706 Reference Manual Name Type Reset Description Bits 31:3 RSVD TIM3MODE 1’b0 Timer1/2/3 count mode register 1’b0 - pre-load mode 1’b1 - free run mode TIM2MODE 1’b0 Timer1/2/3 count mode register 1’b0 - pre-load mode 1’b1 - free run mode RSVD 13.4.27 TILR2...
  • Page 258 BL702/704/706 Reference Manual 13.4.28 TILR3 Address：0x4000a594 RSVD RSVD TILR TILR TILR Name Type Reset Description Bits 31:3 RSVD TILR32 1’b0 Timer3 match 0/1/2 interrupt mode register 1’b0 - level interrupt 1’b1 - pulse interrupt TILR31 1’b0 Timer3 match 0/1/2 interrupt mode register 1’b0 - level interrupt...
  • Page 259 BL702/704/706 Reference Manual 13.4.30 WFAR Address：0x4000a59c RSVD WFAR Name Type Reset Description Bits 31:16 RSVD 15:0 WFAR 16’b0 WDT access key1 - 16’hBABA 13.4.31 WSAR Address：0x4000a5a0 RSVD WSAR Name Type Reset Description Bits 31:16 RSVD 15:0 WSAR 16’b0 WDT access key2 - 16’hEB10 13.4.32 TCVWR2...
  • Page 260 BL702/704/706 Reference Manual 13.4.33 TCVWR3 Address：0x4000a5ac TCVWR3 TCVWR3 Name Type Reset Description Bits 31:0 TCVWR3 32’h0 Timer3 capture value of counter 13.4.34 TCVSYN2 Address：0x4000a5b4 TCVSYN2 TCVSYN2 Name Type Reset Description Bits 31:0 TCVSYN2 32’h0 Timer2 synchronous value of counter 13.4.35 TCVSYN3 Address：0x4000a5b8...
  • Page 261 BL702/704/706 Reference Manual 13.4.36 TCDR Address：0x4000a5bc WCDR TCDR3 TCDR2 RSVD Name Type Reset Description Bits 31:24 WCDR 8’h0 WDT clock division value register 23:16 TCDR3 8’h0 Timer3 clock division value register 15:8 TCDR2 8’h0 Timer2 clock division value register RSVD...
  • Page 262 • Built-in a LED function that can flash with sampling (LED on/off 0~511 us/sample) • Interrupt can be configured (sample interrupt, report interrupt, error interrupt, overflow interrupt) • Can be configured as a wake-up source for PDS (clock source needs to be configured as 32k) 262/ 375 @2021 Bouffalo Lab BL702/704/706 Reference Manual...
  • Page 263 BL702/704/706 Reference Manual 14.3 QDEC function description The expected operating frequency of QDEC is 1MHz, and the faster the detection speed, the higher the operating frequency required. Each sampling will decode the A/B two-phase pulse output by the encoder into high and low levels. Compare the previous sampling results to get the current encoder rotation direction and pulse count change (clockwise rotation +1, counterclockwise rotation -1 , No change, no change, error report and count).

  • Page 264: Qdec Functional Block Diagram

    BL702/704/706 Reference Manual Phase A Phase A Phase B Quadrature Encoder Quadrature decoder Phase B QDEC work at 1MHz = XCLK/(div+1) led_period XCLK select 32MHz div is 31 spl_period: 0: 32 us/sample 1: 64 us/sample 2: 128 us/sample 3: 256 us/sample...
  • Page 265 BL702/704/706 Reference Manual Description Name qdec1_value QDEC1 value qdec1_int_en QDEC1 interrupt enable qdec1_int_sts QDEC1 interrupt status qdec1_int_clr QDEC1 interrupt clear qdec2_ctrl0 QDEC2 control0 qdec2_ctrl1 QDEC2 control1 qdec2_value QDEC2 value qdec2_int_en QDEC2 interrupt enable qdec2_int_sts QDEC2 interrupt status qdec2_int_clr QDEC2 interrupt clear 14.4.1 qdec0_ctrl0...
  • Page 266 BL702/704/706 Reference Manual Name Type Reset Description Bits 11:8 4’h2 ”SPL” sample period in [us/sample]. The SAMPLE register will be updated for every new sample (at 1MHz) 0: 32 us 1: 64 2: 128 3: 256 4: 512 5: 1 ms...
  • Page 267 BL702/704/706 Reference Manual Name Type Reset Description Bits spl option 0: Stop sample if rpt_rdy 1: Continue sample acc option 0: Stop accumulate if overflow 1: Continue ac- cumulate 14.4.3 qdec0_value Address：0x4000a808 RSVD SPLVAL RSVD ACC2VAL ACC1VAL Name Type Reset...
  • Page 268 BL702/704/706 Reference Manual Name Type Reset Description Bits OFEN overflow interrupt enable DREN double error interrupt enable SREN sample interrupt enable RREN report interrupt enable 14.4.5 qdec0_int_sts Address：0x4000a814 RSVD RSVD Name Type Reset Description Bits 31:4 RSVD OFSTS ACC1 or ACC2 overflow...
  • Page 269 BL702/704/706 Reference Manual Name Type Reset Description Bits DRCL double error interrupt clear SRCL sample interrupt clear RRCL report interrupt clear 14.4.7 qdec1_ctrl0 Address：0x4000a840 RSVD DEGCNT QDEC Name Type Reset Description Bits 31:28 RSVD 27:12 16’d10 ”RPT” report period in [samples/report]. Specifies the num-...
  • Page 270 BL702/704/706 Reference Manual Name Type Reset Description Bits LEDEN qdec led enable QDECEN qdec enable 14.4.8 qdec1_ctrl1 Address：0x4000a844 RSVD LEDPED RSVD Name Type Reset Description Bits 31:25 RSVD 24:16 LEDPED Period in us the LED is switched on prior to sampling...
  • Page 271 BL702/704/706 Reference Manual Name Type Reset Description Bits 29:28 SPLVAL Sample value. Direction of last change 00: no change 01: clockwise 11: counter-clockwise 10: Error 27:20 RSVD 19:16 ACC2VAL Double error accumulation (0 15) 15:0 ACC1VAL Sample accumulation (-32768 32767) clockwise +1, counter-clockwise -1 14.4.10 qdec1_int_en...
  • Page 272 BL702/704/706 Reference Manual Name Type Reset Description Bits 31:4 RSVD OFSTS ACC1 or ACC2 overflow DRSTS ACC2 double error SRSTS Event being generated for every new sample value written to the SAMPLE register RRSTS Non-null report ready 14.4.12 qdec1_int_clr Address：0x4000a858...
  • Page 273 BL702/704/706 Reference Manual Name Type Reset Description Bits 27:12 16’d10 ”RPT” report period in [samples/report]. Specifies the num- ber of samples to be accumulated in the ACC1 register be- fore the RPT_RDY and DBL_RDY events can be generated ”RPT_US” report period in [us/report] = SP * RP 11:8 4’h2...
  • Page 274 BL702/704/706 Reference Manual Name Type Reset Description Bits input a/b swap rpt option 0: Count time only if sample change 1: Continue time spl option 0: Stop sample if rpt_rdy 1: Continue sample acc option 0: Stop accumulate if overflow 1: Continue ac- cumulate 14.4.15 qdec2_value...
  • Page 275 BL702/704/706 Reference Manual Name Type Reset Description Bits 31:4 RSVD OFEN overflow interrupt enable DREN double error interrupt enable SREN sample interrupt enable RREN report interrupt enable 14.4.17 qdec2_int_sts Address：0x4000a894 RSVD RSVD Name Type Reset Description Bits 31:4 RSVD OFSTS...
  • Page 276 BL702/704/706 Reference Manual Name Type Reset Description Bits OFCL overflow interrupt clear DRCL double error interrupt clear SRCL sample interrupt clear RRCL report interrupt clear BL702/704/706 Reference Manual 276/ 375 @2021 Bouffalo Lab...
  • Page 277 GPIO with the function of ROW_0, that is, from any one of GPIO0/GPIO8/GPIO16/GPIO24. The column pins need to be selected in order from the GPIO with the function of COL_0, that is, from any one of GPIO0/GPIO20. 277/ 375 @2021 Bouffalo Lab BL702/704/706 Reference Manual...
  • Page 278 BL702/704/706 Reference Manual 15.3.3 Key value The key value will be stored in the register KEYCODE_VALUE, every 8 bits is a key value, and the first key value will be stored in the lowest 8 bits. When the bit corresponding to the serial number in the register KEYCODE_CLR is set to one, the corresponding key value and interrupt flag bit will be cleared.
  • Page 279 BL702/704/706 Reference Manual Name Type Reset Description Bits RCEXT 2’d3 idle duration between column scans DEGCNT deglitch count DEGEN deglitch GHEN ghost key event detection RSVD KSEN Keyscan en 15.4.2 ks_int_en Address：0x4000a910 RSVD RSVD KSIT Name Type Reset Description Bits...
  • Page 280 BL702/704/706 Reference Manual 15.4.4 keycode_clr Address：0x4000a918 RSVD RSVD KCCLR Name Type Reset Description Bits 31:4 RSVD KCCLR Keycode clear 15.4.5 keycode_value Address：0x4000a91c Name Type Reset Description Bits 31:24 8’hff Col = keycode / (row_num+1) Row = keycode % (row_num+1) 23:16 8’hff...

  • Page 281: I2S Pin List

    • The width of the data transmission FIFO is 32 bits and the depth is 16 • The width of the data receiving FIFO is 32 bits and the depth is 16 16.3 I2S function description Table 16.1: I2S pin list 281/ 375 @2021 Bouffalo Lab BL702/704/706 Reference Manual...
  • Page 282 BL702/704/706 Reference Manual Name Type Description I2Sx_DI input Serial data input I2Sx_DO output Serial data output I2Sx_BCLK input/output Synchronous transmission clock, output when used as a master, and input when used as a slave I2Sx_FS input/output Data start/end signal, output when used as master, input when used as slave 16.4 Register description...
  • Page 283 BL702/704/706 Reference Manual Name Type Reset Description Bits OFSEN 1’b0 Offset enable 1’b0: Disabled, 1’b1: Enabled 24:20 OFSCNT 5’d0 Offset cycle count (unit: cycle of I2S BCLK) 5’d0: 1 cycle 5’d1: 2 cycles … MONORCH 1’b0 RX mono mode channel select signal 1’b0: L-channel...
  • Page 284 BL702/704/706 Reference Manual Name Type Reset Description Bits TXDEN 1’b0 Enable signal of I2S TXD signal SLAEN 1’b0 Enable signal of I2S Slave function, cannot enable both csr_i2s_m_en & csr_i2s_s_en MASEN 1’b0 Enable signal of I2S Master function, cannot enable both csr_i2s_m_en &...
  • Page 285 BL702/704/706 Reference Manual 16.4.3 i2s_bclk_config Address：0x4000aa10 RSVD BDIVH RSVD BDIVL Name Type Reset Description Bits 31:28 RSVD 27:16 BDIVH 12’d1 I2S BCLK active high period (unit: cycle of i2s_clk) 15:12 RSVD 11:0 BDIVL 12’d1 I2S BCLK active low period (unit: cycle of i2s_clk) 16.4.4 i2s_fifo_config_0...
  • Page 286 BL702/704/706 Reference Manual Name Type Reset Description Bits LRMG 1’b0 Each FIFO entry contains both L/R channel data if this bit is enabled Can only be enabled if data size is 8 or 16 bits Note: cr_fifo_lr_merge &cr_mono_mode should NOT be enabled at the same time Note: cr_fifo_lr_merge &cr_fifo_l_shift should NOT be en-...
  • Page 287 BL702/704/706 Reference Manual 16.4.6 i2s_fifo_wdata Address：0x4000aa88 FIWD FIWD Name Type Reset Description Bits 31:0 FIWD I2S FIFO write data 16.4.7 i2s_fifo_rdata Address：0x4000aa8c FIRD FIRD Name Type Reset Description Bits 31:0 FIRD 32’h0 I2S FIFO read data 16.4.8 i2s_io_config Address：0x4000aafc RSVD...
  • Page 288 BL702/704/706 Reference Manual Name Type Reset Description Bits DEGCNT 3’d0 Deglitch cycle count (unit: cycle of I2S kernel clock) 3’d0: 1 cycle 3’d1: 2 cycles … BCLKINV 1’b0 Inverse BCLK signal 0: No inverse, 1: Inverse FSINV 1’b0 Inverse FS signal...
  • Page 289 • Support 10Mbps and 100Mbps Ethernet • Support half duplex and full duplex • In full duplex mode, support automatic flow control and control frame generation • Support collision detection and retransmission in half-duplex mode 289/ 375 @2021 Bouffalo Lab BL702/704/706 Reference Manual...
  • Page 290 BL702/704/706 Reference Manual • Support CRC generation and verification • Data frame preamble generation and removal • When sending, automatically expand short data frames • Detect too long or too short data frame (length limit) • Can transmit long data frames (> standard Ethernet frame length) •...

  • Page 291: Emac Architecture

    BL702/704/706 Reference Manual Ethernet Core Tx Data Tx Data Tx Control Signals Tx PHY TX Ethernet MAC Control Tx Control Signals Signals Tx Control Signals MAC Control Module (Flow control) Host Interface Ethernet Ethernet PHY Rx Data Tx Control Signals...

  • Page 292: Transmission Signal

    BL702/704/706 Reference Manual The send and receive buffer descriptor group is connected to the external RAM, which is used to store the Ethernet data frames sent and received. Each descriptor contains the corresponding control status word and the corresponding buffer memory address. There are 128 groups of descriptors, which can be flexibly allocated for sending or receiving.

  • Page 293: Transmission Signal

    BL702/704/706 Reference Manual Table 17.1: Transmission signal RMII Name ECOL ECOL: collision detection ERXDV ERXDV: data valid ECRSDV: Carrier detect/data valid ERX0-ERX3 ERX0-ERX3: 4-bit receive data ERX0-ERX1: 2-bit receive data ERXER ERXER: Receive error indication ERXER: Receive error indication ERXCK...
  • Page 294 BL702/704/706 Reference Manual 17.7.2 Send data frame • Configure bit fields such as data frame format and interval in the EMAC_MODE register • By configuring the TXBDNUM field in the EMAC_TX_BD_NUM register to specify the number of BDs used for transmission, the remaining BDs are RX BDs •...
  • Page 295 BL702/704/706 Reference Manual • In particular, if it is the last valid receiving BD, the WR bit needs to be set, and EMAC will ”wrap around” to the first receiving BD for processing after processing this BD • If there are multiple BDs available to receive data, repeat the steps of setting BD to fill all BDs •...
  • Page 296 BL702/704/706 Reference Manual Description Name TXCTRL TX control 17.8.1 MODE Address：0x4000d000 RSVD RMII RECS MALL RSVD FULL RSVD RSVD TXEN RXEN Name Type Reset Description Bits 31:18 RSVD RMIIEN 1’b0 RMII mode enable 0: MII PHY I/F is used 1: RMII PHY I/F is used RECSMALL 1’b0...
  • Page 297 BL702/704/706 Reference Manual Name Type Reset Description Bits 1’b0 Inter frame gap check 0: IFG is verified before each frame be received. 1: All frames are received regardless to IFG requirement. 1’b0 Promiscuous mode enable 0: The destination address is checked before receiving.
  • Page 298 BL702/704/706 Reference Manual Name Type Reset Description Bits 1’b0 Receive control frame This bit indicates that the control frame was received. It is cleared by writing 1 to it. Bit RXFLOW in the CTRLMODE register must be set to 1 in order to get the RXC bit set.
  • Page 299 BL702/704/706 Reference Manual 17.8.3 INT_MASK Address：0x4000d008 RSVD RSVD RXCM TXCM RXEM RXBM TXEM TXBM Name Type Reset Description Bits 31:7 RSVD RXCM 1’b1 Receive control frame mask ENABLE 0: Interrupt is un-masked 1: Interrupt is masked TXCM 1’b1 Transmit control frame mask ENABLE...
  • Page 300 BL702/704/706 Reference Manual 17.8.4 IPGT Address：0x4000d00c RSVD RSVD IPGT Name Type Reset Description Bits 31:7 RSVD IPGT 7’h18 Inter packet gap The recommended value is 0x18 (24 clock cycles), which equals 9.6 us for 10 Mbps and 0.96 us for 100 Mbps mode 17.8.5 PACKETLEN...
  • Page 301 BL702/704/706 Reference Manual 17.8.6 COLLCONFIG Address：0x4000d01c RSVD MAXRET RSVD COLLVAL Name Type Reset Description Bits 31:20 RSVD 19:16 MAXRET 4’hF Maximum retry This field specifies the maximum number of consequential retransmission attempts after the collision is detected. When the maximum number has been reached, the TX MAC reports an error and stops transmitting the current packet.
  • Page 302 BL702/704/706 Reference Manual Name Type Reset Description Bits RSVD 22:16 TXBDPTR 7’h0 TX buffer descriptors (BD) pointer, pointing at the TXBD currently being used 15:8 RSVD TXBDNUM 8’h40 TX buffer descriptors (BD) number Number of TX BD. TX and RX share 128 (0x80) descriptors, so the number of RX BD equals 0x80 - TXBDNUM.
  • Page 303 BL702/704/706 Reference Manual 17.8.9 MIICOMMAND Address：0x4000d02c RSVD RSVD WCTR RSTA SCAS DATA Name Type Reset Description Bits 31:3 RSVD WCTRDATA 1’b0 Write control data, setting this bit to 1 will trigger the com- mand (auto cleared) Note: [2]/[1]/[0] cannot be asserted at the same time, exe-...
  • Page 304 BL702/704/706 Reference Manual 17.8.11 MIITX_DATA Address：0x4000d034 RSVD CTRLDATA Name Type Reset Description Bits 31:16 RSVD 15:0 CTRLDATA 16’h0 Control Data to be written to PHY 17.8.12 MIIRX_DATA Address：0x4000d038 RSVD PRSD Name Type Reset Description Bits 31:16 RSVD 15:0 PRSD 16’h0 Received Data from PHY 17.8.13 MIISTATUS...
  • Page 305 BL702/704/706 Reference Manual Name Type Reset Description Bits 31:2 RSVD MIIMBUSY 1’b0 MIIM I/F busy signal 0: The MIIM I/F is ready. 1: The MIIM I/F is busy. MIIMLF 1’b0 MIIM I/F link fail signal 17.8.14 MAC_ADDR0 Address：0x4000d040 MACB2 MACB3...
  • Page 306 BL702/704/706 Reference Manual 17.8.16 HASH0_ADDR Address：0x4000d048 HASH0 HASH0 Name Type Reset Description Bits 31:0 HASH0 32’h0 Lower 32-bit of HASH register 17.8.17 HASH1_ADDR Address：0x4000d04c HASH1 HASH1 Name Type Reset Description Bits 31:0 HASH1 32’h0 Upper 32-bit of HASH register 17.8.18 TXCTRL Address：0x4000d050...
  • Page 307 BL702/704/706 Reference Manual Name Type Reset Description Bits TXPRQ 1’b0 TX Pause Request Writing 1 to this bit starts sending control frame and is au- tomatically cleared to zero. 15:0 TXPTV 16’h0 TX Pause Timer Value The value that is sent in the pause control frame.
  • Page 308 1. Configure the internal transceiver, the corresponding addresses are 0x40000228 and 0x4000022C 2. Configure usb_config and epx_config of each endpoint 3. Configure USB interrupt related registers 4. Configure USB DMA related (optional) 5. Configure GPIO as USB function (internal transmitter----function is 10) 308/ 375 @2021 Bouffalo Lab BL702/704/706 Reference Manual...
  • Page 309 BL702/704/706 Reference Manual 6. 0x40000228[20]usb_enum is set to 1, so that the host recognizes that the USB device is inserted and triggers the enumeration process 18.3.2 Part of the register configuration and function description • swrdy:Read only, only when this bit is 0, can write 1 to cr_usb_ep0_sw_rdy •...

  • Page 310: Usb Interrupt Trigger Mode

    BL702/704/706 Reference Manual Trigger e0scit Trigger e0sdit interrupt interrupt device -> host host -> device host -> device SETUP DATA Trigger e0icit Trigger e0idit interrupt interrupt host -> device device -> host host -> device DATA Trigger e0ocit Trigger ep0dit...
  • Page 311 BL702/704/706 Reference Manual 18.3.3 USB enumeration phase interrupt processing flow 1. The first is a reset of more than 10ms, which will trigger the reset interrupt. 2. When the reset ends, the reset end interrupt will be triggered. 3. The SETUP transaction, IN transaction, and OUT transaction of the enumeration process will trigger e0sdit, e0icit, and ep0dit respectively.
  • Page 312 BL702/704/706 Reference Manual – Clear interrupt flag – Exit interrupt • EPx(x=1...7)——IN transaction data transmission: – Enter interrupt – Determine the epxcit interrupt flag bit – Wait for exrs to be 0 before writing data to extfw (exs needs to be changed to 1 only when only 1 byte is sent) –...

  • Page 313: Usb Communication Method

    BL702/704/706 Reference Manual Only a er swrdy=0 can you fill in data to e0 w; Se ng a crsr a er the data is filled will make the handshake phase reply ACK; device -> host host -> device host -> device...

  • Page 314: Register Configuration

    BL702/704/706 Reference Manual Table 18.1: Register configuration 1 usb_xcvr value usb_rcv read only usb_vip read only usb_vim read only usb_bd read only pu_usb 0->1 usb_sus usb_spd usb_enum 0->1 usb_data_convert usb_oeb read only usb_oeb_reg usb_oeb_sel usb_rout_pmos usb_rout_nmos pu_usb_ldo usb_ldo_vfb Table 18.2: Register configuration 2...

  • Page 315: Register Configuration

    BL702/704/706 Reference Manual Table 18.2: Register configuration 2 usb_xcvr_config value usb_v_hys_m Note: You need to set pu_usb and usb_enum to one when you are ready to open the internal transceiver. 18.4 Register description Description Name usb_config USB configuration usb_lpm_config USB lpm configuration...
  • Page 316 BL702/704/706 Reference Manual Description Name ep1_fifo_status EP1 fifo status ep1_tx_fifo_wdata EP1 tx fifo write data ep1_rx_fifo_rdata EP1 rx fifo write data ep2_fifo_config EP2 fifo configuration ep2_fifo_status EP2 fifo status ep2_tx_fifo_wdata EP2 tx fifo write data ep2_rx_fifo_rdata EP2 rx fifo write data...
  • Page 317 BL702/704/706 Reference Manual 18.4.1 usb_config Address：0x4000d800 RSVD CRSR E0SS E0SIZE EOSWADDR E0SC RSVD RBEN RSVD Name Type Reset Description Bits 31:29 RSVD SWRDY 1’b0 EP0 transaction ready status bit. Asserted with sw_rdy, and de-asserted when ACK is sent/received. CRSR 1’b0 EP0 transaction ready.
  • Page 318 BL702/704/706 Reference Manual Name Type Reset Description Bits E0SC 1’b0 EP0 software control enable 1’b1: EP0 IN/OUT transaction is fully contolled by SW 1’b0: EP0 IN/OUT transaction is controlled by HW must be 1 RSVD RBEN 1’b1 Enable signal of ROM-based descriptors (don’t care if ep0_- sw_ctrl is asserted) 1’b1: USB descriptors stored in ROM will be used...
  • Page 319 BL702/704/706 Reference Manual 18.4.3 usb_resume_config Address：0x4000d808 RSFC RSVD RSVD RSTG RSVD RSWD Name Type Reset Description Bits RSFC 1’b0 Force to output K-state 30:13 RSVD RSTG 1’b0 Resume K-state trigger RSVD 10:0 RSWD 11’d26 Resume K-state width (unit: 2.67us) 18.4.4 usb_frame_no Address：0x4000d818...
  • Page 320 BL702/704/706 Reference Manual 18.4.5 usb_error Address：0x4000d81c RSVD RSVD CRC16 CRC5 PCSE PSEO IEEO TTEO UREO Name Type Reset Description Bits 31:7 RSVD CRC16ERR 1’b0 Data CRC error occurs, cleared by cr_usb_err_clr, enabled by ueen CRC5ERR 1’b0 Token CRC error occurs, cleared by cr_usb_err_clr, en-...
  • Page 321 BL702/704/706 Reference Manual Name Type Reset Description Bits UEEN 1’b1 Interrupt enable of usb_err_int S3EN 1’b0 Interrupt enable of sof_3ms_int SOF is absent for 3 times (3ms) interrupt enable LPEN 1’b0 Interrupt enable of lpm_pkt_int receive link power mangement packet interrupt enable LWEN 1’b0...
  • Page 322 BL702/704/706 Reference Manual Name Type Reset Description Bits VTEN 1’b1 Interrupt enable of vbus_tgl_int vbus voltage toggle interrupt enable, for detect equipment plug UREN 1’b1 Interrupt enable of usb_reset_int reset interrupt enable 1’b1 Interrupt enable of sof_int SOF interrupt enable 18.4.7 usb_int_sts...
  • Page 323 BL702/704/706 Reference Manual Name Type Reset Description Bits EP3CIT 1’b0 EP3 IN or OUT command is received EP2DIT 1’b0 EP2 IN or OUT command is finished EP2CIT 1’b0 EP2 IN or OUT command is received EP1DIT 1’b0 EP1 IN or OUT command is finished EP1CIT 1’b0...
  • Page 324 BL702/704/706 Reference Manual Name Type Reset Description Bits E7DM 1’b1 Interrupt mask of ep7_done_int E7CM 1’b1 Interrupt mask of ep7_cmd_int E6DM 1’b1 Interrupt mask of ep6_done_int E6CM 1’b1 Interrupt mask of ep6_cmd_int E5DM 1’b1 Interrupt mask of ep5_done_int E5CM 1’b1...
  • Page 325 BL702/704/706 Reference Manual Name Type Reset Description Bits 1’b0 Interrupt clear of usb_err_int 1’b0 Interrupt clear of sof_3ms_int 1’b0 Interrupt clear of lpm_pkt_int 1’b0 Interrupt clear of lpm_wkup_int 1’b0 Interrupt clear of usb_rend_int 26:24 RSVD E7DC 1’b0 Interrupt clear of ep7_done_int E7CC 1’b0...
  • Page 326 BL702/704/706 Reference Manual 18.4.10 ep1_config Address：0x4000d840 RSVD EPRS ENRE ESRE EPMP Name Type Reset Description Bits 31:20 RSVD EPRS 1’b0 Endpoint ready status bit. Asserted with ep_rdy, and de- asserted when ACK is sent/received. 1’b0 Endpoint ready. When Endpoint NACK is enabled, assert-...
  • Page 327 BL702/704/706 Reference Manual 18.4.11 ep2_config Address：0x4000d844 RSVD E2RS Name Type Reset Description Bits 31:20 RSVD E2RS 1’b0 Endpoint ready status bit. Asserted with ep_rdy, and de- asserted when ACK is sent/received. 1’b0 Endpoint ready. When Endpoint NACK is enabled, assert- ing this bit will allow one packet to be transferred 1’b1...
  • Page 328 BL702/704/706 Reference Manual 18.4.12 ep3_config Address：0x4000d848 RSVD E3RS E3RS Name Type Reset Description Bits 31:20 RSVD E3RS 1’b0 Endpoint ready status bit. Asserted with ep_rdy, and de- asserted when ACK is sent/received. E3RS 1’b0 Endpoint ready. When Endpoint NACK is enabled, assert- ing this bit will allow one packet to be transferred 1’b1...
  • Page 329 BL702/704/706 Reference Manual 18.4.13 ep4_config Address：0x4000d84c RSVD E4RS Name Type Reset Description Bits 31:20 RSVD E4RS 1’b0 Endpoint ready status bit. Asserted with ep_rdy, and de- asserted when ACK is sent/received. 1’b0 Endpoint ready. When Endpoint NACK is enabled, assert- ing this bit will allow one packet to be transferred 1’b1...
  • Page 330 BL702/704/706 Reference Manual 18.4.14 ep5_config Address：0x4000d850 RSVD E5RS E5RS Name Type Reset Description Bits 31:20 RSVD E5RS 1’b0 Endpoint ready status bit. Asserted with ep_rdy, and de- asserted when ACK is sent/received. E5RS 1’b0 Endpoint ready. When Endpoint NACK is enabled, assert- ing this bit will allow one packet to be transferred 1’b1...
  • Page 331 BL702/704/706 Reference Manual 18.4.15 ep6_config Address：0x4000d854 RSVD E6RS Name Type Reset Description Bits 31:20 RSVD E6RS 1’b0 Endpoint ready status bit. Asserted with ep_rdy, and de- asserted when ACK is sent/received. 1’b0 Endpoint ready. When Endpoint NACK is enabled, assert- ing this bit will allow one packet to be transferred 1’b1...
  • Page 332 BL702/704/706 Reference Manual 18.4.16 ep7_config Address：0x4000d858 RSVD E7RS Name Type Reset Description Bits 31:20 RSVD E7RS 1’b0 Endpoint ready status bit. Asserted with ep_rdy, and de- asserted when ACK is sent/received. 1’b0 Endpoint ready. When Endpoint NACK is enabled, assert- ing this bit will allow one packet to be transferred 1’b1...
  • Page 333 BL702/704/706 Reference Manual 18.4.17 ep0_fifo_config Address：0x4000d900 RSVD RSVD DREN DTEN Name Type Reset Description Bits 31:8 RSVD E0RFU 1’b0 Underflow flag of RX FIFO, can be cleared by rx_fifo_clr E0RFO 1’b0 Overflow flag of RX FIFO, can be cleared by rx_fifo_clr E0TFU 1’b0...
  • Page 334 BL702/704/706 Reference Manual Name Type Reset Description Bits 22:16 E0RFC 7’d0 RX FIFO available count E0TFF 1’b0 TX FIFO full flag E0TFE 1’b1 TX FIFO empty flag 13:7 RSVD E0TFC 7’d64 TX FIFO available count 18.4.19 ep0_tx_fifo_wdata Address：0x4000d908 RSVD RSVD...
  • Page 335 BL702/704/706 Reference Manual 18.4.21 ep1_fifo_config Address：0x4000d910 RSVD RSVD DREN DTEN Name Type Reset Description Bits 31:8 RSVD E1RFU 1’b0 Underflow flag of RX FIFO, can be cleared by rx_fifo_clr E1RFO 1’b0 Overflow flag of RX FIFO, can be cleared by rx_fifo_clr E1TFU 1’b0...
  • Page 336 BL702/704/706 Reference Manual Name Type Reset Description Bits 22:16 E1RFC 7’d0 RX FIFO available count E1TFF 1’b0 TX FIFO full flag E1TFE 1’b1 TX FIFO empty flag 13:7 RSVD E1TFC 7’d64 TX FIFO available count 18.4.23 ep1_tx_fifo_wdata Address：0x4000d918 RSVD RSVD...
  • Page 337 BL702/704/706 Reference Manual 18.4.25 ep2_fifo_config Address：0x4000d920 RSVD RSVD DREN DTEN Name Type Reset Description Bits 31:8 RSVD E2RFU 1’b0 Underflow flag of RX FIFO, can be cleared by rx_fifo_clr E2RFO 1’b0 Overflow flag of RX FIFO, can be cleared by rx_fifo_clr E2TFU 1’b0...
  • Page 338 BL702/704/706 Reference Manual Name Type Reset Description Bits 22:16 E2RFC 7’d0 RX FIFO available count E2TFF 1’b0 TX FIFO full flag E2TFE 1’b1 TX FIFO empty flag 13:7 RSVD E2TFC 7’d64 TX FIFO available count 18.4.27 ep2_tx_fifo_wdata Address：0x4000d928 RSVD RSVD...
  • Page 339 BL702/704/706 Reference Manual 18.4.29 ep3_fifo_config Address：0x4000d930 RSVD RSVD DTEN DTEN Name Type Reset Description Bits 31:8 RSVD E3RFU 1’b0 Underflow flag of RX FIFO, can be cleared by rx_fifo_clr E3RFO 1’b0 Overflow flag of RX FIFO, can be cleared by rx_fifo_clr E3TFU 1’b0...
  • Page 340 BL702/704/706 Reference Manual Name Type Reset Description Bits 22:16 E3RFC 7’d0 RX FIFO available count E3TFF 1’b0 TX FIFO full flag E3TFE 1’b1 TX FIFO empty flag 13:7 RSVD E3TFC 7’d64 TX FIFO available count 18.4.31 ep3_tx_fifo_wdata Address：0x4000d938 RSVD RSVD...
  • Page 341 BL702/704/706 Reference Manual 18.4.33 ep4_fifo_config Address：0x4000d940 RSVD RSVD DREN DTEN Name Type Reset Description Bits 31:8 RSVD E4RFU 1’b0 Underflow flag of RX FIFO, can be cleared by rx_fifo_clr E4RFO 1’b0 Overflow flag of RX FIFO, can be cleared by rx_fifo_clr E4TFU 1’b0...
  • Page 342 BL702/704/706 Reference Manual Name Type Reset Description Bits 22:16 E4RFC 7’d0 RX FIFO available count E4TFF 1’b0 TX FIFO full flag E4TFE 1’b1 TX FIFO empty flag 13:7 RSVD E4TFC 7’d64 TX FIFO available count 18.4.35 ep4_tx_fifo_wdata Address：0x4000d948 RSVD RSVD...
  • Page 343 BL702/704/706 Reference Manual 18.4.37 ep5_fifo_config Address：0x4000d950 RSVD RSVD DREN DTEN Name Type Reset Description Bits 31:8 RSVD E5RFU 1’b0 Underflow flag of RX FIFO, can be cleared by rx_fifo_clr E5RFO 1’b0 Overflow flag of RX FIFO, can be cleared by rx_fifo_clr E5TFU 1’b0...
  • Page 344 BL702/704/706 Reference Manual Name Type Reset Description Bits 22:16 E5RFC 7’d0 RX FIFO available count E5TFF 1’b0 TX FIFO full flag E5TFE 1’b1 TX FIFO empty flag 13:7 RSVD E5TFC 7’d64 TX FIFO available count 18.4.39 ep5_tx_fifo_wdata Address：0x4000d958 RSVD RSVD...
  • Page 345 BL702/704/706 Reference Manual 18.4.41 ep6_fifo_config Address：0x4000d960 RSVD RSVD DREN DTEN Name Type Reset Description Bits 31:8 RSVD E6RFU 1’b0 Underflow flag of RX FIFO, can be cleared by rx_fifo_clr E6RFO 1’b0 Overflow flag of RX FIFO, can be cleared by rx_fifo_clr E6TFU 1’b0...
  • Page 346 BL702/704/706 Reference Manual Name Type Reset Description Bits 22:16 E6RFC 7’d0 RX FIFO available count E6TFF 1’b0 TX FIFO full flag E6TFE 1’b1 TX FIFO empty flag 13:7 RSVD E6TFC 7’d64 TX FIFO available count 18.4.43 ep6_tx_fifo_wdata Address：0x4000d968 RSVD RSVD...
  • Page 347 BL702/704/706 Reference Manual 18.4.45 ep7_fifo_config Address：0x4000d970 RSVD RSVD DREN DTEN Name Type Reset Description Bits 31:8 RSVD E7RFU 1’b0 Underflow flag of RX FIFO, can be cleared by rx_fifo_clr E7RFO 1’b0 Overflow flag of RX FIFO, can be cleared by rx_fifo_clr E7TFU 1’b0...
  • Page 348 BL702/704/706 Reference Manual Name Type Reset Description Bits 22:16 E7RFC 7’d0 RX FIFO available count E7TFF 1’b0 TX FIFO full flag E7TFE 1’b1 TX FIFO empty flag 13:7 RSVD E7TFC 7’d64 TX FIFO available count 18.4.47 ep7_tx_fifo_wdata Address：0x4000d978 RSVD RSVD...

  • Page 349: Low Power Mode

    Working Mode Natural wake up Idle Power Saving Mode Sleep Mode interrupt Fig. 19.1: Low power mode 349/ 375 @2021 Bouffalo Lab BL702/704/706 Reference Manual...
  • Page 350 • Sleep Control (HBN): Contains 3 levels of HBN0/1/2, global power saving, long response time 19.3 Function description 19.3.1 Power domain There are 9 power domains in BL702, and the main functions of each power domain are as follows: • PD_AON – HBN state machine controls power/isolation/reset/clock –...

  • Page 351: Power Mode

    BL702/704/706 Reference Manual – Peripherals (analog part) • PD_CPU – CPU/Cache Controller – ROM/High-speed RAM • PD_BZ – Bluetooth and ZigBee • PD_USB – USB Each power domain is controlled by 9 different power modes. The specific control methods are shown in the following table: Table 19.1: Power mode...
  • Page 352 BL702/704/706 Reference Manual 19.3.2 Wakeup source The chip supports multiple wake-up sources and can wake up from different power modes. The CPU will not reset after the PDS0/1/2/3 mode wakes up, and the CPU will reset after the PDS4/5/6/7/31 and HBN0/1/2 modes wake up.
  • Page 353 BL702/704/706 Reference Manual time delay. 1. Enter sleep mode The software can make this module enter the power-down mode through PDS configuration and wait for processing. After entering the waiting interrupt mode (WFI), the PDS module will trigger the clock control module to enter the gate clock operation and notify the analog circuit to turn off the PLL and external crystal oscillator.
  • Page 354 BL702/704/706 Reference Manual Description Name RTC_TIME_L RTC time latched value RTC_TIME_H RTC time latched value HBN_IRQ_MODE HBN irq mode HBN_IRQ_STAT HBN irq state HBN_IRQ_CLR HBN irq clear HBN_PIR_CFG HBN pir configuration HBN_PIR_VTH PIR compare threshold HBN_PIR_INTERVAL PIR interval HBN_MISC HBN misc configuration...
  • Page 355 BL702/704/706 Reference Manual Name Type Reset Description Bits POFFVRT Set 1 to disable power off VDDCORE_RT at HBN mode (for low power) POFFVCOR Set 1 to disable power off VDDCORE at HBN mode (for debug) SRST soft reset POFFHRTC Power Off HBN RTC @ Enter hibernate...
  • Page 356 BL702/704/706 Reference Manual Name Type Reset Description Bits 31:8 RSVD HBNTIMH 8’h0 RTC timer compare bit 39:32 19.4.4 RTC_TIME_L Address：0x4000f00c RTCTIMLL RTCTIMLL Name Type Reset Description Bits 31:0 RTCTIMLL 32’h0 RTC time latched value bit 31:0 19.4.5 RTC_TIME_H Address：0x4000f010 RSVD...
  • Page 357 BL702/704/706 Reference Manual 19.4.6 HBN_IRQ_MODE Address：0x4000f014 RSVD PWUSEL A1EN A0EN RSVD RSVD PUPD RSVD AONPADIE HPAM HPWMODE Name Type Reset Description Bits 31:28 RSVD PWUEN Pin wakeup delay enable 26:24 PWUSEL 3’d3 Pin wakeup delay 1 7 sec 23:22 A1EN...
  • Page 358 BL702/704/706 Reference Manual 19.4.7 HBN_IRQ_STAT Address：0x4000f018 IRQSTATE IRQSTATE Name Type Reset Description Bits 31:0 IRQSTATE [22] acomp1 [20] acomp0 [18] brown-out [17] irq_pir state [16] irq_rtc state [4:0] hbn_pin_wakeup state (GPIO13 GPIO9) 19.4.8 HBN_IRQ_CLR Address：0x4000f01c IRQCLR IRQCLR Name Type Reset...
  • Page 359 BL702/704/706 Reference Manual 19.4.9 HBN_PIR_CFG Address：0x4000f020 RSVD RSVD CGEN RSVD PIRDIS RSVD HPFSEL SYNC Name Type Reset Description Bits 31:10 RSVD NOSYNC gpadc no sync CGEN gpadc force cgen=1 PIREN pir enable RSVD PIRDIS pir disable [4] low -> high won’t trigger interrupt [5] high ->...
  • Page 360 BL702/704/706 Reference Manual 19.4.11 HBN_PIR_INTERVAL Address：0x4000f028 RSVD RSVD PIRINTERV Name Type Reset Description Bits 31:12 RSVD 11:0 PIRINTERV 12’d2621 pir_lpf_sel = 0: 32768 / (pir_interval+1) Hz, default 12.5Hz ( 80ms) pir_lpf_sel = 1: 32768 / (pir_interval*2+1) Hz, default 6.25Hz ( 160ms) 19.4.12 HBN_MISC...
  • Page 361 BL702/704/706 Reference Manual Name Type Reset Description Bits 23:22 RSVD 21:16 PULLUPAON 6’h0 [5] : 1 : Turn on Flash PAD PU (GPIO28), Only Set this bit when Flash @ Deep Power Down Mode [4] : 1 : Turn on Flash PAD PU (GPIO27), Only Set this bit...
  • Page 362 BL702/704/706 Reference Manual Name Type Reset Description Bits 27:24 RTIDOVEC 4’ha ldo output voltage external control: 0:0.60V, 1:0.65V, 2:0.70V, 3:0.75V, 4:0.80V, 5:0.85V, 6:0.9V, 7:0.95V 8:1.0V, 9:1.05V, 10:1.1V, 11:1.15V, 12:1.2V, 13:1.25V, 14:1.3V, 15:1.35V 23:20 RSVD 19:16 V11SOVSEL 4’hA vdd11soc output voltage selection...
  • Page 363 BL702/704/706 Reference Manual 19.5 Register description Description Name PDS_CTL PDS control register PDS_TIME1 PDS sleep time PDS_INT PDS interrupt PDS_CTL2 PDS control register 2 PDS_CTL3 PDS control register 3 PDS_CTL4 PDS control register 4 pds_stat PDS state pds_ram1 PDS ram control...
  • Page 364 BL702/704/706 Reference Manual Name Type Reset Description Bits 29:28 CTRLRF 2’b01 00 : PDS don’t control RF on/off 01 : PDS control RF on/off depend on soc_en 10 : PDS control RF on/off depend on BLE power on/off 11 : PDS control RF on/off whe pds at idle state...
  • Page 365 BL702/704/706 Reference Manual Name Type Reset Description Bits GATECLK 0 : don’ t_touch clock gating during PDS (all power domain) 1 : gate clock during PDS (each pwr domain has its own control) CPFS 0 : don’’t touch Flash power during all PDS (Flash Power...
  • Page 366 BL702/704/706 Reference Manual 19.5.3 PDS_INT Address：0x4000e00c WUEV WUSEN INCL RSVD PDMS RDMS RSVD WUMS CRSE RSEV PDIT RDIT RSVD WKIT Name Type Reset Description Bits 31:24 WUEV Record Wakeup resason, and be clear by cr_pds_int_clr [31]: wakeup trigger by kys_int...
  • Page 367 BL702/704/706 Reference Manual Name Type Reset Description Bits RSVD WKIT PDS Wakeup Interrupt 19.5.4 PDS_CTL2 Address：0x4000e010 RSVD FUSB RSVD GCLK GCLK GCLK FUSB RSVD FUSB FBZP RSVD FUSB RSVD FUSB RSVD MSLP MSLP MSLP PRST ISEN ISEN ISEN PWOF PWOF...
  • Page 368 BL702/704/706 Reference Manual Name Type Reset Description Bits RSVD FNPPWOF manual force NP power off 19.5.5 PDS_CTL3 Address：0x4000e014 RSVD MSIS RSVD RSVD RSVD FBLE FMIS RSVD FBLE FMIS RSVD FBLE FMIS RSVD FBLE RSVD FBLE FMIS RSVD GCLK GCLK MSTB...
  • Page 369 BL702/704/706 Reference Manual Name Type Reset Description Bits RSVD FBLEISO manual force BZ_BLE iso_en RSVD FBLEPWOF manual force BZ_BLE pwr_off FMISPWOF manual force MISC pwr_off RSVD 19.5.6 PDS_CTL4 Address：0x4000e018 MISC MISC RSVD MISC MISC MISC MISC DPOF APOF GCLK MSTB...
  • Page 370 BL702/704/706 Reference Manual Name Type Reset Description Bits MISCPWOF 1 : make core_misc Power off at PDS Sleep state 0 : make core_misc power on at PDS Sleep state USBGCLK 1 : make usb clock gated at PDS Sleep state...
  • Page 371 BL702/704/706 Reference Manual 19.5.7 pds_stat Address：0x4000e01c RSVD PLLSTA RSVD RFSTA RSVD Name Type Reset Description Bits 31:18 RSVD 17:16 PLLSTA 2’b00 ST_PDS_PLL_OFF = 2’b00 ; ST_PDS_PLL_SFREG = 2’b01 ; ST_PDS_PLL_PU = 2’b10 ; ST_PDS_PLL_RDY = 2’b11 ; 15:12 RSVD 11:8 RFSTA 4’b0...
  • Page 372 BL702/704/706 Reference Manual 19.5.8 pds_ram1 Address：0x4000e020 RSVD RSVD RAMPGEN RAMRET2N RAMRET1N Name Type Reset Description Bits 31:12 RSVD 11:8 RAMPGEN 4’h0 [3] : 48 64KB np_ram Low Power Enable [2] : 32 48KB np_ram Low Power Enable [1] : 16 32KB np_ram Low Power Enable...
  • Page 373 BL702/704/706 Reference Manual Name Type Reset Description Bits 31:30 RSVD 29:24 IO2823PU 6’h0 pu, pd 00 : no PD/PU/IE on PAD 01 : Pulldown PAD 10 : Pullup PAD 11 : Active IE [0] : PAD_GPIO_23 [1] : PAD_GPIO_24 ….
  • Page 374 BL702/704/706 Reference Manual Name Type Reset Description Bits IO2217PD 6’h0 pu, pd 00 : no PD/PU/IE on PAD 01 : Pulldown PAD 10 : Pullup PAD 11 : Active IE [0] : PAD_GPIO_17 [1] : PAD_GPIO_18 …. [5] : PAD_GPIO_22 19.5.10 pds_gpio_int...

  • Page 375: Document Revision History

    Revision history Table 20.1: Document revision history Date Revision Changes 2020/9/9 Initial release 2021/3/8 Modify the GPIO port corresponding to the DAC 2021/9/30 Update KeyScan register description, introduction of low-power wake-up source 375/ 375 @2021 Bouffalo Lab BL702/704/706 Reference Manual...

This manual is also suitable for:

Bl704Bl706

Table of Contents

Save PDF