User Manuals: Bouffalo Lab BL602 WiFi Bluetooth Module

User Manuals: Bouffalo Lab BL602 WiFi Bluetooth Module

Manuals and User Guides for Bouffalo Lab BL602 WiFi Bluetooth Module. We have 1 Bouffalo Lab BL602 WiFi Bluetooth Module manual available for free PDF download: Reference Manual

Bouffalo Lab BL602 Reference Manual

Bouffalo Lab BL602 Reference Manual (195 pages)

Brand: Bouffalo Lab | Category: Medical Equipment | Size: 2 MB

Table of Contents

Table of Contents

2
List of Figures

13
- Function Description
  16
- Introduction
  16
- Main Features
  16
- System and Memory Overview
  16
- Address Mapping
  17
- Bus Connection
  17
- Address Mapping
  18
- Interrupt Distribution
  18
- Interrupt Source
  18
- Interrupt Distribution
  19
- Introduction
  20
- Reset and Clock
  20
- Reset Source
  20
- Clock Source
  21
- Reset Source
  21
- Clock Block Diagram
  22
- Bus
  23
- Clock
  23
- Glb
  23
- GLB Function Description
  23
- Introduction
  23
- Reset
  23
- GPIO Function Description
  24
- GPIO Main Features
  24
- GPIO Overview
  24
- Memory
  24
- GPIO Basic Struct
  25
- GPIO Function
  25
- Pin Description
  26
- GPIO Output
  27
- Pin Description
  27
- GPIO Input
  28
- GPIO Interrupt
  28
- GPIO Optional Function
  28
- Register Description
  28
- Clk_Cfg0
  29
- Clk_Cfg2
  30
- Clk_Cfg3
  30
- Gpadc_32M_Src_Ctrl
  31
- Gpio_Cfgctl0
  32
- Gpio_Cfgctl1
  32
- Gpio_Cfgctl2
  33
- Gpio_Cfgctl3
  34
- Gpio_Cfgctl4
  35
- Gpio_Cfgctl5
  36
- Gpio_Cfgctl6
  37
- Gpio_Cfgctl7
  37
- Gpio_Cfgctl8
  38
- Gpio_Cfgctl9
  39
- Gpio_Cfgctl10
  40
- Gpio_Cfgctl11
  41
- Gpio_Cfgctl12
  42
- Gpio_Cfgctl13
  42
- Gpio_Cfgctl14
  43
- Adc
  45
- ADC Main Features
  45
- Introduction
  45
- ADC Block Diagram
  46
- ADC Functional Description
  46
- ADC Channel
  47
- ADC External Pins
  47
- ADC Internal Signals
  47
- ADC Pins and Internal Signals
  47
- ADC Clock
  48
- ADC Consequence
  49
- ADC Conversion Mode
  49
- ADC Interrupt
  50
- Meaning of ADC Conversion Result
  50
- Adc Fifo
  51
- DMA Architecture
  72
- LLI Architecture
  74
- L1C Architecture
  95
- Waydisable Settings
  96
- Cache Architecture
  97
- Nec Logical
  101
- Rc5 Logical
  101
- SPI Clock
  116
- SPI Ignore
  117
- UART Data
  127
- UART Clock
  128
- UART Sample
  129
- UART Fixed Character Mode
  130
- UART Flow Control
  131
- Pin Lists
  142
- I2C Stop/Start Condition
  143
- Master Rx and Slave Tx
  144
- Master Transmission
  144
- Master Tx and Slave Rx
  144
- Tx and Rx Together
  145
- Duty Cycle Parameters
  159
- Pwm
  159
- Timer Block Diagram
  174
- Watchdog Timer Block Diagram
  175
- Timer Preload
  176
- Watchdog Timing
  177
- Watchdog Alarm Mechanism
  178
- Document Revision History
  195

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