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Bouffalo Lab BL602 Reference Manual

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BL602/604
Reference Manual
version：1.2
copyright @ 2020
www.bouffalolab.com

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Summary of Contents for Bouffalo Lab BL602

  • Page 1 BL602/604 Reference Manual version：1.2 copyright @ 2020 www.bouffalolab.com...

  • Page 2: Table Of Contents

    GPIO input ....... . . 3.2.10 2/ 195 @2020 Bouffalo Lab BL602/604 Reference Manual...
  • Page 3 BL602/604 Reference Manual GPIO optional function ......3.2.11 GPIO interrupt ....... .
  • Page 4 BL602/604 Reference Manual ADC configuration process ......4.3.8 VBAT measurement ......
  • Page 5 BL602/604 Reference Manual ......6.3.4 Linked List Mode DMA interrupt ....... .
  • Page 6 BL602/604 Reference Manual DMA_C2LLI ....... . . 6.5.27 DMA_C2Control .......
  • Page 7 BL602/604 Reference Manual irtx_data_word1 ....... 8.4.4 irtx_pulse_width .......
  • Page 8 BL602/604 Reference Manual spi_int_sts ........9.4.2 spi_bus_busy ....... .
  • Page 9 BL602/604 Reference Manual uart_int_mask ....... . 10.4.9 10.4.10 uart_int_clear ....... .
  • Page 10 BL602/604 Reference Manual i2c_int_sts ........11.9.2 i2c_sub_addr ....... .
  • Page 11 BL602/604 Reference Manual 12.4.16 pwm2_thre2 ....... . . 12.4.17 pwm2_period ....... .
  • Page 12 BL602/604 Reference Manual TCR2 ........
  • Page 13 11.2 Master transmission ..........13/ 195 @2020 Bouffalo Lab BL602/604 Reference Manual...
  • Page 14 BL602/604 Reference Manual 11.3 Master tx and slave rx ..........
  • Page 15 14.1 Document revision history ......... . 15/ 195 @2020 Bouffalo Lab BL602/604 Reference Manual...

  • Page 16: System And Memory Overview

    • Off-chip memory Flash 1.3 Function description The BL602 bus connection and address access are summarized as follows: The bus master includes CPU, SDIO, DMA, encryption engine, and debug interface. The bus includes memory, peripherals, WiFi / BLE. Except the en- cryption engine can only access the memory, all other bus masters can access all bus slaves.

  • Page 17: Bus Connection

    BL602/604 Reference Manual Table 1.1: Bus connection SDIO encryption Debug Slave/Master engine interface memory Peripheral WiFi/BLE The address access mainly distinguishes ”memory” or ”peripheral” by [27:24], and the [31:28] bits can be ignored. The memory space is consecutive addresses 0x2008000 ~ 0x204BFFF (272KB SRAM), the read-only memory address is 0x1000000, and the deep sleep memory address is 0x0010000.

  • Page 18: Interrupt Source

    0x22008000 for access 0x21000000 128KB Read-only memory 1.4 Interrupt source BL602/BL604 contains a total of 18 interrupt sources. The interrupt sources and corresponding interrupt numbers are shown in the following table: Table 1.3: Interrupt distribution Interrupt source Description Number...

  • Page 19: Interrupt Distribution

    BL602/604 Reference Manual Table 1.3: Interrupt distribution Interrupt source Description Number TIMER TIMER_CH0 IRQ_NUM_BASE+36 Timer Channel 0 Interrupt TIMER_CH1 IRQ_NUM_BASE+37 Timer Channel 1 Interrupt TIMER_WDT IRQ_NUM_BASE+38 Watch Dog Interrupt GPIO GPIO_INT0 IRQ_NUM_BASE+44 GPIO Interrupt PDS_WAKEUP IRQ_NUM_BASE+50 PDS Wakeup Interrupt HBN_OUT0...

  • Page 20: Reset And Clock

    CPU part of the system – Retain necessary logic processing such as power management unit, perform chip system reset – Software module reset: Set software reset according to the requirements of specific modules 20/ 195 @2020 Bouffalo Lab BL602/604 Reference Manual...

  • Page 21: Clock Source

    BL602/604 Reference Manual EXT _RST _N ana_pwrst_n ana_powb ~pds_misc_rst wdt _rst_src_ ana_ext_pwr_rst_n Sync pwronrst_n reg_ctrl _pwron _rst reg_ctrl _cpu_reset cpu_porst_n Sync cpu_rst_n efuse_cpu_rst_dis ~pds_cpu_rst efuse_autoload_done ~pds_soc_rst Sync hreset_n reg_ctrl _sys_reset cpu_sys_rstreq_ Sync nwdt_hreset_n Figure 2.1: Reset source 2.3 Clock source Clock source contains: •...

  • Page 22: Clock Block Diagram

    BL602/604 Reference Manual 11bit f 32k_clk XTAL32K RC32K f32k_sel ir clk (~2MHz) general adc clk 96 MHz 6bit 6bit xtal_clk xclk pwm clk RC32M 16bit root_clk_sel[0] gpdac clk 512KHz i2c clk 8bit spi clk 5bit bclk bclk_div bclk_en flash clk...

  • Page 23: Glb

    Provide bus arbitration settings and bus error settings. You can set whether to generate an interrupt when a bus error occurs, and provide error bus address information to facilitate user debugging procedures. 23/ 195 @2020 Bouffalo Lab BL602/604 Reference Manual...

  • Page 24: Memory

    BL602/604 Reference Manual 3.2.4 Memory Provides the power management of each memory module in the low-power mode of the chip system, including two setting modes: • retention mode：In this mode, the data on the memory can be saved, but cannot be read or written until exiting the low power mode.

  • Page 25: Gpio Function

    BL602/604 Reference Manual • Floating output • Analog input optional function • Analog output optional function • Digital optional functions The basic block diagram of the GPIO module is shown below: analog input/ peripheral optional function input bus read ON/OFF...

  • Page 26: Pin Description

    BL602/604 Reference Manual The functions that GPIO can set include: • Flash/QSPI：set GPIO as QSPI function, can be connected to Flash as program storage / run medium • SPI: set GPIO as SPI function • I2C: set GPIO to I2C function •...

  • Page 27: Gpio Output

    BL602/604 Reference Manual Table 3.1: Pin description SDIO FLASH UART Analog SWGPIO JTAG GPIO GPIO17 MOSI SIG1 DC_TP_OUT SWGPIO17 GPIO18 SIG2 SWGPIO18 GPIO19 SCLK SIG3 SWGPIO19 GPIO20 MISO SIG4 SWGPIO20 GPIO21 MOSI SIG5 SWGPIO21 GPIO22 CLK_OUT SIG6 SWGPIO22 In the above table, when the UART function is selected, only one signal of the UART is selected, and the specific function of the pin is not specified (such as UART TX or UART RX).

  • Page 28: Gpio Input

    BL602/604 Reference Manual 3.2.10 GPIO input Set func_sel to SWGPIO, set ie to 1, and oe to 0. The user can configure the GPIO as an input function, set whether to enable the Schmitt trigger through the smt control bit, and set the pull-down property through the pd, pu control bit.

  • Page 29: Clk_Cfg0

    BL602/604 Reference Manual Description Name GPIO_CFGCTL0 GPIO0, GPIO1 configuration GPIO_CFGCTL1 GPIO2, GPIO3 configuration GPIO_CFGCTL2 GPIO4, GPIO5 configuration GPIO_CFGCTL3 GPIO6, GPIO7 configuration GPIO_CFGCTL4 GPIO8, GPIO9 configuration GPIO_CFGCTL5 GPIO10, GPIO11 configuration GPIO_CFGCTL6 GPIO12, GPIO13 configuration GPIO_CFGCTL7 GPIO14, GPIO15 configuration GPIO_CFGCTL8 GPIO16, GPIO17 configuration...

  • Page 30: Clk_Cfg2

    BL602/604 Reference Manual Name Type Reset Description Bits RCSEL root clock selection from HBN (0: RC32M 1: XTAL 2/3: PLL others) PLLSEL pll clock selection (0: 48MHz 1: 120MHz 2: 160MHz 3: 192MHz) RSVD 3.3.2 clk_cfg2 Address：0x40000008 DMAEN RSVD RSVD...

  • Page 31: Gpadc_32M_Src_Ctrl

    BL602/604 Reference Manual RSVD I2CDIV RSVD RSVD SPIDIV Name Type Reset Description Bits 31:25 RSVD I2CEN I2C Master Clock Out Enable 23:16 I2CDIV 8’d255 I2C Master Clock Out Divider (Freq_of_BCLK/(N+1)) 15:9 RSVD SPIEN SPI Clock Enable (Default : Enable) RSVD SPIDIV 5’d3...

  • Page 32: Gpio_Cfgctl0

    BL602/604 Reference Manual 3.3.5 GPIO_CFGCTL0 Address：0x40000100 RSVD GP1FUNC RSVD GP1DRV RSVD GP0FUNC RSVD GP0DRV Name Type Reset Description Bits 31:28 RSVD 27:24 GP1FUNC 4’h1 GPIO Function Select (Default : SDIO) 23:22 RSVD GP1PD GPIO Pull Down Control GP1PU GPIO Pull Up Control...

  • Page 33: Gpio_Cfgctl2

    BL602/604 Reference Manual RSVD GP3FUNC RSVD GP3DRV RSVD GP2FUNC RSVD GP2DRV Name Type Reset Description Bits 31:28 RSVD 27:24 GP3FUNC 4’h1 GPIO Function Select (Default : SDIO) 23:22 RSVD GP3PD GPIO Pull Down Control GP3PU GPIO Pull Up Control 19:18...

  • Page 34: Gpio_Cfgctl3

    BL602/604 Reference Manual Name Type Reset Description Bits 31:28 RSVD 27:24 GP5FUNC 4’h1 GPIO Function Select (Default : SDIO) 23:22 RSVD GP5PD GPIO Pull Down Control GP5PU GPIO Pull Up Control 19:18 GP5DRV GPIO Driving Control GP5SMT GPIO SMT Control...

  • Page 35: Gpio_Cfgctl4

    BL602/604 Reference Manual Name Type Reset Description Bits 19:18 GP7DRV GPIO Driving Control GP7SMT GPIO SMT Control GP7IE GPIO Input Enable 15:12 RSVD 11:8 GP6FUNC 4’hB GPIO Function Select (Default : SWGPIO ) RSVD GP6PD GPIO Pull Down Control GP6PU...

  • Page 36: Gpio_Cfgctl5

    BL602/604 Reference Manual Name Type Reset Description Bits RSVD GP8PD GPIO Pull Down Control GP8PU GPIO Pull Up Control GP8DRV GPIO Driving Control GP8SMT GPIO SMT Control GP8IE GPIO Input Enable 3.3.10 GPIO_CFGCTL5 Address：0x40000114 RSVD GP11FUNC RSVD GP11 GP11 GP11DRV...

  • Page 37: Gpio_Cfgctl6

    BL602/604 Reference Manual Name Type Reset Description Bits GP10IE GPIO Input Enable 3.3.11 GPIO_CFGCTL6 Address：0x40000118 RSVD GP13FUNC RSVD GP13 GP13 GP13DRV GP13 GP13 RSVD GP12FUNC RSVD GP12 GP12 GP12DRV GP12 GP12 Name Type Reset Description Bits 31:28 RSVD 27:24 GP13FUNC 4’hB...

  • Page 38: Gpio_Cfgctl8

    BL602/604 Reference Manual RSVD GP15FUNC RSVD GP15 GP15 GP15DRV GP15 GP15 RSVD GP14FUNC RSVD GP14 GP14 GP14DRV GP14 GP14 Name Type Reset Description Bits 31:28 RSVD 27:24 GP15FUNC 4’hB GPIO Function Select (Default : SWGPIO ) 23:22 RSVD GP15PD GPIO Pull Down Control...

  • Page 39: Gpio_Cfgctl9

    BL602/604 Reference Manual Name Type Reset Description Bits 31:28 RSVD 27:24 GP17FUNC 4’hE GPIO Function Select (Default : JTAG ) 23:22 RSVD GP17PD GPIO Pull Down Control GP17PU GPIO Pull Up Control 19:18 GP17DRV GPIO Driving Control GP17SMT GPIO SMT Control...

  • Page 40: Gpio_Cfgctl10

    BL602/604 Reference Manual Name Type Reset Description Bits 19:18 GP19DRV GPIO Driving Control GP19SMT GPIO SMT Control GP19IE GPIO Input Enable 15:12 RSVD 11:8 GP18FUNC 4’hB GPIO Function Select (Default : SWGPIO ) RSVD GP18PD GPIO Pull Down Control GP18PU...

  • Page 41: Gpio_Cfgctl11

    BL602/604 Reference Manual Name Type Reset Description Bits RSVD GP20PD GPIO Pull Down Control GP20PU GPIO Pull Up Control GP20DRV GPIO Driving Control GP20SMT GPIO SMT Control GP20IE GPIO Input Enable 3.3.16 GPIO_CFGCTL11 Address：0x4000012c RSVD GP23FUNC RSVD GP23 GP23 GP23DRV...

  • Page 42: Gpio_Cfgctl12

    BL602/604 Reference Manual Name Type Reset Description Bits GP22IE GPIO Input Enable 3.3.17 GPIO_CFGCTL12 Address：0x40000130 RSVD GP25FUNC RSVD GP25 GP25 GP25DRV GP25 GP25 RSVD GP24FUNC RSVD GP24 GP24 GP24DRV GP24 GP24 Name Type Reset Description Bits 31:28 RSVD 27:24 GP25FUNC 4’hB...

  • Page 43: Gpio_Cfgctl14

    BL602/604 Reference Manual RSVD GP27FUNC RSVD GP27 GP27 GP27DRV GP27 GP27 RSVD GP26FUNC RSVD GP26 GP26 GP26DRV GP26 GP26 Name Type Reset Description Bits 31:28 RSVD 27:24 GP27FUNC 4’hB GPIO Function Select (Default : SWGPIO ) 23:22 RSVD GP27PD GPIO Pull Down Control...
  • Page 44 BL602/604 Reference Manual Name Type Reset Description Bits 31:6 RSVD GP28PD GPIO Pull Down Control GP28PU GPIO Pull Up Control GP28DRV GPIO Driving Control GP28SMT GPIO SMT Control GP28IE GPIO Input Enable BL602/604 Reference Manual 44/ 195 @2020 Bouffalo Lab...

  • Page 45: Adc

    – Two input modes: single-ended and differential – Support jitter compensation – User can set conversion result offset value – Scanning mode supports up to 1M, non-scanning mode is 2M • Analog channels – 12 external analog channels 45/ 195 @2020 Bouffalo Lab BL602/604 Reference Manual...

  • Page 46: Adc Functional Description

    BL602/604 Reference Manual – 2 DAC internal channels – 1 VBAT / 2 channel – 1 TSEN channel 4.3 ADC functional description The basic block diagram of the ADC is shown below. VDD33(1.7~3.6V) IVBIAS Pga_gain REF_gen Pos/neg_sel Diff/single Scan Data_final[25:0]...

  • Page 47: Adc Pins And Internal Signals

    BL602/604 Reference Manual pushed into the FIFO. 4.3.1 ADC pins and internal signals Table 4.1: ADC internal signals Internal Signal type Description signals VBAT/2 Input Voltage signal divided from the power pin TSEN Input Internal temperature sensor output voltage VREF...

  • Page 48: Adc Clock

    BL602/604 Reference Manual • ADC CH7 • ADC CH8 • ADC CH9 • ADC CH10 • ADC CH11 • DAC OUTA • DAC OUTB • VBAT/2 • TSEN • VREF • GND It should be noted that if VBAT/2 or TSEN is selected as the input signal to be acquired, gpadc_vbat_en or gpadc_- ts_en needs to be set.

  • Page 49: Adc Conversion Mode

    BL602/604 Reference Manual clock of the ADC module is 2M by default. Users can adjust the ADC’s clock source and various frequency division coefficients according to actual sampling requirements. The gpadc_32m_clk_div divider register width is 6 bits, and the maximum divider is 64. Frequency division formula: fout = fsource / (gpadc_32m_clk_div + 1).

  • Page 50: Adc Interrupt

    BL602/604 Reference Manual The gpadc_data_out register stores the ADC result. This result contains the ADC result, sign bit and channel infor- mation. The data format is as follows: Table 4.3: Meaning of ADC conversion result BitS 25 24 23 22...

  • Page 51: Adc Fifo

    BL602/604 Reference Manual When the interrupt is generated, the interrupt status can be queried by the gpadc_pos_satur, and gpadc_neg_satur registers, and the interrupt can be cleared by gpadc_pos_satur_clr and gpadc_neg_satur_clr. This function can be used to determine whether the input voltage is abnormal.
  • Page 52 BL602/604 Reference Manual Set GPIO according to the channel used According to the analog pin used, determine the channel number used, initialize the corresponding GPIO as an analog function. It should be noted that when setting the GPIO as an analog input, do not set the GPIO pull-up or pull-down, you need to set it to float.
  • Page 53 BL602/604 Reference Manual call it Temperature Sensor, referred to as TSEN. The test principle of TSEN is to generate a fitted curve by measuring the voltage difference ∆V generated by two different currents on a diode with temperature. Regardless of the measurement of the external or internal diode, the final output value is related to temperature, which can be expressed as ∆(ADC_out) = 7.753T + X.
  • Page 54 BL602/604 Reference Manual Description Name gpadc_reg_raw_result GPADC raw result register gpadc_reg_define GPADC define register 4.4.1 gpadc_config Address：0x40002000 RSVD FIFOTHL FIFODACN RSVD FURM FORM RDYM RSVD URCL ORCL RSVD FIFO FIFO FIFO FIFO FIFO FULL Name Type Reset Description Bits 31:24...
  • Page 55 BL602/604 Reference Manual Name Type Reset Description Bits FIFONE 1’b0 FIFO not empty flag FIFOCLR 1’b0 FIFO clear signal DMAEN 1’b0 GPADC DMA enbale 4.4.2 gpadc_dma_rdata Address：0x40002004 RSVD DMARDA DMARDA Name Type Reset Description Bits 31:26 RSVD 25:0 DMARDA 26’d0 GPADC finial conversion result stored in the FIFO 4.4.3 gpadc_reg_cmd...
  • Page 56 BL602/604 Reference Manual Name Type Reset Description Bits CSPU 1’b0 enable chip sensor test 1’b0: disable 1’b1: enable 26:24 RSVD MBEN 1’b0 micboost 32db enable 1’b0: 16dB 1’b1: 32dB 22:21 2’h0 mic_pga2_gain 2’h0: 0dB 2’h1: 6dB 2’h2: -6dB 2’h3: 12dB 1’b0...
  • Page 57 BL602/604 Reference Manual Name Type Reset Description Bits 12:8 POSSEL 5’hf select adc positive input in none-scan mode 5’h0 gpip_ch[0] 5’h1 gpip_ch[1] 5’h2 gpip_ch[2] 5’h3 gpip_ch[3] 5’h4 gpip_ch[4] 5’h5 gpip_ch[5] 5’h6 gpip_ch[6] 5’h7 gpip_ch[7] 5’h8 gpip_ch[8] 5’h9 gpip_ch[9] 5’h10 gpip_ch[10] 5’h11 gpip_ch[11]...
  • Page 58 BL602/604 Reference Manual 4.4.4 gpadc_reg_config1 Address：0x4000f910 RSVD V18SEL V11SEL DTEN SCEN SCLEN CDRD CAIV RSVD RSVD RSSEL CTCV OCEN Name Type Reset Description Bits RSVD 30:29 V18SEL 2’h0 internal vdd18 select 28:27 V11SEL 2’h0 internal vdd11 select DTEN 1’h0 Dither compensation enable SCEN 1’h0...
  • Page 59 BL602/604 Reference Manual Name Type Reset Description Bits 24:21 SCLEN 4’h0 select scan mode length 4’b0000 : select gpadc_scan_pos_0 and gpadc_scan_- neg_0 4’b0001 : select gpadc_scan_pos_1 and gpadc_scan_- neg_1 4’b0010 : select gpadc_scan_pos_2 and gpadc_scan_- neg_2 4’b0011 : select gpadc_scan_pos_3 and gpadc_scan_- neg_3 4’b0100 : select gpadc_scan_pos_4 and gpadc_scan_-...
  • Page 60 BL602/604 Reference Manual Name Type Reset Description Bits RSSEL 3’h0 adc resolution/over-sample rate select 3’b000 12bit 2MS/s, OSR=1 3’b001 14bit 125kS/s, OSR=16 3’b010 14bit 31.25kS/s, OSR=64 3’b011 16bit 15.625KS/s, OSR=128 (voice mode16KS/s) 3’b100 16bit 7.8125KS/s, OSR=256 (voice mode 8KS/s) CTCV 1’b1...
  • Page 61 BL602/604 Reference Manual Name Type Reset Description Bits ATEN 1’b0 Analog test enable. BSEL 1’b0 adc analog portion low power mode select 1’h0: Full biasing current 1’h1: Half biasing current 16:15 2’h3 2’b11 all off 2’b11 Vref AZ on 2’b11 Vref AZ and PGA chop on 2’b11 Vref AZ and PGA chop+RPC on...
  • Page 62 BL602/604 Reference Manual Name Type Reset Description Bits 31:30 RSVD 29:25 SCANP5 5’hf definition is the same as adc_reg_cmd.adc_pos_sel 24:20 SCANP4 5’hf definition is the same as adc_reg_cmd.adc_pos_sel 19:15 SCAN3 5’hf definition is the same as adc_reg_cmd.adc_pos_sel 14:10 SCANP2 5’hf definition is the same as adc_reg_cmd.adc_pos_sel...
  • Page 63 BL602/604 Reference Manual Name Type Reset Description Bits 31:30 RSVD 29:25 SCANN5 5’hf definition is the same as adc_reg_cmd.adc_neg_sel 24:20 SCANN4 5’hf definition is the same as adc_reg_cmd.adc_neg_sel 19:15 SCAN3 5’hf definition is the same as adc_reg_cmd.adc_neg_sel 14:10 SCANN2 5’hf definition is the same as adc_reg_cmd.adc_neg_sel...
  • Page 64 BL602/604 Reference Manual Name Type Reset Description Bits 31:1 RSVD DRDY 1’b0 ADC final conversion data ready 4.4.11 gpadc_reg_isr Address：0x4000f92c RSVD RSVD RSVD RSVD Name Type Reset Description Bits 31:10 RSVD 1’h0 write 1 mask 1’h0 write 1 mask RSVD 1’b0...
  • Page 65 BL602/604 Reference Manual Name Type Reset Description Bits 25:0 DATAOUT 26’h1EF0000 ADC finial conversion result data, after calibration and signed/unsigned process 4.4.13 gpadc_reg_raw_result Address：0x4000f934 RSVD RSVD RAWDATA Name Type Reset Description Bits 31:12 RSVD 11:0 RAWDATA 12’h0 ADC Raw data 4.4.14 gpadc_reg_define...
  • Page 66 • Support dual channel playback DMA transport mode • The output pin of DAC is fixed to ChannelA as GPIO13, Channel as GPIO14 5.3 Function description The basic block diagram of the DAC module is shown in the figure. 66/ 195 @2020 Bouffalo Lab BL602/604 Reference Manual...
  • Page 67 BL602/604 Reference Manual • DAC module supports up to two modulation outputs • DAC module supports dual-channel DMA data transfer mode • DAC module supports a DMA data interface with a length of 32-bit, in which the high 16 bits will be modulated on the pins of ChannelA, and the low 16 bits will be modulated on the pins of ChannelB 5.4 Register description...
  • Page 68 BL602/604 Reference Manual RSVD CHBSEL CHASEL RSVD MODE RSVD DSMMODE RSVD Name Type Reset Description Bits 31:24 RSVD 23:20 CHBSEL Channel B Source Select 0: Reg 1: DMA 2: DMA + Filter 3: Sin Gen 4: A (The same as channel A)
  • Page 69 BL602/604 Reference Manual Name Type Reset Description Bits 31:6 RSVD DMAFM DMA TX format (Data 12-bit) 0: A0, A1, A2… 1: B0,A0, B1,A1, B2,A2… 2: A1,A0, A3,A2, A5,A4… (Note: 20’h0,[11:0] or 4’h0,[27:16],4’h0,[11:0]) RSVD DMATXEN GPDAC DMA TX enable 5.4.3 gpdac_dma_wdata Address：0x40002048...
  • Page 70 – DMA flow control, source memory, target peripheral – DMA flow control, source peripheral, target memory – DMA flow control, source peripheral, target peripheral – Target peripheral process control, source peripheral, target peripheral 70/ 195 @2020 Bouffalo Lab BL602/604 Reference Manual...
  • Page 71 BL602/604 Reference Manual – Target peripheral process control, source memory, target peripheral – Source peripheral process control, source peripheral, target memory – Source peripheral process control, source peripheral, target peripheral • Support LLI linked list function to improve DMA efficiency 6.3 DMA functional description...

  • Page 72: Dma Architecture

    BL602/604 Reference Manual DMA Controller DMA_Channel0 REQ0 REQ1 «« FIFO «« REQ31 DMA_Channel1 REQ0 REQ1 «« FIFO «« REQ31 AHB Master DMA_Channe2 REQ0 REQ1 «« FIFO «« REQ31 DMA_Channe3 REQ0 REQ1 AHB slave «« FIFO AHB Slave Programming «« REQ31 Figure 6.1: DMA architecture...
  • Page 73 BL602/604 Reference Manual 6.3.2 DMA channel configuration DMA supports 4 channels in total, each channel does not interfere with each other and can run at the same time. The following is the configuration process of DMA channel x: 1. Set 32-bit source address in DMA_C0SrcAddr register 2.

  • Page 74: Lli Architecture

    BL602/604 Reference Manual 2. Set the value of the DMA_C0Config [DSTPH] bit to 10, that is, set the Destination peripheral to SPI_RX ADC0/1 uses DMA to transfer data The configuration is as follows: 1. Set the value of the DMA_C0Config [SRCPH] bit to 22/23, that is, set the Source peripheral to GPADC0 / GPADC1 6.3.4 Linked List Mode...
  • Page 75 BL602/604 Reference Manual 6.3.5 DMA interrupt • DMA_INT_TCOMPLETED – Data transmission completed interrupt. When a data transmission is completed, this interrupt will be entered. • DMA_INT_ERR – Data transmission error interrupt, when an error occurs during data transmission, this interrupt will be entered 6.4 Transmission mode...
  • Page 76 BL602/604 Reference Manual peripheral mode 4. Set the value of the corresponding bit in the DMA_C0Control register: set the DI and SI bits to 1 to enable the automatic address accumulation mode, the DTW and STW bits set the transmission width of the source and destination, and the DBS and SBS bits set the burst type of the source and destination 5.
  • Page 77 BL602/604 Reference Manual Description Name DMA_SoftSReq Software single request DMA_SoftLBReq Software last burst request DMA_SoftLSReq Software last single request DMA_Config DMA general configuration DMA_Sync DMA request asynchronous setting DMA_C0SrcAddr Channel DMA source address DMA_C0DstAddr Channel DMA Destination address DMA_C0LLI Channel DMA link list...
  • Page 78 BL602/604 Reference Manual RSVD RSVD INTSTA Name Type Reset Description Bits 31:8 RSVD INTSTA Status of the DMA interrupts after masking 6.5.2 DMA_IntTCStatus Address：0x4000c004 RSVD RSVD INTTCSTA Name Type Reset Description Bits 31:8 RSVD INTTCSTA Interrupt terminal count request status 6.5.3 DMA_IntTCClear...
  • Page 79 BL602/604 Reference Manual 6.5.4 DMA_IntErrorStatus Address：0x4000c00c RSVD RSVD Name Type Reset Description Bits 31:8 RSVD Interrupt error status 6.5.5 DMA_IntErrClr Address：0x4000c010 RSVD RSVD Name Type Reset Description Bits 31:8 RSVD Interrupt error clear 6.5.6 DMA_RawIntTCStatus Address：0x4000c014 RSVD RSVD SOTCIPTM Name...
  • Page 80 BL602/604 Reference Manual Name Type Reset Description Bits 6.5.7 DMA_RawIntErrorStatus Address：0x4000c018 RSVD RSVD SOTEIPTM Name Type Reset Description Bits 31:8 RSVD SOTEIPTM Status of the error interrupt prior to masking 6.5.8 DMA_EnbldChns Address：0x4000c01c RSVD RSVD Name Type Reset Description Bits...
  • Page 81 BL602/604 Reference Manual Name Type Reset Description Bits 31:0 Software burst request 6.5.10 DMA_SoftSReq Address：0x4000c024 Name Type Reset Description Bits 31:0 Software single request 6.5.11 DMA_SoftLBReq Address：0x4000c028 SLBR SLBR Name Type Reset Description Bits 31:0 SLBR Software last burst request 6.5.12 DMA_SoftLSReq...
  • Page 82 BL602/604 Reference Manual Name Type Reset Description Bits 31:0 SLSR Software last single request 6.5.13 DMA_Config Address：0x4000c030 RSVD RSVD SDMA Name Type Reset Description Bits 31:2 RSVD AHBMEC AHB Master endianness configuration: 0 = little-endian, 1 = big-endian SDMAEN SMDMA Enable.
  • Page 83 BL602/604 Reference Manual DMASA DMASA Name Type Reset Description Bits 31:0 DMASA DMA source address 6.5.16 DMA_C0DstAddr Address：0x4000c104 DMADA DMADA Name Type Reset Description Bits 31:0 DMADA DMA Destination address 6.5.17 DMA_C0LLI Address：0x4000c108 FLLI FLLI Name Type Reset Description Bits...
  • Page 84 BL602/604 Reference Manual PROTECT RSVD IMTM MODE Name Type Reset Description Bits TCIEN Terminal count interrupt enable bit. It controls whether the current LLI is expected to trigger the terminal count inter- rupt. 30:28 PROTECT Protection. Destination increment. When set, the Destination address is incremented after each transfer.
  • Page 85 BL602/604 Reference Manual Name Type Reset Description Bits 29:20 LLICOUNT LLI counter. Increased 1 each LLI run. Cleared 0 when config Control. RSVD HALT Halt: 0 = enable DMA requests, 1 = ignore subsequent source DMA requests. ACTIVE Active: 0 = no data in FIFO of the channel, 1 = FIFO of the channel has data.
  • Page 86 BL602/604 Reference Manual Name Type Reset Description Bits 31:0 SRCADDR DMA source address 6.5.21 DMA_C1DstAddr Address：0x4000c204 DSTADDR DSTADDR Name Type Reset Description Bits 31:0 DSTADDR DMA Destination address 6.5.22 DMA_C1LLI Address：0x4000c208 RSVD Name Type Reset Description Bits 31:2 First linked list item. Bits [1:0] must be 0.
  • Page 87 BL602/604 Reference Manual Name Type Reset Description Bits Terminal count interrupt enable bit. It controls whether the current LLI is expected to trigger the terminal count inter- rupt. 30:28 PROT Protection. Destination increment. When set, the Destination address is incremented after each transfer.
  • Page 88 BL602/604 Reference Manual Name Type Reset Description Bits 13:11 FLOWCTRL 000: Memory-to-memory (DMA) 001: Memory-to-peripheral (DMA) 010: Peripheral-to-memory (DMA) 011: Source peripheral-to-Destination peripheral (DMA) 100: Source peripheral-to-Destination peripheral (Destina- tion peripheral) 101: Memory-to-peripheral (peripheral) 110: Peripheral-to-memory (peripheral) 111: Source peripheral-to-Destination peripheral (Source...
  • Page 89 BL602/604 Reference Manual DSTADDR DSTADDR Name Type Reset Description Bits 31:0 DSTADDR DMA Destination address 6.5.27 DMA_C2LLI Address：0x4000c308 RSVD Name Type Reset Description Bits 31:2 First linked list item. Bits [1:0] must be 0. RSVD 6.5.28 DMA_C2Control Address：0x4000c30c PROT RSVD...
  • Page 90 BL602/604 Reference Manual Name Type Reset Description Bits Source increment. When set, the source address is incre- mented after each transfer. 25:24 RSVD 23:21 DWIDTH 3’b010 Destination transfer width: 8/16/32 20:18 SWIDTH 3’b010 Source transfer width: 8/16/32 17:15 DBSIZE 3’b001...
  • Page 91 BL602/604 Reference Manual Name Type Reset Description Bits 13:11 FLOWCTRL 000: Memory-to-memory (DMA) 001: Memory-to-peripheral (DMA) 010: Peripheral-to-memory (DMA) 011: Source peripheral-to-Destination peripheral (DMA) 100: Source peripheral-to-Destination peripheral (Destina- tion peripheral) 101: Memory-to-peripheral (peripheral) 110: Peripheral-to-memory (peripheral) 111: Source peripheral-to-Destination peripheral (Source...
  • Page 92 BL602/604 Reference Manual DSTADDR DSTADDR Name Type Reset Description Bits 31:0 DSTADDR DMA Destination address 6.5.32 DMA_C3LLI Address：0x4000c408 RSVD Name Type Reset Description Bits 31:2 First linked list item. Bits [1:0] must be 0. RSVD 6.5.33 DMA_C3Control Address：0x4000c40c PROT RSVD...
  • Page 93 BL602/604 Reference Manual Name Type Reset Description Bits Source increment. When set, the source address is incre- mented after each transfer. 25:24 RSVD 23:21 DWIDTH 3’b010 Destination transfer width: 8/16/32 20:18 SWIDTH 3’b010 Source transfer width: 8/16/32 17:15 DBSIZE 3’b001...
  • Page 94 BL602/604 Reference Manual Name Type Reset Description Bits 13:11 FLOWCTRL 000: Memory-to-memory (DMA) 001: Memory-to-peripheral (DMA) 010: Peripheral-to-memory (DMA) 011: Source peripheral-to-Destination peripheral (DMA) 100: Source peripheral-to-Destination peripheral (Destina- tion peripheral) 101: Memory-to-peripheral (peripheral) 110: Peripheral-to-memory (peripheral) 111: Source peripheral-to-Destination peripheral (Source...

  • Page 95: L1C Architecture

    Flash, the waiting time represents wasteful time. The L1C cache can be used as a lubricating role between the processor and the Flash to improve the efficiency of the processor. 95/ 195 @2020 Bouffalo Lab BL602/604 Reference Manual...

  • Page 96: Waydisable Settings

    BL602/604 Reference Manual 7.2 Main features • 4-way Set-Associative mapping • Variable cache size • Connect to TCM address space, can easily configure L1C space as TCM space • Support cache performance statistics 7.3 Function description 7.3.1 Mutual conversion between TCM and Cache RAM resources...

  • Page 97: Cache Architecture

    BL602/604 Reference Manual index offset valid Word 3 Word 2 Word 1 Word 0 Figure 7.2: Cache architecture Each set of associative mapping caches contains two parts, the first is a tag, which contains the valid value and the address mapping relationship. The second part is data storage. When the processor accesses the cache, the cache processor compares the relationship between the address and the tag.
  • Page 98 BL602/604 Reference Manual 7.4.1 l1c_config Address：0x40009000 RSVD RSVD WAYDIS RSVD ABLE Name Type Reset Description Bits 31:12 RSVD 11:8 WAYDIS 4’b1111 Disable part of cache ways & used as ITCM RSVD CNTEN Cache performance counter enable CACABLE Cachable region enable 7.4.2 hit_cnt_lsb...
  • Page 99 BL602/604 Reference Manual Name Type Reset Description Bits 31:0 CNTMSB total hit count = hit_cnt_msb*23̂ 2 + hit_cnt_lsb 7.4.4 miss_cnt Address：0x4000900c MISSCNT MISSCNT Name Type Reset Description Bits 31:0 MISSCNT Miss counter BL602/604 Reference Manual 99/ 195 @2020 Bouffalo Lab...
  • Page 100 • Programmable carrier frequency and duty cycle • The maximum operating frequency is 32MHz 8.3 Function description 8.3.1 Fixed receiving protocol IR receiver supports two fixed protocols, NEC protocol and RC-5 protocol. • NEC protocol 100/ 195 @2020 Bouffalo Lab BL602/604 Reference Manual...

  • Page 101: Nec Logical

    BL602/604 Reference Manual The logic 1 and logic 0 waveforms of the NEC protocol are shown in the following figure: Logical”1” Logical”0” 560us 560us 560us 2.25ms 1.12ms Figure 8.1: nec logical Logic 1 is 2.25ms, pulse time is 560us; logic 0 bit is 1.12ms, pulse time is 560us.
  • Page 102 BL602/604 Reference Manual bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit9 bit10 bit11 bit12 bit13 bit14 “1” “1” “0” “0” “1” “0” “1” “1” “1” “0” “1” “0” “1” “0” Address Command Start bits always“1” Figure 8.4: rc5 The first two bits are the start bit, fixed to logic 1, and the third bit is the flip bit. When a key value is issued and then pressed, the bit will be inverted.
  • Page 103 BL602/604 Reference Manual 8.3.5 Carrier modulation Setting the upper 16 bits of the IRTX_PULSE_WIDTH register can generate carriers with different frequencies and duty cycles. The <TXMPH1W> bit in this register sets the width of carrier phase 1, and the <TXMPH0W> bit sets the width of carrier phase 0.
  • Page 104 BL602/604 Reference Manual Description Name irrx_data_word0 IR RX data word0 irrx_data_word1 IR RX data word1 irrx_swm_fifo_config_0 IR RX FIFO configuration irrx_swm_fifo_rdata IR RX software mode pulse width data 8.4.1 irtx_config Address：0x4000a600 RSVD TXDATANU TXDATANU TPHL TXTP RSVD TXL1 TXL0 TXDA...
  • Page 105 BL602/604 Reference Manual Name Type Reset Description Bits TXMDEN 1’b0 Enable signal of output modulation TXOEN 1’b0 Output inverse signal 1’b0: Output stays at Low during idle state 1’b1: Output stays at High during idle state TXEN 1’b0 Enable signal of IRTX function...
  • Page 106 BL602/604 Reference Manual TXDW0 TXDW0 Name Type Reset Description Bits 31:0 TXDW0 32’h0 TX data word 0 (Don’t care if SWM is enabled) 8.4.4 irtx_data_word1 Address：0x4000a60c TXDW1 TXDW1 Name Type Reset Description Bits 31:0 TXDW1 32’h0 TX data word 1 (Don’t care if SWM is enabled) 8.4.5 irtx_pulse_width...
  • Page 107 BL602/604 Reference Manual 8.4.6 irtx_pw Address：0x4000a614 TXTPH1W TXTPH0W TXHPH1W TXHPH0W TXL1PH1W TXL1PH0W TXL0PH1W TXL0PH0WS Name Type Reset Description Bits 31:28 TXTPH1W 4’d0 Pulse width of tail pulse phase 1 (Don’t care if SWM is en- abled) 27:24 TXTPH0W 4’d0 Pulse width of tail pulse phase 0 (Don’t care if SWM is en-...
  • Page 108 BL602/604 Reference Manual Name Type Reset Description Bits 31:0 TXSWPW0 32’h0 IRTX Software Mode pulse width data #0 #7, each pulse is represented by 4-bit ([3:0] is the 1st pulse, [7:4] is the 2nd pulse, [11:8] is the 3rd pulse, etc) 8.4.8 irtx_swm_pw_1...
  • Page 109 BL602/604 Reference Manual 8.4.10 irtx_swm_pw_3 Address：0x4000a64c TXSWPW3 TXSWPW3 Name Type Reset Description Bits 31:0 TXSWPW3 32’h0 IRTX Software Mode pulse width data #24 #31, each pulse is represented by 4-bit ([3:0] is the 1st pulse, [7:4] is the 2nd pulse, [11:8] is the 3rd pulse, etc) 8.4.11 irtx_swm_pw_4...
  • Page 110 BL602/604 Reference Manual Name Type Reset Description Bits 31:0 TXSWPW5 32’h0 IRTX Software Mode pulse width data #40 #47, each pulse is represented by 4-bit ([3:0] is the 1st pulse, [7:4] is the 2nd pulse, [11:8] is the 3rd pulse, etc) 8.4.13 irtx_swm_pw_6...
  • Page 111 BL602/604 Reference Manual 8.4.15 irrx_config Address：0x4000a680 RSVD RSVD RXDEGCNT RSVD RXDG RXMODE RXIN RXEN Name Type Reset Description Bits 31:12 RSVD 11:8 RXDEGCNT 4’d0 De-glitch function cycle count RSVD RXDGEN 1’b0 Enable signal of IRRX input de-glitch function RXMODE 2’d0...
  • Page 112 BL602/604 Reference Manual Name Type Reset Description Bits 23:17 RSVD RXECLR 1’b0 Interrupt clear of irrx_end_int 15:9 RSVD RXEMASK 1’b1 Interrupt mask of irrx_end_int RSVD RXEINT 1’b0 IRRX transfer end interrupt 8.4.17 irrx_pw_config Address：0x4000a688 RXETH RXDATH Name Type Reset Description...
  • Page 113 BL602/604 Reference Manual 8.4.19 irrx_data_word0 Address：0x4000a694 RXDAW0 RXDAW0 Name Type Reset Description Bits 31:0 RXDAW0 32’h0 RX data word 0 8.4.20 irrx_data_word1 Address：0x4000a698 RXDAW1 RXDAW1 Name Type Reset Description Bits 31:0 RXDAW1 32’h0 RX data word 1 8.4.21 irrx_swm_fifo_config_0 Address：0x4000a6c0...
  • Page 114 BL602/604 Reference Manual Name Type Reset Description Bits RXFOF 1’b0 Overflow flag of RX FIFO, can be cleared by rx_fifo_clr RSVD RXFCLR 1’b0 Clear signal of RX FIFO 8.4.22 irrx_swm_fifo_rdata Address：0x4000a6c4 RSVD RXFRDA Name Type Reset Description Bits 31:16 RSVD...
  • Page 115 According to different clock phases and polarity settings, the SPI clock has four modes, which can be set by bit4 (CPOL) and bit5 (CPHA) of the SPI_CONFIG register. CPOL is used to determine the level of the SCK clock signal 115/ 195 @2020 Bouffalo Lab BL602/604 Reference Manual...

  • Page 116: Spi Clock

    BL602/604 Reference Manual when idle, CPOL = 0 means the idle level is low, and CPOL = 1 means the idle level is high. CPHA is used to determine the sampling time. CPHA = 0 samples on the first clock edge of each cycle, and CPHA = 1 samples on the second clock edge of each cycle.

  • Page 117: Spi Ignore

    BL602/604 Reference Manual Address Opcode Dummy Byte High-Impedance State Figure 9.2: SPI ignore In the figure above, the start bit of the filter is set to 0, the end bit is set to 7, the dummy byte is received, and the end bit is set to 15, the dummy byte is discarded.
  • Page 118 BL602/604 Reference Manual is greater than its set threshold, a DMA request will be initiated , DMA will move data to TX FIFO or out of RX FIFO according to the setting. 9.3.8 SPI interrupt SPI has a variety of interrupt control, including the following interrupt modes: •...
  • Page 119 BL602/604 Reference Manual Description Name spi_fifo_rdata SPI FIFO read data 9.4.1 spi_config Address：0x4000a200 RSVD DEGCNT RSVD MCEN IGNR BYTE SCLK SCLK FSIZE Name Type Reset Description Bits 31:16 RSVD 15:12 DEGCNT 4’d0 De-glitch function cycle count DEGEN 1’b0 Enable signal of all input de-glitch function...
  • Page 120 BL602/604 Reference Manual Name Type Reset Description Bits FSIZE 2’d0 SPI frame size (also the valid width for each FIFO entry) 2’d0: 8-bit 2’d1: 16-bit 2’d2: 24-bit 2’d3: 32-bit 1’b0 Enable signal of SPI Slave function, Master and Slave should not be both enabled at the same time (This bit becomes don’t-care if cr_spi_m_en is enabled)
  • Page 121 BL602/604 Reference Manual Name Type Reset Description Bits 15:14 RSVD FERMASK 1’b1 Interrupt mask of spi_fer_int TXUMASK 1’b1 Interrupt mask of spi_txu_int STOMASK 1’b1 Interrupt mask of spi_sto_int RXFMASK 1’b1 Interrupt mask of spi_rxv_int TXFMASK 1’b1 Interrupt mask of spi_txe_int ENDMASK 1’b1...
  • Page 122 BL602/604 Reference Manual Name Type Reset Description Bits 9.4.4 spi_prd_0 Address：0x4000a210 PRDPH1 PRDPH0 PRDP PRDS Name Type Reset Description Bits 31:24 PRDPH1 8’d15 Length of DATA phase 1 (please refer to ”Timing” tab) 23:16 PRDPH0 8’d15 Length of DATA phase 0 (please refer to ”Timing” tab)
  • Page 123 BL602/604 Reference Manual RSVD RXDIGS RSVD RXDIGP Name Type Reset Description Bits 31:21 RSVD 20:16 RXDIGS 5’d0 Starting point of RX data ignore function 15:5 RSVD RXDIGP 5’d0 Stopping point of RX data ignore function 9.4.7 spi_sto_value Address：0x4000a21c RSVD RSVD...
  • Page 124 BL602/604 Reference Manual Name Type Reset Description Bits RFOF 1’b0 Overflow flag of RX FIFO, can be cleared by rx_fifo_clr TFUF 1’b0 Underflow flag of TX FIFO, can be cleared by tx_fifo_clr TFOF 1’b0 Overflow flag of TX FIFO, can be cleared by tx_fifo_clr 1’b0...
  • Page 125 BL602/604 Reference Manual FWDATA FWDATA Name Type Reset Description Bits 31:0 FWDATA SPI FIFO write data 9.4.11 spi_fifo_rdata Address：0x4000a28c FRDATA FRDATA Name Type Reset Description Bits 31:0 FRDATA 32’h0 SPI FIFO read data BL602/604 Reference Manual 125/ 195 @2020 Bouffalo Lab...
  • Page 126 Universal Asynchronous Receiver / Transmitter (commonly known as UART) is an asynchronous transceiver that provides a flexible way to exchange full-duplex data with external devices. BL602 has two sets of UART ports (UART0 and UART1). By using with DMA, you can achieve efficient data com- munication.

  • Page 127: Uart Data

    10.3.1 Data format description Normal UART communication data is composed of a start bit, a data bit, a parity bit, and a stop bit. The BL602’s UART supports configurable data bits, parity bits, and stop bits, all of which are set in the UTX_CONFIG and URX_CONFIG registers.

  • Page 128: Uart Clock

    BL602/604 Reference Manual 160M FCLK hbn_uart_clk_sel Figure 10.2: UART clock 10.3.4 Baud rate setting The user can generate the required baud rate by setting the register UART_BIT_PRD. The upper 16 bits and lower 16 bits of this register correspond to RX and TX respectively, that is, the baud rates of RX and TX can be set independently.

  • Page 129: Uart Sample

    BL602/604 Reference Manual UART Clock 160M Stop 1389 Start 1389 1389 Baud rate 115200 = 160M/1389 Sampling Time 8834 16667 16667 Start 16667 Baud rate 9600 = 160M/16667 Figure 10.3: UART sample 10.3.5 Transmitter The transmitter contains a 32-byte transmit FIFO to store the data to be transmitted. Software can write the TX FIFO through the APB bus, and can also move data into the TX FIFO through DMA.

  • Page 130: Uart Fixed Character Mode

    BL602/604 Reference Manual <CR_URX_DEG_CNT> of the URX_CONFIG register are used to enable the deburring function and set the threshold value, which controls the filtering part before UART sampling. The UART filters the glitches below the threshold width in the waveform and sends them for sampling.

  • Page 131: Uart Flow Control

    BL602/604 Reference Manual The formula for calculating the detected baud rate is as follows: Baud rate = source clock/(16-bit detection value + 1) 10.3.8 Hardware flow control The UART supports hardware flow control in CTS / RTS mode to prevent data in the FIFO from being lost because it is too late to process.
  • Page 132 BL602/604 Reference Manual • RX transmission end interrupt • TX FIFO request interrupt • RX FIFO request interrupt • RX timeout interrupt • RX parity error interrupt • TX FIFO overflow interrupt • RX FIFO overflow interrupt TX and RX can set a transmission length value through the upper 16 bits of the UTX_CONFIG and URX_CONFIG registers.
  • Page 133 BL602/604 Reference Manual Description Name uart_status UART status control register sts_urx_abr_prd Auto baud detection control register uart_fifo_config_0 UART FIFO configuration register0 uart_fifo_config_1 UART FIFO configuration register1 uart_fifo_wdata UART FIFO write data uart_fifo_rdata UART FIFO read data 10.4.1 utx_config Address：0x4000a000 TXLEN...
  • Page 134 BL602/604 Reference Manual Name Type Reset Description Bits 1’b0 Enable signal of UART TX function Asserting this bit will trigger the transaction, and should be de-asserted after finish 10.4.2 urx_config Address：0x4000a004 RXLEN DEGCNT RXBCNTD IRRX IRRX RXPR RXPR Name Type...
  • Page 135 BL602/604 Reference Manual RBITPRD TBITPRD Name Type Reset Description Bits 31:16 RBITPRD 16’d255 Period of each UART RX bit, related to baud rate 15:0 TBITPRD 16’d255 Period of each UART TX bit, related to baud rate 10.4.4 data_config Address：0x4000a00c RSVD...
  • Page 136 BL602/604 Reference Manual 10.4.6 urx_ir_position Address：0x4000a014 RSVD RXIRPS Name Type Reset Description Bits 31:16 RSVD 15:0 RXIRPS 16’d111 START position of UART RXD pulse recovered from IR sig- 10.4.7 urx_rto_timer Address：0x4000a018 RSVD RSVD RXRTOVA Name Type Reset Description Bits 31:8...
  • Page 137 BL602/604 Reference Manual Name Type Reset Description Bits 31:8 RSVD RFERINT 1’b0 UART RX FIFO error interrupt, auto-cleared when FIFO overflow/underflow error flag is cleared TFIN 1’b0 UART TX FIFO error interrupt, auto-cleared when FIFO overflow/underflow error flag is cleared RPCEINT 1’b0...
  • Page 138 BL602/604 Reference Manual Name Type Reset Description Bits 10.4.10 uart_int_clear Address：0x4000a028 RSVD RSVD RPCE RRTO RSVD RECL TECL Name Type Reset Description Bits 31:6 RSVD RPCECLR 1’b0 Interrupt clear of urx_pce_int RRTOCLR 1’b0 Interrupt clear of urx_rto_int RSVD RECL 1’b0...
  • Page 139 BL602/604 Reference Manual Name Type Reset Description Bits TFIF 1’b1 Interrupt enable of utx_fifo_int REND 1’b1 Interrupt enable of urx_end_int TEND 1’b1 Interrupt enable of utx_end_int 10.4.12 uart_status Address：0x4000a030 RSVD RSVD Name Type Reset Description Bits 31:2 RSVD 1’b0 Indicator of UART RX bus busy 1’b0...
  • Page 140 BL602/604 Reference Manual RSVD RSVD RFIU RFIO TFIU TFIO Name Type Reset Description Bits 31:8 RSVD RFIU 1’b0 Underflow flag of RX FIFO, can be cleared by rx_fifo_clr RFIO 1’b0 Overflow flag of RX FIFO, can be cleared by rx_fifo_clr TFIU 1’b0...
  • Page 141 BL602/604 Reference Manual Name Type Reset Description Bits TFICNT 6’d32 TX FIFO available count 10.4.16 uart_fifo_wdata Address：0x4000a088 RSVD RSVD UFIWD Name Type Reset Description Bits 31:8 RSVD UFIWD UART FIFO write data 10.4.17 uart_fifo_rdata Address：0x4000a08c RSVD RSVD UFIRD Name Type...

  • Page 142: Pin Lists

    If two or more hosts are initialized at the same time, data transmission can prevent data from being destroyed through collision detection and arbitration. BL602 includes an I2C controller host, which can be flexibly configured with slaveAddr, subAddr, and data transmission to facilitate communication with slave devices. It provides 2 word depth fifo and provides interrupt functions. It can be used with DMA to improve efficiency and flexibly adjust clock frequency.

  • Page 143: I2C Stop/Start Condition

    BL602/604 Reference Manual Name Type Description I2Cx_SCL input/output I2C serial clock signal I2Cx_SDA input/output I2C serial data signal 11.3.1 Start and stop conditions All transfers begin with a START condition and end with a STOP condition. The start and stop conditions are generally generated by the master. The bus is considered to be in a busy state after the start condition, and is considered to be in an idle state for a period of time after the stop condition.

  • Page 144: Master Transmission

    BL602/604 Reference Manual STOP START ADDRESS DATA DATA condition condition Figure 11.2: Master transmission Timing of master transmission and slave reception SLAVE ADDRESS DATA A/A DATA data transferred '0'(write) (n bytes + acknowledge) A = acknowledge(SDA LOW) from master to slave...

  • Page 145: Tx And Rx Together

    BL602/604 Reference Manual the bus is free. During the transmission process, all hosts need to check whether SDA is consistent with the data they want to send when SCL is high. When the SDA level is different from expected, it means that other hosts are also transmitting at the same time.
  • Page 146 BL602/604 Reference Manual • Slave address • Slave device address • Slave device address length • Data (when sending, configure the data to be sent; when receiving, store the received data) • Data length • Enable signal 11.5.2 Read and write flags I2C supports two working states: sending and receiving.
  • Page 147 BL602/604 Reference Manual 11.5.7 Data length Decrement the data length by one and write to the register PKTLEN. 11.5.8 Enable signal After the above configurations are completed, write the enable signal register MEN to 1 to automatically start the I2C transmission process.
  • Page 148 BL602/604 Reference Manual FIFO, the register RFIU will be set; • RX FIFO overflow: When I2C receives data until the 2 words of RX FIFO are filled. Without reading the RX FIFO, I2C receives the data again and the register RFIO will be set;...
  • Page 149 BL602/604 Reference Manual 11.7.2 DMA receiving process 1. Configure the read and write flags to 1 2. Configure the slave device address 3. Configure Slave Device Address 4. Configure slave device address length 5. Data length 6. Set the enable signal register 7.
  • Page 150 BL602/604 Reference Manual Description Name i2c_bus_busy I2C bus busy control register i2c_prd_start I2C length of start phase i2c_prd_stop I2C length of stop phase i2c_prd_data I2C length of data phase i2c_fifo_config_0 I2C FIFO configuration register0 i2c_fifo_config_1 I2C FIFO configuration register1 i2c_fifo_wdata...
  • Page 151 BL602/604 Reference Manual Name Type Reset Description Bits DEGEN 1’b0 Enable signal of I2C input de-glitch function (for all input pins) PKTDIR 1’b1 Transfer direction of the packet 1’b0: Write; 1’b1: Read 1’b0 Enable signal of I2C Master function Asserting this bit will trigger the transaction, and should be de-asserted after finish 11.9.2 i2c_int_sts...
  • Page 152 BL602/604 Reference Manual Name Type Reset Description Bits NAKMASK 1’b1 Interrupt mask of i2c_nak_int RXFMASK 1’b1 Interrupt mask of i2c_rxf_int TXFMASK 1’b1 Interrupt mask of i2c_txf_int ENDMASK 1’b1 Interrupt mask of i2c_end_int RSVD FERINT 1’b0 I2C TX/RX FIFO error interrupt, auto-cleared when FIFO...
  • Page 153 BL602/604 Reference Manual RSVD RSVD BUSY BUSY Name Type Reset Description Bits 31:2 RSVD BUSYCLR 1’b0 Clear signal of bus_busy status, not for normal usage (in case I2C bus hangs) BUSY 1’b0 Indicator of I2C bus busy 11.9.5 i2c_prd_start Address：0x4000a310...
  • Page 154 BL602/604 Reference Manual Name Type Reset Description Bits 31:24 PRDPPH3 8’d15 Length of STOP condition phase 3 23:16 PRDPPH2 8’d15 Length of STOP condition phase 2 15:8 PRDPPH1 8’d15 Length of STOP condition phase 1 PRDPPH0 8’d15 Length of STOP condition phase 0 11.9.7 i2c_prd_data...
  • Page 155 BL602/604 Reference Manual Name Type Reset Description Bits TFIU 1’b0 Underflow flag of TX FIFO, can be cleared by tx_fifo_clr TFIO 1’b0 Overflow flag of TX FIFO, can be cleared by tx_fifo_clr RFICLR 1’b0 Clear signal of RX FIFO TFICLR 1’b0...
  • Page 156 BL602/604 Reference Manual FIWD FIWD Name Type Reset Description Bits 31:0 FIWD I2C FIFO write data 11.9.11 i2c_fifo_rdata Address：0x4000a38c FIRD FIRD Name Type Reset Description Bits 31:0 FIRD 32’h0 I2C FIFO read data BL602/604 Reference Manual 156/ 195 @2020 Bouffalo Lab...
  • Page 157 B. XTAL - External crystal clock C. f32k - System RTC clock Each counter has its own 16-bit frequency divider. The selected clock can be divided by APB. The PWM counter will 157/ 195 @2020 Bouffalo Lab BL602/604 Reference Manual...
  • Page 158 BL602/604 Reference Manual use the divided clock as the counting cycle unit, and perform one action every time a counting cycle passes . 12.3.2 Pulse generation principle There is a counter in the PWM. When the counter is in the middle of two settable thresholds, the PWM output is 1, otherwise when the counter is outside the two set thresholds, the PWM output is 0.

  • Page 159: Pwm

    BL602/604 Reference Manual PWMn_THRE2[15:0]=0+40000*20%=8000 12.3.3 PWM interrupt For each PWM channel, you can set the cycle count value. When the number of cycles of the PWM output reaches this count value, a PWM interrupt will be generated. Table 12.1: Duty Cycle Parameters F/MHz Supported duty cycle (n is an integer, and 2 <= n <= 65535^2)
  • Page 160 BL602/604 Reference Manual Description Name pwm1_clkdiv PWM1 clock division configuration register pwm1_thre1 PWM1 first counter threshold configuration register pwm1_thre2 PWM1 sencond counter threshold configuration register pwm1_period PWM1 period setting register pwm1_config PWM1 configuration register pwm1_interrupt PWM1 interrupt register pwm2_clkdiv PWM2 clock division configuration register...
  • Page 161 BL602/604 Reference Manual RSVD RSVD INTCLR RSVD INTSTS Name Type Reset Description Bits 31:14 RSVD 13:8 INTCLR 6’d0 PWM channel interrupt clear RSVD INTSTS 6’d0 PWM channel interrupt status 12.4.2 pwm0_clkdiv Address：0x4000a420 RSVD CLKDIV Name Type Reset Description Bits 31:16...
  • Page 162 BL602/604 Reference Manual Name Type Reset Description Bits 12.4.4 pwm0_thre2 Address：0x4000a428 RSVD THRE2 Name Type Reset Description Bits 31:16 RSVD 15:0 THRE2 16’d0 PWM sencond counter threshold, can’t be smaller that pwm_thre1 12.4.5 pwm0_period Address：0x4000a42c RSVD PERIOD Name Type Reset...
  • Page 163 BL602/604 Reference Manual RSVD RSVD STOP STOP STOP CLKSEL MODE FVAL MODE Name Type Reset Description Bits 31:8 RSVD STOPSTA 1’b0 PWM stop status STOPEN 1’b0 PWM stop enable SWMODE 1’b0 PWM SW Mode setting SWFVAL 1’b0 PWM SW Mode force value STOPMODE 1’b1...
  • Page 164 BL602/604 Reference Manual RSVD CLKDIV Name Type Reset Description Bits 31:16 RSVD 15:0 CLKDIV 16’b0 PWM clock division 12.4.9 pwm1_thre1 Address：0x4000a444 RSVD THRE1 Name Type Reset Description Bits 31:16 RSVD 15:0 THRE1 16’b0 PWM first counter threshold, can’t be larger that pwm_- thre2 12.4.10 pwm1_thre2...
  • Page 165 BL602/604 Reference Manual 12.4.11 pwm1_period Address：0x4000a44c RSVD PERIOD Name Type Reset Description Bits 31:16 RSVD 15:0 PERIOD 16’d0 PWM period setting 12.4.12 pwm1_config Address：0x4000a450 RSVD RSVD STOP STOP STOP CLKSEL MODE FVAL MODE Name Type Reset Description Bits 31:8 RSVD STOPSTA 1’b0...
  • Page 166 BL602/604 Reference Manual RSVD INTPECN Name Type Reset Description Bits 31:17 RSVD INTEN 1’b0 PWM interrupt enable 15:0 INTPECN 16’d0 PWM interrupt period counter threshold 12.4.14 pwm2_clkdiv Address：0x4000a460 RSVD CLKDIV Name Type Reset Description Bits 31:16 RSVD 15:0 CLKDIV 16’b0 PWM clock division 12.4.15 pwm2_thre1...
  • Page 167 BL602/604 Reference Manual Name Type Reset Description Bits 12.4.16 pwm2_thre2 Address：0x4000a468 RSVD THRE2 Name Type Reset Description Bits 31:16 RSVD 15:0 THRE2 16’d0 PWM sencond counter threshold, can’t be smaller that pwm_thre1 12.4.17 pwm2_period Address：0x4000a46c RSVD PERIOD Name Type Reset...
  • Page 168 BL602/604 Reference Manual RSVD RSVD STOP STOP STOP CLKSEL MODE FVAL MODE Name Type Reset Description Bits 31:8 RSVD STOPSTA 1’b0 PWM stop status STOPEN 1’b0 PWM stop enable SWMODE 1’b0 PWM SW Mode setting SWFVAL 1’b0 PWM SW Mode force value STOPMODE 1’b1...
  • Page 169 BL602/604 Reference Manual RSVD CLKDIV Name Type Reset Description Bits 31:16 RSVD 15:0 CLKDIV 16’b0 PWM clock division 12.4.21 pwm3_thre1 Address：0x4000a484 RSVD THRE1 Name Type Reset Description Bits 31:16 RSVD 15:0 THRE1 16’b0 PWM first counter threshold, can’t be larger that pwm_- thre2 12.4.22 pwm3_thre2...
  • Page 170 BL602/604 Reference Manual 12.4.23 pwm3_period Address：0x4000a48c RSVD PERIOD Name Type Reset Description Bits 31:16 RSVD 15:0 PERIOD 16’d0 PWM period setting 12.4.24 pwm3_config Address：0x4000a490 RSVD RSVD STOP STOP STOP CLKSEL MODE FVAL MODE Name Type Reset Description Bits 31:8 RSVD STOPSTA 1’b0...
  • Page 171 BL602/604 Reference Manual RSVD INTPECN Name Type Reset Description Bits 31:17 RSVD INTEN 1’b0 PWM interrupt enable 15:0 INTPECN 16’d0 PWM interrupt period counter threshold 12.4.26 pwm4_clkdiv Address：0x4000a4a0 RSVD CLKDIV Name Type Reset Description Bits 31:16 RSVD 15:0 CLKDIV 16’b0 PWM clock division 12.4.27 pwm4_thre1...
  • Page 172 BL602/604 Reference Manual Name Type Reset Description Bits 12.4.28 pwm4_thre2 Address：0x4000a4a8 RSVD THRE2 Name Type Reset Description Bits 31:16 RSVD 15:0 THRE2 16’d0 PWM sencond counter threshold, can’t be smaller that pwm_thre1 12.4.29 pwm4_period Address：0x4000a4ac RSVD PERIOD Name Type Reset...
  • Page 173 BL602/604 Reference Manual RSVD RSVD STOP STOP STOP CLKSEL MODE FVAL MODE Name Type Reset Description Bits 31:8 RSVD STOPSTA 1’b0 PWM stop status STOPEN 1’b0 PWM stop enable SWMODE 1’b0 PWM SW Mode setting SWFVAL 1’b0 PWM SW Mode force value STOPMODE 1’b1...

  • Page 174: Timer Block Diagram

    Timer, which can trigger interrupt or system reset according to the setting. BL_TIMER 32-bit timer fclk xtal_ clk_mux clk_div timer_cnt timer_irq f32k _ Figure 13.1: Timer block diagram 174/ 195 @2020 Bouffalo Lab BL602/604 Reference Manual...

  • Page 175: Watchdog Timer Block Diagram

    BL602/604 Reference Manual BL_WDT watch-dog timer fclk wdt_ir q xtal_ clk_mux clk_div wdt_cnt f32k_ Figure 13.2: Watchdog timer block diagram 13.2 Main features • Multiple clock sources, up to 160M clock • 8-bit clock divider with a division factor of 1-256.

  • Page 176: Timer Preload

    BL602/604 Reference Manual • Fclk–System master clock • 32K–32K clock • 1K–1K clock (32K frequency division) • Xtal–External crystal Each counter has its own 8-bit frequency divider. The selected clock can be divided by 1-256 through APB. Specifically, when it is set to 0, it means no frequency division, and when it is set to 1, it divides it by 2. , The maximum frequency division coefficient is 256, the counter will use the divided clock as the unit of the counting cycle, each time a counting cycle is increased by one.

  • Page 177: Watchdog Timing

    BL602/604 Reference Manual In FreeRun mode, the timer working sequence is basically the same as PreLoad, the difference is that the counter will start to accumulate from 0 to the maximum value. The mechanism of the generated compare flags and compare interrupts is the same as in FreeRun mode.

  • Page 178: Watchdog Alarm Mechanism

    BL602/604 Reference Manual that software can read the WSR register through APB to know if a watchdog system reset has occurred. Idle Software enable (APB) Counter reset Software trigger (APB) Counter count Counter reaches alarm value wrie==0 wrie==1 Reset alarm...
  • Page 179 BL602/604 Reference Manual Description Name TMSR2 Timer2 match register status TMSR3 Timer3 match register status TIER2 Timer2 match interrupt enable register TIER3 Timer3 match interrupt enable register TPLVR2 Timer2 pre-load value register TPLVR3 Timer3 pre-load value register TPLCR2 Timer2 pre-load control register...
  • Page 180 BL602/604 Reference Manual 13.4.1 TCCR Address：0x4000a500 RSVD RSVD CSWDT RSVD RSVD RSVD Name Type Reset Description Bits 31:10 RSVD CSWDT 2’d0 Clock Source for Timer #1/#2/#3/WDT 2’d0 - fclk 2’d1 - f32k_clk 2’d2 - 1 kHz 2’d3 - PLL 32MHz RSVD 2’d0...
  • Page 181 BL602/604 Reference Manual Name Type Reset Description Bits 31:0 TMR20 32’hffffffff Timer2 match register 0 13.4.3 TMR2_1 Address：0x4000a514 TMR21 TMR21 Name Type Reset Description Bits 31:0 TMR21 32’hffffffff Timer2 match register 1 13.4.4 TMR2_2 Address：0x4000a518 TMR22 TMR22 Name Type Reset...
  • Page 182 BL602/604 Reference Manual Name Type Reset Description Bits 31:0 TMR30 32’hffffffff Timer3 match register 0 13.4.6 TMR3_1 Address：0x4000a520 TMR31 TMR31 Name Type Reset Description Bits 31:0 TMR31 32’hffffffff Timer3 match register 1 13.4.7 TMR3_2 Address：0x4000a524 TMR32 TMR32 Name Type Reset...
  • Page 183 BL602/604 Reference Manual Name Type Reset Description Bits 31:0 TCR2COUT 32’h0 Timer2 counter register 13.4.9 TCR3 Address：0x4000a530 TCR3COUT TCR3COUT Name Type Reset Description Bits 31:0 TCR3COUT 32’h0 Timer3 counter register 13.4.10 TMSR2 Address：0x4000a538 RSVD RSVD Name Type Reset Description Bits...
  • Page 184 BL602/604 Reference Manual RSVD RSVD Name Type Reset Description Bits 31:3 RSVD T3MR2S 1’b0 Timer3 match register 2 status/Clear interrupt would also clear this bit T3MR1S 1’b0 Timer3 match register 1 status/Clear interrupt would also clear this bit T3MR0S 1’b0...
  • Page 185 BL602/604 Reference Manual RSVD RSVD TIER TIER31 TIER30 Name Type Reset Description Bits 31:3 RSVD TIER32 1’b0 Timer3 match register 2 interrupt enable register TIER31 1’b0 Timer3 match register 1 interrupt enable register TIER30 1’b0 Timer3 match register 0 interrupt enable register 13.4.14 TPLVR2...
  • Page 186 BL602/604 Reference Manual 13.4.16 TPLCR2 Address：0x4000a55c RSVD RSVD TPLCR2 Name Type Reset Description Bits 31:2 RSVD TPLCR2 2’h0 Timer2 pre-load control register 2’d0 - No pre-load 2’d1 - Pre-load with match comparator 0 2’d2 - Pre-load with match comparator 1 2’d3 - Pre-load with match comparator 2...
  • Page 187 BL602/604 Reference Manual RSVD RSVD WRIE Name Type Reset Description Bits 31:2 RSVD WRIE 1’b0 WDT reset/interrupt mode register 1’b0 - WDT expiration to generate interrupt 1’b1 - WDT expiration to generate reset source 1’b0 WDT enable register 13.4.19 WMR Address：0x4000a568...
  • Page 188 BL602/604 Reference Manual Name Type Reset Description Bits 13.4.21 WSR Address：0x4000a570 RSVD RSVD Name Type Reset Description Bits 31:1 RSVD 1’b0 WDT timer reset indication, Indicates that reset was caused by the WDT. (Write)1’b0 - clear the WDT reset status (Write)1’b1 - no affect...
  • Page 189 BL602/604 Reference Manual 13.4.23 TICR3 Address：0x4000a57c RSVD RSVD TCLR TCLR TCLR Name Type Reset Description Bits 31:3 RSVD TCLR32 1’b0 Timer3 Interrupt clear for match comparator 2 TCLR31 1’b0 Timer3 Interrupt clear for match comparator 1 TCLR30 1’b0 Timer3 Interrupt clear for match comparator 0 13.4.24 WICR...
  • Page 190 BL602/604 Reference Manual RSVD RSVD TIM3 TIM2 RSVD Name Type Reset Description Bits 31:3 RSVD TIM3EN 1’b0 Timer3 count enable TIM2EN 1’b0 Timer2 count enable RSVD 13.4.26 TCMR Address：0x4000a588 RSVD RSVD TIM3 TIM2 RSVD MODE MODE Name Type Reset Description...
  • Page 191 BL602/604 Reference Manual RSVD RSVD TILR TILR TILR Name Type Reset Description Bits 31:3 RSVD TILR22 1’b0 Timer2 match 0/1/2 interrupt mode register 1’b0 - level interrupt 1’b1 - pulse interrupt TILR21 1’b0 Timer2 match 0/1/2 interrupt mode register 1’b0 - level interrupt 1’b1 - pulse interrupt...
  • Page 192 BL602/604 Reference Manual Name Type Reset Description Bits 13.4.29 WCR Address：0x4000a598 RSVD RSVD Name Type Reset Description Bits 31:1 RSVD 1’b0 WDT timer count reset register 13.4.30 WFAR Address：0x4000a59c RSVD WFAR Name Type Reset Description Bits 31:16 RSVD 15:0 WFAR 16’b0...
  • Page 193 BL602/604 Reference Manual Name Type Reset Description Bits 31:16 RSVD 15:0 WSAR 16’b0 WDT access key2 - 16’hEB10 13.4.32 TCVWR2 Address：0x4000a5a8 TCVWR2 TCVWR2 Name Type Reset Description Bits 31:0 TCVWR2 32’h0 Timer2 capture value of counter 13.4.33 TCVWR3 Address：0x4000a5ac TCVWR3...
  • Page 194 BL602/604 Reference Manual Name Type Reset Description Bits 31:0 TCVSYN2 32’h0 Timer2 synchronous value of counter 13.4.35 TCVSYN3 Address：0x4000a5b8 TCVSYN3 TCVSYN3 Name Type Reset Description Bits 31:0 TCVSYN3 32’h0 Timer3 synchronous value of counter 13.4.36 TCDR Address：0x4000a5bc WCDR TCDR3 TCDR2...

  • Page 195: Document Revision History

    Date Revision Changes 2020/2/13 Initial release 2020/4/20 Add related content of HBN register 2020/8/26 Add ADC and DAC 2020/12/14 Add the introduction of interrupt sources and the maximum operating speed of peripherals 195/ 195 @2020 Bouffalo Lab BL602/604 Reference Manual...

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