ASIX AX11001 Manuals

Manuals and User Guides for ASIX AX11001. We have 1 ASIX AX11001 manual available for free PDF download: Manual

ASIX AX11001 Manual

ASIX AX11001 Manual (55 pages)

Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY

Brand: ASIX | Category: Microcontrollers | Size: 1 MB

Table of Contents

Table of Contents
4
Introduction
7
General Description
7
Ax11001/Ax11005 Block Diagram
7
Figure 7: Ax11005 Block Diagram
7
Ax11001/Ax11005 Pinout Diagram
8
Figure 8: Ax11001/Ax11005 Pinout
8
Signal Description
9
Table 1: Pinout Description
9
Function Description
14
Clock Generation
14
Reset Generation
14
Voltage Regulator
14
Cpu Core and Debugger
15
CPU Core
15
Debugger
15
Figure 9: Typical Debugger and Figure 10: Flash Memoryp
16
On-Chip Flash Memory
17
Memory Arbiter and Boot Loader
18
Boot Loader
18
Memory Arbiter
18
Flash Programming Controller
18
Dma Engine
19
Interrupt Controller
19
Watchdog Timer
20
Table 2: Interrupt Controller
20
Power Management Unit
21
Pmm
21
STOP Mode
22
Timers and Counters
22
Uarts
23
UART 0 and UART 1
23
Uart 2
24
Figure 13: I/O Buffer of Rxd0
24
Gpios
25
Tcp/Ip Offload Engine
25
Figure 14: the I/O Buffer of Gpio P
25
10/100M Ethernet Mac
26
10/100M Ethernet Phy
27
Programmable Counter Array
27
Figure 15:Programmable Counter
27
I2C Controller
28
Figure 16: I2C Controller Block
28
1-Wire Controller
29
Spi Controller
29
Figure 17: 1-Wire Controllerb
29
Memory Map Description
31
I2C Configuration Eeprom Memory Map
31
Length (0X00)
31
Table 3: I2C Configuration
31
Flag (0X01)
32
Multi-Function Pin Setting (0X02~0X03)
32
Programmable Output Driving Strength (0X04)
33
Node ID (0X06~0X0B)
34
Maximum Packet Size (0X0C~0X0D)
34
Primary/Secondary PHY Type and PHY ID (0X0E~0X0F)
34
Pause Frame Low Water and High Water Mark (0X10~0X11)
34
TOE TX VLAN Tag (0X14~0X15)
35
TOE RX VLAN Tag (0X16~0X17)
35
TOE ARP Cache Timeout (0X18)
35
TOE Source IP Address (0X19~0X1C)
35
TOE Subnet Mask (0X1D~0X20)
35
TOE L4 DMA Transfer Gap (0X21)
35
Program Memory Map
36
Table 4: Sfr Register Map
37
Figure 23: Xtl25P Clock Timing
45
Figure 24: Lb_Clk C
45
Table 5: I2C Master Controller
46
Table 6: I2C Slave Controller
46
Figure 25: Spi Master Controller
47
Figure 26: Spi Slave Controller
47
Figure 27: One -Wire Resetp
48
Figure 28: One -Wire Write and Figure 29: One -Wire Stpz R
49
Figure 30: Eci Timing Diagram and Figure 31: Cex[4:0] Timingd
50
Figure 32: Tm_Ck[2:0] Timingd
51
Figure 33: Tm_Gt[2:0] Timingd
51
Figure 34: 10/100M Ethernet
52
Table 7: 10/100M Ethernet Phy R
52

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