ASIX AX11001 Manual

Features
MCU
8-bit pipelined RISC, single cycle per
instruction with maximum operating frequency
of 100Mhz (100 MIPS)
100% software compatible with standard
8051/80390
2 GPIO ports of 8 bits each
2 external interrupt sources with 2 priority
levels
Support power
programmable watchdog timer, and 3 16-bit
timer/counters
Debug port for connecting to In-Circuit
Emulation (ICE) adaptor
5 channels of programmable counter array
On-chip Program and Data Memory
Embed 128K (AX11001) or 512KB (AX11005)
Flash memory without bank select, and 16KB
SRAM for program code mirroring
Support initial Flash memory programming via
UART or ICE adaptor, the so-called In System
Programming (ISP)
Support run-time firmware or driver update
through Ethernet or UART, the so-called In
Application Programming (IAP)
Embed 32KB SRAM for data memory
Buffer Management
Embed DMA engine and memory arbiter.
Support 3 DMA channels for high performance
data movement needed for network protocol
stack processing
On-chip 10/100M Fast Ethernet MAC and PHY
Integrate IEEE 802.3 10BASE-T/100BASE-TX
compatible Fast Ethernet MAC and PHY with
Product Description
The AX11001/AX11005, Single Chip Micro-controller with TCP/IP and 10/100M Fast Ethernet MAC/PHY, is a
System-on-Chip (SoC) solution which offers a high performance embedded micro-controller and rich communication
peripherals for wide varieties of application which need access to the LAN or Internet. With built-in network protocol
stack, the AX11001/AX11005 provides very cost effective networking solution to enable simple, easy, and low cost
Internet connection capability for many applications such as consumer electronics, networked home appliances, industrial
equipments, security systems, remote data collection equipments, remote control, remote monitoring, and remote
management. In addition to stand-alone application, the AX11001/AX11005, with popular TCP/IP protocol suite on-chip
and built-in I2C bus or SPI bus, can be used as network co-processor to offload TCP/IP protocol processing loading from
system CPU in an embedded system.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No
liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
4F, NO.8, Hsin Ann Rd., HsinChu Science Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500
FAX: 886-3-579-9558
http://www.asix.com.tw
Single Chip Microcontroller with TCP/IP
management unit,
Always contact ASIX for possible updates before starting a design.
and 10/100M Fast Ethernet MAC/PHY
Document No: AX1100x/V0.6/05/03/06
dedicated 12KB SRAM for Ethernet packet
buffering. Support full-duplex and half-duplex
operations
Support twisted pair crossover detection and
auto-correction
Support wakeup via Link-up, Magic packet,
Wakeup frame or external input pin
TCP/IP
Build in TCP/IP accelerator in hardware to
improve network transfer throughput. Support
IP/TCP/UDP/ICMP/IGMP checksum and ARP
in hardware
Support TCP, UDP, ICMP, IGMP, IPv4,
DHCP, BOOTP, ARP, and HTTP in software
Communication Interface
3 UART interface
921.6Kbps and Modem control)
1 I2C interface (master and slave mode)
SPI/Micro wire interface (3 masters or 1 slave
mode)
1 1-Wire controller interface (master mode)
10/100 Ethernet PHY interface
Support network boot over Ethernet using DHCP and
TFTP
Integrate on-chip voltage regulator and require single
power supply of 3.3V only
Integrate on-chip oscillator and PLL. Require only
one 25Mhz crystal to operate
Integrate on-chip power-on reset circuit
80-pin LQFP RoHS package
Operating temperature: 0 to 70°C or -40 to 85°C
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respective holders.
AX11001/AX11005
(with 1 supporting
Release Date: 5/3/2006