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ARM GP4020 Design Manual

Gps baseband processor
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GP4020 GPS Baseband Processor Design Manual
Publication Number: DM5280
Issue: 3
Revision: 002
Issued: January 2002
Zarlink Semiconductor, Cheney Manor
Swindon, Wiltshire, United Kingdom, SN2 2QW

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Summary of Contents for ARM GP4020

  • Page 1 GP4020 GPS Baseband Processor Design Manual Publication Number: DM5280 Issue: 3 Revision: 002 Issued: January 2002 Zarlink Semiconductor, Cheney Manor Swindon, Wiltshire, United Kingdom, SN2 2QW...

  • Page 2: Manual Revision History

    Version Revision Date February 2000 August 2000 November 2001 January 2002 Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright © 2002, Zarlink Semiconductor Inc. All Rights Reserved. Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable.

  • Page 3: Table Of Contents

    Functional Description... 2 Typical Application... 8 GP4020 PACKAGE AND ELECTRICAL CONNECTIONS... 11 GP4020 100-pin Package Dimensions ... 11 GP4020 100-pin Package Electrical Connection Details ... 13 ARM7TDMI MICROPROCESSOR ... 19 ARM7TDMI Instruction Set Architecture... 19 The Thumb Concept ... 19 Thumb’s Advantages ...
  • Page 4 10 INTERRUPT CONTROLLER (INTC) ... 107 11 MEMORY PERIPHERAL CONTROLLER (MPC) ... 109 11.1 Introduction ... 109 11.2 GP4020 Memory Area 1 Configuration ... 109 11.3 GP4020 Memory Area 2 Configuration ... 110 11.4 GP4020 Memory Area 3 Configuration ... 111 11.5 GP4020 Memory Area 4 Configuration ...

  • Page 5: Trademarks

    19.2 GP4020 Firefly MF1 Address Map... 183 20 INPUT / OUTPUT PIN CHARACTERISTICS ... 185 20.1 Pin Types ... 185 20.2 Input Delays ... 187 20.3 Output Delays... 188 20.4 Cell DC Characteristics ... 190 21 TIMING CHARACTERISTICS... 193 21.1 Memory Peripheral Controller (MPC) External Read & Write timing parameters with on-chip Wait-state Control ...

  • Page 6: Document References

    Document References References to the following documents are made within the GP4020 GPS Baseband Processor Design Manual: "ARM7TDMI Technical Reference Manual" ARM DDI 0029F, Rev 4 Arm Ltd. Documentation website (http://www.arm.com/arm/documentation?OpenDocument) Document Conventions The following terms which appear in the Manual, are defined here:...

  • Page 7: Introduction

    Semiconductor Firefly MF1 Microcontroller Core (ref. Firefly MF1 Core Design Manual (DM5003)), and a custom Navstar GPS C/A code 12-channel spread-spectrum correlator. The GP4020 is a complete digital baseband processor for a Global Positioning System (GPS) receiver. It combines the 12-channel correlator function of the GP2021 with an advanced ARM7TDMI achieve a higher level of integration, reduced system cost, reduced power consumption and added functionality.

  • Page 8: Functional Description

    GPS correlator, a Zarlink Firefly MF1 micro-controller core (incorporating the ARM7TDMI Thumb microprocessor), Real time Clock, 8k bytes of on-chip SRAM and a boot ROM. The GP4020 uses a fully configurable memory interface, allowing the use of both 8-bit and 16-bit external memory. A Block Diagram of the GP4020 appears in Figure 1.1 GP4020 Block Diagram"...
  • Page 9 The GP4020 BOOT ROM contains code, which is executed every time there is a complete system reset (i.e. when main power has been removed from the GP4020). The code installed on the BOOT ROM, allows the GP4020 to undertake either of 2 functions after a complete reset: •...
  • Page 10 Logic Analyser coupled with an Inverse Assembler accessed via the SSM debug interface. The GP4020 can use any of these options, but special emphasis has been placed on the EmbeddedICE and Logic Analyser options. The JTAG and SSM debug interfaces are multiplexed onto the same pins, and can be selected by setting the NICE (pin 84) to High for SSM, or Low for JTAG.

  • Page 11: Internal Sram

    Signal input/output multiplex control Details can be found in section 12 "PERIPHERAL CONTROL LOGIC (PCL)" on page 113. 1.3.13 Internal SRAM The GP4020 contains 8k bytes (configured as 2k x 32-bit) of high-speed (6ns) Static RAM. This can be used for either: •...
  • Page 12 The GP4020 Real Time Clock uses an external 32kHz crystal to give an indication of time to the GP4020 chip, when the device is in Reset / Power Down. If a backup battery is included in a GPS receiver using the GP4020, the RTC will continue to operate regardless of the reset-state of the rest of the device.
  • Page 13 The TIC functions provided by this module are part of the Firefly MF1 core. Timer 1 (TIC1) appears at GP4020 Base Address 0xE000 E000, and Timer 2 (TIC2) appears at Address 0xE000 F000. TIC enable (TEN) lines are not available externally on the GP4020, but are tied Low on- chip.

  • Page 14: Typical Application

    1: Introduction 1.4 Typical Application INTERFACE JTAG NICE M_CLK Figure 1.2 Block Diagram of typical GP4020 based GPS receiver GP4020 GPS Baseband Processor Design Manual...
  • Page 15 (the ’Navigation Message’) and to control the software signal tracking loops. Note that the GP4020 is designed to operate from an independent PSU supply, so that it can remain active while all the peripheral components are powered off. This is signified by the use of the PSU names "Main +3.3V", and "GP4020 +3.3V".
  • Page 16 1: Introduction This page intentionally left blank. GP4020 GPS Baseband Processor Design Manual...

  • Page 17: Gp4020 Package And Electrical Connections

    2 GP4020 PACKAGE AND ELECTRICAL CONNECTIONS 2.1 GP4020 100-pin Package Dimensions The GP4020 GPS Baseband Processor is available from Zarlink Semiconductor in a 100-pin gull-wing Thin Quad Flat Package (TQFP). Ordering information for the GP4020 are shown in the “GP4020 GPS Baseband Processor Datasheet”...
  • Page 18 2: GP4020 Package and Electrical Connections Figure 2.2 GP4020 100-pin package outline drawing GP4020 GPS Baseband Processor Design Manual...

  • Page 19: Gp4020 100-Pin Package Electrical Connection Details

    Symbol Table 2.1 GP4020 100-pin package dimensions 2.2 GP4020 100-pin Package Electrical Connection Details All Vdd and GND pins must be connected to ensure reliable operation. Any unused input pins must be tied either High or Low; no inputs should be left unconnected.
  • Page 20 60 (GND) to ensure optimum noise immunity. Master Clock (M_CLK) Input from RF Front-end - 40MHz 100mV rms. Inverted Master Clock (M_CLK) Input from RF Front- end - 40MHz 100mV rms. GP4020 GPS Baseband Processor Design Manual Description Notes...
  • Page 21 Sample Clock output to the RF front end. Provides a 5.714MHz clock with a 4:3 mark–to–space ratio. Power Monitor input. High for normal operation. Low forces the GP4020 into Power Down mode. System Clock Oscillator - crystal oscillator output for 10 to 16MHz crystal.
  • Page 22 GP2010 / GP2015 RF Front-end is NOT possible, without a bias-shift circuit (refer to Block Diagram of typical GP4020 based GPS receiver" on page 8, and Section 14.2 "40MHz Low Level Differential Input" on page 136 for more information).

  • Page 23: Test Function

    Pin 90 = NTRST NICE = High and NTRST = High: This is the Normal mode of operation for GP4020. The System Services Module Broadcast Diagnostic debug output signals are connected to pins 86, 87, 88, 89 as follows: Pin 86...
  • Page 24 Pin 89 = XCon System test inputs are used in Firefly MF1 macrocell test mode for manufacturing test. Refer to Section 2.10 of Firefly MF1 Core Design Manual (DM5003), from Zarlink Semiconductor, for more information. GP4020 GPS Baseband Processor Design Manual...

  • Page 25: Arm7Tdmi Microprocessor

    16-bit architecture will take at least two instructions to perform the same task as a single ARM instruction. However, not all the code in a program will process 32-bit data (for example, code that performs character string handling), and some instructions, like Branches, do not process any data at all. GP4020 GPS Baseband Processor Design Manual...
  • Page 26 Thumb code to ARM code is folded into sub-routine entry time. Various portions of a system can be optimised for speed or for code density by switching between Thumb and ARM execution as appropriate. Figure 3.1 ARM7TDMI Architecture GP4020 GPS Baseband Processor Design Manual...
  • Page 27 Software Interrupt Swap register with memory Test bitwise equality Test bits Table 3.1 Standard 32-bit ARM instruction set GP4020 GPS Baseband Processor Design Manual 3: ARM7TDMI Microprocessor Action Rd := Rn + Op2 + Carry Rd := Rn + Op2...

  • Page 28: Operating Modes

    [Rb + Immediate5] := Rd8 [Rb + Immediate5] := Rd16 OS call Rd := Rd - Immediate8 CPSR flags :=Rd AND Rs Table 3.2 16-bit Thumb instruction set GP4020 GPS Baseband Processor Design Manual Lo/Hi Condition register codes set operands...

  • Page 29: Register Sets

    R0-R7, as well as the Program Counter (PC), a stack pointer register (SP), a link register (LR), and the CPSR. There are banked Stack Pointers, Link Registers and Saved Process Status Registers (SPSRs) for each privileged mode. GP4020 GPS Baseband Processor Design Manual 3: ARM7TDMI Supervisor...

  • Page 30: Low Power Arm7Tdmi Sleep Mode

    ARM7TDMI, but keep it enabled to other parts of the Firefly MF1. This is different to the F_SLEEP utility in the Peripheral Control Logic block of the GP4020, as it allows all other Firefly blocks to remain operable while the ARM7TDMI is halted.
  • Page 31 "Firefly MF1 Core Design Manual" DM5003, available from Zarlink Semiconductor. In addition Rev 3 of the ARM7TDMI Technical Reference Manual (document reference ARM DDI 0029F), is downloadable (1.7 MB PDF) from ARM's website http://www.arm.com. The documentation download page can be found at: http://www.arm.com/arm/documentation?OpenDocument. GP4020 GPS Baseband Processor Design Manual 3: ARM7TDMI Microprocessor...
  • Page 32 3: ARM7TDMI Microprocessor This page intentionally left blank. GP4020 GPS Baseband Processor Design Manual...

  • Page 33: Boot Rom

    4.1 Functional Description The GP4020 Boot ROM is an internal part of the IC. The code in the Boot ROM will allow the GP4020 based GPS receiver to up-load a software routine into RAM from an external data source (e.g. a PC), and run the routine from RAM.

  • Page 34: Uart Download Data Protocol

    16 x Baud Rate of 0.90909MHz. The actual baud rate is 56.8kBaud, which is in error by -1.3%. The protocol to be used for downloading data to the GP4020 is detailed below. The main purpose of the protocol is to provide simple but reliable data transfer.
  • Page 35 BYTE N DATA BYTES Header Bytes 1, 2, 3 produce 24-bit number indicating total number of Data Bytes (N) to be received. Byte 1 = Most Significant. Figure 4.1 Boot ROM UART Download Data Protocol GP4020 GPS Baseband Processor Design Manual...
  • Page 36 4: Boot ROM This Page intentionally left blank. GP4020 GPS Baseband Processor Design Manual...

  • Page 37: The Bµild Bus

    Bus for µController Integration in Low-Power Designs (BµILD). Although the GP4020 user does NOT need to know details of the internal operation of the BµILD bus for most applications, the implementation details are included for information.

  • Page 38: Bus Signals

    General Purpose Input Output 5.3 Bus Signals The BµILD bus, internal to the GP4020 has full 32-bit un-multiplexed address and data busses, b_addr<31:0> and b_data<31:0>. The direction of the current transaction is denoted by a write not read signal, b_write. The BµILD bus also supports multiple transaction sizes of byte, half-word (16-bits) and word (32-bits), as denoted by b_size<1:0>.

  • Page 39: Bµild Serial Input Output (Bsio) Interface

    6 BµILD SERIAL INPUT OUTPUT (BSIO) INTERFACE 6.1 Overview A 3-wire serial input/output is included in the GP4020 to allow serial data connection to any device with a three-pin serial interface. The BSIO pins are multiplexed with the General Purpose Input Output (GPIO) pins within the Peripheral Control Logic block.

  • Page 40: Operational Description

    The Serial block copies the RWBUF register to an internal register and generates a write interrupt to the ARM7TDMI to notify the RWBUF buffer is empty and begins sending data once the first four bytes have been sent. DATA IN EEPROM DATA OUT DATA GP4020 GPS Baseband Processor Design Manual...
  • Page 41 The timing for a Read and Write operation from the BSIO to a Slave device is shown in Figure 6.3 and Figure 6.4 below. Refer to “Electrical Characteristics” in the “GP4020 GPS Baseband Processor Datasheet”, DS5134 for values of these timing parameters.
  • Page 42 6: BSIO Interface Figure 6.2 BµILD Serial Input Output (BSIO) Block Diagram GP4020 GPS Baseband Processor Design Manual...
  • Page 43 SS0 - SS1 SCLK SLAVE DATA IN SLAVE DATA OUT Figure 6.4 BSIO Write Operation Timing Diagram GP4020 GPS Baseband Processor Design Manual (N-5)SCLK TSERSU Note: Last SCLK cycle shown for reference only - not actually generated in BSIO TSERCDC (N-5)SCLK TSERDOD...
  • Page 44 SDIO DATA OUT SDIO RXD0 DATA IN Figure 6.5 BSIO Bit timing options GP4020 GPS Baseband Processor Design Manual TXDn RXD0 WRPOL = 1, RDPOL = 0, CYCDELAY = 0 TXDn RXD0 WRPOL = 1, RDPOL = 0, CYCDELAY = 1...

  • Page 45: Bsio Frequency Divider

    Slave Select Register (High if CPOL = 1). The Timing Diagram for this is shown in Figure 6.7 below. Note that if there is a change in the polarity of SCLK_INT, when selecting between two devices, the start of the first operation can be delayed as required. GP4020 GPS Baseband Processor Design Manual 9 BIT SCLK_CTR...

  • Page 46: Bsio Slave Select Logic

    Slave Note: ENPOL = 0000 Figure 6.7 BSIO SCLK Polarity Timing SSEL Reserved Reserved Reserved Reserved Reserved Reserved SLAVE SELECT LOGIC Figure 6.8 BSIO Slave Select Logic GP4020 GPS Baseband Processor Design Manual Enable Enable Slave Slave SS0_OP - SS1_OP...

  • Page 47: Bsio Interrupt Control

    The internal output WFIFO_WR will be set when the first word in an Operation is written to the FIFO, and is cleared at the end of an Operation. Whilst in Standard Mode, it will be used to set the OPERATION bit in the Status Register. GP4020 GPS Baseband Processor Design Manual CWORD_WR CONTROL...

  • Page 48: Bsio Read Buffer

    The Sequencer consists of Read/Write Counters and Control logic as shown in Figure 6.11 below. 32 BIT BUS RX_CLK FIFO 2 X 32 bits Figure 6.10 BSIO Read Buffer GP4020 GPS Baseband Processor Design Manual RECEIVE SHIFT REGISTER RDREADY READERR...
  • Page 49 Write Buffer in Standard Mode, • the Control Word is written in Page Mode. The bit is cleared after the last bit of the current operation has been sent or received. GP4020 GPS Baseband Processor Design Manual wfifo_wr shift_tx cword_wr...

  • Page 50: Bsio Registers

    SCLK. RDPOL, WRPOL and SSEL select the clock polarity for read and write cycles for each of the slave select outputs SS0 and SS1. 6.9 BSIO Registers The BSIO uses nine separate registers. The GP4020 BSIO Base Address is 0xE000 7000. Address Offset 0x000...
  • Page 51 SDIO pin will remain driven low if the last bit transmitted is '0'. Therefore, to do a Transmit followed by a Receive, you need to ensure that the last bit transmitted from the SDIO port on the GP4020 is a “1” (i.e.
  • Page 52 Table 6.4 BSIO Transfer Register Memory Offset 0x0008 Description Table 6.5 BSIO Mode Register Memory Offset (SLAVE0 = 0x0010, SLAVE1 Description Table 6.6 BSIO Slave Select Register GP4020 GPS Baseband Processor Design Manual Reset Value 00000 00000 00000 00000 Reset...
  • Page 53 WRREADYEN Write Ready Enable. Active High Interrupt Enable for the WRREADY bit in the Status Register Table 6.8 BSIO Interrupt Control Register GP4020 GPS Baseband Processor Design Manual Memory Offset - 0x0030 Description Table 6.7 BSIO Status Register Memory Offset - 0x0034...
  • Page 54 2- to 32-bits via the CWORD bits in the Mode Register. Table 6.10 BSIO Control Word Buffer Register Memory Offset - 0x0038 Description All = 0 Memory Offset - 0x003C Description All = 0 GP4020 GPS Baseband Processor Design Manual Reset Value Reset Value...

  • Page 55: 12-Channel Correlator (Corr)

    7 12-CHANNEL CORRELATOR (CORR) 7.1 Introduction The 12-Channel Correlator forms the GPS-specific module of the GP4020 GPS Baseband Processor. It comprises 12 parallel Spread-spectrum signal tracking modules, including Carrier offset mixers, C/A code generators and mixers, and 1ms Accumulate and Dump registers. Figure 7.1 below shows a block diagram of the correlator. It consists of the following blocks: 7.1.1...
  • Page 56 7: 12-Channel Correlator A<9:2> D<15:0> CLOCKS MULTI-PHASE CLOCKS MULTI-PHASE Figure 7.1 12-Channel Correlator Block Diagram GP4020 GPS Baseband Processor Design Manual...

  • Page 57: Status Registers

    The Bus Interface controls the transfer of data between the external 16-bit wide data bus and the internal 32-bit data bus. Apart from the code and carrier DCO increment values, all data transfers are 16-bits wide. Write GP4020 GPS Baseband Processor Design Manual...

  • Page 58: Uim Interface

    DUMP - Q PROMPT C/A CODE GENERATOR CODE SLEW CODE CODE PHASE COUNTER EPOCH COUNTERS 16 BIT ACCUMULATE AND DUMP - I PROMPT 16 BIT ACCUMULATE AND DUMP - I TRACKING GP4020 GPS Baseband Processor Design Manual DATA BUS DUMP...
  • Page 59 The Code DCO is similar to the Carrier DCO block. It is also clocked at the SAMPCLK frequency, and synthesises the oscillator required to drive the code generator at twice the required chipping rate. The nominal frequency of the GP4020 GPS Baseband Processor Design Manual Sequence...
  • Page 60 Codes, but are transmitted on the same frequency (L1 = 1575.42MHz). For the GP4020 to effectively de-modulate GLONASS signals, it would ideally need to have a separate set of RF signal inputs for each correlator channel, in order for it to differentiate between the different frequencies used by each GLONASS satellite.

  • Page 61: Software Requirements

    The GP4020 12-channel correlator can be operated in different ways dependent upon the GPS Receiver system required by the user. So to accommodate this and to allow dynamic adjustment of loop parameters, the GP4020 12-channel correlator has been designed to use software for as many functions as possible. This flexibility means that the device cannot be used without a microprocessor closely linked to it.
  • Page 62 Satellite Navigation message re-transmission (18 to 36 seconds). The 12-channel correlator on the GP4020 contains four different types of registers: •...
  • Page 63 Carrier DCO. Corrections to the Gold code phase smaller than a half chip cannot be done by programming CHx_CODE_SLEW registers in the Code Generator. This can be done by setting the GP4020 GPS Baseband Processor Design Manual...

  • Page 64: Signal Tracking

    'early minus late' Gold code to implement a null steering loop. Others use a dithering code that alternates between a code one-half chip late and a code one-half chip early. In the GP4020 12-channel correlator, the dithering rate is 20 ms (20 code epochs) each way, starting with Early after a reset, when this type of code is selected through the CHx_CNTL register.

  • Page 65: Controlling The 12 Channel Correlator

    Due to the receiver clock drifting with time, the clock-bias changes with time, and this must be tracked by the Navigation software. 7.4 Controlling the 12 Channel Correlator The following section describes typical methods for controlling the 12-channel correlator block in the GP4020. These include signal acquisition tracking and carrier phase measurement. 7.4.1...
  • Page 66 The reading of measurement data can be either interrupt driven or polled. For the interrupt driven method the microprocessor reads the ACCUM_STATUS_B or MEAS_STATUS_A register after each MEAS_INT, and if the TIC bit is set, subsequently reads the Measurement data. CHx_CARRIER_DCO_PHASE, GP4020 GPS Baseband Processor Design Manual CHx_CARRIER_CYCLE_HIGH,...

  • Page 67: Preset Mode

    Less the time between the correlation and the TIC clock phase that is before the accumulator latch phase (75ns). This gives a total Signal path delay of 400ns, less the SAMPCLK delay. GP4020 GPS Baseband Processor Design Manual Registers: CHx_CODE_DCO_PHASE,...
  • Page 68 TICs. For position smoothing all delta–ranges may be included in the input to the navigation filter, as that filter will perform a running average of the delta–ranges as well as the ranges. GP4020 GPS Baseband Processor Design Manual...

  • Page 69: Channel Correlator Interface Timing

    (in particular write to write cycle and write to read cycle). In the GP4020, it must be ensured that no attempts are made to access the 12-channel correlator for the 300ns following the end of a correlator write cycle.

  • Page 70: 12-Channel Correlator Register Maps

    7.6 12-Channel Correlator Register Maps The register map of the 12-Channel Correlator within the GP4020 is shown in Table 7.2 below. The Base Address for the GP4020 12-channel Correlator block is 0x4010 0000. The addresses are complete, and it should be noted that all the register addresses are 32-bit word–aligned but are 16-bits wide, i.e.
  • Page 71 It can be seen in Table 7.3 below that the addresses for the Channel Control registers are used to Control the channel in write mode, but give the channel Measurement Data when in read mode. GP4020 GPS Baseband Processor Design Manual Direction (see Table 7.3)
  • Page 72 4 MSBs of Carrier Cycle Count WRITE 16 LSBs of Code DCO phase increment READ Instantaneous values of 1ms and 20ms EPOCH counters. WRITE 1ms and 20ms EPOCH Counter load values. GP4020 GPS Baseband Processor Design Manual Function (test mode only) (test mode only)
  • Page 73 A write to the STATUS register (irrespective of what data is written) will latch the state of the various status flags into ACCUM_STATUS_A, ACCUM_STATUS_B, ACCUM_STATUS_C registers for all channels. This allows polling based, rather than Interrupt driven tracking scheme. GP4020 GPS Baseband Processor Design Manual Register Direction...
  • Page 74 (as bit 11 but for channel 4) (as bit 11 but for channel 3) (as bit 11 but for channel 2) (as bit 11 but for channel 1) (as bit 11 but for channel 0) Description GP4020 GPS Baseband Processor Design Manual Reset Value Reset Value...
  • Page 75 Channel specific bits of this register will not show their new value until after an active edge of ACCUM_INT or a write to the STATUS register. Disabling a channel will however, clear the bit immediately. GP4020 GPS Baseband Processor Design Manual Description...
  • Page 76 When these locations are written to, the data is irrelevant. Mnemonic 15:0 Not used Table 7.9 CORR CHx_ACCUM_RESET Register Description Offset <CHx_Accumulate> + 0x04 Description Reset Accumulator Status Registers GP4020 GPS Baseband Processor Design Manual Reset Value Reset Value 0x0000...
  • Page 77 Carrier DCO (4-bits are in HIGH and 16-bits in LOW). Refer to CHx_CARRIER_CYCLE_HIGH for more information Mnemonic 15:0 CHx_CARRIER_CYCLE [15:0] Table 7.12 CORR CHx_CARRIER_CYCLE_LOW Register GP4020 GPS Baseband Processor Design Manual Offset <CHx_Control> + 0x08 Offset (0x180 + 0x08) Offset (0x1C0 + 0x08) Description Offset <CHx_Control> + 0x18...
  • Page 78 Must be written before CHx_CARRIER_DCO_INCR_LOW values. Offset <CHx_Control> + 0x10 Offset 0x180 + 0x10 Offset 0x1C0 + 0x10 Description Bits 15:0 of the 26-bit Carrier DCO Increment Register GP4020 GPS Baseband Processor Design Manual Reset Value 0x000 Reset Value 0x0000...
  • Page 79 CHx_CODE_DCO_INCR register will generate a chip rate of 1.022999968 MHz. Mnemonic 15:9 Not used CHx_CODE_DCO_INCR [24:16] Table 7.16 CORR CHx_CODE_DCO_INCR_HIGH Register GP4020 GPS Baseband Processor Design Manual Description '0' when read Bits 9:0 of the 10-bit Carrier DCO Phase Count. Offset <CHx_Control> + 0x14 - Offset 0x180 + 0x14...
  • Page 80 Offset 0x2E0 + 0x0C Description More significant bits (25 to 18) of the Code DCO phase which is to be loaded at the next TIC event in PRESET mode. GP4020 GPS Baseband Processor Design Manual Reset Value 0x0000 Reset Value...
  • Page 81 DUMP and then cause the transfer of this new value into the counter. This situation may be avoided by synchronising the access with the associated CHx_NEW_ACCUM_DATA status bit. GP4020 GPS Baseband Processor Design Manual Read Offset <CHx_Control> + 0x04 Write Offset <CHx_Control>...
  • Page 82 Count, in steps of half a chip. Description '0' when read. Test register only. Indicates a non-zero result if read whilst actual slew occurs. Read Address Offset <CHx_Control> + 0x1C GP4020 GPS Baseband Processor Design Manual 1025.5 CHIPS DUMP TIME Reset Value...
  • Page 83 Mnemonic 15:14 Not used 13:8 CHx_20MS_EPOCH[5:0] Not used CHx_1MS_EPOCH[4:0] GP4020 GPS Baseband Processor Design Manual Description '0' when read. Instantaneous value of the CHx_20MS_EPOCH. Valid range = 0 to 49 '0' when read. Instantaneous value of the CHx_1MS_EPOCH Valid range = 0 to 19 Read Address Offset <CHx_Control>...
  • Page 84 It also is used to set-up either PRESET or UPDATE mode, and to select either SIGN0/MAG0 or SIGN1/MAG1 inputs from a RF Front-end (this feature not available on the 100-pin version of GP4020!). CHx_SATCNTL is a write–only register that can be written into at any time. Any modification to the content is effective at the next DUMP in UPDATE mode or at the next TIC in PRESET mode for all bits, apart from PRESET UPDATEB, which defines whether a channel is in PRESET or UPDATE mode.
  • Page 85 0x100 0x113 0x226 0x04C 0x098 0x130 0x260 0x267 Table 7.28 G2 LOAD settings required for C/A code generator, for valid PRN Numbers GP4020 GPS Baseband Processor Design Manual GPS PRN G2_LOAD GPS PRN Signal No [9:0] Signal No 0x338 0x270...
  • Page 86 SOURCESEL Selects which input source to be used by the channel, for test purposes only ( MAG1 and SIGN1 are NOT separately bonded out on 100pin GP4020 device). '0' = selects SIGN0 and MAG0 inputs. '1' = selects SIGN1 and MAG1 inputs, via GPIO[0] (pin 100) and GPIO[1] (pin 99), when GP4020 UIM_TEST mode enabled.
  • Page 87 Carrier DCO to the same frequency; adjust all selected channels by the same value, (such as a Code Slew to shift the code phases together to a new search area). GP4020 GPS Baseband Processor Design Manual Description Write Address Offset 0x1F4...
  • Page 88 ACCUM_INT Period = (PROG_ACCUM_INT + 1) * 7 /(40MHZ) Mnemonic 15:13 Not used 12:0 ACCUM_INT[12:0] Table 7.32 CORR PROG_ACCUM_INT Register Description Write Address Offset 0x1AC Description 13-bit ACCUM_INT down-count period value. GP4020 GPS Baseband Processor Design Manual Reset Value Reset Value 0x0B45...

  • Page 89: Reset_Control Register

    CHx tracking channel. It also resets the Accumulated Data flags, Code DCO and Carrier DCO accumulators, the I & Q accumulators, and the Code Phase Counter. A CHx_RSTB does not reset the Carrier GP4020 GPS Baseband Processor Design Manual Write Address Offset 0x1B4 Description Bits 20:16 of the 21-bit TIC Period Register.
  • Page 90 '0' = activate software reset of 12-channel correlator. Table 7.35 CORR RESET_CONTROL Register Description Channel 11, and resets the Accumulated Data flags, Code DCO and Carrier DCO accumulators, the I & Q accumulators, and the Code Phase Counter. GP4020 GPS Baseband Processor Design Manual Reset Value...

  • Page 91: Status Register

    '0X1X' = Channel 0 DUMP signal. Indicates when a DUMP event '010X' = Raw_Timemark output (NOT 1pps Timemark). '0001' = High ('1') output '0000' = Low ('0') output GP4020 GPS Baseband Processor Design Manual Description Table 7.36 CORR STATUS Register Write Address Offset 0x1F8 Description register.
  • Page 92 This bit sets the sign of the modulation of the test data generated when TEST_SOURCE is set. TEST_SOURCE '0' = Enable self-test generator '1' = Disable self-test generator (See Note 2) Description Write Address Offset 0x1F0 Description GP4020 GPS Baseband Processor Design Manual Reset Value Reset Value...
  • Page 93 Low. This allows the evaluation of the RF Front end SIGN (on channel 5) and MAG (on channel 11) duty cycles. The Front end to be tested is selected by the SOURCESEL bits in CH5_SATCNTL and CH11_SATCNTL. GP4020 GPS Baseband Processor Design Manual Description...
  • Page 94 = N MAG3 + N MAG1 , ACC11 = –3 * N MAG3 –N MAG1 = NSIGN1 / N = (N + ACC5) / 2N (nominally 0.50) = NMAG3 / N = – (N + ACC11) / 2N (nominally 0.30). GP4020 GPS Baseband Processor Design Manual...
  • Page 95 1PPS output without the assistance of the 1PPS Timemark generator, but the resolution of the Timemark will be 175ns which is often considered too slack for high precision time-keeping. In the GP4020, RAW_TIMEMARK can be accessed through: DISCOP, if the SYSTEM_SETUP register is configured to output RAW_TIMEMARK, and DISCOP_MUX in the PCL IO_REV register is set to output DISCOP onto GPIO[5] (pin 93 (100-pin package));...
  • Page 96 7: 12-Channel Correlator This Page intentionally left blank. GP4020 GPS Baseband Processor Design Manual...

  • Page 97: Dma Controller (Dmac)

    8 DMA CONTROLLER (DMAC) The GP4020 contains a DMA controller, which assists the processor to move large blocks of data around a system. Data transfer between memory blocks, or between memory and a peripheral can be extremely cycle-intensive for a processor.
  • Page 98 Set-up the source of DMAC Triggering (i.e. the prompt that initiates the DMA transfers following the DMAC program cycle). The GP4020 DMAC can take triggers from both software and Hardware sources. For DMA Fly-by transfers using UART 1 as a peripheral, DMAC Channel 1 must be used. Similarly if using UART 2 as a peripheral, DMAC Channel 2 must be used.
  • Page 99 Clear to ”0” the Transfer Type bit (bit 10) to allow Packet Data Transfers to occur. Packet Data transfers must be used in Single-addressed transfers with the GP4020 UARTs, as the UARTs do not have the bandwidth to cope with data transfers at full BµILD bus bandwidth (28MHz x 4 = 112Mbytes/second).
  • Page 100 Refer to Section 8.3 "DMAC Triggering" on page 99 for information of how both Software and Hardware triggering operates with a DMA transfer. So if the transfer is to be for 10,000 8-bit bytes, the setting GP4020 GPS Baseband Processor Design Manual...
  • Page 101 Set up example of DMAC for a Fly-by transfer from UART RX to memory The following example shows the sequence of events required to program and enable the GP4020 DMAC to provide a Fly-by data transfer from a UART Receiver input to an area of memory.
  • Page 102 Clear to ”0” the Transfer Type bit (bit 10) to allow Packet Data Transfers to occur. Packet Data transfers must be used in Single-addressed transfers with the GP4020 UARTs, as the UARTs do not have the bandwidth to cope with data transfers at full BµILD bus bandwidth (28MHz x 4 = 112Mbytes/second).

  • Page 103: Dual-Addressed (Buffered) Data Transfers

    Set up example of DMAC for a Dual-Addressed transfer between two memory locations. The following text shows an example of the sequence of events required to program and enable the GP4020 DMAC to provide a Dual-Addressed Data transfer between two contiguous areas of memory. A Dual-addressed transfer uses both DMAC channels simultaneously, one to read from one location into a "buffer", and the other to...
  • Page 104 (bit 16) of the DMAC CSR; if NOT required, Clear this bit to "0". 2.1.11) Clear to “0” the Bus Lock bit (bit 17), to prevent the DMAC from being interrupted during a transfer from a Higher priority BµILD Bus Master (e.g. ARM7TDMI, SSM) GP4020 GPS Baseband Processor Design Manual...

  • Page 105: Dmac Triggering

    DMAC Channel 2 can only be hardware triggered from UART2, and no other source. The DMAC trigger is actually configured by the type of interrupt set-up in the UART 2 either on Transmit Buffer Empty, or Receive Buffer Full. GP4020 GPS Baseband Processor Design Manual...
  • Page 106 BµILD bus to the ARM7TDMI. Otherwise, when the number of transfers defined in the Base Transfer Count Register (BTR) has been completed, the DMAC will clear the Software Request bit (CSR bit 2) to "0". GP4020 GPS Baseband Processor Design Manual...

  • Page 107: Cautionary Notes

    8.4.2 ARM FIQ Promotion The ARM7TDMI has the lowest priority on the GP4020 BµILD bus, under the DMA and SSM blocks (refer to Section 2.5 in the Firefly MF1 Core Design Manual (DM5003) for more information). When the DMAC is undertaking a data transfer, the DMAC has priority over the ARM7TDMI.
  • Page 108 8: DMA Controller This Page intentionally left blank. GP4020 GPS Baseband Processor Design Manual...

  • Page 109: General Purpose Input Output (Gpio) Interface

    9.1 Introduction A set of 8 general purpose static input output logic lines are included in the GP4020 to allow multiple static data to be provided to external features, or allow multiple input data lines to be read. The GPIO pins are multiplexed by the Peripheral Control Logic (PCL) between the BµILD Serial Input Output (BSIO) lines, and control lines to the...

  • Page 110: Write Cycle

    Figure 9.2 GPIO Pad Cell Configuration Valid Bus hold Driven Read Cycle GP4020 GPS Baseband Processor Design Manual Bus hold Valid Bus hold Driven Write Cycle...

  • Page 111: Initialisation

    '0' on all bits of both the INPUT and OUTPUT Registers. iii) Tri-state the BµILD Bus signal drivers. All other B_MODE states are ignored (normal run state assumed). 9.3 GPIO Registers The GP4020 GPIO interface has a Base Address of 0xE000 5000. Address Offset Register 0x000 Direction...
  • Page 112 GPIO pin. (i.e. GPIO_OUTPUT[4] maps to GPIO[4] (pin 95 (100-pin package))). When configured as an output, a "1" drives a High output, a "0" drives a Low. Table 9.5 GPIO_OUTPUT Register GP4020 GPS Baseband Processor Design Manual Reset Value Reset Value...

  • Page 113: Interrupt Controller (Intc)

    10 INTERRUPT CONTROLLER (INTC) The Interrupt Controller can manage upto 32 Interrupt sources. In the GP4020, 18 interrupt sources are present: 16 internal sources, and 2 external sources. The Interrupt controller processes these raw interrupt sources down into two main CPU interrupts. These are called FIQ and IRQ. The names come from the two prioritised interrupts on the ARM family of processors.
  • Page 114 In the GP4020, the interrupt channels are allocated as shown in Table 10.2 below. In each case the application software for the GPS receiver will need to configure the interrupt channels as shown. The GP4020 Interrupt Controller has a Base Address of 0xE000 6000.

  • Page 115: Memory Peripheral Controller (Mpc)

    11.2 GP4020 Memory Area 1 Configuration GP4020 Memory Area 1 is at the base of the Address Map (0x0000 0000 through to 0x000F FFFF), and is typically shared between an internal BOOT ROM and an external 16-bit FLASH EPROM via chip-select line NSCS[0]. The control of whether the BOOT ROM or the External memory space is selected, is controlled by the state of MULTI_FNIO (pin 54 (100-pin package)) at chip reset.

  • Page 116: Gp4020 Memory Area 2 Configuration

    Firefly in time. 11.3 GP4020 Memory Area 2 Configuration GP4020 Memory Area 2 is specified by addresses 0x2000 0000 through to 0x200F FFFF, and is typically used by high-speed external 16-bit SRAM via chip-select line NSCS[1].

  • Page 117: Gp4020 Memory Area 3 Configuration

    11.4 GP4020 Memory Area 3 Configuration GP4020 Memory Area 3 is a special case where a number of internal components share resources with an External chip select line – NSCS[2A]. The 12-channel correlator which resides in Memory Area 3 uses a re-timing UIM interface, to retime data from Firefly speed (any frequency from the System Clock Generator (SCG)) to the Correlator speed (nominally 40MHz).

  • Page 118: Gp4020 Memory Area 4 Configuration

    11.5 GP4020 Memory Area 4 Configuration GP4020 Memory Area 4 is used to access the internal SRAM only in the GP4020, and NO other components. The internal SRAM is configured as 2k x 32-bit data or 8k bytes and can be configured to have either 8-bit, 16-bit or 32- bit data width.

  • Page 119: Peripheral Control Logic (Pcl)

    Also, if POWG_EN (bit 15 in the POW_CNTL register) is set to '1', the POWER_GOOD line will also power down the whole GP4020 chip, except for the Real Time Clock and Data Retention register. A reset of the Firefly MF1 and the 12-channel correlator will occur, along with a power-down of most GP4020 functions. Refer to Section 12.6 "Chip-wide Power Control modes"...
  • Page 120 Reset Button. A system reset will occur as shown in Figure 12.6 on page 117, if this pin is taken Low (i.e. '0'). This is the only reset source by which ALL GP4020 registers, which can be reset, are completely reset (except for the Data Retention Register in TIC_RET within the 1PPS Timemark Generator, and the Real Time Clock Counters).
  • Page 121 The reset occurs as shown in Figure 12.8 on page 117. The reset state for this signal is '0' for a read and '1' for a write. Figure 12.2 Peripheral Control Logic - Reset Logic GP4020 GPS Baseband Processor Design Manual...
  • Page 122 Front-end fails, and RF_PLL_LOCK is low for upto 5ms after power-up. 3 CYCLES Any Freq 3 CYCLES Any Freq derived from an RF Front-end. POWER DOWN MODE 3 CYCLES - 150ns CLKI / CLKT UNDEFINED GP4020 GPS Baseband Processor Design Manual 20MHz...
  • Page 123 NPOR_RESET. Used to reset all registers in the Peripheral Control Logic, System Clock Generator and 1PPS Timemark Generator, and some registers in the Real Time Clock (see below for exceptions). It is derived from GP4020 GPS Baseband Processor Design Manual 3 CYCLES - 150ns...

  • Page 124: Pll Enable Logic

    PLL_ENABLE uses a delay of seven cycles of the Real Time Clock (upto 183µs) to ensure that the PLL clock output is only enabled after the PLL output frequency is stable on the GP4020 chip. The timing diagram in Figure 12.9 below illustrates this.

  • Page 125: Multiplex Logic

    12.4 Multiplex Logic The standard GP4020 is packaged in a 100-pin package. Ten additional signals can be accessed non- simultaneously via some configurable Input / Output lines, as shown in Figure 12.10 below. The GP4020 pins that allow this are: DISCIO (pin 55 (100-pin package)).
  • Page 126 RF Front-end PLL. UART_CLK output. '0' output '1' output Table 12.2 MULTI_FNIO pin signal multiplex options CLK100KHz UART_CLK BSIO_MUX[1:0] MFNIO_CFG[2:0] RF_PD RF_SLEEP GPIO[0:7] DISCIO_CFG[2:0] DISCIO Function MULTI_FNIO Function GP4020 GPS Baseband Processor Design Manual MULTI_FNIO_READ MULTI_FNIO DISCIO_READ DISCIO...

  • Page 127: Interrupt And Wake-Up Logic

    WAK_UART DISCIP1 WAK_DISC WATCH_INT NRESET Figure 12.11 Peripheral Control Logic - Peripheral Interrupt and Wake-up control logic GP4020 GPS Baseband Processor Design Manual BSIOCLK BSIO_MUX[1:0] = '10', '01', '11' SIGN 1 UIM_TEST = '1' (i.e. TEST = High TESTMODE = High)
  • Page 128 RTC_CMP_INT line goes High. Essentially, this is a variable length wake-up timer facility, which allows blocks of the GP4020 to be put to sleep for any period from between 30.5us and 256s. This feature can be enabled / inhibited using RCMP_INT_EN in the PER_STAT register.

  • Page 129: Chip-Wide Power Control Modes

    12.6.1 Full Power-Down A Full Power-down of the GP4020 (i.e. Clocks removed from the whole chip, except for the Real Time Clock) can be made to occur, if a '1' is written to the POWG_EN bit (POW_CNTL[15]), and the POWER_GOOD input (pin 64 (100-pin package)) is set Low.

  • Page 130: Peripheral Control Logic Registers

    (Note: Setting IDDQ_TEST to High is NOT a mode required in normal operation, and is primarily involved with manufacturing test of the GP4020. It is used to disable the Crystal Oscillator in the Real Time Clock, and the Processor Clock Crystal Oscillator, the PLL and the 40MHz Low Level Differential Input cell in the System Clock Generator).
  • Page 131 12.7.1 PCL Power Control Register - POW_CNTL - This register is used to configure Power Control modes in the GP4020, and configure signal inputs and outputs for the PLL in the System Clock Generator. This is primarily a write-only register, but on reading the register, the settings made by the previous Write can be observed.
  • Page 132 '0' = re-enable the Differential Block and apply an active Low power-on signal to the RF Front-end (via DISCIO (pin 55 (100-pin package)), if so configured (ref. IO_REV register). Description Table 12.5 PCL POW_CNTL Register GP4020 GPS Baseband Processor Design Manual Reset Value...
  • Page 133 15:10 CHIP_REV[5:0] Read Only Chip Revision number (MSB = Bit 5). '000000' = Rev 0. First version of GP4020 ‘000001’ = Rev 1. Second version , etc. EXT_NCS0 '1' = Disable Internal Boot ROM, at reset, if MULTI_FNIO (pin 54 (100-pin package)) is set High.

  • Page 134: Test Mode

    12.7.3 PCL Input Read register - IP_READ - This Read-only register allows the most recent state of a number of GP4020 input signals to be read. Mnemonic PER_INT PER_INT interrupt line, sourced by Peripheral Control Logic to Firefly MF1 core.
  • Page 135 '1' = Reset due to RF_PLL_LOCK = Low, has occurred since last CLR_RST or NSRESET clear-event. (See Note 2) ‘0’ = No reset event due to RF_PLL_LOCK has occurred GP4020 GPS Baseband Processor Design Manual Description ALL Interrupt Read bits). ALL "Reset-Source" Read bits).
  • Page 136 Bits 4:0 reset by setting CLR_RST ='0' or NSRESET='0' only. All other reset sources have no effect. Description Table 12.8 PCL PER_STAT Register GP4020 GPS Baseband Processor Design Manual Reset Value...

  • Page 137: Real Time Clock (Rtc)

    The Pierce oscillator relies on a resistor to provide negative feedback, which is set by a resistor. The 32kHz oscillator requires a resistor of high value (10MΩ), and is needed externally to the GP4020. A 32kHz crystal has a high Effective Series Resistance (ESR), in the region of 40kΩ. The nominal loading capacitors C1 and C2 for the...

  • Page 138: Real Time Clock Registers

    Table 13.1 Real Time Clock Register Map Whilst most of the registers in the GP4020 can be reset by a reset event (POWER_GOOD, RF_PLL_LOCK, SFT_RESET, NSRESET and Watchdog), there are a couple of areas where a reset will only occur by writing a ‘0’...
  • Page 139 RTC Second Counter are equal, and the values in the COMP_RTCP register equals the 15-bits of the RTC Pre-scaler, an Interrupt signal RTC_CMP_INT is produced. The comparator is disabled during a write to this register. GP4020 GPS Baseband Processor Design Manual Description Table 13.2 RTC_PRE Register seconds = 16.7Mseconds = 194days.
  • Page 140 Note: This data ONLY reset by writing ‘0’ to bit 0 of RTC_PRE. NOT resettable by any other reset source. COMP_RTCS[7:0] 8-bit RTC Counter Comparison Value. Most Significant Bit = Bit 7. Description Table 13.5 RTC COMP_RTCS Register GP4020 GPS Baseband Processor Design Manual Reset Value 0x00 0xFF...

  • Page 141: System Clock Generator (Scg)

    14 SYSTEM CLOCK GENERATOR (SCG) 14.1 Introduction The System Clock Generator (SCG) is used to generate two clock signals for the GP4020: • The UART_CLK which runs UART2 continuously and produces the BµILD Clock. The BµILD Clock runs all the BµILD bus components, including the Firefly MF1 core with the ARM7TDMI microprocessor via a disable gate...

  • Page 142: 40Mhz Low Level Differential Input

    If using the GP4020 in conjunction with a GP201x RF Front-end, care should be observed to ensure that the DC bias applied to the CLK_T (pin 58 (100-pin package)) and CLK_I (pin 59) inputs of the GP4020 is set correctly. The maximum output bias of the GP201x RF Front end on the OPCLK+ and OPCLK- signals is Vcc - 0.8V, which could...

  • Page 143: Processor Crystal Oscillator

    If the RF Front-end is to be used in a Power-down or sleep mode; powering down the RF Front-end will disable the 40MHz from the RF Front-end and also disable the 40MHz Low level Differential block, leaving the GP4020 potentially locked up without any system clock;...
  • Page 144 The GP4020 presents a noisy load to any analogue signals connected to it. As the TCXO drives the RF Front-end PLL, it is imperative to ensure that the RF PLL does not get interference via the TCXO from the GP4020. The GPS system performance can be severely degraded if the RF Front-end cannot produce an accurate set of Local- Oscillator signals for the IF down-conversions.

  • Page 145: Phase Locked Loop (Pll)

    10.0MHz TCXO 10uF 100nF Figure 14.4 Connections of a TCXO frequency reference to the GP4020 Processor Crystal Oscillator 14.4 Phase Locked Loop (PLL) 14.4.1 Features • Output clock frequencies from 10MHz to 250MHz • Phase alignment offset: • Phase alignment jitter: •...
  • Page 146 The PLL in the GP4020 has been configured for Clock Multiplication, where the output frequency is a multiplied version of the reference input clock frequency. To achieve clock multiplication, a programmable divider is used in the feedback path of the PLL, as shown in Figure 14.6 below.
  • Page 147 CLK_I and CLK_T signals (40MHz from a RF Front-end) are shown in Table 14.2 below. Additional frequencies beyond the specified maximum speed for the GP4020 are also shown in Table 14.3 on page 143. Whilst in normal operation, it is not recommended to exceed the maximum specified operating frequency, the numbers in this table are shown for experimental purposes.
  • Page 148 This can potentially produce spurious radiation at any of the RF Front-end IF frequencies, or, in some cases in the Receive RF L1 band. Whilst every attempt has been made to ensure that the GP4020 will respond at many key UART_CLK frequencies, it cannot be ruled out that there will be values where self-generated interference occurs.
  • Page 149 ALL Wake-up event control bits are de-activated (i.e. bits 13:11 are set to ‘0’) ALL Sleep enable bits are de-activated (i.e. bits 10:8 are set to ‘0’) Processor Crystal Oscillator block is disabled (i.e. bit 1 is set to ‘0’). GP4020 GPS Baseband Processor Design Manual Charge Pump SYNC Freq.
  • Page 150 00000 01011 00001 10000 00000 00101 00001 01000 00010 01011 00011 01101 00100 10000 00001 00100 00010 00101 00011 00111 00100 01000 00101 01001 GP4020 GPS Baseband Processor Design Manual Comments VCO Freq. Worst case Range settling time. VCOD[1:0] (µs)

  • Page 151: System Clock Generator Power Consumption Issues

    PLL block; enabled or disabled Input frequency and division ratio of the UART_CLK divider block, after the PLL; the higher the input frequency and the higher the output frequency, the more current consumed. GP4020 GPS Baseband Processor Design Manual Prog. Charge...

  • Page 152: System Clock Generator Registers

    12.7.1 "PCL Power Control Register - POW_CNTL - Memory Offset 0x008" on page 125, but the System Clock Generator functions, associated with this register are documented here. All registers in Table 14.6 below can be accessed as either byte, half-word, or word. The GP4020 System Clock Generator Base Address is 0x4010 1000. Address Register...
  • Page 153 (100-pin package)), if so configured (ref. IO_REV register). Note: Wake up event: event which reverses the Sleep activation mode. These are explained in Section 12.5 "Interrupt and Wake-up logic" on page 121. GP4020 GPS Baseband Processor Design Manual Description Table 14.7 POW_CNTL Register Reset...
  • Page 154 These bits [15:13] are NOT latched in the PLL_CNTL register. All the other bits in the PLL_CNTL register, will be updated at the negative edge of UART_CLK, while the write to the PLL_CNTL address continues). Memory Offset 0x00A Description Table 14.8 PLL_CNTL Register GP4020 GPS Baseband Processor Design Manual Reset Value Note 1 Note 1...

  • Page 155: 1Pps Timemark Generator

    TCXO Receiver Clock Reference (RCR) on a GPS receiver, via numerous frequency dividers in the RF Front-end and GP4020 itself. Consequently, without the use of GPS software to align Timemark to TIC, the Raw Timemark is only as accurate as the frequency stability of the TCXO.
  • Page 156 15: 1PPS Timemark Generator DATA & ADDRESS Figure 15.1 1PPS Timemark Generator, with interface to 12-channel correlator block GP4020 GPS Baseband Processor Design Manual...
  • Page 157 The TIC period can only be adjusted in steps of 175ns ( 7 / 40MHz = 175ns). Therefore, the closest that TIC can be set to 0.1000000s is either 0.0999999s or 0.100000075s. The GP4020 employs some additional fine-resolution adjustment techniques to effectively reduce the TIC period adjustment resolution from 175ns to 25ns; these techniques are indicated later in this section.

  • Page 158: Issues To Consider When Aligning Timemark To Utc

    TIMEMARK DELAY Figure 15.3 Typical timing relationship between UTC, TIC and Timemark, for small Timemark Delay values The GP4020 employs two separate sets of logic to allow the Timemark output to be aligned to UTC to a resolution of 25ns:...

  • Page 159: Utc Error Budget

    For example: 1ppm/°C x 5°C/min x 1sec = (b) Due to bias in drift estimation about 50ns max. (rough guess) GP4020 GPS Baseband Processor Design Manual 83ns for a temperature step change or 41.5ns (rounded to 50ns) for a linear ramp.
  • Page 160 2ns. The main delay will be due to getting the Timemark signal off-chip. With the GP4020 using a CLAOP01L1 output for Timemark, the delay through this port is approx. 11ns with a 10pF external load, and 19ns with a 50pF external load.

  • Page 161: Fine-Resolution Timemark Setting, Using Tic Period Slewing

    15.4 Fine-resolution Timemark setting, using TIC period slewing 15.4.1 Functional description The GP4020 includes some logic within the 1PPS Timemark Generator which allows the TIC period to be specified to a resolution of 1 M_CLK cycle (25ns), without significantly affecting the existing logic in the correlator core.
  • Page 162 '00'. If it is left in this condition, the only observable difference to the TIC and TIMEMARK behaviour (between GP4020 and GP2021) is the additional half M_CLK cycle delay on TIMEMARK output. 15.4.3 Timemark setting example 1; TIC period Slewing with No Receiver Clock Offset It is assumed that the Receiver Clock Reference (i.e.
  • Page 163 There are eight TIC events out of 10, where the TIC period needs to be adjusted, appearing as coarse 'Phase_clock' corrections inside the correlator core. Timemark output is corrected to the appropriate M_CLK cycle. GP4020 GPS Baseband Processor Design Manual Offset...
  • Page 164 100000 100000 Offset Over Next TIC Cumulated delay flow Overflow Period (µs) (ns) 99999.975 99999.975 99999.975 99999.975 99999.975 GP4020 GPS Baseband Processor Design Manual Overflow Total delay (ns) Delay (ns) 1050 1050 1225 1225 1400 1400 1575 1575 1750 1750...

  • Page 165: Fine-Resolution Timemark Setting, Using Timemark Delay Counter

    15.5.1 Functional Description In addition to the TIC slewing logic, described earlier, the GP4020 also includes an alternative method for generating delays of 25ns resolution to the TIC signal, without needing to change the TIC period. Since TIC is used to time most functions within the 12-channel correlator, this can be a very useful method for generating a 1PPS Timemark if the GPS software needs to keep the TIC period constant.
  • Page 166 80040 9999.990000 10000 440000 10000.989999 10001 440040 99998.900001 99999 4039960 99999.900000 100000 4040000 99999.9999999 40004 100000.9999989 40044 GP4020 GPS Baseband Processor Design Manual TIM_DEL TIM_DEL 0x9C40 0x40 0x9C68 0x40 0x9C90 0x40 0x9CB8 0x40 0xABE0 0x40 0xAC08 0x40 0xFFF0 0x40 0x0018...
  • Page 167 TIC, when the Counter delay can be rolled over, and a TIC will be skipped by withholding the TIM_DEL register value. In this instance, the TIC skip will occur once every 285,000 TICs (approx. every 8 hours), as shown in Table 15.7 below. GP4020 GPS Baseband Processor Design Manual TIC Time (s) Required...
  • Page 168 35000 1440000 10000.9649965 35003.5 1440140 28570.9000015 99998.5 4039940 28571.899998 100002.0 4040080 28571.99999765 2.35 40094 28572.99999415 5.85 40234 GP4020 GPS Baseband Processor Design Manual TIM_DEL TIM_DEL_ 0x9C40 0x40 0x9CCC 0x40 0x9D58 0x40 0x9DE4 0x40 0xD2F0 0x40 0xD37C 0x40 0xFFC8 0x40 0x0054...

  • Page 169: Data Retention Register

    The 1PPS Timemark Generator includes a Data Retention register (TIC_RET[15:8]). This is an 8-bit register, which is NOT reset by any control signals from within the GP4020, and can only be reset by a chip power failure, or by writing a new value to it.

  • Page 170: 1Pps Timemark Generator Registers

    15.7.1 1PPS Timemark STATUS Register - PER_STAT - This register is used to control Interrupts and Resets within the GP4020, and most of the controls are handled within the PCL block. The 1PPS Timemark generator uses 2-bits from this register as write bits for the Control of the Timemark Overflow Control block.
  • Page 171 This register combines control and monitor lines for the 1PPS Timemark Generator TIC period slewing logic, with an 8-bit data retention register. Note: The Data Retention register bits in the TIC_RET register are NOT reset by any reset event. This can only be cleared by writing ‘0x00’ or powering off GP4020. Mnemonic 15:8 RETEN[7:0] Data Retention Register.
  • Page 172 Period Slewing logic. 6 MSBs of number of M_CLK clock cycles by which TIC should be delayed before a Timemark Pulse is produced, and completed. Most Significant Bit = Bit 5. GP4020 GPS Baseband Processor Design Manual Memory Offset Reset Value 0x00...

  • Page 173: Up-Integration Module (Uim)

    The GP4020 contains the Firefly MF1 core, within which is a Memory Peripheral Controller (MPC) which contains a module called the Up Integration Module (UIM). Within the GP4020, the UIM is used to interface the Firefly MF1 core via the MPC to the following internal memory mapped components: •...
  • Page 174 16: Up-Integration Module This Page intentionally left blank. GP4020 GPS Baseband Processor Design Manual...

  • Page 175: Universal Asynchronous Receiver Transmitter (Uart)

    • Digital input filter to improve noise immunity The GP4020 incorporates a standard UART as part of the Firefly MF1 Core and an additional UART that is similarly configured, except for the following differences: UART1 is clocked by the Firefly BµILD_CLK, which can be disabled by the F_SLEEP function (refer to Section 12.5 "Interrupt and Wake-up logic"...
  • Page 176 The Baud-rate needs to be only approximately correct to allow reliable transmission of data to and from a UART. With this in mind, the baud-rates that can be achieved will be influenced directly by the frequency that the GP4020 System Clock Generator will be asked to run at. There will always be an error in the baud-rate, but this can be minimised by selecting the correct combination of values.
  • Page 177 Value 1200 2400 4800 9600 19200 38400 57600 76800 115200 Table 17.4 UART baud-rate settings with UART_CLK (BµILD_CLK) frequency = 23.75MHz GP4020 GPS Baseband Processor Design Manual Reference Baud Rate Prog. Clock (MHz) Ratio Value 2.65625 137.34635 5.3125 137.34635 10.625 137.34635...
  • Page 178 6.875 178.03646 13.75 178.03646 27.5 178.03646 27.5 88.518229 27.5 43.759115 27.5 28.83941 27.5 21.379557 27.5 13.919705 GP4020 GPS Baseband Processor Design Manual Programmed Baud Rate Baud Rate Error (%) 1198.236 0.147 2396.472 0.147 4792.945 0.147 9585.89 0.147 19290.12 -0.469 38109.76 0.756...
  • Page 179 Table 17.9 UART baud-rate settings with UART_CLK (BµILD_CLK) frequency = 30MHz Note: The data supplied in Table 17.10 and Table 17.11 below is provided for information only. Operating the GP4020 UART_CLK at a frequency above 30MHz is NOT recommended for normal operation. Baud Rate...

  • Page 180: Connections To The Bµild Bus And The Firefly Mf1 Core

    Table 17.11 UART baud-rate settings with UART_CLK (BµILD_CLK) frequency = 35MHz 17.3 Connections to the B µ ILD bus and the Firefly MF1 Core The GP4020 UARTs are configured such that UART1 is a standard Firefly MF1 component, and UART2 is also connected to Firefly via the external BµILD bus.
  • Page 181 17: UARTs This Page intentionally left Blank GP4020 GPS Baseband Processor Design Manual...

  • Page 182: Watchdog Timer (Wdog)

    POW_CTRL register in the PCL block) to a Logic '1'. Either a time-out failure signal is triggered by the 8-bit timer expiring, or a register bit set to raise the signal. In either case this signal is intended to shut off the GP4020 in order to reset it.

  • Page 183: Operational Description

    Write the “Restart key” to the Watchdog RESTART register (see below for details); Once the watchdog is enabled, it cannot be disabled without resetting the GP4020. However, the watchdog can be held off if the Watchdog RESTART key will need to be written to the RESTART register.

  • Page 184: Watchdog Register Map

    Watchdog Time-out period is: In a GPS system using the GP4020, it is recommended that the Interrupt service routine which is generated in software allows for the fact that the Watchdog Interrupt should be serviced quickly, in order to avoid a complete chip reset.
  • Page 185 WDOG re-start or a system reset. After reloading the WDOG counts from this value down towards zero. Watchdog Primary Counter Read Register - READ - 18.3.3 Mnemonic 31: 0 PC_READ GP4020 GPS Baseband Processor Design Manual Memory Offset 0x000 Description Description Table 18.3 Watchdog RELOAD Register Memory Offset 0x008 Description Current primary counter read value.
  • Page 186 Watchdog TEST Register - TEST - 18.3.5 This register is only accessible when the GP4020 is put into TEST mode (i.e. ‘TEST’ (pin 67 (100-pin package)) is set to Logic ‘1’, and ‘TESTMODE’ (pin 74 (100-pin package)) is set to Logic ‘0’).

  • Page 187: Address Maps

    0x4000 0000 and 0x5FFF FFFF, including the internal logic blocks as defined below: • (System Address Bit 20 = 1 AND System Address Bit 12 = 0) selects the GP4020 Correlator. • (System Address Bit 20 = 1 AND System Address Bit 12 = 1) selects the GP4020 Peripherals (Peripheral Control Logic, Real Time Clock, System Clock Generator, and 1PPS Timemark Generator).
  • Page 188 Table 19.3 GP4020 Memory Area 3 Addressing, with modified NSCS[2A] logic Use a GPIO line from GP4020 to externally gate NSCS[2A]. This will allow the maximum utilisation of the external Memory Area 3 space, but requires software to configure the GPIO line, which could be inefficient.

  • Page 189: System Address Map

    0xE001 9000 - 0xE001 9FFF All other areas in the range : Further details on how to configure all the GP4020 Memory Areas, is described in Section 11 "MEMORY PERIPHERAL CONTROLLER (MPC)" on page 109. Further details on Wait-state Generation can be found in Section 3.3.3 of the “Firefly MF1 Core Design Manual”...
  • Page 190 19: System Address Map This page intentionally left blank. GP4020 GPS Baseband Processor Design Manual...

  • Page 191: Input / Output Pin Characteristics

    The data shown here should be used in conjunction with the data in the datasheet specified above. 20.1 Pin Types The definitions of the type of each pin for the 100-pin GP4020 is shown in Table 20.1 below, with some additional notes relating to them. Pin Name...
  • Page 192 CLAIP1NR CLAOP01N CLAIP1NR CLGOSC1016 CLGOSC1016 CLAIP1GD CLALLVP CLAOP01L1 CLHIDDQ CLALLVM CLGOSC32K CLGOSC32K CLAIP1NR CLAIP1NR CLAOP03L1 GP4020 GPS Baseband Processor Design Manual Pull-up/ - Tri- Notes down state None None None None None Note 3 2, 3 None Note 3 2, 3...

  • Page 193: Input Delays

    Pin set to be High Impedance (Tri-state) when GP4020 in Test Mode 20.2 Input Delays The following tables show the delays for all Logic Inputs on the GP4020. The delays quoted below are shown at midpoint temperature (+25°C), supply voltage (+3.3V) and silicon process for all input lines in the GP4020.

  • Page 194: Tolerant Inputs

    0.60 20.3 Output Delays All delays quoted below are shown at midpoint temperature (+25°C), supply voltage (+3.3V) and silicon process for all logic / data output lines in the GP4020. D → OP ↑ Key: signifies Time from Data in going High, to Output going High D →...
  • Page 195 D → OP ↓ 8.09 9.52 T → OP ↑ 6.32 8.02 T → OP ↓ 8.09 9.51 Table 20.7 X03 Slow L1 3.3V Output delays GP4020 GPS Baseband Processor Design Manual Input edge 1.5ns Load (pF) 8.89 11.75 15.76 5.55 6.72 8.60 11.18...

  • Page 196: Cell Dc Characteristics

    6.91 8.49 11.04 14.33 6.30 CLAIO1HD01N, CLAIO1HD03N, CLAIO1NR01N, CLAIP1GD, CLAIP1GU, CLAIP1NR SCJIO1NR01N, SCJIP1NR, CLAOP01L1, CLAIO1HD01N, CLAIO1NR01N, CLAOP01N, SCJIO1NR01N CLAOP03L1, CLAIO1HD03N, CLAOP03N GP4020 GPS Baseband Processor Design Manual Input edge 1.5ns Load (pF) 6.72 8.62 11.48 15.49 7.56 9.42 11.99 15.30 8.08...
  • Page 197 High Output Level – CMOS VOH Low Output Current IOL High Output Current IOH Low Output Current IOL High Output Current IOH Table 20.9 Input & Output Cell DC Characteristics GP4020 GPS Baseband Processor Design Manual Cell Unit Type All IP µ A All OP µ...
  • Page 198 20: Input / Output pin Characteristics This Page intentionally left blank. GP4020 GPS Baseband Processor Design Manual...

  • Page 199: Timing Characteristics

    21.1 Memory Peripheral Controller (MPC) External Read & Write timing parameters with on-chip Wait-state Control BuILD_CLK SADDR NSCS NSWE Tnoeh NSOE SDATA Figure 21.1 MPC Timing Diagram - External Memory Write Cycle GP4020 GPS Baseband Processor Design Manual Taddr Tncs Tnwe Taddrh Tncsh Tnweh Tdoh...
  • Page 200 Data setup before Sclk Data input hold time Data enable time after Sclk 31.6 Data valid time after Sclk 29.3 Data disable time after Sclk 28.4 Data out hold time after Sclk GP4020 GPS Baseband Processor Design Manual Taddrh Tncsh Tnoeh Tdisu Tdih...

  • Page 201: Memory Peripheral Controller (Mpc) External Read & Write Timing Parameters With Swait Control

    Table 21.2 Simulated SWait Timing parameters for MPC External Transactions 21.3 Direct Memory Access Controller (DMAC) single address transfer timing BuILD_CLK Tdreq Dreq1,2 Dack1,2 Figure 21.4 DMAC timing: Single address transfer. GP4020 GPS Baseband Processor Design Manual Read Transaction External wait state Completion cycle Twsu Unit Description and notes SWait setup time before B µ...

  • Page 202: External Interrupt Inputs: Timing For Edge Sensitivity Mode

    Dreq hold time after B µ ILD_CLK 29.8 B µ ILD_CLK to Dack active 29.0 Dack hold after B µ ILD_CLK (Dack1 & Dack2) Tint_min Figure 21.5 Interrupt timing Unit Description and notes Minimum external interrupt width GP4020 GPS Baseband Processor Design Manual...

  • Page 203: System Services Module (Ssm) Broadcast Diagnostic Timing Diagrams

    The data for the JTAG interface timing has been copied from Rev 3 of the ARM7TDMI Technical Reference Manual (document reference ARM DDI 0029F), which is downloadable (1.7 MB PDF) from ARM's website http://www.arm.com. http://www.arm.com/arm/documentation?OpenDocument Figure 21.7 JTAG Interface Characteristics GP4020 GPS Baseband Processor Design Manual Tbgdo Tbdiag units Description and notes Sdata valid after B µ...
  • Page 204 Description and notes 15.6 TCK low period 15.6 TCK high period TDI,TMS setup to [TCr] TDI,TMS hold from [TCr] TDO hold time TCr to TDO valid Reset period Table 21.6 JTAG Timing parameters GP4020 GPS Baseband Processor Design Manual...

  • Page 205: Indexes

    INDEXES GP4020 GPS Baseband Processor Design Manual Index - I...
  • Page 206 This page intentionally left blank Index - II GP4020 GPS Baseband Processor Design Manual...
  • Page 207 Table of Figures Page Figure 1.1 GP4020 Block Diagram ...2 Figure 1.2 Block Diagram of typical GP4020 based GPS receiver...8 Figure 2.1 GP4020 100-pin package pin distribution... 11 Figure 2.2 GP4020 100-pin package outline drawing... 12 Figure 3.1 ARM7TDMI Architecture ... 20 Figure 4.1 Boot ROM UART Download Data Protocol ...
  • Page 208 Figure 14.2 Circuit to interface OPCLK+/- from GP2015 to CLK_T / _I on GP4020... 136 Figure 14.3 Processor Clock Oscillator, crystal connection configuration... 137 Figure 14.4 Connections of a TCXO frequency reference to the GP4020 Processor Crystal Oscillator ... 139 Figure 14.5 GP4020 System Clock Generator PLL Configuration ... 140 Figure 14.6 PLL Programmable Divider Configuration ...
  • Page 209 This page intentionally left blank GP4020 GPS Baseband Processor Design Manual Index - V...
  • Page 210 Table of Data Tables Page Table 2.1 GP4020 100-pin package dimensions ...13 Table 2.2 GP4020 100-pin package Signal Descriptions ...16 Table 3.1 Standard 32-bit ARM instruction set ...21 Table 3.2 16-bit Thumb instruction set ...22 Table 3.3 ARM State General Registers and Program Counter...23 Table 3.4 ARM State Program Status Registers...23...
  • Page 211 Table 12.3 GPIO pin signal multiplex options ...121 Table 12.4 Peripheral Control Logic Register Map...125 Table 12.5 PCL POW_CNTL Register ...126 Table 12.6 PCL IO_REV Register...127 Table 12.7 PCL IP_READ Register...128 GP4020 GPS Baseband Processor Design Manual Index - VII...
  • Page 212 Table 17.9 UART baud-rate settings with UART_CLK (BµILD_CLK) frequency = 30MHz ...173 Table 17.10 UART baud-rate settings with UART_CLK (BµILD_CLK) frequency = 32.5MHz ...173 Table 17.11 UART baud-rate settings with UART_CLK (BµILD_CLK) frequency = 35MHz ...174 Index - VIII GP4020 GPS Baseband Processor Design Manual...
  • Page 213 Table 19.2 Truth Table for NSCS[2A] to avoid external reflection of internal accesses, using SADD[19] Table 19.3 GP4020 Memory Area 3 Addressing, with modified NSCS[2A] logic ...182 Table 19.4 Truth Table for NSCS[2A] to avoid external reflection of internal accesses, using GPIO line Table 19.5 GP4020 Memory Area 3 Addressing, with modified NSCS[2A] logic ...182...
  • Page 214 This page intentionally left blank Index - X GP4020 GPS Baseband Processor Design Manual...
  • Page 215 For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use.

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