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AMD5K86
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AMD AMD5K86 Technical Reference
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Contents
Table of Contents
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Table of Contents
Table of Contents
Overview
Features
Internal Architecture
FIGURE 2-1. Internal Architecture, with Pipeline Stage
Prefetch and Predecode
Execution Pipeline
FIGURE 2-2. Pipeline Stage Functions
Fetch
Decode
Execute
Integer/Shift Units
TABLE 2-1. ALU Instruction Classes
Floating-Point Unit
Result
Retire
Cache Organization and Management
Instruction Cache
Data Cache
Cache Tags
Cache-Line Fills
Cache Coherency
TABLE 2-2. Cache States for Read and Write Accesses
TABLE 2-3. Cache States for Snoops, Invalidation, and Replacements
Snooping
TABLE 2-4. Snoop Action
Internal Snooping
Buffers
Prefetch Cache
Replacement and Invalidation Writeback Buffer
Snoop Writeback Buffer
Read/Write Reordering
Paging and the Tlbs
Software Environment and Extensions
FIGURE 3-1. Control Register 4 (CR4)
TABLE 3-1. Control Register 4 (CR4) Fields
Machine-Check Exceptions
Mbyte Pages
FIGURE 3-2. 4-Kbyte Paging Mechanism
FIGURE 3-3. 4-Mbyte Paging Mechanism
TABLE 3-2. Page-Directory Entry (PDE) Fields
Global Pages
FIGURE 3-5. Page-Table Entry (PTE)
TABLE 3-3. Page-Table Entry (PTE) Fields
Virtual-8086 Mode Extensions (VME)
Hardware Interrupts and the VIF and VIP Extensions
FIGURE 3-6. EFLAGS Register
TABLE 3-4. Virtual-Interrupt Additions to EFLAGS Register
TABLE 3-5. Instructions that Modify the if or VIF Flags
Bitmap (IRB) Extension
FIGURE 3-7. Task State Segment (TSS)
TABLE 3-6. Interrupt Behavior and Interrupt-Table Access
Protected Virtual Interrupt (PVI) Extensions
FIGURE 3-8. Machine-Check Address Register (MCAR)
Model-Specific Registers (Msrs)
FIGURE 3-9. Machine-Check Type Register (MCTR)
TABLE 3-7. Machine-Check Type Register (MCTR) Fields
Time Stamp Counter (TSC)
Hardware Configuration Register (HWCR)
Cpuid
Cmpxchg8B
MOV to and from CR4
Rdtsc
RDMSR and WRMSR
Illegal Instruction (Reserved Opcode)
Performance
Dispatch and Execution Timing
TABLE 4-1. Integer Instructions
Integer Dot Product Example
TABLE 4-2. Integer Dot Product Internal Operations Timing
TABLE 4-3. Floating-Point Instructions
Bus Interface
FIGURE 5-1. Signal Groups
TABLE 5-1. Summary of Signal Characteristics
Signal Overview
Signal Characteristics
Conditions for Driving and Sampling Signals
TABLE 5-2. Conditions for Driving and Sampling Signals
External Interrupts
TABLE 5-3. Summary of Interrupts and Exceptions
Bus Signal Compatibility with Pentium Processor
A20M (Address Bit 20 Mask)
A31–A3 (Address Bus)
TABLE 5-4. Address-Generation Sequence During Bursts
ADS (Address Strobe)
ADSC (Address Strobe Copy)
AHOLD (Address Hold)
AP (Address Parity)
APCHK (Address Parity Check)
BE7–BE0 (Byte Enables)
TABLE 5-5. Relation of BE7-BE0 to Other Signals
TABLE 5-6. Encodings for Special Bus Cycles
BF (Bus Frequency)
TABLE 5-7. Processor-To-Bus Clock Ratios
BOFF (Backoff)
TABLE 5-8. Outputs Floated When BOFF Is Asserted
BRDY (Burst Ready)
RDYC (Burst Ready)
BREQ (Bus Request)
BUSCHK (Bus Check)
CACHE (Cacheable Access)
TABLE 5-9. MESI-State Transitions for Reads
CLK (Bus Clock)
D/C (Data or Code)
D63–D0 (Data Bus)
TABLE 5-10. Relation between D63-D0, BE7-BE0, and DP7-DP0
DP7–DP0 (Data Parity)
EADS (External Address Strobe)
EWBE (External Write Buffer Empty)
FERR (Floating-Point Error)
FLUSH (Cache Flush)
FRCMC (Functional-Redundancy Check Master/Checker)
HIT (Inquire-Cycle Hit)
TABLE 5-11. MESI-State Transitions for Inquire Cycles
HITM (Inquire Cycle Hit to Modified Line)
TABLE 5-12. Outputs Floated When HLDA Is Asserted
HLDA (Bus-Hold Acknowledge)
HOLD (Bus-Hold Request)
IERR (Internal Error)
IGNNE (Ignore Numeric Error)
INIT (Initialization)
INTR (Maskable Interrupt)
TABLE 5-13. Interrupt Acknowledge Operation Definition
INV (Invalidate Cache Line)
KEN (External Cache Enable)
LOCK (Bus Lock)
M/IO (Memory or I/O)
NA (Next Address)
NMI (Non-Maskable Interrupt)
PCD (Page Cache Disable)
PCHK (Parity Status)
PEN (Parity Enable)
PRDY (Probe Ready)
TABLE 5-14. PWT, Writeback/Writethrough, and MESI
PWT (Page Writethrough)
R/S (Run or Stop)
RESET (Reset)
TABLE 5-15. Register State after RESET or INIT
TABLE 5-16. Outputs at RESET
SCYC (Split Cycle)
SMI (System Management Interrupt)
SMIACT (System Management Interrupt Active)
STPCLK (Stop Clock)
TCK (Test Clock)
TDI (Test Data Input)
TDO (Test Data Output)
TMS (Test Mode Select)
TRST (Test Reset)
W/R (Write or Read)
WB/WT (Writeback or Writethrough)
TABLE 5-17. MESI-State Transitions for Reads
TABLE 5-18. MESI-State Transitions for Writes
TABLE 5-19. Bus Cycle Definitions
Bus Cycle Overview
Addressing
Alignment
Bus Speed and Typical DRAM Timing
Bus Cycle Timing
Single-Transfer Reads and Writes
FIGURE 5-2. Single-Transfer Memory Read and Write
Single-Transfer Memory Write Delayed by EWBE Signal
FIGURE 5-3. Single-Transfer Memory Write Delayed by
FIGURE 5-4. I/O Read and Write
TABLE 5-20. Bus-Cycle Order During Misaligned Transfers
Single-Transfer Misaligned Memory and I/O Transfers
FIGURE 5-5. Single-Transfer Misaligned Memory and
Burst Cycles
TABLE 5-21. Address-Generation Sequence During Bursts
FIGURE 5-6. Burst Reads
FIGURE 5-7. Burst Read (NA Sampled)
Burst Writeback
FIGURE 5-8. Burst Writeback Due to Cache-Line Replacement
Bus Arbitration and Inquire Cycles
AHOLD-Initiated Inquire Miss
FIGURE 5-9. AHOLD-Initiated Inquire Miss
FIGURE 5-10. AHOLD-Initiated Inquire Hit to Shared or Exclusive Line
AHOLD-Initiated Inquire Hit to Modified Line
FIGURE 5-11. AHOLD-Initiated Inquire Hit to Modified Line
Bus Backoff (BOFF)
FIGURE 5-12. Basic BOFF Operation
BOFF-Initiated Inquire Hit to Modified Line
FIGURE 5-13. BOFF-Initiated Inquire Hit to Modified Line
HOLD-Initiated Inquire Hit to Shared or Exclusive Line
FIGURE 5-14. HOLD-Initiated Inquire Hit to Shared or Exclusive Line
FIGURE 5-15. HOLD-Initiated Inquire Hit to Modified Line
Locked Cycles
FIGURE 5-16. Basic Locked Operation
TLB Miss (4-Kbyte Page)
FIGURE 5-17. TLB Miss (4-Kbyte Page)
Locked Operation with BOFF Intervention
FIGURE 5-18. Locked Operation with BOFF Intervention
TABLE 5-22. Interrupt Acknowledge Operation Definition
TABLE 5-23. Encodings for Special Bus Cycles
FIGURE 5-20. Basic Special Bus Cycle (Halt Cycle)
FIGURE 5-21. Shutdown Cycle
FIGURE 5-22. FLUSH-Acknowledge Cycle
FIGURE 5-23. Cache-Invalidation Cycle (INVD Instruction)
FIGURE 5-24A. Cache-Writeback and Invalidation Cycle
FIGURE 5-24B. Cache-Writeback and Invalidation Cycle
TABLE 5-24. Branch-Trace Message Special Bus Cycle Fields
FIGURE 5-25. Branch-Trace Message Cycle
Mode Transitions, Reset, and Testing
Stop-Grant and Stop-Clock States
Real Mode
FIGURE 5-28. INIT-Initiated Transition from Protected Mode to Real Mode
System Design
Memory Map
FIGURE 6-1. Typical Desktop-System BIOS Memory Map
Memory-Decoder Aliasing of Boot ROM Space
SMM Memory Space and Cacheability
FIGURE 6-2. Default SMM Memory Map
Cache
L2 Cache
Writethrough Vs. Writeback Coherency States
Inquire Cycles
Bus Arbitration for Inquire Cycles
BOFF Arbitration
FIGURE 6-3. BOFF Example
AHOLD Arbitration
FIGURE 6-4. AHOLD and BOFF Example
HOLD Arbitration
FIGURE 6-5. Write-Once Protocol
Cache Invalidations
System Management Mode (SMM)
Operating Mode and Default Register Values
TABLE 6-1. Initial State of Registers in SMM
SMM State-Save Area
TABLE 6-2. SMM State-Save Area Map
SMM Revision Identifier
Halt Restart Slot
I/O Trap Dword
Exceptions and Interrupts in SMM
SMM Compatibility with Pentium Processor
State Transitions
FIGURE 6-6. Clock Control State Transitions
Stop Grant State
Stop Clock State
Clock Design
FIGURE 6-8. CLK Delay Function
FIGURE 6-9. CLK Synthesizer with Output Enable
FIGURE 6-10. CPUCLK Clamping Circuit
Noise Reduction
Thermal Design
Design Support and Peripheral Products
Test and Debug
FIGURE 7-1. Hardware Configuration Register (HWCR)
TABLE 7-1. Hardware Configuration Register (HWCR) Fields
Built-In Self Test (BIST)
TABLE 7-2. bist Error Bit Definition in EAX Register
Test Access Port (TAP) bist
Output-Float Test
FIGURE 7-2. Array Access Register (AAR)
TABLE 7-3. Array Ids in Array Pointers
Array Pointer
FIGURE 7-3. Test Formats: Data-Cache Tags
Array Test Data
FIGURE 7-4. Test Formats: Data-Cache Data
FIGURE 7-5. Test Formats: Instruction-Cache Tags
FIGURE 7-6. Test Formats: Instruction-Cache Instructions
FIGURE 7-7. Test Formats: 4-Kbyte TLB
FIGURE 7-8. Test Formats: 4-Mbyte TLB
Debug Registers
Debug Compatibility with Pentium Processor
Functional-Redundancy Checking
Boundary-Scan Test Access Port (TAP)
Device Identification Register
Public Instructions
Hardware Debug Tool (HDT)
A.1 Bus Signals
A.2 Bus Interface
A.2.3 Bus Cycle Order of Misaligned Memory and I/O Cycles
Comments
A.3 Bus Mastering Operations (Including Snooping)
Comments
A.3.6 Write Hit to a Shared Line in the DCACHE
A.4 Memory Management
A.5 Power Saving Features
A.5.5 NMI Recognition During SMM
A.6 Exceptions
A.7 Debug
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AMD5
86™ Processor
K
Technical Reference Manual
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