Altera MegaCore User Manual
  1. Manuals
  2. Brands
  3. Altera Manuals
  4. Network Router
  5. MegaCore
  6. User manual
Altera MegaCore User Manual

Altera MegaCore User Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
101 Innovation Drive
San Jose, CA 95134
www.altera.com
Triple Speed Ethernet
MegaCore Function User Guide
MegaCore Version:
Document Date:
7.1
May 2007

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the MegaCore and is the answer not in the manual?

Questions and answers

Summary of Contents for Altera MegaCore

  • Page 1 Triple Speed Ethernet MegaCore Function User Guide MegaCore Version: 101 Innovation Drive Document Date: May 2007 San Jose, CA 95134 www.altera.com...
  • Page 2 Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al- tera products are protected under numerous U.S.

  • Page 3: Table Of Contents

    MegaWizard Plug-in Manager Flow ....................2–5 Specify MegaCore Function Parameters ..................2–5 Generated Files ..........................2–6 Simulate the MegaCore Function with Provided Testbench ............. 2–7 Simulating with the ModelSim Simulator ................2–8 Simulating with Other Simulators .................... 2–8 Instantiate the MegaCore Function in your Design ..............2–9 Timing Constraints ..........................
  • Page 4 Magic Packet Detection ......................... 4–25 Sleep Mode ..........................4–26 Magic Packet Detection ......................4–26 Wakeup ............................4–26 Software Reset ..........................4–27 PHY Management (MDIO) ......................4–28 MDIO Frame Format ........................ 4–29 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet MegaCore Function User Guide...
  • Page 5 PCS Control Register ........................ 4–72 Status Register ........................... 4–72 Dev_Ability and Partner_Ability Registers ................4–74 An_Expansion Register ......................4–75 If_Mode Register ........................4–76 Signals ..............................4–77 10/100/1000 Ethernet MAC Signals ................... 4–77 Altera Corporation MegaCore Function Version 7.1 Triple Speed Ethernet MegaCore Function User...
  • Page 6 Default Testbench Configuration ................... 5–10 Test Flow ............................ 5–10 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS ..........5–11 Overview ............................ 5–11 Default Testbench Configuration ................... 5–12 Test Flow ............................ 5–12 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet MegaCore Function User Guide...
  • Page 7 ......................... 6–6 tse_mac_setGMII mode() ........................ 6–7 tse_mac_setMIImode() ........................6–8 tse_mac_SwReset() ........................... 6–9 Constants .............................. 6–10 Appendix A. Simulation Parameters Functionality Configuration Parameters ................... A–1 Test Configuration Parameters ......................A–4 Altera Corporation MegaCore Function Version 7.1 Triple Speed Ethernet MegaCore Function User...
  • Page 8 Contents viii MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet MegaCore Function User Guide...

  • Page 9: About This User Guide

    About This User Guide Introduction This user guide comprises the following chapters: ■ Chapter 1, About This MegaCore Function introduces the Triple ® Speed Ethernet MegaCore Function and gives a high-level description of the features. ■ Chapter 2, Getting Started describes the design flow for creating a custom variation of the MegaCore function.

  • Page 10: Revision History

    Product literature www.altera.com/literature/ Altera literature services literature@altera.com FTP site ftp.altera.com Note to table: You can also contact your local Altera sales office or sales representative. MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet MegaCore Function User Guide...

  • Page 11: Typographic Conventions

    A warning calls attention to a condition or possible situation that can cause injury to the user. The angled arrow indicates you should press the Enter key. The feet direct you to more information on a particular topic. Altera Corporation MegaCore Function Version 7.1 Triple Speed Ethernet MegaCore Function User...
  • Page 12 Typographic Conventions MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet MegaCore Function User Guide...

  • Page 13: Chapter 1. About This Megacore Function

    Altera device families: Support ■ Full support means the MegaCore function meets all functional and timing requirements for the device family and may be used in production designs ■ Preliminary support means the MegaCore function meets all functional requirements, but may still be undergoing timing analysis for the device family;...

  • Page 14: Features

    Other device families No support Features The Triple Speed Ethernet MegaCore function combines the features of a 10/100/1000 Ethernet media access controller (MAC) and a 1000BASE-X physical coding sub-layer (PCS). The following list provides a high-level overview of the features of the MAC and PCS functions.
  • Page 15 ● CRC, length) and pause frames, enabling Simple Network Management Protocol (SNMP) management environments. The MegaCore function provides optional support for IEEE 802.3 basic and mandatory Management Information Database (MIB) package, as well as Ethernet MIB (RFC 2665) and Remote...

  • Page 16: General Description

    GbE and SGMII data streams in Stratix II GX and Arria GX Devices using integrated GX transceivers General The Triple Speed Ethernet MegaCore function provides an integrated Ethernet MAC and PCS solution for ethernet applications, such as line Description cards, NIC cards, and switches, operating at 10/100 Mbps (Fast Ethernet) or 1000 Mbps (Gigabit Ethernet).
  • Page 17 About This MegaCore Function Figure 1–1 shows a block diagram of the Triple Speed Ethernet MegaCore function. The function comprises the following main blocks: MAC, PCS, and PMA. All blocks are optional and configurable at synthesis time. A memory-mapped register interface controls the MAC and PCS blocks.
  • Page 18 Figure 1–2 illustrates an example application using the Triple Speed Ethernet MegaCore function as a stand-alone IP block, serving as a bridge between the user application and standard 10/100 and gigabit Ethernet PHY chips. This example application does not include the PCS function.
  • Page 19 In this case, the transceiver I/O connects to an off-the-shelf Ethernet PHY that supports SGMII (10BASE-T, 100BASE-T or 1000BASE- T Ethernet PHY.) Figure 1–4. 1000BASE-X/SGMII PCS MegaCore with GX Transceiver PMA (GMII to SGMII Bridge Mode) Altera FPGA or HardCopy Structured ASIC...

  • Page 20: Megacore Verification

    ■ Flow control ■ Retransmission in half-duplex Hardware Verification Altera has validated the Triple Speed Ethernet MegaCore function in both optical and copper platforms using the following development kits: ■ Altera Nios II Development Kit, Cyclone II Edition (2C35) ■...

  • Page 21: Copper Platform

    About This MegaCore Function Copper Platform In the copper platform, Altera tested the Triple Speed Ethernet MegaCore function with an external 1000BASE-T PHY devices. The MegaCore function is connected to the external PHY device using GMII, RGMII and SGMII, in conjunction with the 1000BASE-X/SGMII PCS function.

  • Page 22: Installation And Licensing

    3 M512 Statistics counters enabled 46 M4K Note: This column indicates the speed grade used to obtain the performance and utilization data. The MegaCore function supports all device speed grades unless otherwise noted. Uses 1 GX transceiver. Installation and The Triple Speed Ethernet MegaCore function is included in Altera...

  • Page 23: Opencore Plus Evaluation

    For MegaCore functions, the untethered timeout is 1 hour; the tethered timeout value is indefinite. Your design stops working after the hardware evaluation time expires.
  • Page 24 Installation and Licensing 1–12 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet MegaCore Function User Guide May 2007...

  • Page 25: Chapter 2. Getting Started

    2. Getting Started Triple Speed The following figure shows the stages for creating a system with the Triple Speed Ethernet MegaCore function and the Quartus II software. Ethernet Design Each of the stages is described in detail in subsequent sections.

  • Page 26: Parameterization Flow Selection

    SOPC Builder The SOPC Builder flow allows you to add the Triple Speed Ethernet MegaCore function directly to a new or existing SOPC Builder system. Flow You can also easily add other available components to quickly create an...

  • Page 27: Specify Megacore Function Parameters

    For detailed explanation of the parameters, refer to the “Configuring the MegaCore Function” on page 3–1. Click Finish to complete the Triple Speed Ethernet MegaCore function and add it to the system. Complete the SOPC Builder System Follow the steps below to complete the SOPC Builder system.

  • Page 28: Simulate The System

    During system generation, SOPC Builder optionally generates a simulation model and testbench for the entire system which you can use to easily simulate your system in any of Altera's supported simulation tools. SOPC Builder also generates a set of Modelsim Tcl scripts and...

  • Page 29: Megawizard Plug-In Manager Flow

    Getting Started MegaWizard The MegaWizard Plug-in Manager flow allows you to customize the Triple Speed Ethernet MegaCore function, and manually integrate the Plug-in Manager function into your design. Flow For Information About Refer To MegaWizard Plug-in Manager Quartus II Help...

  • Page 30: Generated Files

    For more information about the files generated to your project directory, refer to “Generated Files” on page 2–6. Click Finish to generate the MegaCore function and supporting files. Generated Files Table 2–2 lists the files generated in your project directory. The names...

  • Page 31: Simulate The Megacore Function With Provided Testbench

    Notes: The files generated are dependent on the custom variation of the MegaCore function you created. Some files might be absent or their names might be different. This file is only created when targeting the Stratix II GX device family and the option to use the serial transceiver is selected.

  • Page 32: Simulating With The Modelsim Simulator

    On the Simulation page (Assignments > EDA Tools Settings > Simulation), make the following selection: From the Tool name list, select your preferred simulator. ● Under NativeLink settings, select Compile test bench. ● 2–8 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet MegaCore Function User Guide May 2007...

  • Page 33: Instantiate The Megacore Function In Your Design

    Simulation Tools chapter in volume 3 of the Quartus II Handbook Instantiate the MegaCore Function in your Design You can now integrate your Triple Speed Ethernet MegaCore function variation into your design, and simulate the system with your custom testbench Timing Altera provides constraint files to ensure that the Triple Speed Ethernet MegaCore function meets IEEE 802.3 specification and design timing...

  • Page 34: Design Compilation And Device Programming

    Quartus II Handbook Quartus II Help Design You can use the Quartus II software to compile your design. After a successful compilation, you can program the targeted Altera device and Compilation and verify the design in hardware. Device Programming...

  • Page 35: Chapter 3. Configuring The Megacore Function

    SOPC Builder in the Quartus II software. This chapter describes the parameters and how they affect the behavior of the MegaCore function. Each section corresponds to a page in the Parameter Settings tab in the Triple Speed Ethernet MegaWizard interface.

  • Page 36: Core Configuration

    10/100/1000 Mbps Ethernet MAC only ■ 10/100/1000 Mbps Ethernet MAC with 1000BASE-X/SGMII PCS ■ 1000BASE-X/SGMII PCS only When instantiating the Triple Speed Ethernet MegaCore function using the SOPC Builder flow, 1000BASE-X PCS/SGMII only option is not available. 3–2 MegaCore Function Version 7.1...

  • Page 37: Interface

    When turned off, the PCS block implements a Ten-bit Interface (TBI) to an external SERDES chip or optical module. ■ When turned on, the MegaCore function includes the GX transceivers to implement a 1.25 Gbps Medium Dependent Interface (MDI). This option is only available when targeting a device with GX transceivers.

  • Page 38: Mac Options

    ■ Enable MAC 10/100 half duplex support—Turn on this option to include support for half duplex operation on 10/100 Mbps connections. 3–4 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet MegaCore Function User Guide May 2007...

  • Page 39: Mdio Module

    FIFO width is 32 bits. This helps reduce software overhead processing in realignment of data buffers. Turn on this option if you intend to use the Triple-speed Ethernet MegaCore function with the Interniche TCP/IP protocol stack. MDIO Module The following options control the PHY Management Module associated with the MAC block.

  • Page 40: Fifo Options

    Width—Determines the data width of the transmit and receive FIFOs. The available widths are 8 and 32 bits. Set the data width to 32 bits if you intend to use the Triple Speed Ethernet MegaCore function with the Interniche TCP/IP protocol stack.

  • Page 41: Depth

    Available depths range between 64 and 64k in powers of two. PCS/SGMII The options on the PCS/SGMII Options page allows you to configure the PCS block. These options are only available if the MegaCore function Options includes the PCS block.
  • Page 42 Turn off this option to connect the powerdown signal internally to the PCS control register interface to control transceiver powerdown by the host processor in your system. 3–8 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet MegaCore Function User Guide May 2007...

  • Page 43: Chapter 4. Specifications

    GMII Receive MAC Transmit Control Transmit Avalon-ST Transmit FIFO Transmit RGMII Pause Transmit Frame Generation Generation GMII Transmit Magic Packet Configuration MDIO Management Detection and Statistics Master Interface Avalon-MM Register Interface Altera Corporation MegaCore Function Version 7.1 4–1 May 2007...

  • Page 44: Ethernet Frame Format

    P802.1Q Specification. VLAN tagged frames have a maximum length of 1522 bytes, excluding the preamble and the SFD bytes. Figure 4–3 shows a MAC frame format with optional VLAN tag fields. 4–2 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...
  • Page 45 Frame length 2 octets VLAN info 2 octets MAC CLIENT LENGTH/TYPE PAYLOAD DATA 0..1500/9000 octets 0..38 octets 4 octets FRAME CHECK SEQUENCE EXTENSION (half dup only) Altera Corporation MegaCore Function Version 7.1 4–3 May 2007 Triple Speed Ethernet User Guide...
  • Page 46 Although the IEEE specification defines a maximum frame length, the MAC function provides users the flexibility to configure the maximum frame length to any value. 4–4 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...

  • Page 47: Mac Receive Operation

    96 bits Inter Packet Gap (IPG), the MAC function is designed to accept frames separated by only 48 and 64 bits in GMII (1000 Mbps operation) and MII (10/100 Mbps operation), respectively. Altera Corporation MegaCore Function Version 7.1 4–5 May 2007 Triple Speed Ethernet User Guide...

  • Page 48: Collision Detection In Half-Duplex Mode

    Mbps Ethernet connections, with gigabit Ethernet connections, this task can significantly load the host processor. To reduce the load from the host processor, the MAC function implements a hardware multicast address resolution engine. 4–6 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...
  • Page 49 XORing the MAC address bits as detailed in Table 4–2. The 6-bit code is used to address the look-up table. For each code (look-up address), a one Altera Corporation MegaCore Function Version 7.1 4–7 May 2007 Triple Speed Ethernet User Guide...

  • Page 50: Frame Length/Type Checking

    Control and VLAN frames, indicated by values of 0x8808 and 0x8100, respectively, are processed by the MAC function as described in the following sections. 4–8 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...
  • Page 51 0x0001, are always accepted regardless of the value of the CNTL_FRM_ENA bit. Pause frames are controlled by the PAUSE_FWD and PAUSE_IGNORE bits in the command_config register. Altera Corporation MegaCore Function Version 7.1 4–9 May 2007 Triple Speed Ethernet User Guide...

  • Page 52: Payload Pad Removal

    1 to indicate length error. If the RX_ERR_DISC bit in the command_config register is set to 1, received frames with length error are discarded. The payload length check is disabled when the register bit NO_LGTH_CHECK is 1. 4–10 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...

  • Page 53: Crc Checking

    If a CRC-32 error is detected, the frame is marked invalid and the frame status, rx_err(2) is set to 1. The MAC function discards received frames with CRC-32 error if the RX_ERR_DISC bit in the command_config register is 1. Altera Corporation MegaCore Function Version 7.1 4–11 May 2007 Triple Speed Ethernet User Guide...

  • Page 54: Receive Fifo Thresholds

    FIFO is empty. The receive FIFO thresholds are configured via the registers. For more information on the threshold registers, refer to Table 4–13 on page 4–32. 4–12 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...
  • Page 55 Set this threshold to 0 to enable store and forward on the receive datapath. When store and forward is enabled, the signal ff_rx_dsav is asserted as soon as a complete frame is written to the FIFO. Altera Corporation MegaCore Function Version 7.1 4–13 May 2007 Triple Speed Ethernet User Guide...

  • Page 56: Mac Transmit Operation

    MAC transmit flow. Figure 4–8. MAC Transmit Flow Send Preamble Send Destination Address Send Local MAC Address (Overwrite FIFO Data) Send Payload Send Padding (if necessary) Send CRC 4–14 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...

  • Page 57: Mac Address Insertion

    The 32 bits of the CRC value are placed in the FCS field so that the X term is the right-most bit of the first octet. The CRC bits are thus transmitted in the following order: X ,..., X Altera Corporation MegaCore Function Version 7.1 4–15 May 2007 Triple Speed Ethernet User Guide...

  • Page 58: Inter Packet Gap

    64-byte retransmit buffer. The backoff period is generated from a pseudo random process, truncated binary exponential backoff. Figure 4–9 illustrates packet retransmission. 4–16 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...
  • Page 59 If a collision occurs after 16 consecutive retransmissions, the MAC function reports an excessive collision condition by setting the EXCESS_COL bit in the command_config register to 1, and discards the current packet from the FIFO. Altera Corporation MegaCore Function Version 7.1 4–17 May 2007 Triple Speed Ethernet User Guide...

  • Page 60: Transmit Fifo Thresholds

    FIFO is empty. The transmit FIFO thresholds are configured via the registers. For more information on the threshold registers, refer to Table 4–13 on page 4–32. 4–18 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...

  • Page 61: Transmit Fifo Underflow

    After the underflow, the application completes the frame transfer. The MAC transmit control discards any new data in the FIFO until the end of packet is reached. Altera Corporation MegaCore Function Version 7.1 4–19 May 2007 Triple Speed Ethernet User Guide...

  • Page 62: Transmit Fifo Overflow

    The FIFO protection logic truncates the frame which is sent on the RGMII/GMII/MII interface with an error (tx_control/gm_tx_err/m_tx_err). The MAC function discards any new data from the user application after the frame truncation. 4–20 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...

  • Page 63: Mac Receive And Transmit Fifo Interfaces

    Decoded information on received frames can be found in rx_err(5:0), rx_frm_type(3:0) and rx_err_stat(17:0). The information is valid when the signal ff_rx_eop is asserted. Altera Corporation MegaCore Function Version 7.1 4–21 May 2007 Triple Speed Ethernet User Guide...

  • Page 64: Mac Full Duplex Flow Control Operation

    MAC function completes the transfer of the current frame and stops sending data for the amount of time specified by the pause quanta in 512 bit times increments. 4–22 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...

  • Page 65: Local Device / Fifo Congestion

    Pause frames generated are compliant to the IEEE 802.3 annex 31A & B. For more information on pause frames, refer to “Pause Frames” on page 4–24. Altera Corporation MegaCore Function Version 7.1 4–23 May 2007 Triple Speed Ethernet User Guide...

  • Page 66: Pause Frames

    In pause frames, the opcode field is always set to 0x0001. A 16-bit pause quanta is defined in the frame payload bytes 2 (byte P1) and 4–24 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide...

  • Page 67: Magic Packet Detection

    The sequence can be located anywhere in the magic packet payload and the magic packet is formed with a standard Ethernet header, optional padding and CRC. Altera Corporation MegaCore Function Version 7.1 4–25 May 2007 Triple Speed Ethernet User Guide...

  • Page 68: Sleep Mode

    Magic packet detection is disabled when the SLEEP bit in the command_config register is deasserted. Deasserting the SLEEP bit also resets the WAKEUP bit to 0 and resumes the MAC FIFO transmit and receive operations. 4–26 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...

  • Page 69: Software Reset

    (for example, cable is disconnected), the statistics registers may not be cleared. The READ_TIMEOUT bit in the reg_status register is then set to 1 to indicate that the statistics registers were not cleared. Altera Corporation MegaCore Function Version 7.1 4–27 May 2007 Triple Speed Ethernet User Guide...

  • Page 70: Phy Management (Mdio)

    10/100/1000 Ethernet MAC Management Regs Addr 0 - 31 Addr MDIO Frame Generation and MDIO Frame Decoding Generation & MDIO MDIO Decoding Register Interface Avalon Memory Mapped Interface 4–28 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...

  • Page 71: Mdio Frame Format

    2 bit of the turnaround phase. Data 16-bit data written to or read from the PHY device. Idle Between frames, the MDIO data signal is tri-stated. Altera Corporation MegaCore Function Version 7.1 4–29 May 2007 Triple Speed Ethernet User Guide...

  • Page 72: Mdio Registers

    2.5 MHz. MDIO Buffer Connection Figure 4–16 illustrates the buffers used for the MDIO tri-state bus. Figure 4–16. MDIO Buffer Connection mdio_in MDIO mdio_out mdio_oeN 4–30 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...

  • Page 73: Mac Interface Register Map

    Specifications MAC Interface Register Map The control interface to the Triple Speed Ethernet MegaCore function has a register space of 256 registers, providing access to all functional blocks within the MAC function. Table 4–12 provides an overview of the register space for the MAC function.

  • Page 74: Complete Mac Interface Register Map

    ● Bits 15:0: MegaCore function revision, set to 0x0701 ● Bit 31:16: Customer specific revision, set to 0 during MegaCore function configuration. This field is controlled by CUST_VERSION the parameter defined in the top level generated for the Triple Speed Ethernet MegaCore function instance.
  • Page 75 MAC function never asserts the signal ff_tx_a_empty . This register is typically set to a value greater than or equal to 8. Bits 12 to 31 are unused. Altera Corporation MegaCore Function Version 7.1 4–33 May 2007 Triple Speed Ethernet User Guide...

  • Page 76: Reg_Status Register

    Table 4–19 on page 4–45. edOK aOctetsReceivedO 0x07C Table 4–19 on page 4–45. aTxPAUSEMACCtrlF 0x080 Number of transmitted pause frames. See rames Table 4–19 on page 4–45. 4–34 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...
  • Page 77 4–47. Octets etherStatsPkts65 0x0C4 Table 4–21 on page 4–47. to127Octets etherStatsPkts12 0x0C8 Table 4–21 on page 4–47. 8to255Octets etherStatsPkts25 0x0CC Table 4–21 on page 4–47. 6to511Octets Altera Corporation MegaCore Function Version 7.1 4–35 May 2007 Triple Speed Ethernet User Guide...
  • Page 78 (bits 0 to 5) are accepted by the MAC. If a 0 is written, matching multicast addresses are rejected. 4–36 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...
  • Page 79 Supplemental MAC Address 0, bits 32 to – Register bit 0 maps to bit 32 of the MAC address. Register bits 16 to 31 are reserved. Altera Corporation MegaCore Function Version 7.1 4–37 May 2007 Triple Speed Ethernet User Guide...
  • Page 80 Register bit 0 maps to bit 32 of the MAC address. Register bits 16 to 31 are reserved. 0x320 – Reserved – – – – 0x3FC 4–38 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...
  • Page 81 When the MAC operates in gigabit mode, the output signal eth_mode is asserted. PROMIS_EN Promiscuous enable. Setting this bit to 1 enables the MAC promiscuous operation. All frames are received without unicast address filtering. Altera Corporation MegaCore Function Version 7.1 4–39 May 2007 Triple Speed Ethernet User Guide...
  • Page 82 This bit is set to 1 when the MAC function discards a frame after detecting a collision on 16 consecutive packet retransmissions. ● This bit is cleared following a hardware or software reset. See SW_RESET bit description. 4–40 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...
  • Page 83 Pause Frame Generation. If this bit is set to 1, the MAC function generates a pause frame with the pause quanta set to the value pause_quant configured in the register, independent of the receive FIFO status. Altera Corporation MegaCore Function Version 7.1 4–41 May 2007 Triple Speed Ethernet User Guide...
  • Page 84 Self-clearing counter reset command. Setting this bit to 1 clears the statistics counters. This bit is automatically cleared when the counter reset sequence is completed. Note: RW = Read/Write, RC = Read/Clear, WC = Write/Clear 4–42 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...

  • Page 85: Tx_Cmd_Stat Register

    Note: RC = Read/Clear Tx_Cmd_Stat Register shows the bits and fields that comprise the tx_cmd_stat Figure 4–19 register. Figure 4–18. Tx_Cmd_Stat Register RESERVED TX_SHIFT16 OMIT_CRC RESERVED Altera Corporation MegaCore Function Version 7.1 4–43 May 2007 Triple Speed Ethernet User Guide...

  • Page 86: Rx_Cmd_Stat Register

    If this bit is set to 1, the MAC function shifts the beginning of the packet to the right by 2 bytes and inserts zeros in the empty bytes to word align the packet Note: RW = Read/Write 4–44 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...

  • Page 87: Mac Snmp Mib Statistics Registers

    Number of frames received with a Errors CRC error. aAlignmentErrors Frame received with an alignment error. aOctetsTransmittedOK Sum of payload and padding octets of frames transmitted without error. Altera Corporation MegaCore Function Version 7.1 4–45 May 2007 Triple Speed Ethernet User Guide...
  • Page 88 ● Length error ● Alignment error ifOutErrors Number of frames transmitted with error: ● FIFO overflow error ● FIFO underflow error ● User application defined error 4–46 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...
  • Page 89 To extend the management information base, the following counters and objects can be derived by the management or driver software, based on the counters available as indicated in the above tables. Altera Corporation MegaCore Function Version 7.1 4–47 May 2007 Triple Speed Ethernet User Guide...
  • Page 90 Any valid multicast frame, including pause frames: = ifInMulticastPkts + aPAUSEMACCtrlFramesReceived etherStatsCRCAlignErrors Incremented when frames of correct length but with CRC error are received: = aFrameCheckSequenceErrors 4–48 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...

  • Page 91: Mii, Gmii And Rgmii Interfaces

    If a frame is received on the FIFO interface with an error (asserted with ff_tx_eop), the frame is subsequently transmitted with the GMII gm_tx_err error signal at any time during the packet transfer, as shown Figure 4–21. Altera Corporation MegaCore Function Version 7.1 4–49 May 2007 Triple Speed Ethernet User Guide...
  • Page 92 If the PHY detects an error on the frame received from the line, the PHY asserts the GMII error signal, gm_rx_err, for at least one clock cycle at any time during the packet transfer, as shown in Figure 4–23. 4–50 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...

  • Page 93: Rgmii Interface

    RGMII tx_control error signal (at the falling edge of tx_clk) at any time during the packet transfer, as shown in Figure 4–25. Altera Corporation MegaCore Function Version 7.1 4–51 May 2007 Triple Speed Ethernet User Guide...

  • Page 94: Mii Interface

    Between frames, m_tx_en remains de- asserted. Figure 4–28 shows this operation. 4–52 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...
  • Page 95 Between frames, m_rx_en remains de- asserted. Figure 4–30 shows this operation. Altera Corporation MegaCore Function Version 7.1 4–53 May 2007 Triple Speed Ethernet User Guide...

  • Page 96: Connecting Mac To External Phy

    The interface can be used in multiple applications. This section provides implementation guidelines for the following three typical network applications: ■ Gigabit Ethernet only operation ■ Programmable 10/100 Ethernet operation ■ Programmable 10/100/1000 Ethernet operation 4–54 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...

  • Page 97: Gigabit Ethernet

    PLL, a delay line or a DDR flip-flop. The MAC GMII transmit and receive interfaces are connected to the PHY interface, the MAC MII interface is not used. Altera Corporation MegaCore Function Version 7.1 4–55 May 2007 Triple Speed Ethernet User Guide...

  • Page 98: Programmable 10/100/1000 Operation

    When eth_mode is set to one, the MAC GMII interface should be driven to the PHY interface and when eth_mode is set to zero, the MAC MII interface should be driven to the PHY interface. 4–56 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...
  • Page 99 10/100/1000 Optional tie to 0 10/100/1000 PHY eth_mode Ethernet if not used set_1000 set_10 Unused en_10 rx_clk m_rx_d(3:0) m_rx_en m_rx_err 125/25/2.5 MHz gm_rx_d(7:0) gm_rx_dv gm_rx_err Altera Corporation MegaCore Function Version 7.1 4–57 May 2007 Triple Speed Ethernet User Guide...

  • Page 100: 1000Base-X/Sgmii Pcs With Optional Pma

    IEEE 1000BASE-X PMA specification. PMA interoperates with an external Physical Medium Dependent (PMD) device, which drives the external copper or optical network. The interconnect between Altera and PMD devices can be TBI or 1.25 Gpbs serial. Figure 4–35 shows a block diagram of the PCS function without PMA.

  • Page 101: Pcs Receive

    PMA. When the K28.5 comma code group is detected, the stream is re-aligned on a valid 10-bit character boundary. The aligned stream can subsequently be decoded with a standard 8b/10b decoder. Altera Corporation MegaCore Function Version 7.1 4–59 May 2007 Triple Speed Ethernet User Guide...

  • Page 102: 8B/10B Decoding

    The PCS function drives the signal led_link to 1 when link synchronization is acquired. This signal can be used as a common visual activity check using a board LED. 4–60 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...

  • Page 103: Carrier Sense

    PHY device. 8b/10b Encoding The 8B/10B encoder maps 8-bit words to 10-bit symbols to generate a DC balanced stream with a maximum run length of 5. Altera Corporation MegaCore Function Version 7.1 4–61 May 2007 Triple Speed Ethernet User Guide...

  • Page 104: Sgmii Converter

    The receive MAC clock (rx_clk) is generated from a division of the TBI 125 MHz line recovered clock tbi_rx_clk. Figure 4–37 provides a block diagram for the clock distribution with an external PMA. 4–62 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...
  • Page 105 The MAC Clock speed depends on the PCS function operation listed in Table 4–24. Table 4–24. MAC Clock Frequency PCS Function Operation MAC Clock Frequency Gigabit 125 Mhz 100 Mbps 25 MHz 10 Mbps 2.5 MHz Altera Corporation MegaCore Function Version 7.1 4–63 May 2007 Triple Speed Ethernet User Guide...

  • Page 106: Clock Distribution With Embedded Pma

    1000BASE-X/SGMII PCS with Optional PMA Clock Distribution with Embedded PMA When the PCS function is implemented in Altera devices with GX transceivers, a rate matching function is implemented and a single clock is then used on the PCS transmit and receive domains.

  • Page 107: Auto-Negotiation

    The auto-negotiation is successfully completed when three consecutive idle sequences are received after the link timer expires. This sequence of activities is illustrated by Figure 4–39. Altera Corporation MegaCore Function Version 7.1 4–65 May 2007 Triple Speed Ethernet User Guide...
  • Page 108 Auto-negotiation is restarted if link synchronization is lost and re- acquired or if the RESTART_AUTO_NEGOTIATION bit in the PCS control register (Table 4–26 on page 4–72) is set to 1 by the user application. 4–66 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...

  • Page 109: Sgmii Auto-Negotiation

    1.25Gbps Serial Stream On receive, the SERDES must serialize the TBI least significant bit first and the TBI most significant bit last, as Figure 4–41 illustrates. Altera Corporation MegaCore Function Version 7.1 4–67 May 2007 Triple Speed Ethernet User Guide...

  • Page 110: Phy Loopback

    PCS function drives the powerdown signal, which can be used to control a technology specific circuit to switch off the PCS function clocks to reduce the application activity. 4–68 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...

  • Page 111: Power-Down With Embedded Pma

    When the PCS function is implemented with an embedded PMA, the power-down signal is internally connected to the power-down of the GX transceiver. In Altera devices with internal GX transceivers, the power-down functionality is shared across quad-port transceiver blocks. Multi-port Ethernet designs must share a common gxb_powerdown_in signal to use the same quad-port transceiver block.

  • Page 112: Pcs Control Interface Register Map

    1000BASE-X and SGMII mode, refer to Table 4–28 on page 4–74 Table 4–29 on page 4–75, respectively. an_expansion 0x0C Auto-negotiation expansion register. Contains the PCS function capability and auto-negotiation status. 4–70 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...
  • Page 113 Interface mode. Use this register to specify the operating mode of the PCS function; 1000BASE-X or SGMII. 0x2A to Reserved 0x3E Note: RW = Read/Write, RO = Read only Altera Corporation MegaCore Function Version 7.1 4–71 May 2007 Triple Speed Ethernet User Guide...

  • Page 114: Pcs Control Register

    8b/10b encoder and decoder. For normal operation, set this bit to 0 (asynchronous reset value). Note: RW = Read/Write, RO = Read only, SC = Self-clearing 4–72 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...

  • Page 115: Status Register

    The PCS function does not support 100BASE-X operation. Always set to 0. 100BASE-X_FULL_DUPLEX 100BASE-T4 The PCS function does not support 100Base-T4 operation. Always set to 0. Altera Corporation MegaCore Function Version 7.1 4–73 May 2007 Triple Speed Ethernet User Guide...

  • Page 116: Dev_Ability And Partner_Ability Registers

    0. Note: dev_ability All bits in the register have read/write access. partner_ability All bits in the register are read-only. 4–74 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...

  • Page 117: An_Expansion Register

    0 (reset value) when the system management agent performs a read access. NEXT_PAGE_ABLE The PCS function does not support next page. This bit is always 0. 3 to 15 Reserved Altera Corporation MegaCore Function Version 7.1 4–75 May 2007 Triple Speed Ethernet User Guide...

  • Page 118: If_Mode Register

    1 SGMII_DUPLEX SGMII duplex mode. Setting this bit to 1 enables full duplex. 5 to 15 Reserved Note: RW = Read/Write, RO = Read only 4–76 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...

  • Page 119: Signals

    Magic mdio_in magic_sleep_n Packet Signals magic_wakeup Management mdio_oen Signals mdio_out address(7:0) write Register read set_10 Interface Signals Interface writedata(31:0) set_1000 Control readdata(31:0) ena_10 Signals eth_mode waitrequest Altera Corporation MegaCore Function Version 7.1 4–77 May 2007 Triple Speed Ethernet User Guide...

  • Page 120: Control Interface Signals

    The control register interface is an Avalon Memory Mapped (Avalon- MM) slave port. This interface controls both the MAC and PCS blocks in the MegaCore function. The slave port has the following properties, and behaves in accordance with the Avalon Memory-Mapped Interface Specification: ■...

  • Page 121: Mac System-Side Signals

    Refer To Avalon-ST interface protocol Avalon Streaming Interface Specification When instantiating the MegaCore function in an SOPC Builder system, SOPC Builder automatically connects the Avalon-ST ports to the rest of the system. When instantiating the MegaCore function stand-alone, the Avalon-ST signals appear at the top-level of the variant HDL file, and you must manually connect them.
  • Page 122 Table 4–35 on specific signal page 4–81. ff_rx_a_full component Receive FIFO almost-full threshold. This signal is specific signal asserted when the FIFO reaches the almost full threshold. 4–80 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...
  • Page 123 ( asserted) Unicast frame indication. Asserted together with ff_rx_sop and remains asserted until the end of the ff_rx_eop frame. ( asserted) Altera Corporation MegaCore Function Version 7.1 4–81 May 2007 Triple Speed Ethernet User Guide...
  • Page 124 Data width of 8 or 32 bits ■ Support for packets using start, end of packet signals and partial final packet signals ■ Error reporting ■ Optional calculation of CRC 4–82 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...
  • Page 125 DATAWIDTH Transmit data. is either 8 or 32 depending TAWIDTH-1]:0) on the FIFO data width configuring during MegaCore DATAWIDTH parameterization. When is 32, the first byte ff_tx_data(31:24) transmitted is followed by ff_tx_data(23:16) and so forth.
  • Page 126 FIFO status, a pause frame with the pause pause_quant quanta programmed in the register. xoff_gen This signal is ignored if the bit in the command_config register is set to 1. 4–84 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...

  • Page 127: Mac Ethernet-Side Signals

    The Ethernet-side interface for the MAC block uses the standard MII, GMII and RGMII interfaces to connect to an external PHY device. The MAC block provides an MDIO PHY management interface and other interface control signals. Altera Corporation MegaCore Function Version 7.1 4–85 May 2007 Triple Speed Ethernet User Guide...
  • Page 128 CRC field is received. m_rx_err Asserted by the PHY to Indicate that the current frame contains erroneous data. MII PHY Status 4–86 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...
  • Page 129 10 Mbps enable. Set to 1 to indicate that the PHY interface should operate eth_mode in 10 Mbps mode. This signal is only valid when the signal set to 0. Altera Corporation MegaCore Function Version 7.1 4–87 May 2007 Triple Speed Ethernet User Guide...
  • Page 130 This signal is ignored when the register bit ENA_10 ENA_10 set to 1 or when the register bit is set to 1. The software configuration bit has a higher priority than this signal. 4–88 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...

  • Page 131: 10/100/1000 Ethernet Mac With 1000Base-X/Sgmii Pcs Signals

    Pause xon_gen xoff_gen Management Magic mdio_oen Signals magic_sleep_n Packet mdio_out Signals magic_wakeup address(7:0) write Register Interface read Signals writedata(31:0) SERDES sd_loopback readdata(31:0) Control waitrequest powerdown Signals Altera Corporation MegaCore Function Version 7.1 4–89 May 2007 Triple Speed Ethernet User Guide...

  • Page 132: Control Interface Signals

    . Data from the external SERDES can be arbitrary aligned. Phy Management Signals For more information about PHY Management signals, refer to “PHY Management Signals” on page 4–87. 4–90 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...
  • Page 133 SERDES Loopback Control. Set to 1 when the PCS function is configured by the system management agent to operate in loopback mode. This signal can be used to configure an external SERDES device to operate in loopback mode. Altera Corporation MegaCore Function Version 7.1 4–91 May 2007 Triple Speed Ethernet User Guide...

  • Page 134: 10/100/1000 Ethernet Mac With 1000Base-X/Sgmii Pcs And Pma Signals

    Pause xoff_gen Management Magic mdio_oen magic_sleep_n Signals Packet mdio_out magic_wakeup Signals address(7:0) write Register Interface read Signals writedata(31:0) SERDES pcs_pwrdn_out readdata(31:0) Control gxb_pwrdn_in waitrequest Signals 4–92 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...

  • Page 135: Control Interface Signals

    Management Signals” on page 4–87. Status LED Control Signals For more information about Status LED Control Signals, refer to “Status LED Control Signals” on page 4–91. Altera Corporation MegaCore Function Version 7.1 4–93 May 2007 Triple Speed Ethernet User Guide...
  • Page 136 Power-down enable input. Powers down the tranceiver quad block when set to 1. Only implemented when an internal SERDES is used with the option to export the power-down signal. 4–94 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...

  • Page 137: 1000Base-X/Sgmii Pcs Signals

    Status set_100 led_col Status set_1000 led_char_err Signals Signals hd_ena led_link led_disp_err reg_clk reg_addr(4:0) reg_wr Register Interface reg_rd Signals reg_data_in(15:0) SERDES reg_data_out(15:0) sd_loopback Control reg_busy powerdown Signals Altera Corporation MegaCore Function Version 7.1 4–95 May 2007 Triple Speed Ethernet User Guide...

  • Page 138: Control Interface Signals

    Resets the logic rx_clk synchronized by the clock reset_tx_clk tx_clk Active high reset signal for PCS clock domain. Resets the logic tx_clk synchronized by the clock 4–96 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...

  • Page 139: Pcs Mac-Side Signals

    CRC field is received. gmii_rx_err Asserted by the PHY to indicate that the current frame contains erroneous data. Altera Corporation MegaCore Function Version 7.1 4–97 May 2007 Triple Speed Ethernet User Guide...
  • Page 140 USE_SGMII_AN SGMII_SPEED ● if the bit is set to 0 and the bit is set to 01 4–98 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...

  • Page 141: Pcs Ethernet-Side Signals

    For more information about Status LED signals, refer to “Status LED Control Signals” on page 4–91. SERDES Control Signals For more information about SERDES Control signals, refer to“SERDES Control Signals” on page 4–91. Altera Corporation MegaCore Function Version 7.1 4–99 May 2007 Triple Speed Ethernet User Guide...

  • Page 142: 1000Base-X/Sgmii Pcs And Pma Signals

    SERDES readdata(15:0) pcs_pwrdn_out Control waitrequest gxb_pwrdn_in Signals Control Interface Signals For more information about control interface signals, refer to “Control Interface Signals” on page 4–78. 4–100 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...

  • Page 143: Pcs Mac-Side Signals

    For more information about Status LED Control signals, refer to “Status LED Control Signals” on page 4–91. SERDES Control Signals For more information about SERDES Control signals, refer to “SERDES Control Signals” on page 4–94. Altera Corporation MegaCore Function Version 7.1 4–101 May 2007 Triple Speed Ethernet User Guide...
  • Page 144 Signals 4–102 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet User Guide May 2007...

  • Page 145: Chapter 5. Testbench

    5. Testbench Introduction You can use the testbench provided with the Triple Speed Ethernet MegaCore function to exercise your custom MegaCore function variation. The testbench includes the following features: ■ Easy-to-use simulation environment for any standard HDL simulator ■ Simulation of all basic Ethernet packet transactions ■...

  • Page 146: Mdio Slave

    You can also customize other aspects of the testbench using the testbench simulation parameters. For more information on the testbench simulation parameters, refer to Appendix A, Simulation Parameters. 5–2 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet MegaCore Function User Guide May 2007...

  • Page 147: Verification

    Simulation fails only if the testbench is not able to detect deliberately inserted errors. At the end of a simulation, the testbench displays messages in the simulator console indicating its results. Altera Corporation MegaCore Function Version 7.1 5–3 May 2007 Triple Speed Ethernet MegaCore Function User...

  • Page 148: Testbench Architecture

    CRC-32 inserted by the MAC function. Short frames are always padded by the MAC function up to at least 64 bytes in length. 5–4 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet MegaCore Function User Guide May 2007...

  • Page 149: Default Testbench Configuration

    Write to MDIO slave address and command registers to exercise the MDIO slave. This is done only if MDIO ports are in use by setting the parameter TB_MDIO_SIMULATION to 1. Altera Corporation MegaCore Function Version 7.1 5–5 May 2007 Triple Speed Ethernet MegaCore Function User...
  • Page 150 End transmission and read the MAC statistics registers, if they are implemented. ■ Compare the statistics generated by the frame generator and monitor to determine if the simulation is successful. 5–6 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet MegaCore Function User Guide May 2007...

  • Page 151: 1000Base-X/Sgmii Pcs

    The simulated link speed is assumed to be Gigabit. ■ The if_mode register is programmed to 0x0000. ■ Auto-negotiation between the local PHY and remote link PHY is bypassed. Altera Corporation MegaCore Function Version 7.1 5–7 May 2007 Triple Speed Ethernet MegaCore Function User...

  • Page 152: Test Flow

    The Ethernet frames sent to the GMII transmit are the same as ● the Ethernet frames received from the GMII receive. No Ethernet protocol errors detected. ● 5–8 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet MegaCore Function User Guide May 2007...

  • Page 153: 1000Base-X/Sgmii Pcs With Embedded Pma

    On the receiving end, the PCS function is able to receive frames from the 1.25 Gbps receive serial interface and de-encapsulate the frames before forwarding them in GMII format onto the GMII receive interface. Altera Corporation MegaCore Function Version 7.1 5–9 May 2007 Triple Speed Ethernet MegaCore Function User...

  • Page 154: Default Testbench Configuration

    The Ethernet frames sent to the GMII transmit are the same as ● the Ethernet frames received from the GMII receive. No Ethernet protocol errors detected. ● 5–10 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet MegaCore Function User Guide May 2007...

  • Page 155: 10/100/1000 Ethernet Mac With 1000Base-X/Sgmii Pcs

    On the receiving end, the PCS function is able to receive frames on the TBI receive, de-encapsulate the frames and optionally discard the CRC-32 before forwarding the frames onto the Avalon-ST receive interface. Altera Corporation MegaCore Function Version 7.1 5–11 May 2007 Triple Speed Ethernet MegaCore Function User...

  • Page 156: Default Testbench Configuration

    Write to MDIO slave address and command registers to exercise the MDIO slave. This is done only if MDIO ports are in use by setting the parameter TB_MDIO_SIMULATION to 1. 5–12 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet MegaCore Function User Guide May 2007...
  • Page 157 End transmission and read the MAC statistics registers, if they are implemented. ■ Compare the statistics generated by the frame generator and monitor to determine if the simulation is successful. Altera Corporation MegaCore Function Version 7.1 5–13 May 2007 Triple Speed Ethernet MegaCore Function User...

  • Page 158: 10/100/1000 Ethernet Mac With 1000Base-X/Sgmii Pcs And Embedded Pma

    On the receiving end, the PCS function is able to receive frames on the 1.25 Gbps serial receive interface, de-encapsulate the frames and discard the CRC-32 before forwarding the frames onto the Avalon- ST receive interface. 5–14 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet MegaCore Function User Guide May 2007...

  • Page 159: Default Testbench Configuration

    Write to MDIO slave address and command registers to exercise the MDIO slave. This is done only if MDIO ports are in use by setting the parameter TB_MDIO_SIMULATION to 1. Altera Corporation MegaCore Function Version 7.1 5–15 May 2007 Triple Speed Ethernet MegaCore Function User...
  • Page 160 End transmission and read the MAC statistics registers, if they are implemented. ■ Compare the statistics generated by the frame generator and monitor to determine if the simulation is successful. 5–16 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet MegaCore Function User Guide May 2007...

  • Page 161: Chapter 6. Software Programming Interface

    TX DESCRIPTOR Setup RX DESCRIPTOR descriptors instance name = “descriptor_memory” Process & write back status SGDMA RX MII/GMII instance name = RX FIFO “sgdma_rx” MEMORY TSE MAC instance name = “tse_mac” Altera Corporation MegaCore Function Version 7.1 6–1 May 2007...
  • Page 162 FIFO data width, refer to “FIFO Options” on page 3–6. ■ PHYs other than National DP83865 (10/100/1000) and Marvell 88E1111 (10/100/1000). 6–2 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet MegaCore Function User Guide May 2007...

  • Page 163: Directory Structure

    Structure source files it contains. Figure 6–2. Directory Structure altera_triple_speed_ethernet triple_speed_ethernet.h triple_speed_ethernet_regs.h UCOSII iniche ins_tse_mac.h triple_speed_ethernet-iniche.h component.mk iniche ins_tse_mac.c triple_speed_ethernet.c Altera Corporation MegaCore Function Version 7.1 6–3 May 2007 Triple Speed Ethernet MegaCore Function User Guide...

  • Page 164: Api Functions

    A pointer to the Triple Speed Ethernet device instance. Return: SUCCESS if the Triple Speed Ethernet driver is successfully initialized. See Also: tse_mac_close() 6–4 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet MegaCore Function User Guide May 2007...

  • Page 165: Tse_Mac_Close()

    Return: SUCCESS if the close operations are successful. An error code if de-registration of SGDMA RX from the operating system failed. See Also: triple_speed_ethernet_init() Altera Corporation MegaCore Function Version 7.1 6–5 May 2007 Triple Speed Ethernet MegaCore Function User Guide...

  • Page 166: Tse_Mac_Raw_Send()

    SUCCESS if the current data buffer is successfully transmitted. SEND_DROPPED if the number of data bytes is less than the Ethernet header size. ENP_RESOURCE if the SGDMA TX engine is busy. 6–6 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet MegaCore Function User Guide May 2007...

  • Page 167: Tse_Mac_Setgmii Mode()

    Argument: pmac A pointer to the MAC control interface base address. Return: SUCCESS See Also: tse_mac_setMIImode() Altera Corporation MegaCore Function Version 7.1 6–7 May 2007 Triple Speed Ethernet MegaCore Function User Guide...

  • Page 168: Tse_Mac_Setmiimode()

    Argument: pmac A pointer to the MAC control interface base address. Return: SUCCESS See Also: tse_mac_setGMIImode() 6–8 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet MegaCore Function User Guide May 2007...

  • Page 169: Tse_Mac_Swreset()

    Argument: pmac A pointer to the MAC control interface base address. Return: SUCCESS See Also: tse_mac_setGMIImode() Altera Corporation MegaCore Function Version 7.1 6–9 May 2007 Triple Speed Ethernet MegaCore Function User Guide...

  • Page 170: Constants

    ALTERA_TSEMAC_CMD_EXCESS_COL_MSK 0x800 ALTERA_TSEMAC_CMD_LATE_COL_OFST LATE_COL Configures the bit. ALTERA_TSEMAC_CMD_LATE_COL_MSK 0x1000 ALTERA_TSEMAC_CMD_SW_RESET_OFST SW_RESET Configures the bit. ALTERA_TSEMAC_CMD_SW_RESET_MSK 0x2000 ALTERA_TSEMAC_CMD_MHASH_SEL_OFST MHAS_SEL Configures the bit. ALTERA_TSEMAC_CMD_MHASH_SEL_MSK 0x4000 6–10 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet MegaCore Function User Guide May 2007...
  • Page 171 ALTERA_TSEMAC_TX_CMD_STAT_OMITCRC_MSK 0x20000 ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_OFS TX_SHIFT16 Configures the bit. ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_MSK 0x40000 Rx_Cmd_Stat Register (Table 4–18 on page 4–44) ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_OFS Configures the RX_SHIFT16 bit ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_MSK 0x2000000 Altera Corporation MegaCore Function Version 7.1 6–11 May 2007 Triple Speed Ethernet MegaCore Function User Guide...
  • Page 172 Constants 6–12 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet MegaCore Function User Guide May 2007...

  • Page 173: Appendix A. Simulation Parameters

    MegaCore function variation. Configuration In VHDL testbenches, the parameter names are in UPPER case; Parameters in Verilog, the names are in lower case. Table A–1. MegaCore Functionality Configuration Parameters (Part 1 of 4) Parameter Description Default Supported In ETH_MODE Defines the MAC operation.
  • Page 174 Functionality Configuration Parameters Table A–1. MegaCore Functionality Configuration Parameters (Part 2 of 4) Parameter Description Default Supported In TB_MACINSERT_ADDR When enabled, the MAC forwards the Configurations that source address received from the contains the application, when disabled, the MAC 10/100/1000...
  • Page 175 Table A–1. MegaCore Functionality Configuration Parameters (Part 3 of 4) Parameter Description Default Supported In RX_FIFO_AF Set the Receive FIFO almost full Configurations that threshold to any value between 0 and the contains the Maximum memory depth, 10/100/1000 Ethernet MAC...
  • Page 176 Test Configuration Parameters Table A–1. MegaCore Functionality Configuration Parameters (Part 4 of 4) Parameter Description Default Supported In TB_SGMII_ENA When selected, set, via a Register Configurations that management access that the PCS contains the operates in SGMII mode. When 1000BaseX PCS or...
  • Page 177 If enabled, All configurations that Contain the Configurations that 10/100/1000 Mbps Ethernet MAC frames contains the sent/received will be VLAN type of frames 10/100/1000 Ethernet MAC Altera Corporation MegaCore Function Version 7.1 A–5 May 2007 Triple Speed Ethernet MegaCore Function User Guide...
  • Page 178 When set to 0, disable contains the collision generation, option only available if 10/100/1000 the MAC operates in Half Duplex mode. Ethernet MAC A–6 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet MegaCore Function User Guide May 2007...
  • Page 179 1000BaseX PCS or SGMII TB_SGMII_1000 When selected, the PCS Core is configured Configurations that for Gigabit operation. contains the 1000BaseX PCS or SGMII Altera Corporation MegaCore Function Version 7.1 A–7 May 2007 Triple Speed Ethernet MegaCore Function User Guide...

  • Page 180: Test Configuration Parameters

    Configurations that for 10 Mbps operation. contains the 1000BaseX PCS or SGMII TB_TX_ERR Enable GMII Error Configurations that contains the 10/100/1000 Mbps Ethernet MAC A–8 MegaCore Function Version 7.1 Altera Corporation Triple Speed Ethernet MegaCore Function User Guide May 2007...

Table of Contents