Altera Arria V GZ Manuals

Manuals and User Guides for Altera Arria V GZ. We have 1 Altera Arria V GZ manual available for free PDF download: User Manual

Altera Arria V GZ User Manual (300 pages)

Hard IP for PCI Express

Brand: Altera | Category: PCI Card | Size: 7 MB

Table of Contents
3
Chapter 1. Arria V GZ Datasheet

9
- Features
  9
- Release Information
  12
- Device Family Support
  13
- Configurations
  13
- Debug Features
  15
- IP Core Verification
  15
  - Compatibility Testing Environment
    16
- Performance and Resource Utilization
  16
- Recommended Speed Grades
  17
Chapter 2 .Getting Started with the Arria V GZ Hard IP for PCI Express

21
Chapter 3 .Getting Started with the Avalon-MM Arria V GZ Hard IP for PCI Express

40
Chapter 4. Parameter Settings

57
Chapter 5. IP Core Architecture

71
- Key Interfaces
  73
  - Avalon-ST Interface
    73
    
    RX Datapath
    73
    
    TX Datapath
    73
  - Clocks and Reset
    74
  - Local Management Interface (LMI Interface)
    74
  - Hard IP Reconfiguration
    74
  - Transceiver Reconfiguration
    74
  - Interrupts
    75
  - Pipe
    75
- Transaction Layer
  75
  - Configuration Space
    77
- Data Link Layer
  77
- Physical Layer
  79
- PCI Express Avalon-MM Bridge
  81
- Avalon-MM Bridge Tlps
  83
- Completer Only Single Dword Endpoint
  91
  - RX Block
    92
  - Avalon-MM RX Master Block
    92
  - TX Block
    93
  - Interrupt Handler Block
    93
Chapter 6. IP Core Interfaces

95
Chapter 7. Register Descriptions

159
Chapter 8. Reset and Clocks

185
- Reset
  185
- Clocks
  188
  - Arria V GZ V Hard IP for PCI Express Clock Domains
    189
    
    Pclk
    189
    
    Coreclkout
    189
    
    Pld_Clk
    189
  - Additional Clocks
    191
  - Clock Summary
    191
Chapter 9. Transaction Layer Protocol (TLP) Details

194
- Transaction Layer Routing Rules
  195
- Receive Buffer Reordering
  196
Chapter 10. Optional Features

199
- Configuration Via Protocol (Cvp)
  199
- Ecrc
  200
  - ECRC on the RX Path
    201
  - ECRC on the TX Path
    201
- Lane Initialization and Reversal
  202
Chapter 11 .Interrupts

205
Chapter 12. Flow Control

213
- Throughput of Posted Writes
  213
- Throughput of Non-Posted Reads
  215
Chapter 13. Error Handling

217
- Physical Layer Errors
  218
- Data Link Layer Errors
  218
- Transaction Layer Errors
  219
- Error Reporting and Data Poisoning
  221
- Uncorrectable and Correctable Error Status Bits
  222
Chapter 14. SDC Timing Constraints

223
- SDC Constraints for the Hard IP for Pcie
  223
- SDC Constraints for the Example Design
  224
Chapter 15. Hard IP Reconfiguration and Transceiver Reconfiguration

225
- Hard IP Reconfiguration Interface
  225
- Transceiver PHY IP Reconfiguration
  233
  - Connecting the Transceiver Reconfiguration Controller IP Core
    233
  - Learning more about Transceiver PHY Reconfiguration
    235
Chapter 16. Testbench and Design Example Endpoint Testbench

239
- Root Port Testbench
  240
- Chaining DMA Design Examples
  240
- Test Driver Module
  250
  - DMA Write Cycles
    251
  - DMA Read Cycles
    253
- Root Port Design Example
  254
- Root Port BFM
  256
- BFM Procedures and Functions
  264
  - BFM Read and Write Procedures
    264
    
    Ebfm_Barwr Procedure
    264
    
    Ebfm_Barwr_Imm Procedure
    265
    
    Ebfm_Barrd_Wait Procedure
    266
    
    Ebfm_Barrd_Nowt Procedure
    266
    
    Ebfm_Cfgwr_Imm_Wait Procedure
    267
    
    Ebfm_Cfgwr_Imm_Nowt Procedure
    268
    
    Ebfm_Cfgrd_Wait Procedure
    269
    
    Ebfm_Cfgrd_Nowt Procedure
    269
  - BFM Configuration Procedures
    270
    
    Ebfm_Cfg_Decode_Bar Procedure
    271
  - BFM Shared Memory Access Procedures
    271
    
    Shared Memory Constants
    271
    
    Shmem_Write
    272
    
    Shmem_Read Function
    272
    
    Shmem_Display Verilog HDL Function
    272
    
    Shmem_Fill Procedure
    273
    
    Shmem_Chk_Ok Function
    273
  - BFM Log and Message Procedures
    273
    
    Ebfm_Display Verilog HDL Function
    275
    
    Ebfm_Log_Stop_Sim Verilog HDL Function
    275
    
    Ebfm_Log_Set_Suppressed_Msg_Mask Verilog HDL Function
    275
    
    Ebfm_Log_Set_Stop_On_Msg_Mask Verilog HDL Function
    276
    
    Ebfm_Log_Open Verilog HDL Function
    276
    
    Ebfm_Log_Close Verilog HDL Function
    276
  - Verilog HDL Formatting Functions
    276
    
    Himage1
    277
    
    Himage2
    277
    
    Himage4
    277
    
    Himage8
    277
    
    Himage16
    278
    
    Dimage1
    278
    
    Dimage2
    278
    
    Dimage3
    279
    
    Dimage4
    279
    
    Dimage5
    279
    
    Dimage6
    279
    
    Dimage7
    280
  - Procedures and Functions Specific to the Chaining DMA Design Example
    280
    
    Chained_Dma_Test Procedure
    280
    
    Dma_Rd_Test Procedure
    281
    
    Dma_Wr_Test Procedure
    281
    
    Dma_Set_Rd_Desc_Data Procedure
    281
    
    Dma_Set_Wr_Desc_Data Procedure
    281
    
    Dma_Set_Header Procedure
    282
    
    Rc_Mempoll Procedure
    282
    
    Msi_Poll Procedure
    283
    
    Dma_Set_Msi Procedure
    283
    
    Find_Mem_Bar Procedure
    284
    
    Dma_Set_Rclast Procedure
    284
    
    Ebfm_Display_Verb Procedure
    284
Chapter 17. Debugging

285
Appendix A.transaction Layer Packet (TLP) Header Formats

295
- TLP Packet Format Without Data Payload
  295
- TLP Packet Format with Data Payload
  297
Additional Information

299
- Revision History
  299
- How to Contact Altera
  299
- Typographic Conventions
  299

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Altera Arria V GZ Manuals

Altera Arria V GZ User Manual (300 pages)

Table of Contents

Chapter 1. Arria V GZ Datasheet

Chapter 2 .Getting Started with the Arria V GZ Hard IP for PCI Express

Chapter 3 .Getting Started with the Avalon-MM Arria V GZ Hard IP for PCI Express

Chapter 4. Parameter Settings

Chapter 5. IP Core Architecture

Chapter 6. IP Core Interfaces

Chapter 7. Register Descriptions

Chapter 8. Reset and Clocks

Chapter 9. Transaction Layer Protocol (TLP) Details

Chapter 10. Optional Features

Chapter 11 .Interrupts

Chapter 12. Flow Control

Chapter 13. Error Handling

Chapter 14. SDC Timing Constraints

Chapter 15. Hard IP Reconfiguration and Transceiver Reconfiguration

Chapter 16. Testbench and Design Example Endpoint Testbench

Chapter 17. Debugging

Appendix A.transaction Layer Packet (TLP) Header Formats

Additional Information

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