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Altera Arria V GZ User Manual

Altera Arria V GZ User Manual

Hard ip for pci express
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Arria V GZ Hard IP for PCI Express User Guide
Arria V GZ Hard IP for PCI Express
User Guide
101 Innovation Drive
San Jose, CA 95134
www.altera.com
Document last updated for Altera Complete Design Suite version:
12.1
UG-01127-1.0
Document publication date:
November 2012
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Summary of Contents for Altera Arria V GZ

  • Page 1 Arria V GZ Hard IP for PCI Express User Guide Arria V GZ Hard IP for PCI Express User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Document last updated for Altera Complete Design Suite version: 12.1 UG-01127-1.0 Document publication date:...
  • Page 2 © 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.

  • Page 3: Table Of Contents

    Customizing the Arria V GZ Hard IP for PCI Express IP Core ......
  • Page 4 Data Alignment and Timing for the 128-Bit Avalon-ST TX Interface ......6–23 Arria V GZ Hard IP for PCI Express...
  • Page 5 Altera-Defined Vendor Specific Extended Capability (VSEC) ........7–5...
  • Page 6 Arria V GZ V Hard IP for PCI Express Clock Domains ......
  • Page 7 ............... . . 16–41 November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...
  • Page 8 How to Contact Altera ........

  • Page 9: Chapter 1. Arria V Gz Datasheet

    FPGAs. Features The Arria V GZ Hard IP for PCI Express and the Avalon-MM Arria V GZ Hard IP for PCI Express IP cores support the following key features: Complete protocol stack including the Transaction, Data Link, and Physical Layers ■...
  • Page 10 ■ Controller Qsys component and a driver for this component. The Arria V GZ Hard IP for PCI Express offers different features for variants that use the Avalon-ST and Avalon-MM interfaces to the Application Layer. Variants using the Avalon-ST interface offer more features; however, if you are not familiar with the PCI Express protocol, variants using the Avalon-MM interface may be easier to understand.
  • Page 11 Not supported Number of MSI requests 1, 2, 4, 8, or 16 MSI-X Supported Supported Multiple MSI, MSI-X, and INTx Not Supported Supported Legacy interrupts Supported Supported November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...

  • Page 12: Release Information

    Layer. In the interest of brevity, the remainder of this document does not use both product names. The purpose of the Arria V GZ Hard IP for PCI Express User Guide is to explain how to use the Arria V GZ Hard IP for PCI Express and not to explain the PCI Express protocol.

  • Page 13: Device Family Support

    ■ Stratix V Hard IP for PCI Express User Guide ■ Configurations The Arria V GZ Hard IP for PCI Express includes a full hard IP implementation of the PCI Express stack including the following layers: Physical (PHY) ■ ■...
  • Page 14 Chapter 1: Arria V GZ Datasheet Configurations Figure 1–1 shows a PCI Express link between two Arria V GZ FPGAs. One is configured as a Root Port and the other as an Endpoint. Figure 1–1. PCI Express Application with a Single Root Port and Endpoint...

  • Page 15: Debug Features

    Arria V GZ with Hard IP for PCIe Debug Features The Arria V GZ Hard IP for PCI Express includes debug features that allow observation and control of the Hard IP for faster debugging of system-level problems. For more information about debugging refer to Chapter 18, Debugging.

  • Page 16: Compatibility Testing Environment

    Random tests that test a wide range of traffic patterns Compatibility Testing Environment Altera has performed significant hardware testing of the Arria V GZ Hard IP for PCI Express to ensure a reliable solution. In addition, Altera internally tests every release with motherboards and PCI Express switches from a variety of manufacturers.

  • Page 17: Recommended Speed Grades

    For more information about how to effect the Optimization Technique settings, refer Area and Timing Optimization in volume 2 of the Quartus II Handbook. Table 1–6. Arria V GZ Recommended Speed Grades for All Avalon-ST Widths and Frequencies Application Recommended...
  • Page 18 Chapter 1: Arria V GZ Datasheet Recommended Speed Grades Table 1–7 lists the recommended speed grades for the Avalon-MM interface. Table 1–7. Arria V GZ Recommended Speed Grades for All Avalon-MM Widths and Frequencies Application Recommended Lane Rate Link Width...
  • Page 19 Hard IP for PCI Express in <install_dir>/ip/altera/altera_pcie/ altera_pcie_hip_ast_ed/example_design/<device> directory. If you have an existing Arria V GZ 12.0 or older design, you must regenerate it in 12.1 before compiling with the 12.1 version of the Quartus II software. After you install the Quartus II software for 12.1, you can copy the design examples from the <install_dir>/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/...
  • Page 20 Chapter The Arria V GZ Hard IP for PCI Express offers exactly the same feature set in both the MegaWizard and Qsys design flows. Consequently, your choice of design flow depends on whether you want to integrate the Arria V GZHard IP for PCI Express using RTL instantiation or using Qsys, which is a system integration tool available in the Quartus II software.

  • Page 21: Megawizard Plug-In Manager Design Flow

    Chapter 2: Getting Started with the Arria V GZ Hard IP for PCI Express 2–3 MegaWizard Plug-In Manager Design Flow The following sections provide step-by-step instructions for both design flows. Steps 1 to 3 are different for each design flow and are described separately. Step 4 is identical for both flows and is described once.

  • Page 22: Customizing The Endpoint In The Megawizard Plug-In Manager Design Flow

    6. Specify a variation name for output files <working_dir>/example_design/ <variation name>. For this walkthrough, specify <working_dir>/example_design/ gen1_x8. 7. Click Next to open the parameter editor for the Arria V GZ Hard IP for PCI Express. 8. Specify the System Settings values listed inTable 2–1.
  • Page 23 Chapter 2: Getting Started with the Arria V GZ Hard IP for PCI Express 2–5 MegaWizard Plug-In Manager Design Flow Table 2–1. System Settings Parameters (Part 2 of 2) Parameter Value Application Layer interface Avalon-ST 64-bit RX buffer credit allocation - performance for...
  • Page 24 2–6 Chapter 2: Getting Started with the Arria V GZ Hard IP for PCI Express MegaWizard Plug-In Manager Design Flow 12. Specify the Device settings listed in Table 2–4. Table 2–4. Device Settings Parameter Value Maximum payload size 256 bytes...

  • Page 25: Understanding The Files Generated

    Chapter 2: Getting Started with the Arria V GZ Hard IP for PCI Express 2–7 MegaWizard Plug-In Manager Design Flow 23. Click Yes if you are prompted to add the Quartus II IP File (.qip) to the project. The .qip is a file generated by the parameter editor contains all of the necessary assignments and information required to process the IP core in the Quartus II compiler.
  • Page 26 2–8 Chapter 2: Getting Started with the Arria V GZ Hard IP for PCI Express MegaWizard Plug-In Manager Design Flow 3. Click pcie_de_gen1_x8_ast128.qsys to bring up the Qsys design. Figure 2–3 illustrates this Qsys system. Figure 2–3. Qsys System Connecting the Endpoint Variant and Chaining DMA Testbench...

  • Page 27: Qsys Design Flow

    Chapter 2: Getting Started with the Arria V GZ Hard IP for PCI Express 2–9 Qsys Design Flow 4. To display the parameters of the APPS component shown in Figure 2–3, click on it and then select Edit from the right-mouse menu. illustrates this component. Note...
  • Page 28 2–10 Chapter 2: Getting Started with the Arria V GZ Hard IP for PCI Express Qsys Design Flow Figure 2–4 illustrates this Qsys system. Figure 2–4. Complete Gen1 ×4 Endpoint (DUT) Connected to Example Design (APPS) The example design includes the following four components: ■...

  • Page 29: Generating The Testbench

    Chapter 2: Getting Started with the Arria V GZ Hard IP for PCI Express 2–11 Qsys Design Flow ■ Transceiver Reconfiguration Controller—The Transceiver Reconfiguration Controller dynamically reconfigures analog settings to improve signal quality. For Gen1 and Gen2 data rates, the Transceiver Reconfiguration Controller must perform offset cancellation and PLL calibration.

  • Page 30: Simulating The Example Design

    2–12 Chapter 2: Getting Started with the Arria V GZ Hard IP for PCI Express Qsys Design Flow Table 2–10. Qsys Generation Output Files (Part 2 of 2) Directory Description <testbench_dir>/<variant_name>/ Includes testbench subdirectories for the Aldec, Cadence and Mentor simulation testbench/ tools with the required libraries and simulation scripts.
  • Page 31 Chapter 2: Getting Started with the Arria V GZ Hard IP for PCI Express 2–13 Qsys Design Flow Example 2–1. Excerpts from Transcript of Successful Simulation Run (continued) # INFO: 8973 ns RP LTSSM State: CONFIG.LANENUM.WAIT # INFO: 9537 ns EP LTSSM State: CONFIG.LANENUM.WAIT # INFO: 9857 ns EP LTSSM State: CONFIG.LANENUM.ACCEPT...
  • Page 32 2–14 Chapter 2: Getting Started with the Arria V GZ Hard IP for PCI Express Qsys Design Flow Example 2-1Excerpts from Transcript of Successful Simulation Run (continued) # INFO: 72440 ns Writing Descriptor header # INFO: 72480 ns data content of the DT header...

  • Page 33: Understanding Channel Placement Guidelines

    Chapter 2: Getting Started with the Arria V GZ Hard IP for PCI Express 2–15 Quartus II Compilation Example 2-1 Excerpts from Transcript of Successful Simulation Run (continued) # INFO: 105257 ns TASK:rcmem_poll ---> Received Expected Data (00000002) # INFO:...

  • Page 34: Compiling The Design In The Qsys Design Flow

    Quartus II project and add your Qsys files to that project. Complete the following steps to create your Quartus II project: 1. From the Windows Start Menu, choose Programs > Altera > Quartus II 12.1 to run the Quartus II software.
  • Page 35 Chapter 2: Getting Started with the Arria V GZ Hard IP for PCI Express 2–17 Quartus II Compilation 5. On the Directory, Name, Top-Level Entity page, enter the following information: a. The working directory shown is correct. You do not have to change it.
  • Page 36 2–18 Chapter 2: Getting Started with the Arria V GZ Hard IP for PCI Express Quartus II Compilation 14. Add the Synopsys Design Constraint (SDC) shown inExample 2–3, to the top-level design file for your Quartus II project. Example 2–3. Synopsys Design Constraint create_clock -period “100 MHz”...

  • Page 37: Modifying The Example Design

    Chapter 2: Getting Started with the Arria V GZ Hard IP for PCI Express 2–19 Quartus II Compilation Modifying the Example Design To use this example design as the basis of your own design, replace the Chaining DMA Example shown in Figure 2–5...
  • Page 38 2–20 Chapter 2: Getting Started with the Arria V GZ Hard IP for PCI Express Quartus II Compilation Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...
  • Page 39 ■ Transceiver Reconfiguration Controller In the Qsys design flow you select the Avalon-MM Arria V GZ Hard IP for PCI Express as a component. This component supports PCI Express ×1, ×2, ×4, or ×8 Endpoint applications with bridging logic to convert PCI Express packets to Avalon-MM transactions and vice versa.

  • Page 40: Running Qsys

    3–2 Chapter 3: Getting Started with the Avalon-MM Arria V GZ Hard IP for PCI Express Running Qsys Figure 3–1 illustrates, the design example transfers data between an on-chip memory buffer located on the Avalon-MM side and a PCI Express memory buffer located on the root complex side.

  • Page 41: Customizing The Arria V Gz Hard Ip For Pci Express Ip Core

    Chapter 3: Getting Started with the Avalon-MM Arria V GZ Hard IP for PCI Express 3–3 Customizing the Arria V GZ Hard IP for PCI Express IP Core Refer to Creating a System with Qsys in volume 1 of the Quartus II Handbook for more information about how to use Qsys, including information about the Project Settings tab.
  • Page 42 3–4 Chapter 3: Getting Started with the Avalon-MM Arria V GZ Hard IP for PCI Express Customizing the Arria V GZ Hard IP for PCI Express IP Core For more information about the use of BARs to translate PCI Express addresses to Avalon-MM addresses, refer to “PCI Express-to-Avalon-MM Address Translation for...

  • Page 43: Adding The Remaining Components To The Qsys System

    6. Click Finish. 7. To rename the Arria V GZ hard IP for PCI Express, in the Name column of the System Contents tab, right-click on the component name, select Rename, and type DUT r Your system is not yet complete, so you can ignore any error messages generated by Qsys at this stage.
  • Page 44 3–6 Chapter 3: Getting Started with the Avalon-MM Arria V GZ Hard IP for PCI Express Adding the Remaining Components to the Qsys System 3. In the DMA Controller parameter editor, specify the parameters and conditions listed in Table 3–8.
  • Page 45 Chapter 3: Getting Started with the Avalon-MM Arria V GZ Hard IP for PCI Express 3–7 Adding the Remaining Components to the Qsys System Table 3–9. On-Chip Memory Parameters (Part 2 of 2) Parameter Value Enable In-System Memory Content Editor feature D...

  • Page 46: Completing The Connections In Qsys

    3–8 Chapter 3: Getting Started with the Avalon-MM Arria V GZ Hard IP for PCI Express Completing the Connections in Qsys 12. Click Finish. 13. The Transceiver Reconfiguration Controller is added to your Qsys system. For more information about the Transceiver Reconfiguration Controller, refer to the...

  • Page 47: Specifying Clocks And Interrupts

    Chapter 3: Getting Started with the Avalon-MM Arria V GZ Hard IP for PCI Express 3–9 Specifying Clocks and Interrupts Table 3–11. Qsys Connections (Part 2 of 2) Make Connection From: DUT Txs Avalon Memory Mapped Slave dma_0 write_master Avalon Memory Mapped Master...

  • Page 48: Specifying Address Assignments

    3–10 Chapter 3: Getting Started with the Avalon-MM Arria V GZ Hard IP for PCI Express Specifying Address Assignments Specifying Address Assignments Qsys requires that you resolve the base addresses of all Avalon-MM slave interfaces in the Qsys system. You can either use the auto-assign feature, or specify the base addresses manually.

  • Page 49: Simulating The Example Design

    Chapter 3: Getting Started with the Avalon-MM Arria V GZ Hard IP for PCI Express 3–11 Simulating the Example Design Figure 3–2 illustrates the complete system. Figure 3–2. Complete PCI Express Example Design For this example BAR1:0 is 22 bits or 4 MBytes. This BAR accesses Avalon addresses from 0x00200000–...
  • Page 50 3–12 Chapter 3: Getting Started with the Avalon-MM Arria V GZ Hard IP for PCI Express Simulating the Example Design 4. After Qsys reports Generate Completed in the Generate progress box title, click Close. 5. On the File menu, click Save. and type the file name ep_g1x4.qsys.
  • Page 51 Chapter 3: Getting Started with the Avalon-MM Arria V GZ Hard IP for PCI Express 3–13 Simulating the Example Design For more information about IP functional simulation models, refer to Simulating Altera Designs in volume 3 of the Quartus II Handbook.
  • Page 52 3–14 Chapter 3: Getting Started with the Avalon-MM Arria V GZ Hard IP for PCI Express Simulating the Example Design Example 3–1 shows the transcript from a successful simulation run. Example 3–1. Transcript from ModelSim Simulation of Gen1 x4 Endpoint # 464 ns Completed initial configuration of Root Port.
  • Page 53 Chapter 3: Getting Started with the Avalon-MM Arria V GZ Hard IP for PCI Express 3–15 Simulating the Example Design Example 3–1. Transcript from ModelSim Simulation of Gen1 x4 Endpoint (continued) # INFO: 37960 ns EP PCI Express Capabilities Register (0002):...

  • Page 54: Understanding Channel Placement Guidelines

    3–16 Chapter 3: Getting Started with the Avalon-MM Arria V GZ Hard IP for PCI Express Understanding Channel Placement Guidelines Example 3–1. Transcript from ModelSim Simulation of Gen1 x4 Endpoint (continued) # INFO: 54368 ns Setup BAR = 2 # INFO:...

  • Page 55: Compiling The Design

    Chapter 3: Getting Started with the Avalon-MM Arria V GZ Hard IP for PCI Express 3–17 Compiling the Design 2. Click Next in the New Project Wizard: Introduction (The introduction does not appear if you previously turned it off.) 3. On the Directory, Name, Top-Level Entity page, enter the following information: a.
  • Page 56 3–18 Chapter 3: Getting Started with the Avalon-MM Arria V GZ Hard IP for PCI Express Programming a Device Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 57: Chapter 4. Parameter Settings

    Express. This chapter also describes the parameters which you can set for the Avalon-MM Arria V GZ Hard IP for PCI Express in the Qsys design flow. For the most part, the two Arria V GZ Hard IPs for PCI Express offer almost the same parameters Table 4–1...
  • Page 58 Endpoint designs. Select Legacy Endpoint only when you require I/O transaction support for compatibility. The Legacy Endpoint is not Native Endpoint available for the Avalon-MM Arria V GZ Hard IP for PCI Express. Port type Root Port The Endpoint stores parameters in the Type 0 Configuration Space which...
  • Page 59 125 MHz to go to recovery. Arria V GZ PCIe Hard IP in Gen1 or Gen2 modes are not affected by this issue. Systems using the common reference clock (0 ppm) are not affected by this issue. The primary repercussion of this is a slight decrease in bandwidth.

  • Page 60: Base Address Register (Bar) And Expansion Rom Settings

    Specifies the size of the optional ROM. The expansion ROM is not Expansion ROM Disabled–16 MBytes available for the Avalon-MM Arria V GZ Hard IP for PCI Express. Base and Limit Registers for Root Ports Table 4–4 describes the Base and Limit registers which are available in the Type 1 Configuration Space for Root Ports.

  • Page 61: Device Identification Registers

    3.0. Address: 0x02C. Subsystem Sets the read-only value of the Subsystem Device ID register in the 16 bits 0x0000 Device ID PCI Type 0 Configuration Space. Address: 0x02C November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...

  • Page 62: Pci Express And Pci Capabilities Parameters

    Device Control register. This bit is available to the Application Layer on the tl_cfg_ctl output signal as cfg_devcsr[8]. The Avalon-MM Arria V GZ Hard IP for PCI Express always supports 8 tags. You do not need to configure this parameter.
  • Page 63 ■ 1111 Ranges A, B, C, and D ■ All other values are reserved. Altera recommends that the completion timeout mechanism expire in no less than 10 ms. For Endpoints using PCI Express version 2.0, this option must be Implement On.

  • Page 64: Error Reporting

    Table 4–7: (1) Throughout the Arria V GZ Hard IP for PCI Express User Guide, the terms word, dword and qword have the same meaning that they have in the PCI Express Base Specification Revision 2.1 or 3.0. A word is 16 bits, a dword is 32 bits, and a qword is 64 bits.

  • Page 65: Msi And Msi-X Capabilities

    Table 4–6: (1) Throughout The Arria V GZ Hard IP for PCI Express User Guide, the terms word, dword and qword have the same meaning that they have in PCI Express Base Specification Revision 1.0a, 1.1, 2.0 or 2.1. A word is 16 bits, a dword is 32 bits, and a qword is 64 bits.

  • Page 66: Slot Capabilities

    PCI Express Capabilities Register. This parameter is only supported for the Arria V GZ Hard IP for PCI Express in Root Port mode. Defines the characteristics of the slot. You turn on this option by selecting Enable slot capability.

  • Page 67: Power Management

    Device Capabilities Register (0x084). Maximum of 128 n The Arria V GZ Hard IP for PCI Express and Avalon-MM Arria V GZ Hard IP Maximum of 256 ns for PCI Express do not support the L0s or L1 states. However, in a switched...

  • Page 68: Avalon Memory-Mapped System Settings

    Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support. Turning on this option enables the Avalon-MM Arria V GZ Hard IP for PCI Auto Enable PCIe Express interrupt register at power-up. Turning off this option disables the...

  • Page 69: Avalon To Pcie Address Translation Settings

    Specifies the size of each memory segment. Each memory segment must Size of address 4 KByte –4 GBytes be the same size. Refer to Avalon-MM-to-PCI Express Address Translation pages Algorithm for more information about address translation. November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...
  • Page 70 4–14 Chapter 4: Parameter Settings Avalon to PCIe Address Translation Settings Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 71: Chapter 5. Ip Core Architecture

    5. IP Core Architecture November 2012 UG-01097-1.4 This chapter describes the architecture of the Arria V GZ Hard IP for PCI Express. The Arria V GZ Hard IP for PCI Express implements the complete PCI Express protocol stack as defined in the PCI Express Base Specification 3.0.
  • Page 72 The Hard IP includes dedicated clock domain crossing logic (CDC) between the PHYMAC and Data Link Layers. This chapter provides an overview of the architecture of the Arria V GZ Hard IP for PCI Express. It includes the following sections: ■...

  • Page 73: Key Interfaces

    Key Interfaces Key Interfaces If you select the Arria V GZ Hard IP for PCI Express, your design includes an Avalon-ST interface to the Application Layer. If you select the Avalon-MM Arria V GZ Hard IP for PCI Express, your design includes an Avalon-MM interface to the Application Layer.

  • Page 74: Clocks And Reset

    6–17Avalon-MM Interface In Qsys, the Arria V GZ Hard IP for PCI Express is available with either an Avalon-ST interface or an Avalon-MM interface to the Application Layer. When you select the Avalon-MM Arria V GZ Hard IP for PCI Express, an Avalon-MM bridge module connects the PCI Express link to the system interconnect fabric.

  • Page 75: Interrupts

    Chapter 5: IP Core Architecture 5–5 Transaction Layer Interrupts The Arria V GZ Hard IP for PCI Express offers three interrupt mechanisms: ■ Message Signaled Interrupts (MSI)— MSI uses the Transaction Layer's request-acknowledge handshaking protocol to implement interrupts. The MSI Capability structure is stored in the Configuration Space and is programmable using Configuration Space accesses.
  • Page 76 Transaction Layer RX Datapath RX Buffer Avalon-ST RX Data Posted & Completion Control RX Transaction Layer Packet Non-Posted Transaction Layer Avalon-ST Packet FIFO RX Control Reordering Flow Control Update Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 77: Configuration Space

    Management of the retry buffer ■ Link retraining requests in case of error through the Link Training and Status State Machine (LTSSM) of the Physical Layer November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...
  • Page 78 NAK DLLP reception. For ACK DLLP reception, the retry buffer discards all acknowledged packets. ■ ACK/NAK Packets—The ACK/NAK block handles ACK/NAK DLLPs and generates the sequence number of transmitted packets. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 79: Physical Layer

    ACK/NAK FC DLLP (low priority) Physical Layer The Physical Layer is the lowest level of the Arria V GZ Hard IP for PCI Express. It is the layer closest to the link. It encodes and transmits packets across a link and accepts and decodes received packets.
  • Page 80 The Physical Layer integrates both digital and analog elements. Intel designed the PIPE interface to separate the MAC from the PHY. The Arria V GZ Hard IP for PCI Express compiles with the PIPE interface specification.

  • Page 81: Pci Express Avalon-Mm Bridge

    DLL. PCI Express Avalon-MM Bridge In Qsys, the Arria V GZ Hard IP for PCI Express is available with either an Avalon-ST or an Avalon-MM interface to the Application Layer. When you select the Avalon-MM Arria V GZ Hard IP for PCI Express, an Avalon-MM bridge module connects the PCI Express link to the interconnect fabric.
  • Page 82 PCI Link Tx Read Response Tx Slave Module Address Translator Avalon-MM PCI Express Rx Master Rx Controller Avalon-MM Rx Read Response Rx Master Module Rx Master Module Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 83: Avalon-Mm Bridge Tlps

    The Avalon-MM byte enables must be asserted in the first qword of the burst. ■ All subsequent byte enables must be asserted until the deasserting byte enable. November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...

  • Page 84: Avalon-Mm-To-Pci Express Upstream Read Requests

    Avalon-MM Bridge TLPs ■ The Avalon-MM byte enables may deassert, but only in the last qword of the burst. To improve PCI Express throughput, Altera recommends using an Avalon-MM burst master without any byte-enable restrictions. Avalon-MM-to-PCI Express Upstream Read Requests...

  • Page 85: Pci Express-To-Avalon-Mm Downstream Read Requests

    4’b1000 Write byte 3 only In burst mode, the Arria V GZ Hard IP for PCI Express supports only byte enable values that correspond to a contiguous data burst. For the 32-bit data width example, valid values in the first data phase are 4’b1111, 4’b1110, 4’b1100, and 4’b1000, and valid values in the final data phase of the burst are 4’b1111, 4’b0111, 4’b0011, and 4’b0001.

  • Page 86: Pci Express-To-Avalon-Mm Address Translation For Endpoints

    Registers in the GUI. 1. BAR1:0 is a 64-bit prefetchable memory that is 4KBytes -12 bits 2. System software programs BAR1:0 to have a base address of 0x00001234 56789000 Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 87: Minimizing Bar Sizes And The Pcie Address Space

    Instruction_Mem (On-Chip Memory (RAM or ROM)) of 64 KBytes—Qsys auto-assigned a base address of 0x10020000 ■ PCIe (Avalon-MM Arria V GZ Hard IP for PCI Express) Cra (Avalon-MM Slave)—auto assigned base address of 0x10004000 ■ Rxm_BAR0 connects to Offchip_Data_Mem DDR3 avl ■...
  • Page 88 BAR4 is also 29 bits. BAR4 address PCIe Cra which is 16 KBytes. It should only require 14 address bits; however, it is also consuming 512 MBytes of address space. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation...

  • Page 89: Avalon-Mm-To-Pci Express Address Translation Algorithm

    PCI Express address before the request packet is sent to the Transaction Layer. You can specify up to 512 address pages and sizes ranging from 4 KByte to 4 GBytes when you customize your Avalon-MM Arria V GZ Hard IP for PCI Express as described in “Avalon to PCIe Address Translation Settings”...
  • Page 90 For more information about how to access the dynamic address translation table through the CRA slave, refer to the “Avalon-MM-to-PCI Express Address Translation Table 0x1000–0x1FFF” on page 7–15. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 91: Completer Only Single Dword Endpoint

    Read and write requests of a single dword (32 bits) from the Root Complex ■ Completion with Completer Abort status generation for other types of non-posted requests ■ INTX or MSI support with one Avalon-MM interrupt source November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...

  • Page 92: Rx Block

    Figure 5–13 illustrates, the completer-only single dword endpoint connects to a PCI Express root complex. A bridge component includes the Arria V GZ Hard IP for PCI Express TX and RX blocks, an Avalon-MM RX master, and an interrupt handler.

  • Page 93: Tx Block

    IRQ column of Qsys. When the MSI registers in the Configuration Space of the Completer Only Single Dword Arria V GZ Hard IP for PCI Express are updated, there is a delay before this information is propagated to the Bridge module shown in Figure 5–13.
  • Page 94 5–24 Chapter 5: IP Core Architecture Completer Only Single Dword Endpoint Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 95: Chapter 6. Ip Core Interfaces

    November 2012 UG-01097-1.4 This chapter describes the signals that are part of the Arria V GZ Hard IP for PCI Express. It describes the top-level signals in the following variants: Signals in the Arria V GZ Hard IP for PCI Express with Avalon-ST Interface ■...
  • Page 96 Arria V GZ Hard IP for PCI Express using the Avalon-ST interface. Figure 6–1. Signals in the Arria V GZ Hard IP for PCI Express with Avalon-ST Interface Hard IP for Express, Avalon-ST Interface...
  • Page 97 The signals are described in the order in which they are shown in Figure 6–1. Table 6–1. Signal Groups in the Arria V GZ Hard IP for PCI Express Signal Group Description Logical Avalon-ST RX “Avalon-ST RX Interface”...

  • Page 98: Avalon-St Rx Interface

    1 indicates that a TLP ends in rx_st_data[255:128] ■ In single packet per cycle mode, this signal is a single bit which indicates that a TLP ends in this cycle. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...
  • Page 99 <n>, then <n + readyLatency> is a ready cycle, during which the Transaction Layer may assert valid and transfer data. The RX interface supports a readyLatency of 2 cycles. November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...
  • Page 100 1 applies to rx_st_data[255:128] ■ bit 0 applies to rx_st_data[127:0] ■ Altera recommends resetting the Arria V GZ Hard IP for PCI Express when an uncorrectable (double-bit) ECC error is detected. Component Specific Signals The Application Layer asserts this signal to tell the Hard IP to stop sending non-posted requests.

  • Page 101: Data Alignment And Timing For The 64-Bit Avalon-St Rx Interface

    Data Alignment and Timing for the 64-Bit Avalon-ST RX Interface To facilitate the interface to 64-bit memories, the Arria V GZ Hard IP for PCI Express aligns data to the qword or 64 bits by default; consequently, if the header presents an address that is not qword aligned, the Hard IP block shifts the data within the qword to achieve the correct alignment.
  • Page 102 64-bit bus. In this example, the byte address is unaligned and ends with 0x4, causing the first data to correspond to rx_st_data[63:32]. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...
  • Page 103 Figure 6–5. 64-Bit Avalon-ST rx_st_data<n> Cycle Definitions for 4-Dword Header TLPs with Qword Aligned Addresses pld_clk rx_st_data[63:32] header1 header3 data1 rx_st_data[31:0] header0 header2 data0 rx_st_sop rx_st_eop rx_st_be[7:4] rx_st_be[3:0] November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...
  • Page 104 Figure 6–7 illustrates the timing of the RX interface when the Application Layer backpressures the Arria V GZ Hard IP for PCI Express by deasserting rx_st_ready. The rx_st_valid signal deasserts within three cycles after rx_st_ready is deasserted. In this example, rx_st_valid is deasserted in the next cycle. rx_st_data is held until the Application Layer is able to accept it.

  • Page 105: Data Alignment And Timing For The 128-Bit Avalon-St Rx Interface

    Figure 6–9. 128-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-Dword Header TLPs with Qword Aligned Addresses pld_clk data3 rx_st_data[127:96] header2 data2 rx_st_data[95:64] header1 data1 data<n> rx_st_data[63:32] header0 data0 data<n-1> rx_st_data[31:0] rx_st_bardec[7:0] rx_st_sop rx_st_eop rx_st_empty rx_st_valid November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...
  • Page 106 Header 3 Data 2 rx_st_data[127:96] Data n Header 2 Data 1 rx_st_data[95:64] Data n-1 Header 1 Data 0 rx_st_data[63:32] Data n-2 Header 0 rx_st_data[31:0] rx_st_sop rx_st_eop rx_st_empty Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...
  • Page 107 4562 . . . c19a . . . 000a7896c000bc34... 3458ce. . . 2457ce. . . 0217b . . . 134c . . . 8945 . . . rx_st_data[127:0] rx_st_sop rx_st_eop rx_st_empty rx_st_ready rx_st_valid November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...

  • Page 108: Single Packet Per Cycle

    256-bit Avalon-ST interface. Turn on Enable Multiple Packets per Cycle on the System Settings tab of the parameter editor to change multiple packets per cycle. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 109: Data Alignment And Timing For 256-Bit Avalon-St Rx Interface

    Figure 6–17. 256-Bit Avalon-ST RX Packets Use of rx_st_empty and Single-Cycle Packets pld_clk XXXXXXXXXXXXXXXX. . . 4592001487DF08876210... XX..BE ... rx_st_data[255:0] rx_st_sop rx_st_eop rx_st_empty[1:0] rx_st_ready rx_st_valid November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...

  • Page 110: Multiple Packets Per Cycle (256-Bit Interface Only)

    12... 12... 00... 12... 12... 12... 12... 12... 12... 12... 003458 FF... FFFFFFFF FFFFFFFF rx_st_be[31:0] rx_st_sop[0] rx_st_eop[0] rx_st_sop[1] rx_st_eop[1] rx_st_ready rx_st_valid rx_st_bardec1[7:0] rx_st_bardec2[7:0] rx_st_empty[1:0] rx_st_err rx_st_mask Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 111: Avalon-St Tx Interface

    2 cycles to facilitate timing closure; however, a readyLatency of 1 cycle is possible. If no other delays are added to the read-valid latency, the resulting delay corresponds to a readyLatency of 2. November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...
  • Page 112 ■ bit 0 applies to tx_st_data[127:0] ■ To facilitate timing closure, Altera recommends that you register both the tx_st_ready and tx_st_valid signals. If no other delays are added to the ready-valid latency, the resulting delay corresponds to a readyLatency of 2.
  • Page 113 [0]: completion data ■ During a single cycle, the IP core can consume either a single header credit or both a header and a data credit. November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...

  • Page 114: Avalon-St Packets To Pci Express Tlps

    For additional information about TLP packet headers, refer to Appendix A, Transaction Layer Packet (TLP) Header Formats and Section 2.2.1 Common Packet Header Fields in the PCI Express Base Specification 2.1. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 115: Data Alignment And Timing For The 64-Bit Avalon-St Tx Interface

    (4) Header3 = pcie_hdr _byte12, pcie_hdr _byte13, header_byte14, pcie_hdr _byte15}, 4 dword header only (5) Data0 = {pcie_data_byte3, pcie_data_byte2, pcie_data_byte1, pcie_data_byte0} (6) Data1 = {pcie_data_byte7, pcie_data_byte6, pcie_data_byte5, pcie_data_byte4} November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...
  • Page 116 Figure 6–22 illustrates the timing of the TX interface when the Arria V GZ Hard IP for PCI Express backpressures the Application Layer by deasserting tx_st_ready. Because the readyLatency is two cycles, the Application Layer deasserts tx_st_valid after two cycles and holds tx_st_data until two cycles after tx_st_ready is asserted.

  • Page 117: Data Alignment And Timing For The 128-Bit Avalon-St Tx Interface

    Data 4 tx_st_data[127:96] tx_st_data[95:64] Header 2 Data 3 Header 1 Data 2 Data (n) tx_st_data[63:32] Header 0 Data 1 Data (n-1) tx_st_data[31:0] tx_st_sop tx_st_eop tx_st_valid tx_st_empty tx_st_err November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...
  • Page 118 Data 2 tx_st_data[127:96] Data n Header 2 Data 1 tx_st_data[95:64] Data n-1 Header 1 Data 0 tx_st_data[63:32] Data n-2 Header 0 tx_st_data[31:0] tx_st_sop tx_st_eop tx_st_valid tx_st_empty Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 119: Data Alignment And Timing For The 256-Bit Avalon-St Tx Interface

    Figure 6–29 illustrates the timing of the TX interface when the Arria V GZ Hard IP for PCI Express backpressures the Application Layer by deasserting tx_st_ready. Because the readyLatency is two cycles, the Application Layer deasserts tx_st_valid after two cycles and holds tx_st_data until two cycles after tx_st_ready is reasserted Figure 6–29.

  • Page 120: Single Packet Per Cycle

    Header 1 Header 0 tx_st_data[63:0] Data 0 Header 2 XXXXXXXX Header 2 tx_st_data[127:64] XXXXXXXX Data 0 XXXXXXXXX XXXXXXXX tx_st_data[191:128] XXXXXXXXX XXXXXXXX XXXXXXXXX XXXXXXXX tx_st_data[255:192] tx_st_sop tx_st_empty[1:0] Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 121: Multiple Packets Per Cycle

    ECRC data for TX data. For packets with no payload data, the ECRC position corresponds to the position of Data0 in these figures. November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...

  • Page 122: Clock Signals

    Table 6–6. Clock Signals Hard IP Implementation Signal Description Reference clock for the Arria V GZ Hard IP for PCI Express. It must have the frequency refclk specified under the System Settings heading in the parameter editor. Clocks the Application Layer. You must drive this clock from coreclkout_hip.
  • Page 123 “Configuration via Protocol (CvP)” on page 10–1. Arria V GZ devices have up to 4 instances of the Hard IP for PCI Express. Each instance has its own pin_perst signal. Every Arria V GZ device has 4 nPERST pins, even devices with fewer than 4 instances of the Hard IP for PCI Express.
  • Page 124 ■ 11010: Speed.Recovery ■ 11011: Recovery.Equalization, Phase 0 ■ ltssmstate[4:0] (continued) 11100: Recovery.Equalization, Phase 1 ■ 11101: Recovery.Equalization, Phase 2 ■ 11110: recovery.Equalization, Phase 3 ■ Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 125: Error Signals

    If a specific location of MRAM has errors, as long as that data is in the ECC decoder, the flag indicates the error. When a correctable ECC error occurs, the Arria V GZ Hard IP for PCI Express recovers without any loss of information. No Application Layer intervention is required.

  • Page 126: Interrupts For Endpoints

    Refer to Figure 11–5 on page 11–4 Figure 11–6 on page 11–5 for timing information. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 127: Interrupts For Endpoints When Multiple Msi/Msi-X Support Is Enabled

    Table 6–12 describes the signals that comprise the completion side band signals for the Avalon-ST interface. The Arria V GZ Hard IP for PCI Express provides a completion error interface that the Application Layer can use to report errors, such as programming model errors.
  • Page 128 Many cases of unexpected completions are detected and reported internally by the Transaction Layer. For a list of these cases, refer to “Transaction Layer Errors” on page 13–3. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 129: Transaction Layer Configuration Space Signals

    Table 6–15 on page 6–38. Configuration status bits. This information updates every pld_clk cycle. Refer to Table 6–14 tl_cfg_sts[52:0] for a detailed description of the status bits. November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...
  • Page 130 Link Status Register[15:0] Bit 12: Slot clock configuration ■ Bit 11: Link Training ■ Bit 10: Undefined ■ Bits[9:4]: Negotiated Link Width ■ Bits[3:0] Link Speed ■ Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 131: Configuration Space Register Access Timing

    Configuration Space register information is being driven onto tl_cfg_ctl. Figure 6–33. tl_cfg_ctl Timing pld_clk tl_cfg_add[3:0] 00... 00... 00... 7F... 00... 00... 00000000 00000000 tl_cfg_ctl[31:0] November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...

  • Page 132: Configuration Space Register Access

    Device Control for the PCI Express Table 7–7 on cfg_dev_ctrl capability structure. page 7–4 cfg_dev2ctrl[15:0] is device control 2 for the PCI Express Table 7–8 on cfg_dev_ctrl2 capability structure. page 7–5 Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...
  • Page 133 7–4 L0 state. Retraining directs the LTSSM to the Recovery state. Retraining to a higher data rate is not automatic for the Arria V GZ Hard IP for PCI Express IP Core even if both devices on the link are capable of a higher data rate.
  • Page 134 — cfg_tcvcmap cfg_tcvcmap[8:6]: Mapping for TC2. cfg_tcvcmap[11:9]: Mapping for TC3. cfg_tcvcmap[14:12]: Mapping for TC4. cfg_tcvcmap[17:15]: Mapping for TC5. cfg_tcvcmap[20:18]: Mapping for TC6. cfg_tcvcmap[23:21]: Mapping for TC7. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...
  • Page 135 3’b010: 4 MSI allocated ■ [6:4] message 3’b011: 8 MSI allocated ■ enable 3’b100: 16 MSI allocated ■ 3’b101: 32 MSI allocated ■ 3’b110: Reserved ■ 3’b111: Reserved ■ November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...

  • Page 136: Parity Signals

    System Settings heading of the parameter editor. Parity is odd. This option is not available for the Avalon-MM Arria V GZ Hard IP for PCI Express. Parity protection provides some data protection in systems that do not use ECRC checking.

  • Page 137: Lmi Signals

    ■ which drives 2’b01 to indicate the error. Altera recommends resetting the Arria V GZ Hard IP for PCI Express when this error is detected. Contact Altera if resetting becomes unworkable. When asserted for a single cycle, indicates that a parity error was detected in a TLP at the input of the RX buffer.
  • Page 138 AER header logging, and debugging purposes only. In Root Port mode, do not access the Configuration Space using TLPs and the LMI bus simultaneously. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 139: Lmi Read Operation

    10-bit address and 16-bit data. You can use this bus dynamically modify the value of configuration registers that are read-only at run time. To ensure proper system operation, Altera recommends that you reset or repeat device enumeration of the PCI Express link after changing the value of read-only configuration registers of the Hard IP.
  • Page 140 D2 D3 3 clks avmm_rd avmm_rdata[15:0] For a detailed description of the Avalon-MM protocol, refer to the Avalon Memory-Mapped Interfaces chapter in the Avalon Interface Specifications. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 141: Power Management Signals

    Table 6–23 shows the layout of the Power Management Capabilities register. Table 6–23. Power Management Capabilities Register data rsvd PME_status data_scale data_select PME_EN rsvd PM_state register November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...
  • Page 142 Then, the Application Layer sends the PME_to_ack message to the Root Port by asserting pme_to_cr. Figure 6–38. pme_to_sr and pme_to_cr in an Endpoint IP core pme_to_sr hard pme_to_cr Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 143: Avalon-Mm Interface

    6–39, signals listed for rxm_bar0 are also exist for rxm_bar1 through rxm_bar5 when those BARs are enabled in the parameter editor. Figure 6–39. Signals in the Qsys Avalon-MM Arria V GZ Hard IP for PCI Express Avalon-MM Hard IP for PCI Express...

  • Page 144: 32-Bit Non-Bursting Avalon-Mm Control Register Access (Cra) Slave Signals

    Avalon-MM Arria V GZ Hard IP for PCI Express with links to the sections that describe them. Table 6–25. Signal Groups in the Avalon-MM Arria V GZ Hard IP for PCI Express Variants Completer Full...

  • Page 145: Rx Avalon-Mm Master Signals

    16 individual interrupt signals (<m> 15). Note to Table 6–27: (1) <n> represents the BAR number for all signals. The core supports up to 6 BARs. November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...

  • Page 146: 64-Bit Bursting Tx Avalon-Mm Slave Signals

    64-Bit Bursting TX Avalon-MM Slave Signals This optional Avalon-MM bursting slave port propagates requests from the interconnect fabric to the full-featured Avalon-MM Arria V GZ Hard IP for PCI Express. Requests from the interconnect fabric are translated into PCI Express request packets.

  • Page 147: Physical Layer Interface Signals

    PHY, the MegaWizard Plug-In Manager generates a SERDES variation file, <variation>_serdes.<v or vhd >, in addition of the Hard IP variation file, <variation>.<v or vhd>. For Arria V GZ devices the SERDES entity is included in the library files for PCI Express.

  • Page 148: Transceiver Reconfiguration

    You can use the Altera Transceiver Reconfiguration Controller to reconfig_to_xcvr[(<n>70)-1:0] dynamically reconfigure analog settings in Arria V GZ devices. For more information about instantiating the Altera Transceiver Reconfiguration Controller IP core refer to Chapter 15, Hard IP Reconfiguration and Transceiver Reconfiguration.

  • Page 149: Channel Placement For Gen1 And Gen2 Using Cmu Pll

    PCIe Lane 1 Channel 1 - CMU PLL Channel 0 - Channel 0 - Data PCIe Lane 0 PCIe Lane 0 Data LCD = Local Clock Divider November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...
  • Page 150 Channel 2 - Data PCI Express Lane 2 PCI Express Lane 1 Channel 1 - Data Channel 0 -Data PCI Express Lane 0 CCD = Central Clock Divider Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...
  • Page 151 Channel 2 - Data PCI Express Lane 2 Channel 1 - Data PCI Express Lane 1 Channel 0 - Data PCI Express Lane 0 CCD = Central Clock Divider November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...

  • Page 152: Channel Placement For Gen1 And Gen2 Using Atx Pll

    Channel 0 - Channel 0 - PCI Express Lane 0 PCI Express Lane 0 Data Data LCD = Local Clock Divider CCD = Central Clock Divider Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...
  • Page 153 Channel 2 - Data PCI Express Lane 2 PCI Express Lane 1 Channel 1 - Data Channel 0 -Data PCI Express Lane 0 CCD = Central Clock Divider November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...

  • Page 154: Channel Placement For Gen3 Using Both Cmu And Atx Plls

    The Gen3 simulation model supports serial only simulation. The Root Port BFM bypasses Phase 2 and Phase 3 Equalization. You must adjust your third-party Root Port BFM to terminate Equalization after Phase 0 and Phase 1 complete. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...
  • Page 155 Power down <n>. This signal requests the PHY to change its power state powerdown0[1:0] to the specified state (P0, P0s, P1, or P2). Transmit de-emphasis selection. The Arria V GZ Hard IP for PCI Express sets the value for this signal based on the indication received from the tx_deemph0 other end of the link during the Training Sequences (TS).
  • Page 156 5’b 01000: Config.Lanenumaccept ■ 5’b01001: Config.Lanenumwait ■ 5’b01010: Config.Complete ■ 5’b 01011: Config.Idle ■ 5’b01100: Recovery.Rcvlock ■ 5’b01101: Recovery.Rcvconfig ■ 5’b01110: Recovery.Idle ■ 5’b 01111: L0 ■ Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 157: Test Signals

    (2) These signals are for simulation only. For Quartus II software compilation, these pipe signals can be left floating. Test Signals The test_in and test_out buses provide run-time control and monitoring of the internal state of the Arria V GZ Hard IP for PCI Express. Table 6–33 describes the test signals.

  • Page 158: Making Pin Assignments

    I/O standards. 4. Select 1.5-V PCML I/O standard. The Arria V GZ Hard IP for PCI Express IP Core automatically assigns other required PMA analog settings, including 100 ohm internal termination. Arria V GZ Hard IP for PCI Express...

  • Page 159: Chapter 7. Register Descriptions

    Altera-Defined Vendor Specific Extended 0x200:0x240 Capability (VSEC) for details.) 0x300:0x318 Secondary PCI Express Extended Capability Structure (for Gen3 operation) 0x31C:7FC Reserved 0x800:0x834 Advanced error reporting (AER) (optional) 0x838:0x8FF Reserved November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...
  • Page 160 Vendor ID 0x004 Status Command 0x008 Class code Revision ID Primary Latency 0x00C BIST Header Type Cache Line Size Timer 0x010 BAR Registers 0x014 BAR Registers Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...
  • Page 161 Notes to Table 7–4: (1) Specifies the byte offset within Arria V GZ Hard IP for PCI Express IP core’s address space. (2) Refer to Table 7–39 on page 7–22 for a comprehensive list of correspondences between the Configuration Space registers and the PCI Express Base Specification 2.0.
  • Page 162 (1) Refer to Table 7–39 on page 7–22 for a comprehensive list of correspondences between the Configuration Space registers and the PCI Express Base Specification 2.0. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 163: Altera-Defined Vendor Specific Extended Capability (Vsec)

    Configuration via Protocol (CvP) programming and detailed internal error reporting. Table 7–9 the text in green links to the detailed register description. Table 7–9. Altera-Defined Vendor Specific Capability Structure (Part 1 of 2) Register Name Byte Offset 31:20 19:16 15:8...
  • Page 164 Bits Register Description Value Access Altera Marker. This read only register is an additional marker. If you use the standard Altera Programmer software to configure the device with CvP, this [31:0] A Device Value marker provides a value that the programming software reads to ensure that it is operating with the correct VSEC.
  • Page 165 Reserved. — — Reserved. — — Table 7–16 defines the fields of the CvP Mode Control register which provides global control of the CvP operation. November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...
  • Page 166 [7:4] Reserved. CVP_FULLCONFIG. Request that the FPGA control block reconfigure the entire FPGA including the Arria V GZ Hard IP for PCI Express, bring the PCIe link 1’b0 down. HIP_CLK_SEL. Selects between PMA and fabric clock when USER_MODE = 1 and PLD_CORE_READY = 1.
  • Page 167 CvP Programming Control register. This register is written by the programming software to control CvP programming. Refer to Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide more information about using CvP. Table 7–18. CvP Programming Control Register...
  • Page 168 When set, the retry buffer correctable ECC error status indicates an error. RW1CS When set, the RX buffer correctable ECC error status indicates an error. RW1CS Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 169: Pci Express Avalon-Mm Bridge Control Register Access Content

    Root Complex only, from Avalon-MM processors only, or from both types of processors. Because all accesses come across the interconnect fabric—requests from the Avalon-MM Arria V GZ Hard IP for PCI Express are routed through the interconnect fabric—hardware does not enforce restrictions to limit individual processor access to specific regions.

  • Page 170: Avalon-Mm To Pci Express Interrupt Registers

    Avalon-MM bridge logic and allow PCI Express interrupts to be asserted when enabled. Only Root Complexes should access these registers; however, hardware does not prevent other Avalon-MM masters from accessing them. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...
  • Page 171 Enables generation of PCI Express interrupts when a specified Avalon-MM interrupt signal is asserted. Your [15:0] AVL_IRQ[15:0] Qsys system may have as many as 16 individual input interrupt signals. November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...

  • Page 172: Pci Express Mailbox Registers

    Avalon-MM-to-PCI Express Mailbox 3 A2P_MAILBOX3 0x0910 Avalon-MM-to-PCI Express Mailbox 4 A2P_MAILBOX4 0x0914 Avalon-MM-to-PCI Express Mailbox 5 A2P_MAILBOX5 0x0918 Avalon-MM-to-PCI Express Mailbox 6 A2P_MAILBOX6 0x091C Avalon-MM-to-PCI Express Mailbox 7 A2P_MAILBOX7 Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 173: Avalon-Mm-To-Pci Express Address Translation Table

    Memory Space, 32-bit PCI Express address. 32-bit header is generated. Address bits 63:32 of the translation table entries are ignored. Memory space, 64-bit PCI Express address. 64-bit address header is generated. Reserved. Reserved. November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...

  • Page 174: Root Port Tlp Data Registers

    TLP Direct Channel RX_TX_Reg1 RP_TX_FIFO to Hard IP for PCIe Control Avalon-MM Register Master Access Slave RP_RXCPL_ REG0 CTRL RP_RXCPL_FIFO RP_RXCPL_ RP CPL RP_RXCPL_ CTRL STATUS Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 175: Programming Model For Avalon-Mm Root Port

    Aligning the payload data to the TLP address may result in the payload data being either aligned or unaligned to the qword. Figure 7–1 illustrates three dword TLPs with data that is aligned and unaligned to the qword. November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...
  • Page 176 64- and 128-bit interfaces. The Application Layer can only have one outstanding non-posted request at a time. The Application Layer must use tags 16–31 to identify non-posted requests. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 177: Sending A Write Tlp

    — — Set to 1’b1 when the Root Port has received a RW1C Completion TLP for an outstanding Non-Posted request RPRX_CPL_RECEIVED from the TLP Direct channel. November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...

  • Page 178: Pci Express To Avalon-Mm Interrupt Status And Enable Registers For Endpoints

    These registers must not be accessed by the PCI Express Avalon-MM bridge master ports; however, there is nothing in the hardware that prevents a PCI Express Avalon-MM bridge master port from accessing these registers. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 179: Avalon-Mm Mailbox Registers

    A processor local to the interconnect fabric typically requires write access to a set of Avalon-MM-to-PCI Express Mailbox registers and read-only access to a set of PCI Express-to-Avalon-MM Mailbox registers. Eight mailbox registers are available. November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...

  • Page 180: Correspondence Between Configuration Space Registers And The Pcie Specification

    0x000:0x03C PCI Header Type 0 Configuration Registers Type 0 Configuration Space Header 0x000:0x03C PCI Header Type 1 Configuration Registers Type 1 Configuration Space Header 0x040:0x04C Reserved Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...
  • Page 181 Reserved Capabilities PTR Type 0 Configuration Space Header 0x038 Reserved Type 0 Configuration Space Header 0x03C 0x00 0x00 Interrupt Pin Interrupt Line Type 0 Configuration Space Header November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...
  • Page 182 Advanced Error Reporting Enhanced Capability 0x800 PCI Express Enhanced Capability Header Header 0x804 Uncorrectable Error Status Register Uncorrectable Error Status Register 0x808 Uncorrectable Error Mask Register Uncorrectable Error Mask Register Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...
  • Page 183 Root Error Command Register 0x830 Root Error Status Root Error Status Register Error Source Identification Register Correctable 0x834 Error Source Identification Register Error Source ID Register November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...
  • Page 184 7–26 Chapter 7: Register Descriptions Correspondence between Configuration Space Registers and the PCIe Specification Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 185: Chapter 8. Reset And Clocks

    A second reset controller is implemented in hard logic. Software selects the appropriate reset controller depending on the configuration you specify. Both reset controllers reset the Arria V GZ V Hard IP for PCI Express IP Core and provide sample reset logic in the example design.
  • Page 186 8–2 Chapter 8: Reset and Clocks Reset Figure 8–1. Reset Controller in Arria V GZ Devices Example Design top.v Hard IP for PCI Express altpcie_dev_hip_ast_hwtcl.v altpcie_<dev>_hip_256_pipen1b.v npor Transceiver Hard Reset Logic/Soft Reset pin_perst Controller altpcie_rs_serdes.v refclk srst crst rx_freqlock tx_digitalrst...
  • Page 187 Figure 8–3 illustrates the RX transceiver reset sequence. Figure 8–3. RX Transceiver Reset Sequence rx_pll_locked rx_analogreset ltssmstate[4:0] txdetectrx_loopback pipe_phystatus pipe_rxstatus[2:0] rx_signaldetect rx_freqlocked rx_digitalreset November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...

  • Page 188: Clocks

    As a convenience, you may also use a 125 MHz input reference clock as input to the TX PLL. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation...

  • Page 189: Arria V Gz V Hard Ip For Pci Express Clock Domains

    Figure 8–5 illustrates the clock domains when using coreclkout_hip to drive the Application Layer and the pld_clk of the Arria V GZ V Hard IP for PCI Express IP Core. Figure 8–5. Clock Domains and Clock Generation for the Application Layer...
  • Page 190 Application Layer clock along with the pld_clk input to the Arria V GZ V Hard IP for PCI Express IP Core. The pld_clk can optionally be sourced by a different clock than coreclkout_hip. The pld_clk minimum frequency cannot be lower than the coreclkout_hip frequency.

  • Page 191: Additional Clocks

    (non 0 ppm), the PCS occasionally must insert SKP symbols, potentially causing the PCIe link to go to recovery. Arria V GZ PCIe Hard IP in Gen1 or Gen2 modes are not affected by this issue. Systems using the common reference clock (0 ppm) are not affected by this issue.
  • Page 192 8–8 Chapter 8: Reset and Clocks Clocks Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...
  • Page 193 9. Transaction Layer Protocol (TLP) Details November 2012 UG-01097-1.4 This chapter provides detailed information about the Arria V GZ Hard IP for PCI Express TLP handling. It includes the following sections: Supported Message Types ■ ■ Transaction Layer Routing Rules ■...

  • Page 194: Chapter 9. Transaction Layer Protocol (Tlp) Details

    Receive In Root Port mode, through software. Limit Vendor-defined Messages Transmit Transmit Vendor Defined Type 0 Receive Receive Transmit Transmit Vendor Defined Type 1 Receive Receive Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 195: Transaction Layer Routing Rules

    Layer logic processes the requests and generates the read completions, if needed. ■ In Endpoint mode, received Type 0 Configuration requests from the PCI Express upstream port route to the internal Configuration Space and the Arria V GZ Hard IP for PCI Express generates and transmits the completion. ■...

  • Page 196: Receive Buffer Reordering

    The rx_mask signal blocks non-posted request transactions made to the Application Layer interface so that only posted and completion transactions are presented to the Application Layer. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...
  • Page 197 MSI requests are conveyed in exactly the same manner as PCI Express memory write requests and are indistinguishable from them in terms of flow control, ordering, and data integrity. November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...
  • Page 198 9–6 Chapter 9: Transaction Layer Protocol (TLP) Details Receive Buffer Reordering Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 199: Chapter 10. Optional Features

    FPGA and initialize the PCI Express link. In prior devices, a single Program Object File (.pof) programmed the I/O ring and FPGA fabric before the PCIe link training and enumeration began. In Arria V GZ, the .pof file is divided into two parts: The I/O bitstream contains the data to program the I/O ring and the Hard IP for ■...

  • Page 200: Ecrc

    (1) The CvP mode is set in the Quartus II software. For more information, refer to “CvP Settings in Device and Pin Options” in the Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide. (2) The FPGA CvP and the PCIe application in a your design must use the same PCIe configuration settings.

  • Page 201: Ecrc On The Rx Path

    TD=0, without ECRC TD=0, without ECRC TD=1, without ECRC TD=0, without ECRC TD=0, without ECRC TD=1, with ECRC TD=1, without ECRC TD=1, with ECRC ECRC is generated November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...

  • Page 202: Lane Initialization And Reversal

    1, 2, 4, or 8 lanes. The Arria V GZ Hard IP for PCI Express supports lane reversal, which permits the logical reversal of lane numbers for the ×1, ×2, ×4, and ×8 configurations. Lane reversal allows more flexibility in board layout, reducing the number of signals that must cross over each other when routing the PCB.
  • Page 203 Figure 10–2. Using Lane Reversal to Solve PCB Routing Problems No Lane Reversal With Lane Reversal Results in PCB Routing Challenge Signals Route Easily Root Port Endpoint Root Port Endpoint no lane lane reversal reversal November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...
  • Page 204 10–6 Chapter 10: Optional Features Lane Initialization and Reversal Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 205: Interrupts For Endpoints Using The Avalon-St Application Interface

    Interrupts for Endpoints Using the Avalon-ST Application Interface The Arria V GZ Hard IP for PCI Express provides support for PCI Express legacy interrupts, MSI, and MSI-X interrupts when configured in Endpoint mode. The MSI, MSI-X, and legacy interrupts are mutually exclusive. After power up, the Hard IP block...
  • Page 206 Figure 11–2. Example Implementation of the MSI Handler Block app_int_sts Vector 0 app_int_en0 msi_enable & Master Enable app_msi_req0 app_int_sts0 app_msi_req app_msi_ack Arbitration Vector 1 app_int_en1 app_msi_req1 app_int_sts1 Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...
  • Page 207 Figure 11–4 illustrates the interactions among MSI interrupt signals for the Root Port Figure 11–3. The minimum latency possible between app_msi_req and app_msi_ack is one clock cycle. November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...

  • Page 208: Msi-X

    Legacy interrupts are signaled on the PCI Express link using message TLPs that are generated internally by the Arria V GZ Hard IP for PCI Express. The app_int_sts input port controls interrupt generation. When the input port asserts app_int_sts, it causes an Assert_INTA message TLP to be generated and sent upstream.

  • Page 209: Interrupts For Root Ports Using The Avalon-St Interface To The Application Layer

    Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer In Root Port mode, the Arria V GZ Hard IP for PCI Express receives interrupts through two different mechanisms: ■ MSI—Root Ports receive MSI interrupts through the Avalon-ST RX TLP of type MWr.
  • Page 210 (When signal falls DEASSERT_INTA Message Sent) A2P_MAILBOX_INT6 A2P_MB_IRQ6 A2P_MAILBOX_INT5 A2P_MB_IRQ5 A2P_MAILBOX_INT4 A2P_MB_IRQ4 A2P_MAILBOX_INT3 A2P_MB_IRQ3 A2P_MAILBOX_INT2 A2P_MB_IRQ2 A2P_MAILBOX_INT1 MSI Request A2P_MB_IRQ1 A2P_MAILBOX_INT0 A2P_MB_IRQ0 AV_IRQ_ASSERTED AVL_IRQ MSI Enable (Configuration Space Message Control Register[0]) Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 211: Enabling Msi Or Legacy Interrupts

    An MSI/MSI-X Avalon-MM Slave port to receive interrupt control and status from PCIe Root Port. ■ An MSI-X table to store the MSI-X table entries. The PCIe Root Port sets up this table. November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...
  • Page 212 MSI, MSI-X and INTx buses. 1. For more information about implementing MSI or MSI-X interrupts, refer to the PCI Local Bus Specification, Revision 2.3, MSI-X ECN. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 213: Chapter 12. Flow Control

    Flow Control: ■ Posted Headers ■ Posted Data Non-Posted Headers ■ ■ Non-Posted Data ■ Completion Headers ■ Completion Data November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...
  • Page 214 5. The value in the credit allocated register is used to create an FC Update DLLP. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 215: Throughput Of Non-Posted Reads

    (or at least offering enough non-posted header credits) to cover this delay. However, much of the delay encountered in this loop is well outside the Arria V GZ Hard IP for PCI Express and is very difficult to estimate. PCI Express switches can be inserted in this loop, which makes determining a bound on the delay more difficult.
  • Page 216 Application Layer and by the maximum read request size that can be issued. The number of header tag values that can be in use is also limited by the Arria V GZ Hard IP for PCI Express. You can specify 32 or 64 tags though configuration software to restrict the Application Layer to use only 32 tags.

  • Page 217: Chapter 13. Error Handling

    Each PCI Express compliant device must implement a basic level of error management and can optionally implement advanced error management. The Altera Arria V GZ Hard IP for PCI Express implements both basic and advanced error reporting. Given its position and role within the fabric, error handling for a Root Port is more complex than that of an Endpoint.

  • Page 218: Physical Layer Errors

    Data Link Layer protocol block in the Data Link Layer (AckNak_Seq_Num) does not correspond to (fatal) an unacknowledged TLP. (Refer to Figure 5–4 on page 5–8.) Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 219: Transaction Layer Errors

    A 64-bit memory transaction which the 32 MSBs of an address are ■ set to 0. A memory transaction that does not match a Windows address ■ November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...
  • Page 220 ■ the total length of the TLP. A TLP in which the combination of format and type is not specified by ■ the PCI Express specification. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 221: Error Reporting And Data Poisoning

    The poisoned bit is set on a received completion TLP. ■ Poisoned packets received by the Hard IP block are passed to the Application Layer. Poisoned transmit TLPs are similarly sent to the link. November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...

  • Page 222: Uncorrectable And Correctable Error Status Bits

    Header Log Overflow Status Corrected Internal Error Status Advisory Non-Fatal Error Status Replay Timer Timeout Status REPLAY_NUM Rollover Status Bad DLLP Status Bad TLP Status Receiver Error Status Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 223: Chapter 14. Sdc Timing Constraints

    Transceiver PHY Reset Controller IP Core ■ Example 14–1. SDC Timing Constraints Required for the Arria V GZ Hard IP for PCIe and Design Example # Constraints required for the Hard IP for PCI Express # derive_pll_clock is used to calculate all clock derived from PCIe refclk...

  • Page 224: Sdc Constraints For The Example Design

    The .sdc file also specifies some false timing paths for Transceiver Reconfiguration Controller and Transceiver PHY Reset Controller IP Cores. Be sure to include these constraints in your .sdc file. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 225: Chapter 15. Hard Ip Reconfiguration And Transceiver Reconfiguration

    15. Hard IP Reconfiguration and Transceiver Reconfiguration November 2012 UG-01097-1.4 This chapter describes features of the Arria V GZ Hard IP for PCI Express that you can use to reconfigure the core after power-up. It includes the following sections: Hard IP Reconfiguration Interface ■...
  • Page 226 DL_Active state of the Data Link Control and Management state machine. Upstream Port: For upstream ports and components that do not support this optional capability, this bit must be hardwired to 0. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...
  • Page 227 Correctable Error Mask 1.1 compliant cores, this bit should be set to 1. register Table 7–8 on page 7–5, 0x92 Slot Power Limit Scale. b’00 Slot Capability register November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...
  • Page 228 NFTS_SEPCLK. The number of fast training sequences b’10000000 for the separate clock. 0x95 — NFTS_COMCLK. The number of fast training sequences 15:8 b’10000000 for the common clock. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...
  • Page 229 Message Control register for MSI Interrupt pin. b’001 — Reserved. b’00 Table 7–4 on page 7–3, Function supports MSI-X. b’0 Message Control register for MSI November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...
  • Page 230 – 512 ns to less than 1 µs. b’101 – 1 µs to less than 2 µs. b’110 – 2 µs to 4 µs. b’111 – More than 4 µs. 15:3 Reserved. 0x0000 Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...
  • Page 231 BAR4[128]: I/O Space. b’0 BAR4[130:129]: Memory Space (see bit settings for b’0 BAR0). 0xA9 BAR4[131]: Prefetchable. b’0 BAR4[159:132]: Bar size mask. b’0 15:4 BAR4[143:132]. b’0 November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...
  • Page 232 1: 3.5 dB 0: -6 dB. This setting has no effect when operating at the 2.5GT/s rate. Transmit Margin. Directly drives the transceiver tx_pipemargin bits. 0xB1-FF Reserved. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 233: Transceiver Phy Ip Reconfiguration

    You can instantiate this component using the MegaWizard Plug-In Manager or Qsys. It is available for Arria V GZ devices and can be found in the Interfaces/Transceiver PHY category for the MegaWizard design flow. In Qsys, you can find the Transceiver Reconfiguration Controller in the Interface Protocols/Transceiver PHY category.
  • Page 234 Figure 15–3. Specifying the Number of Transceiver Interfaces The Transceiver Reconfiguration Controller includes an Optional interface grouping parameter. Arria V GZ devices include six channels in a transceiver bank. For a ×4 variant, no special interface grouping is required because all 4 lanes and the TX PLL fit in one bank.

  • Page 235: Learning More About Transceiver Phy Reconfiguration

    Application Note 645: Dynamic Reconfiguration of PMA Controls in Stratix V Devices. Although this application note describes dynamic reconfiguration for Stratix V devices, dynamic reconfiguration in Arria V GZ devices operates in the same manner. November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express...
  • Page 236 15–12 Chapter 15: Hard IP Reconfiguration and Transceiver Reconfiguration Transceiver PHY IP Reconfiguration Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...
  • Page 237 Endpoint model consists of an Endpoint variation combined with the chaining DMA application described above. The Altera testbench and Root Port or Endpoint BFM provide a simple method to do basic testing of the Application Layer logic that interfaces to the variation. However, the testbench and Root Port BFM are not intended to be a substitute for a full verification environment.
  • Page 238 Your Application Layer design may need to handle at least the following scenarios that are not possible to create with the Altera testbench and the Root Port BFM: It is unable to generate or receive Vendor Defined Messages. Some systems ■...

  • Page 239: Chapter 16. Testbench And Design Example Endpoint Testbench

    Port BFM. This is the module that you modify to vary the transactions sent to the example Endpoint design or your own design. For more information about this module, refer to “Root Port Design Example” on page 16–18. November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express...

  • Page 240: Root Port Testbench

    DMA read and write transactions. The write DMA module implements write operations from the Endpoint memory to the root complex (RC) memory. The read DMA implements read operations from the RC memory to the Endpoint memory. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation...
  • Page 241 BFM driver and the chaining DMA module The chaining DMA design example only supports dword-aligned accesses. The chaining DMA design example does not support ECRC forwarding for Arria V GZ. The BFM driver writes the descriptor tables into BFM shared memory, from which the chaining DMA design engine continuously collects the descriptor tables for DMA read, DMA write, or both.
  • Page 242 ■ The chaining DMA design example connects to the Avalon-ST interface of the Arria V GZ Hard IP for PCI Express. The connections consist of the following interfaces: The Avalon-ST RX receives TLP header and data information from the Hard IP ■...
  • Page 243 Chapter 16: Testbench and Design Example 16–7 Chaining DMA Design Examples ■ Shows you how to interface to the Arria V GZ Hard IP for PCI Express using the Avalon-ST protocol. Provides a chaining DMA channel that initiates memory read and write ■...
  • Page 244 32-bits wide. Control and status registers include the control registers in the altpcierd_dma_prg_reg module, status registers in the altpcierd_read_dma_requester and altpcierd_write_dma_requester modules, as well as other miscellaneous status registers. altpcierd_dma_dt—This module arbitrates PCI Express packets issued by the ■ Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation...

  • Page 245: Design Example Bar/Address Map

    Maps to 32 KByte target memory block. Use the rc_slave module to bypass the chaining DMA. 64-bit BAR1:0 32-bit BAR2 32-bit BAR3 Maps to DMA Read and DMA write control and status registers, a minimum of 256 bytes. 64-bit BAR3:2 November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express...

  • Page 246: Chaining Dma Control And Status Registers

    MSI signals app_msi_num [4:0]. If there is more than one MSI, the default mapping if all the MSIs are available, is: [24:20] MSI Number MSI 0 = Read ■ MSI 1 = Write ■ Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation...
  • Page 247 Indicates that there are no more descriptors pending in the write DMA. [15:0] Write DMA EPLAST Indicates the number of the last descriptor completed by the write DMA. November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express...

  • Page 248: Chaining Dma Descriptor Tables

    Each subsequent descriptor consists of a minimum of four dwords of data and corresponds to one DMA transfer. (A dword equals 32 bits.) Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation...
  • Page 249 RC Address Lower DWORD Table 16–9 shows the layout of the control fields of the chaining DMA descriptor. Table 16–9. Chaining DMA Descriptor Format Map (Control Fields) 2118 Reserved EPLAST_ENA November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express...

  • Page 250: Test Driver Module

    Either BARs 2 or 3 must be at least a 256-byte memory BAR to perform the DMA channel test. The find_mem_bar procedure in the altpcietb_bfm_driver_chaining does this. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation...

  • Page 251: Dma Write Cycles

    BFM shared memory data buffer 1 lower address value Data Increment by 1 from Data content in the BFM shared memory from address: 0x1800 Buffer 0 0x1515_0001 0x01800–0x1840 November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express...
  • Page 252 0x80c, where the DMA write engine is updating the value of the number of completed descriptor. Calls the procedures rcmem_poll and msi_poll to determine when the DMA write transfers have completed. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation...

  • Page 253: Dma Read Cycles

    BFM shared memory upper address value 0x93c 0x20EF0 BFM shared memory lower address value Data Increment by 1 from Data content in the BFM shared memory from address: 0x20EF0 Buffer 2 0xCCCC_0001 0x20EF0 November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express...

  • Page 254: Root Port Design Example

    Root Port variation (<qsys_systemname>. ■ Avalon-ST Interfaces (altpcietb_bfm_vc_intf_ast)—handles the transfer of TLP requests and completions to and from the Arria V GZ Hard IP for PCI Express variation using the Avalon-ST interface. ■ Root Port BFM tasks—contains the high-level tasks called by the test driver,...
  • Page 255 (which is the test_out signal from the Hard IP) and test_in which allows you to monitor and control internal states of the Hard IP variation. (Refer to “Test Signals” on page 6–63.) November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express...

  • Page 256: Root Port Bfm

    BFM Configuration Procedures BFM Request Interface BFM Log Interface (altpcietb_bfm_req_intf_common) (altpcietb_bfm_log _common) Root Port RTL Model (altpcietb_bfm_rp_top_x8_pipen1b) IP Functional Simulation Avalon-ST Interface Model of the Root (altpcietb_bfm_vc_intf) Port Interface (altpcietb_bfm_driver_rp) Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation...
  • Page 257 Additionally, they handle any requests received from the PCI Express link, and store or fetch data from the shared memory before generating the required completions. November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express...

  • Page 258: Bfm Memory Map

    Sets the Endpoint Max Read Request Size equal to the Max Payload Size because the Root Port does not support breaking the read request into multiple completions. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation...
  • Page 259 This data structure is then used by subsequent BFM procedure calls to generate the full PCI Express addresses for read and write November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express...
  • Page 260 Expansion ROM BAR read back value after being written with all 1’s Reserved The configuration routine does not configure any advanced PCI Express capabilities such as the AER capability. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation...
  • Page 261 0x0020 0000 Endpoint Non Prefetchable Memory Space BARs Assigned Smallest to Largest Unused Endpoint Memory Space BARs (Prefetchable 32 -bit and bit) Assigned Smallest to Largest 0xFFFF FFFF November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express...
  • Page 262 Assigned Smallest to Largest 0x0000 0001 0000 0000 Endpoint Memory Space BARs (Prefetchable 64 bit) Assigned Smallest to Largest BAR size dependent Unused 0xFFFF FFFF FFFF FFFF Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation...

  • Page 263: Issuing Read And Write Transactions To The Application Layer

    Endpoint BAR and stores it in BFM shared memory. This procedure blocks waiting for the completion data to be returned before returning control to the caller. November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express...

  • Page 264: Bfm Procedures And Functions

    Number of the BAR used with pcie_offset to determine PCI Express address. bar_num Address offset from the BAR base. pcie_offset BFM shared memory address of the data to be written. lcladdr Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation...

  • Page 265: Ebfm_Barwr_Imm Procedure

    7 downto 0 Length of the data to be written in bytes. Maximum length is 4 bytes. byte_len Traffic class to be used for the PCI Express transaction. tclass November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express...

  • Page 266: Ebfm_Barrd_Wait Procedure

    Length, in bytes, of the data to be read. Can be 1 to the minimum of the bytes byte_len remaining in the BAR space or BFM shared memory. Traffic Class to be used for the PCI Express transaction. tclass Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation...

  • Page 267: Ebfm_Cfgwr_Imm_Wait Procedure

    This argument is the completion status as specified in the PCI Express specification: Compl_Status Definition SC— Successful completion compl_status UR— Unsupported Request CRS — Configuration Request Retry Status CA — Completer Abort November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express...

  • Page 268: Ebfm_Cfgwr_Imm_Nowt Procedure

    Data to be written Arguments This argument is reg [31:0]. In both languages, the bits written depend on the length: Length Bits Written imm_data [31:0] [23:0] [15:0] [7:0] Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation...

  • Page 269: Ebfm_Cfgrd_Wait Procedure

    Length, in bytes, of the data written. Maximum length is four bytes. The regb_ln and regb_ln regb_ad arguments cannot cross a DWORD boundary. BFM shared memory address where the read data should be placed. lcladdr November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express...

  • Page 270: Bfm Configuration Procedures

    When set to 1 the address map of the simulation system will be limited to 4 addr_map_4GB_limit GBytes. Any 64-bit BARs will be assigned below the 4 GByte limit. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation...

  • Page 271: Ebfm_Cfg_Decode_Bar Procedure

    Specifies a data pattern of incrementing 32-bit dwords (0x00000000, 0x00000001, SHMEM_FILL_DWORD_INC 0x00000002, etc.) Specifies a data pattern of incrementing 64-bit qwords (0x0000000000000000, SHMEM_FILL_QWORD_INC 0x0000000000000001, 0x0000000000000002, etc.) Specifies a data pattern of all ones SHMEM_FILL_ONE November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express...

  • Page 272: Shmem_Write

    “BFM Log and Message Procedures” on page 16–37 for more information about message types. Set to one msg_type of the constants defined in Table 16–36 on page 16–38. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation...

  • Page 273: Shmem_Fill Procedure

    Each displayed message has a specific prefix, based on the message type in Table 16–36. November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express...
  • Page 274 BFM test driver module or the Root Port BFM, that are not caused by the Endpoint Application Layer being tested. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation...

  • Page 275: Ebfm_Display Verilog Hdl Function

    This argument is reg [EBFM_MSG_ERROR_CONTINUE: EBFM_MSG_DEBUG]. Argument msg_mask A 1 in a specific bit position of the msg_mask causes messages of the type corresponding to the bit position to be suppressed. November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express...

  • Page 276: Ebfm_Log_Set_Stop_On_Msg_Mask Verilog Hdl Function

    This section outlines formatting functions that are only used by Verilog HDL. All these functions take one argument of a specified length and return a vector of a specified length. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation...

  • Page 277: Himage1

    This function creates an 8-digit hexadecimal string representation of the input argument that can be concatenated into a larger message string and passed to ebfm_display. Table 16–46. himage8 Location altpcietb_bfm_driver_rp.v syntax string:= himage(vec) November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express...

  • Page 278: Himage16

    Returns a 2-digit decimal representation of the input argument that is padded with leading 0s if necessary. Return data is type reg with a range of 16:1. Return range string Returns the letter U if the value cannot be represented. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation...

  • Page 279: Dimage3

    This function creates a six-digit decimal string representation of the input argument that can be concatenated into a larger message string and passed to ebfm_display. Table 16–53. dimage6 Location altpcietb_bfm_log.v syntax string:= dimage(vec) November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express...

  • Page 280: Dimage7

    When set, the Root Port uses native PCI Express MSI to detect the DMA completion. Use_msi When set, the Root Port uses BFM shared memory polling to detect the DMA completion. Use_eplast Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation...

  • Page 281: Dma_Rd_Test Procedure

    BAR number to analyze. bar_num dma_set_wr_desc_data Procedure Use the dma_set_wr_desc_data procedure to configure the BFM shared memory for the DMA write. Table 16–59. dma_set_wr_desc_data_header Procedure Location altpcietb_bfm_driver_rp.v Syntax dma_set_wr_desc_data_header (bar_table, bar_num) November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express...

  • Page 282: Dma_Set_Header Procedure

    Expected data value of the that is being polled. rc_data Arguments Mask that is logically ANDed with the shared memory data before it is rc_mask compared with rc_data. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation...

  • Page 283: Msi_Poll Procedure

    Returns the MSI traffic class value. Msi_traffic_class Returns the MSI multi message enable status. Multi_message_enable Returns the expected MSI data value, which is msi_data modified by the msi_expected msi_number chosen. November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express...

  • Page 284: Find_Mem_Bar Procedure

    The message string is limited to a maximum of 100 characters. Also, because Verilog HDL does not allow variable length strings, this routine strips off leading message characters of 8'h00 before displaying the message. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation...

  • Page 285: Chapter 17. Debugging

    Typically, PCI Express hardware bring-up involves the following steps: 1. System reset 2. Link training 3. BIOS enumeration The following sections, describe how to debug the hardware bring-up flow. Altera recommends a systematic approach to diagnosing bring-up issues as illustrated in Figure 17–1.
  • Page 286 RxElecIdle (rxelecidle)signal when TxDetectRx=0 (txdetectrx0) at PIPE Link fails with LTSSM stuck For Arria V GZ devices, a workaround is interface. Check if OCT is turned off by in Detect.Active state (1) implemented in the reset sequence.
  • Page 287 RX side of the receiver and the actual voltage supplied to the Confirm that rx_signaldetect bus of FPGA from your boards. Arria V GZ devices the active lanes is all 1’s. If all active require VCCR/VCCT to be 1.0 V. You must apply lanes are driving all 1’s, the LTSSM...
  • Page 288 TXFIFO is full. creating a situation where the Arria V GZ Hard IP for PCI Express IP Core credit calculation is out-of-sink with its link partner. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 289: Link Hangs In L0 Due To Deassertion Of Tx_St_Ready

    For more information about SignalTap, refer to the Design Debugging Using the SignalTap II Embedded Logic Analyzer chapter in volume 3 of the Quartus II Handbook. November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...

  • Page 290: Recommended Reset Sequence To Avoid Link Training Issues

    1. Change to your simulation directory, <work_dir>/<variant>/testbench/<variant>_tb/simulation 2. Open <variant>_tb.v. 3. Search for the string, serial_sim_hwtcl. Set the value of this parameter to 0 if it is 4. Save <variant>_tb.v. Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 291: Reduce Counter Values For Serial Simulations

    2. Search for the string, hip_hard_reset_hwtcl. 3. If hip_hard_reset_hwtcl = 1, the hard reset controller is active. Set hip_hard_reset_hwtcl = 0 to change to the soft reset controller. 4. Save variant.v. November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...

  • Page 292: Using The Pipe Interface

    Gen1 and 16000 UI interval for Gen2 3'b111: Absence of Electrical idle exit in 128 us ■ window for Gen1 Transmit de-emphasis selection. The Arria V GZ Hard IP txdeemph for PCI Express sets the value for this signal based on the [97]...
  • Page 293 2’b01: PHY is in electrical idle. ■ 2’b10: PHY is in loopback mode. ■ 2’b11: Illegal. Not defined. ■ When asserted, the PHY must invert the received data. rxpolarity0 [43] [203] November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...

  • Page 294: Use Third-Party Pcie Analyzer

    Both FPGA programming (configuration) and the initialization of a PCIe link require time. There is some possibility that Altera FPGA including a Hard IP block for PCI Express may not be ready when the OS/BIOS begins enumeration of the device tree.

  • Page 295: Tlp Packet Format Without Data Payload

    (AT) bits in byte 2 of the header and flag the received TLP as malformed if AT is not equal to is 2b’00. The Arria V GZ Hard IP for PCI Express IP core does not perform this optional check.
  • Page 296 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation...

  • Page 297: Tlp Packet Format With Data Payload

    0 0 0 0 0 0 0 0 0 1 Byte 4 0 0 0 0 First BE Requester ID Byte 8 Address[31:2] Byte 12 Reserved November 2012 Altera Corporation Arria V GZ Hard IP for PCI Express User Guide...
  • Page 298 Requester ID Message Code Byte 8 Vendor defined or all zeros for Slot Power Limit Byte 12 Vendor defined or all zeros for Slots Power Limit Arria V GZ Hard IP for PCI Express November 2012 Altera Corporation User Guide...

  • Page 299: Additional Information

    (software licensing) Email authorization@altera.com Note to Table: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions this document uses. Visual Cue Meaning Indicate command names, dialog box titles, dialog box options, and other GUI Bold Type with Initial Capital labels.
  • Page 300 Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents. The feedback icon allows you to submit feedback to Altera about the document. Methods for collecting feedback vary as appropriate for each document.

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