abov MC95FG308U Manuals

Manuals and User Guides for abov MC95FG308U. We have 1 abov MC95FG308U manual available for free PDF download: User Manual

abov MC95FG308U User Manual

abov MC95FG308U User Manual (215 pages)

CMOS single-chip 8-bit MCU with EEPROM and 12-bit A/D converter

Brand: abov | Category: Microcontrollers | Size: 4 MB

Table of Contents

Revision History

2
1 Overview

3
- Description
  3
- Features
  4
- Development Tools
  5
2 Block Diagram

8
3 Pin Assignment

9
4 Package Diagram

14
5 Pin Description

25
6 Port Structures

26
- General Purpose I/O Port
  26
- External Interrupt I/O Port
  27
7 Electrical Characteristics

28
8 Memory

37
- Program Memory
  37
- Data Memory
  39
- EEPROM Data Memory and XSRAM
  41
- SFR Map
  42
  - SFR Map Summary
    42
  - 8051 Compiler Compatible SFR
    43
9 O Ports

45
- I/O Ports
  45
- Port Register
  45
- Px Port
  47
  - Px Port Description
    47
  - Register Description for Px
    47
- Port RESET Noise Canceller
  49
10 Interrupt Controller

50
11 Peripheral Hardware

66
- Clock Generator
  66
  - Overview
    66
  - Block Diagram
    66
  - Register Map
    67
  - Clock Generator Register Description
    67
  - Register Description for Clock Generator
    67
- Basic Interval Timer
  69
  - Overview
    69
  - Block Diagram
    69
  - Register Map
    69
  - Basic Interval Timer Register Description
    70
  - Register Description for Basic Interval Timer
    70
- Watch Dog Timer
  71
  - Overview
    71
  - Block Diagram
    71
  - Register Map
    71
  - Watch Dog Timer Register Description
    72
  - Register Description for Watch Dog Timer
    72
  - WDT Interrupt Timing Waveform
    73
- Watch Timer
  74
  - Overview
    74
  - Block Diagram
    74
  - Register Map
    74
  - Watch Timer Register Description
    75
  - Register Description for Watch Timer
    75
- Timer/Pwm
  77
  - 8-Bit Timer/Event Counter 0, 1
    77
    
    Overview
    77
    
    8-Bit Timer/Counter Mode
    78
    
    16-Bit Timer/Counter Mode
    80
    
    8-Bit Capture Mode
    80
    
    16-Bit Capture Mode
    83
    
    PWM Mode
    84
    
    8-Bit (16-Bit) Compare Output Mode
    94
    
    Register Map
    94
    
    Timer/Counter 0 Register Description
    95
    
    Register Description for Timer/Counter 0, 1
    95
  - 8-Bit Timer/Event Counter 2, 3
    105
    
    Overview
    105
    
    8-Bit Timer/Counter Mode
    106
    
    16-Bit Timer/Counter Mode
    108
    
    8-Bit Capture Mode
    108
    
    16-Bit Capture Mode
    111
    
    PWM Mode
    111
    
    8-Bit (16-Bit) Compare Output Mode
    113
    
    Register Map
    114
    
    Timer/Counter 2, 3 Register Description
    114
    
    Register Description for Timer/Counter 2, 3
    115
  - 16-Bit Timer 4
    118
    
    Overview
    118
    
    16-Bit Timer/Counter Mode
    118
    
    Register Map
    118
    
    Timer 4 Register Description
    119
    
    Register Description for Timer 4
    119
  - Timer Interrupt Status Register (TMISR)
    121
    
    Register Description for TMISR
    121
- Buzzer Driver
  122
  - Overview
    122
  - Block Diagram
    122
  - Register Map
    123
  - Buzzer Driver Register Description
    123
  - Register Description for Buzzer Driver
    123
- Usart
  124
  - Overview
    124
  - Block Diagram
    125
  - Clock Generation
    126
  - External Clock (XCK)
    127
  - Synchronous Mode Operation
    127
  - Data Format
    128
  - Parity Bit
    128
  - USART Transmitter
    129
    
    Sending Tx Data
    129
    
    Transmitter Flag and Interrupt
    129
    
    Parity Generator
    129
    
    Disabling Transmitter
    130
  - USART Receiver
    130
    
    Receiving Rx Data
    130
    
    Receiver Flag and Interrupt
    130
    
    Parity Checker
    131
    
    Disabling Receiver
    131
    
    Asynchronous Data Reception
    131
  - SPI Mode
    133
    
    SPI Clock Formats and Timing
    133
  - Register Map
    135
  - USART Register Description
    135
  - Register Description for USART
    136
  - Baud Rate Setting (Example)
    141
- Spi
  142
  - Overview
    142
  - Block Diagram
    142
  - Data Transmit / Receive Operation
    143
  - SS Pin Function
    143
  - Timing Waveform
    144
  - Register Map
    144
  - SPI Register Description
    144
  - Register Description for SPI
    145
  - Overview
    147
  - Block Diagram
    147
  - I2C Bit Transfer
    148
  - Start / Repeated Start / Stop
    148
  - Data Transfer
    149
  - Acknowledge
    149
  - Synchronization / Arbitration
    150
  - Operation
    151
    
    Master Transmitter
    151
    
    Master Receiver
    152
    
    Slave Transmitter
    153
    
    Slave Receiver
    154
  - Register Map
    155
  - I2C Register Description
    155
  - Register Description for I2C
    156
- 12-Bit A/D Converter
  160
  - Overview
    160
  - Block Diagram
    160
  - ADC Operation
    161
  - Register Map
    162
  - ADC Register Description
    162
  - Register Description for ADC
    163
- Analog Comparator
  165
  - Overview
    165
  - Block Diagram
    165
  - IN/OUT Signal Description
    165
  - Register Map
    166
  - Analog Comparator Register Description
    166
  - Register Description for USI0
    166
12 Power down Operation

167
- Overview
  167
- Peripheral Operation in IDLE/STOP Mode
  167
- IDLE Mode
  168
- STOP Mode
  169
- Release Operation of STOP1, 2 Mode
  170
13 Reset

172
- Overview
  172
- Reset Source
  172
- RESET Block Diagram
  172
- RESET Noise Canceller
  173
- Power on RESET
  173
- External RESETB Input
  176
- Brown out Detector Processor
  177
  - Register Map
    178
  - Reset Operation Register Description
    178
  - Register Description for Reset Operation
    179
14 On-Chip Debug System

180
- Overview
  180
  - Description
    180
  - Feature
    180
- Two-Pin External Interface
  181
  - Basic Transmission Packet
    181
  - Packet Transmission Timing
    182
    
    Data Transfer
    182
    
    Bit Transfer
    183
    
    Start and Stop Condition
    183
    
    Acknowledge Bit
    183
  - Connection of Transmission
    184
15 Memory Programming

185
- Overview
  185
  - Description
    185
  - Features
    185
- Flash and EEPROM Control and Status Register
  185
  - Register Map
    185
  - Register Description for Flash and EEPROM
    186
- Memory Map
  190
  - Flash Memory Map
    190
  - Data EEPROM Memory Map
    191
- Serial In-System Program Mode
  192
  - Flash Operation
    192
    
    Flash Read
    193
    
    Enable Program Mode
    193
    
    Flash Write Mode
    194
    
    Flash Page Erase Mode
    194
    
    Flash Bulk Erase Mode
    194
    
    Flash OTP Area Read Mode
    195
    
    Flash OTP Area Write Mode
    195
    
    Flash OTP Area Erase Mode
    195
    
    Flash Program Verify Mode
    195
    
    OTP Program Verify Mode
    196
    
    Flash Erase Verify Mode
    196
    
    Flash Page Buffer Read
    196
  - Data EEPROM Operation
    196
    
    Data EEPROM Read
    196
    
    Enable Program Mode
    196
    
    EEPROM Write Mode
    197
    
    EEPROM Page Erase Mode
    197
    
    EEPROM Bulk Erase Mode
    197
    
    Data EEPROM Program Verify Mode
    197
    
    Data EEPROM Erase Verify Mode
    198
    
    Data EEPROM Page Buffer Read
    198
  - Summary of Flash and Data EEPROM Program/Erase Mode
    198
- Parallel Mode
  199
  - Overview
    199
  - Parallel Mode Instruction Format
    200
  - Parallel Mode Timing Diagram
    201
- Mode Entrance Method of ISP and Byte-Parallel Mode
  202
  - Mode Entrance Method for ISP
    202
  - Mode Entrance of Byte-Parallel
    202
- Security
  203
16 Configure Option

204
- Configure Option Control Register
  204
17 Appendix

205

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