Table of Contents
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Code
3Dh
42h
45h
46h
2-1-2-3
48h
49h
4Ah
4Bh
4Ch
Code
4Eh
50h
51h
52h
54h
58h
2-2-3-1
59h
5Ah
5Bh
5Ch
60h
62h
64h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Eh
70h
72h
76h
7Ch
7Eh
80h
81h
82h
83h
84h
85h
122
Beeps
Load alternate registers with CMOS values
Initialize interrupt vectors
POST device initialization
Check ROM copyright notice
Check video configuration against CMOS
Initialize PCI bus and devices
Initialize all video adapters in system
QuietBoot start (optional)
Shadow video BIOS ROM
Beeps
Display BIOS copyright notice
Display CPU type and speed
Initialize EISA board
Test keyboard
Set key click if enabled
Test for unexpected interrupts
Initialize POST display service
Display prompt "Press F2 to enter SETUP"
Disable CPU cache
Test RAM between 512 and 640 KB
Test extended memory
Test extended memory address lines
Jump to UserPatch1
Configure advanced cache registers
Initialize Multi Processor APIC
Enable external and CPU caches
Setup System Management Mode (SMM) area
Display external L2 cache size
Load custom defaults (optional)
Display shadow-area message
Display possible high address for UMB recovery
Display error messages
Check for configuration errors
Check for keyboard errors
Set up hardware interrupt vectors
Initialize coprocessor if present
Disable onboard Super I/O ports and IRQs
Late POST device initialization
Detect and install external RS232 ports
Configure non-MCD IDE controllers
Detect and install external parallel ports
Initialize PC-compatible PnP ISA devices
POST Routine Description
POST Routine Description
Chapter 4
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