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Post Codes
These tables describe the POST codes and descriptions during the POST.
Code
02h
Verify Real Mode
03h
Disable Non-Maskable Interrupt (NMI)
04h
Get CPU type
06h
Initialize system hardware
08h
Initialize chipset with initial POST values
09h
Set IN POST flag
0Ah
Initialize CPU registers
0Bh
Enable CPU cache
0Ch
Initialize caches to initial POST values
0Eh
Initialize I/O component
Code
0Fh
10h
11h
12h
13h
14h
16h
1-2-2-3
17h
18h
1Ah
1Ch
20h
1-3-1-1
22h
1-3-1-3
24h
26h
28h
29h
2Ah
2Ch
1-3-4-1
2Eh
1-3-4-3
2Fh
30h
1-4-1-1
32h
33h
36h
38h
3Ah
3Ch
Chapter 4
POST Routine Description
Beeps
Initialize the local bus IDE
Initialize Power Management
Load alternate registers with initial POST values
Restore CPU control word during warm boot
Initialize PCI Bus Mastering devices
Initialize keyboard controller
BIOS ROM checksum
Initialize cache before memory autosize
8254 timer initialization
8237 DMA controller initialization
Reset Programmable Interrupt Controller
Test DRAM refresh
Test 8742 Keyboard Controller
Set ES segment register to 4 GB
Enable A20 line
Autosize DRAM
Initialize POST Memory Manager
Clear 512 KB base RAM
RAM failure on address line xxxx*
RAM failure on data bits xxxx* of low byte of memory bus
Enable cache before system BIOS shadow
RAM failure on data bits xxxx* of high byte of memory bus
Test CPU bus-clock frequency
Initialize Phoenix Dispatch Manager
Warm start shut down
Shadow system BIOS ROM
Autosize cache
Advanced configuration of chipset registers
POST Routine Description
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