1. Manuals
  2. Brands
  3. Maxim Manuals
  4. Extender
  5. DS33R11
  6. User manual

Maxim DS33R11 User Manual

Ethernet mapper with integrated t1/e1/j1 transceiver
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
www.maxim-ic.com

GENERAL DESCRIPTION

The DS33R11 extends a 10/100 Ethernet LAN
segment by encapsulating MAC frames in HDLC or
X.86 (LAPS) for transmission over a T1/E1/J1 data
stream.
The device performs store-and-forward of packets
with full wire-speed transport capability. The built-in
Committed
Information
provides fractional bandwidth allocation up to the line
rate in increments of 512kbps. The DS33R11 can
operate with an inexpensive external processor.
APPLICATIONS
Transparent LAN Service
LAN Extension
Ethernet Delivery Over T1/E1/J1

FUNCTIONAL DIAGRAM

SERIAL STREAM
BERT
HDLC/X.86
MAPPER
10/100
MAC
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
Rate
(CIR)
Controller
T1/E1
T1/E1/J1
TRANSCEIVER
LINE
μC
SDRAM
MII/RMII
10/100
ETHERNET
PHY
DS33R11
Ethernet Mapper with Integrated
T1/E1/J1 Transceiver
FEATURES
10/100 IEEE 802.3 Ethernet MAC (MII and
RMII) Half/Full Duplex with Automatic Flow
Control
Integrated T1/E1/J1 Framer and LIU
HDLC/LAPS Encapsulation with
Programmable FCS and Interframe Fill
Committed Information Rate Controller
Provides Fractional Allocations in 512kbps
Increments
Programmable BERT for Serial (TDM)
Interface
External 16MB, 100MHz SDRAM Buffering
Parallel Microprocessor Interface
1.8V, 3.3V Supplies
Reference Design Routes on Two Signal
Layers
IEEE 1149.1 JTAG Support
Features continued on page 11.

ORDERING INFORMATION

PART
DS33R11
1 of 344
DS33R11
TEMP RANGE
PIN-PACKAGE
-40°C to +85°C
256 BGA
REV: 030807

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the DS33R11 and is the answer not in the manual?

Questions and answers

Related Manuals for Maxim DS33R11

Summary of Contents for Maxim DS33R11

  • Page 1: Ordering Information

    Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. Ethernet Mapper with Integrated FEATURES 10/100 IEEE 802.3 Ethernet MAC (MII and...

  • Page 2: Table Of Contents

    DESCRIPTION ... 9 FEATURE HIGHLIGHTS... 11 ... 11 ENERAL ICROPROCESSOR NTERFACE HDLC E THERNET APPING X.86 (L CCESS HDLC C DDITIONAL ONTROLLERS IN THE OMMITTED NFORMATION SDRAM I ... 12 NTERFACE MAC I ... 12 NTERFACE T1/E1/J1 L NTERFACE 2.10 C ...
  • Page 3 9.14.1 DTE and DCE Mode ...58 9.15 E MAC ... 59 THERNET 9.15.1 MII Mode Options...61 9.15.2 RMII Mode...61 9.15.3 PHY MII Management Block and MDIO Interface ...62 9.16 BERT IN THE THERNET 9.16.1 Receive Data Interface ...63 9.16.2 Repetitive Pattern Synchronization...64 9.16.3 Pattern Monitoring...64 9.16.4 Pattern Generation...64 9.17 T...
  • Page 4 10.17.4 FIFO Information ...96 10.17.5 Receive Packet-Bytes Available ...96 10.18 L FDL S EGACY UPPORT 10.18.1 Overview ...97 10.18.2 Receive Section ...97 10.18.3 Transmit Section ...98 10.19 D4/SLC-96 O PERATION 10.20 P ROGRAMMABLE 10.21 L NTERFACE 10.21.1 LIU Operation...100 10.21.2 Receiver ...100 10.21.3 Transmitter ...102 10.22 MCLK P ...
  • Page 5 12.4 E1 M ... 308 OPERATING PARAMETERS ... 313 13.1 T HERMAL HARACTERISTICS 13.2 MII I ... 315 NTERFACE 13.3 RMII I ... 317 NTERFACE 13.4 MDIO I ... 319 NTERFACE 13.5 T WAN I RANSMIT NTERFACE 13.6 R WAN I ECEIVE NTERFACE 13.7 SDRAM T...
  • Page 6 Figure 9-4. IEEE 802.3 Ethernet Frame ... 56 Figure 9-5. Configured as DTE Connected to an Ethernet PHY in MII Mode ... 58 Figure 9-6. DS33R11 Configured as a DCE in MII Mode... 59 Figure 9-7. RMII Interface... 61 Figure 9-8. MII Management Frame... 62 Figure 9-9.
  • Page 7 DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 12-19. Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)... 307 Figure 12-20. Receive-Side Timing ... 308 Figure 12-21. Receive-Side Boundary Timing (with Elastic Store Disabled) ... 308 Figure 12-22. Receive-Side Boundary Timing, RSYSCLK = 1.544MHz (E-Store Enabled)... 309 Figure 12-23.
  • Page 8 DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver LIST OF TABLES Table 2-1. T1-Related Telecommunications Specifications ... 16 Table 7-1. Detailed Pin Descriptions ... 25 Table 9-1. Clocking Options for the Ethernet Interface ... 43 Table 9-2. Reset Functions... 46 Table 9-3. Registers Related to Connections and Queues ... 52 Table 9-4.

  • Page 9: C Onnections And

    Bit Error Rate Tester (BERT), and integrated T1/E1/J1 Transceiver. The packet interface consists of a MII/RMII Ethernet PHY interface. The Ethernet interface can be configured for 10Mbit/s or 100Mbit/s service. The DS33R11 encapsulates Ethernet traffic with HDLC or X.86 (LAPS) encoding to be transmitted over a T1, E1, or J1 line. The T1/E1/J1 interface also receives encapsulated Ethernet packets and transmits the extracted packets over the Ethernet ports.
  • Page 10 RLCLK pins are not available on the DS33R11. • Multiplexed Microprocessor Bus mode is not supported on the DS33R11. • The Extended System Information Bus (ESIB) is not supported on the DS33R11. • The MODEC pins serve the function of the DS2155’s BTS pin. •...

  • Page 11: I Nterrupt

    FEATURE HIGHLIGHTS 2.1 General • 256-pin, 27mm BGA package • 1.8V and 3.3V supplies • IEEE 1149.1 JTAG boundary scan • Software access to device ID and silicon revision • Development support includes evaluation kit, driver source code, and reference designs •...

  • Page 12: Additional Hdlc Controllers In The Integrated T1/E1/J1 Transceiver

    2.5 Additional HDLC Controllers in the Integrated T1/E1/J1 Transceiver • Two additional independent HDLC controllers • Fast load and unload features for FIFOs • SS7 support for FISU transmit and receive • Independent 128-byte Rx and Tx buffers with interrupt support •...

  • Page 13: T1/E1/J1 Line Interface

    2.9 T1/E1/J1 Line Interface • Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use 1.544MHz for T1 operation • Fully software configurable • Short-haul and long-haul applications • Automatic receive sensitivity adjustments •...

  • Page 14: T1/E1/J1 Framer

    2.12 T1/E1/J1 Framer • Fully independent transmit and receive functionality • Full receive and transmit path transparency • T1 framing formats include D4 (SLC-96) and ESF • Detailed alarm and status reporting with optional interrupt support • Large path and line error counters for: T1: BPV, CV, CRC6, and framing bit errors E1: BPV, CV, CRC4, E-bit, and frame alignment errors •...

  • Page 15: Test And Diagnostics

    2.14 Test and Diagnostics • IEEE 1149.1 support • Programmable on-chip bit error-rate tester (BERT) • Pseudorandom patterns including QRSS • User-defined repetitive patterns • Daly pattern • Error insertion single and continuous • Total bit and errored bit counts •...

  • Page 16: Specifications Compliance

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 2.15 Specifications Compliance The DS33R11 meets relevant telecommunications specifications. The following table provides the specifications and relevant sections that are applicable to the DS33R11. Table 2-1. T1-Related Telecommunications Specifications IEEE 802.3-2002—CSMA/CD access method and physical layer specifications.

  • Page 17: Applications

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 3 APPLICATIONS The DS33R11 is ideal for application areas such as transparent LAN service, LAN extension, and Ethernet delivery over T1/E1/J1, T3/E3, OC-1/EC-1, G.SHDSL, or HDSL2/4. For an example of a complete LAN-to-WAN design, refer to Application Note 3411: DS33Z11—Ethernet LAN to Unframed T1/E1 WAN Bridge, available on our website at www.maxim-ic.com/telecom.

  • Page 18: Acronyms And Glossary

    4 ACRONYMS AND GLOSSARY • BERT: Bit Error-Rate Tester • DCE: Data Communication Interface • DTE: Data Terminating Interface • FCS: Frame Check Sequence • HDLC: High-Level Data Link Control • MAC: Media Access Control • MII: Media Independent Interface •...

  • Page 19: Major Operating Modes

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 5 MAJOR OPERATING MODES Microprocessor control is possible through the 8-bit parallel control port and provides configuration for all the features of the device. The Ethernet Link Transport Engine in the device can be configured for HDLC or X.86 encapsulation.

  • Page 20: Block Diagrams

    6 BLOCK DIAGRAMS Figure 6-1. Main Block Diagram CLAD TTIP TRING BERT RTIP RRING JTAG2 NOTE: SOME PINS NOT SHOWN. THE BLOCK IN THE DIAGRAM LABELED “T1/E1/J1 TRANSCEIVER” IS DIVIDED INTO THREE FUNCTIONAL BLOCKS: LIU, FRAMER, AND BACKPLANE INTERFACE OUTLINED IN THE FOLLOWING DIAGRAMS.

  • Page 21: Figure 6-2. Block Diagram Of T1/E1/J1 Transceiver

    Figure 6-2. Block Diagram of T1/E1/J1 Transceiver CLOCK EXTERNAL ACCESS CLOCK TO RECEIVE SIGNALS ADAPTER EXTERNAL ACCESS TO TRANSMIT SIGNALS HDB3 / B8ZS SYNC SINGALING ALARM DET HDLCs FRAMER SINGALING ALARM GEN HDLCs CRC GEN HDB3 / B8ZS FRAMER JTAG HOST INTERFACE ESIB 21 of 344...

  • Page 22: Figure 6-3. Receive And Transmit T1/E1/J1 Liu

    Figure 6-3. Receive and Transmit T1/E1/J1 LIU 32.768MHz RRING RTIP TRING TTIP VCO / PLL 22 of 344 JACLK RPOS RCLK RNEG TNEG TCLK TPOS INTERNAL SIGNALS FRAMER...

  • Page 23: Figure 6-4. Receive And Transmit T1/E1/J1 Framer

    Figure 6-4. Receive and Transmit T1/E1/J1 Framer RPOS RNEG RCLK TPOS TNEG TCLK INTERNAL SIGNALS FROM HDLC #1 128 Byte FIFO MAPPER DATA RECEIVE CLOCK FRAMER SYNC SYNC TRANSMIT CLOCK FRAMER DATA MAPPER XMIT HDLC #1 128 Byte FIFO 23 of 344 HDLC #2 128 Byte FIFO...

  • Page 24: Figure 6-5. T1/E1/J1 Backplane Interface

    Figure 6-5. T1/E1/J1 Backplane Interface DATA CLOCK SYNC INTERNAL SIGNALS FROM FRAMER SYNC Sa/FDL DATA INSERT CLOCK JACLK Sa BIT/FDL EXTRACTION SIGNALING BUFFER ELASTIC STORE CHANNEL TIMING SIGNALING BUFFER ELASTIC STORE CHANNEL TIMING TCLK 24 of 344 RLINK RLCLK RSIG RSIGFR RSYSCLK RSERO...

  • Page 25: Pin Descriptions

    Data Bit 7: Bidirectional data bit 7 of the microprocessor interface. Most Significant Bit. Not driven when CS = 1 or RST = 0. Write (Intel Mode): The DS33R11 captures the contents of the data bus (D0-D7) on the rising edge of WR and writes them to the addressed register location.
  • Page 26 NAME TYPE RD/DS Read Data Strobe (Intel Mode): The DS33R11 drives the data bus (D0-D7) with the contents of the addressed register while RD and CS are both low. Data Strobe (Motorola Mode): Used to latch data through the microprocessor interface. DS must be low during read and write operations.
  • Page 27 Receive Data 0 through 3 (MII): Four bits of received data, sampled synchronously with the rising edge of RX_CLK. For every clock cycle, the PHY transfers 4 bits to the DS33R11. RXD[0] is the least significant bit of the data. Data is not considered valid when RX_DV is low.
  • Page 28 This required clock can be up to 50MHz and should have ±100ppm accuracy. When in MII mode in DCE operation, the DS33R11 uses this input to generate the RX_CLK and TX_CLK outputs as required for the Ethernet PHY interface. When the MII interface is used with DTE operation, this clock is not required and should be tied low.
  • Page 29 DCE Mode. MII Management data IO (MII): Data path for control information between the PHY and DS33R11. When not used, pull to logic high externally through a 10kΩ resistor. The MDC and MDIO pins are used to write or read up to 32 Control and Status Registers in 32 PHY Controllers.
  • Page 30 At all other times, these pins are high-impedance. Note: All SDRAM operations are controlled entirely by the DS33R11. No user programming for SDRAM buffering is required. SDRAM Address Bus 0 to 11: The 12 pins of the SDRAM address bus output the row address first, followed by the column address.
  • Page 31 NAME TTIP R1, R2 TRING T1,T2 RTIP RRING T1/E1/J1 TRANSMIT FRAMER INTERFACE TSERI TCLKT TCHBLK TCHCLK TSSYNC TSYNC TSYSCLK TYPE T1/E1/J1 ANALOG LINE INTERFACE Transmit Analog Tip Output for the T1/E1/J1 Transceiver: Analog line-driver outputs. Two connections are provided to improve signal quality.
  • Page 32 NAME TYPE TSIG ETHERNET MAPPER TRANSMIT SERIAL INTERFACE TSERO TCLKE TDEN/ TBSYNC T1/E1/J1 RECEIVE FRAMER INTERFACE RSERO RCLKO RCHBLK RCHCLK Transmit Signaling Input for the T1/E1/J1 Transceiver: When enabled, this input will sample signaling bits for insertion into outgoing PCM data stream. Sampled on the falling edge of TCLKT when the transmit-side elastic store is disabled.
  • Page 33 NAME RSYNC RSYSCLK RFSYNC RMSYNC RSIG TYPE Receive Sync for the T1/E1/J1 Transceiver: An extracted pulse, one RCLKO wide, is output at this pin, which identifies either frame (TR.IOCR1.5 = 0) or multiframe (TR.IOCR1.5 = 1) boundaries. If set to output-frame boundaries then via TR.IOCR1.6, RSYNC can also be set to output double-wide pulses on signaling frames in T1 mode.
  • Page 34 NAME TYPE ETHERNET MAPPER RECEIVE SERIAL INTERFACE RSERI RCLKI RDEN/ RBSYNC T1/E1/J1 FRAMER/LIU INTERIM SIGNALS RDCLKI RDCLKO RNEGI RNEGO RPOSI RPOSO RDATA TDCLKI Receive Serial Data Input to Ethernet Mapper: Receive Serial data arrives on the rising edge of RCLKI. Normally connected to RSERO.
  • Page 35 NAME TYPE TDCLKO TNEGI TNEGO TPOSI TPOSO TDATA TESO Transmit Clock Output from the T1/E1/J1 Framer: Buffered clock that is used to clock data through the transmit-side formatter (either TCLKT or RDCLKI). This pin is normally tied to TDCLKI. Transmit Negative-Data Input: Sampled on the falling edge of TDCLKI for data to be transmitted out onto the T1 line.
  • Page 36 NAME LIUC TSTRST MODEC[0], B19, MODEC[1] QOVF RLOS/LTC RSIGF TYPE HARDWARE AND STATUS PINS Line Interface Unit Connect: When a logic low is present on this input pin, the T1/E1/J1 Framer and LIU are not internally connected. The line interface circuitry will be separated from the framer/formatter circuitry and the TPOSI, TNEGI, TDCLKI, RPOSI, RNEGI, and RDCLKI input pins will be active.
  • Page 37 SYSTEM CLOCKS System Clock In for Ethernet Mapper: 100MHz System Clock input to the DS33R11, used for internal operation. This clock is buffered and provided at SDCLKO for the SDRAM interface. The DS33R11 also provides a divided version output at the REF_CLKO pin.
  • Page 38 NAME TYPE JTCLK1 JTDI1 JTDO1 JTMS1 JTRST1 JTCLK2 JTDI2 JTDO2 JTMS2 JTRST2 JTAG INTERFACE JTAG Clock 1 for the Ethernet Mapper: This signal is used to shift data into JTDI1 on the rising edge and out of JTDO1 on the falling edge.
  • Page 39 NAME TYPE RVDD K3, L1 J1, J2, K2, RVSS L2, M2 TVDD P1, R3, T3, TVSS D1–D17, DVDD N4, P4, R4, DVSS B10, B15, C12, F3, J18, J20, VDD1.8 P18, P19, R19, R20, V9, Y9, Y13 D20, F17, G17, G18, H17, J17, K17, L17, VDD3...

  • Page 40: Figure 7-1. 256-Ball Bga Pinout

    Figure 7-1. 256-Ball BGA Pinout RCHBLK TCHBLK RFSYNC TDATA TSSYNC JTCLK2 BPCLK LIUC TPOSI TSIG JTDI2 TSYNC TDCLKO TNEGI TSTRST JTDO2 N.C. TDEN/ TDCLKI TCLKT TNEGO TESO N.C. TBSYNC TPOSO TSERO TSERI TSYSCLK TCLKE RCLKI VDD1.8 RSYSCLK TCHCLK RCHCLK RCLKO RSYNC RSERI RSERO...

  • Page 41: Functional Description

    The Ethernet packet interface supports MII and RMII interfaces, allowing the DSZ33R11 to connect to commercially available Ethernet PHY and MAC devices. The Ethernet interface can be configured for 10Mbit/s or 100Mbit/s service, in DTE and DCE configurations. The DS33R11 MAC interface rejects frames with bad FCS and short frames (less than 64 bytes).

  • Page 42: Processor Interface

    (asynchronous interface). 8.1 Processor Interface Microprocessor control of the DS33R11 is accomplished through the interface pins of the microprocessor port. The 8-bit parallel data bus can be configured for Intel or Motorola modes of operation with the two MODEC[1:0] pins.

  • Page 43: Ethernet Mapper

    9 ETHERNET MAPPER 9.1 Ethernet Mapper Clocks The DS33R11 clocks sources and functions are as follows: • Serial Transmit Data (TCLKE) and Serial Receive Data (RCLKI) clock inputs are used to transfer data from the serial interface. These clocks can be continuous or gapped.

  • Page 44: Figure 9-1. Clocking For The Ds33R11

    Figure 9-1. Clocking for the DS33R11 CLAD TTIP TRING BERT RTIP RRING JTAG2 NOTE THAT THE CLOCKING OPTIONS OF THE INTEGRATED T1/E1/J1 TANSCEIVER ARE DISCUSSED IN SECTION 10.1. HDLC HDLC 44 of 344 μP Port CLAD SYSCLKI REF_CLKO RX_CLK REF_CLK...

  • Page 45: Ethernet Interface Clock Modes

    PHY. While using MII mode with DCE operation, the MII clocks (TX_CLK and RX_CLK) are output by the DS33R11, and are derived from the 25MHz REF_CLK input. More information on MII mode can be found in Section 9.15.1.

  • Page 46: I Nitialization And

    Serial Interface Reset Queue Pointer Reset There are several features in the DS33R11 to reduce power consumption. The reset bit in the minimizes power usage in the Serial Interface. Additionally, the RST pin or GL.CR1.RST bit may be held in reset indefinitely to keep the device in a low-power mode.

  • Page 47: Initialization And Configuration

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 9.3 Initialization and Configuration EXAMPLE DEVICE INITIALIZATION SEQUENCE: STEP 1: Apply 3.3V supplies, then apply 1.8V supplies. STEP 2: Reset the integrated Ethernet Mapper by pulling the RST pin low or by using the software reset bits outlined in Section 9.2.

  • Page 48: Device Interrupts

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 9.6 Device Interrupts Figure 9-2 diagrams the flow of interrupt conditions from their source status bits through the multiple levels of information registers and mask bits to the interrupt pin. When an interrupt occurs, the host can read the Global Latched Status registers GL.LIS, GL.SIS, GL.BIS, and...

  • Page 49: Figure 9-2. Device Interrupt Information Flow Diagram

    Figure 9-2. Device Interrupt Information Flow Diagram Receive FCS Errored Packet Receive Aborted Packet Receive Invalid Packet Detected Receive Small Packet Detected Receive Large Packet Detected Receive FCS Errored Packet Count Receive Aborted Packet Count Receive Size Violation Packet Count <Reserved>...

  • Page 50: Interrupt Information Registers

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 9.7 Interrupt Information Registers The interrupt information registers provide an indication of which status registers (SR1 through SR9) are generating an interrupt. When an interrupt occurs, the host can read TR.IIR1 and TR.IIR2 to quickly identify which of the nine status registers are causing the interrupt.

  • Page 51: Connections And Queues

    The Receive Queue functions in a similar manner. Note that the user must ensure that sizes and watermarks are set in accordance with the configuration speed of the Ethernet and Serial interfaces. The DS33R11 does not provide error indication if the user creates a connection and queue that overwrites data for another connection queue.

  • Page 52: Arbiter

    It is recommended that the user reset the queue pointers for the connection after disconnection. The pointers must be reset before a connection is made. If this disconnect/connect procedure is not followed, incorrect data may be transmitted. The proper procedure for setting up a connection follows: •...

  • Page 53: Flow Control

    9.13 Flow Control Flow control may be required to ensure that data queues do not overflow and packets are not lost. The DS33R11 allows for optional flow control based on the queue high watermark or through host processor intervention. There are 2 basic mechanisms that are used for flow control: •...

  • Page 54: Full Duplex Flow Control

    The value of SU.RQLT does not affect the flow control. When the connection queue high threshold is exceeded the DS33R11 will send a pause frame with the timer value programmed by the user. See Table 9-6 for more information.

  • Page 55: Half Duplex Flow Control

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 9-3. Flow Control Using Pause Control Frame Receive Queue Low Water Receive Queue High Data Water Mark Initiate Flow control Receive Queue Growth 9.13.2 Half Duplex Flow Control Half duplex flow control uses a jamming sequence to exert backpressure on the transmitting node. The receiving node jams the first 4 bytes of a packet that are received from the MAC in order to cause collisions at the distant end.

  • Page 56: Ethernet Interface Port

    50 MHz. In MII operation, the interface contains 17 signals and a clock reference of 25MHz. The DS33R11 can be configured to RMII or MII interface by the Hardware pin RMIIMIIS. If the port is configured for MII in DCE mode, REF_CLK must be 25MHz.

  • Page 57: Table 9-5. Registers Related To Setting The Ethernet Port

    This is also true for the transmitted frames. Frames with errors are usually rejected by the DS33R11. The user has the option of accepting frames by settings in Receive Frame Rejection Control register (SU.RFRC). The user can program whether to reject or accept frames with the following errors: •...

  • Page 58: Dte And Dce Mode

    Mode it can be connected to an Ethernet PHY. In DCE mode, the port can be connected to MII/RMII MAC devices other than an Ethernet PHY. The DTE/DCE connections for the DS33R11 in MII mode are shown in the following two figures.

  • Page 59: Ethernet Mac

    SU.MACAWL and SU.MACAWH. A write command is issued by writing a zero to SU.MACRWC.MCRW and a one to SU.MACRWC.MCS (MAC command status). MCS is cleared by the DS33R11 when the operation is complete. Reading from the MAC registers requires the address for the read operation.

  • Page 60: Table 9-6. Mac Control Registers

    Table 9-6. MAC Control Registers ADDRESS REGISTER 0000h-0003h SU.MACCR 0014h-0017h SU.MACMIIA 0018h-001Bh SU.MACMIID 001Ch-001Fh SU.MACFCR 0100h-0103h SU.MMCCTRL Table 9-7. MAC Status Registers ADDRESS REGISTER 0200h-0203h SU.RxFrmCtr 0204h-0207h SU.RxFrmOkCtr 0300h-0303h SU.TxFrmCtr 0308h-030Bh SU.TxBytesCtr 030Ch-030Fh SU.TxBytesOkCtr 0334h-0337h SU.TxFrmUndr 0338h-033Bh SU.TxBdFrmCtr DESCRIPTION MAC Control Register. This register is used for programming full duplex, half duplex, promiscuous mode, and back-off limit for half duplex.

  • Page 61: Mii Mode Options

    50MHz reference (REF_CLK). Only seven signals are required. The following figure shows the RMII architecture. Note that DCE mode is not supported for RMII mode and RMII is valid only for full duplex operation. Figure 9-7. RMII Interface DS33R11 MAC Figure 9-5 Figure External PHY...

  • Page 62: Phy Mii Management Block And Mdio Interface

    9.15.3 PHY MII Management Block and MDIO Interface The MII Management Block allows for the host to control up to 32 PHYs, each with 32 registers. The MII block communicates with the external PHY using 2-wire serial interface composed of MDC (serial clock) and MDIO for data.

  • Page 63: Receive Data Interface

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 9.16.1 Receive Data Interface 9.16.1.1 Receive Pattern Detection The Receive BERT receives only the payload data and synchronizes the receive pattern generator to the incoming pattern. The receive pattern generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or bit 1 to the most significant bit (MSB) or bit 32.

  • Page 64: Repetitive Pattern Synchronization

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 9.16.2 Repetitive Pattern Synchronization Repetitive pattern synchronization synchronizes the receive pattern generator to the incoming repetitive pattern. The receive pattern generator is synchronized by searching each incoming data stream bit position for the repetitive pattern, and then checking the next 32 data stream bits.

  • Page 65: Transmit Packet Processor

    9.16.4.1 Error Insertion Error insertion inserts errors into the outgoing pattern data stream. Errors are inserted one at a time Single bit error insertion can be initiated from the microprocessor interface. If pattern inversion is enabled, the data stream is inverted before the overhead/stuff bits are inserted.

  • Page 66: Receive Packet Processor

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 9.18 Receive Packet Processor The Receive Packet Processor accepts data from the Receive Serial Interface performs packet descrambling, packet delineation, inter-frame fill filtering, packet abort detection, destuffing, packet size checking, FCS error monitoring, FCS byte extraction, and bit reordering. The data coming from the Receive Serial Interface is a serial data stream.

  • Page 67: Figure 9-11. Hdlc Encapsulation Of Mac Frame

    Bit reordering changes the bit order of each byte. If bit reordering is disabled, the incoming 8-bit data stream DT[1:8] with DT[1] being the MSB and DT[8] being the LSB is output to the Receive FIFO with the MSB in RFD[7] (or 15, 23, or 31) and the LSB in RFD[0] (or 8, 16, or 24) of the receive FIFO data RFD[7:0] (or 15:8, 23:16, or 31:24).

  • Page 68: X.86 E Ncoding And D Ecoding

    Ethernet frames. LAPS encapsulated frames can be used to send data onto a SONET/SDH network. The DS33R11 expects a byte synchronization signal to provide the byte boundary for the X.86 receiver. This is provided by the RBSYNC pin. The functional timing is shown in Figure 12-4.

  • Page 69: Figure 9-13. X.86 Encapsulation Of The Mac Frame

    FCS for MAC FCS for LAPS Flag(0x7E) The DS33R11 will encode the MAC Frame with the LAPS encapsulation on a complete serial stream if configured for X.86 mode in the register LI.TX86E. The DS33R11 provides the following functions: • Control Registers for Address, Control, SAPIH, SAPIL.
  • Page 70 The X86 received frame is aborted if: • If 7d,7E is detected. This is an abort packet sequence in X.86. • Invalid FCS is detected. • The received frame has less than 6 octets. • Control, SAPI and address field are mismatched to the programmed value. •...

  • Page 71: Committed Information Rate Controller

    9.20 Committed Information Rate Controller The DS33R11 provides a CIR provisioning facility. The CIR can be used restricts the transport of received MAC data to a programmable rate. The CIR location is shown in the the Receive MAC to Transmit HDLC. This can be used for provisioning and billing functions towards the WAN. The user must set the CIR register to control the amount of data throughput from the MAC to HDLC transmit.

  • Page 72: Integrated T1/E1/J1 Transceiver

    10 INTEGRATED T1/E1/J1 TRANSCEIVER 10.1 T1/E1/J1 Clocks Figure 10-1 shows the clock map of the T1/E1 transceiver. The routing for the transmit and receive clocks are shown for the various loopback modes and jitter attenuator positions. Although there is only one jitter attenuator, which can be placed in the receive or transmit path, two are shown for simplification and clarity.

  • Page 73: Per-Channel Operation

    TCSS0 The TCLKT pin (C) is always the source of transmit clock. Switch to the recovered clock (B) when the signal at the TCLKT pin fails to transition after one channel time. Use the scaled signal (A) derived from MCLK as the transmit clock.

  • Page 74: T1 Framer/Formatter Control And Status

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.4 T1 Framer/Formatter Control and Status The T1 framer portion of the transceiver is configured through a set of nine control registers. Typically, the control registers are only accessed when the system is first powered up. Once the transceiver has been initialized, the control registers only need to be accessed when there is a change in the system configuration.

  • Page 75: T1 Receive-Side Digital-Milliwatt Code Generation

    Note 2: ANSI specifications use a different nomenclature than this document. The following terms are equivalent: RBL = AIS RCL = LOS RLOS = LOF RYEL = RAI DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver code generation involves using SET CRITERIA...

  • Page 76: E1 Framer/Formatter Control And Status

    8ms Valid MF alignment word found and previous time slot 16 contains code other than all 0s DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver RESYNC CRITERIA Three consecutive incorrect FAS received Alternate: (TR.E1RCR1.2 = 1) The above criteria is met or...

  • Page 77: Automatic Alarm Generation

    10.5.1 Automatic Alarm Generation The device can be programmed to automatically transmit AIS or remote alarm. When automatic AIS generation is enabled (TR.E1TCR2.1 = 1), the device monitors the receive-side framer to determine if any of the following conditions are present: loss-of-receive frame synchronization, AIS alarm (all ones) reception, or loss-of-receive carrier (or signal).

  • Page 78: Error Counters

    10.7 Error Counters The transceiver contains four counters that are used to accumulate line-coding errors, path errors, and synchronization errors. Counter update options include one-second boundaries, 42ms (T1 mode only), 62ms (E1 mode only), or manual. See Error-Counter Configuration Register (TR.ERCNT). When updated automatically, the user can use the interrupt from the timer to determine when to read these registers.

  • Page 79: Path Code Violation Count Register (Tr.pcvcr)

    10.7.2 Path Code Violation Count Register (TR.PCVCR) In T1 mode, the path code violation count register records Ft, Fs, or CRC6 errors in T1 frames. When the receive side of a framer is set to operate in the T1 ESF framing mode, TR.PCVCR records errors in the CRC6 codewords. When set to operate in the T1 D4 framing mode, TR.PCVCR counts errors in the Ft framing bit position.

  • Page 80: Frames Out-Of-Sync Count Register (Tr.foscr)

    10.7.3 Frames Out-of-Sync Count Register (TR.FOSCR) In T1 mode, TR.FOSCR is used to count the number of multiframes that the receive synchronizer is out of sync. This number is useful in ESF applications needing to measure the parameters loss-of-frame count (LOFC) and ESF error events as described in AT&T publication TR54016.

  • Page 81: Ds0 Monitoring Function

    10.8 DS0 Monitoring Function The transceiver has the ability to monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction, the user determines which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the TR.TDS0SEL register.

  • Page 82: Signaling Operation

    10.9 Signaling Operation There are two methods to access receive signaling data and provide transmit signaling data, processor-based (software-based) or hardware-based. Processor-based refers to access through the transmit and receive signaling registers RS1–RS16 and TS1–TS16. Hardware-based refers to the TSIG and RSIG pins. Both methods can be used simultaneously.

  • Page 83: Hardware-Based Receive Signaling

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.9.2 Hardware-Based Receive Signaling In hardware-based signaling the signaling data can be obtained from the RSERO pin or the RSIG pin. RSIG is a signaling PCM stream output on a channel-by-channel basis from the signaling buffer. The signaling data, T1 robbed bit or E1 TS16, is still present in the original data stream at RSERO.

  • Page 84: Processor-Based Transmit Signaling

    Figure 10-3. Simplified Diagram of Transmit Signaling Path T1/E1 DATA STREAM ONLY APPLIES TO T1 MODE 10.9.3 Processor-Based Transmit Signaling In processor-based mode, signaling data is loaded into the transmit signaling registers (TS1–TS16) by the host interface. On multiframe boundaries, the contents of these registers are loaded into a shift register for placement in the appropriate bit position in the outgoing data stream.

  • Page 85: Hardware-Based Transmit Signaling

    10.9.3.2 E1 Mode In E1 mode, TS16 carries the signaling information. This information can be in either CCS (common channel signaling) or CAS (channel associated signaling) format. The 32 time slots are referenced by two different channel number schemes in E1. In “Channel” numbering, TS0–TS31 are labeled channels 1 through 32. In “Phone Channel”...

  • Page 86: Per-Channel Idle Code Generation

    10.10 Per-Channel Idle Code Generation Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. When operated in the T1 mode, only the first 24 channels are used by the device, the remaining channels, CH25–CH32, are not used.

  • Page 87: Idle-Code Programming Examples

    10.10.1 Idle-Code Programming Examples Example 1 Sets transmit channel 3 idle code to 7Eh Write TR.IAAR = 02h ;select channel 3 in the array Write TR.PCICR = 7Eh ;set idle code to 7Eh Example 2 Sets transmit channels 3, 4, 5, and 6 idle code to 7Eh and enables transmission of idle codes for those channels. Write TR.IAAR = 02h ;select channel 3 in the array Write TR.PCICR = 7Eh...

  • Page 88: Channel Blocking Registers

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.11 Channel Blocking Registers The receive channel blocking registers (TR.RCBR1/TR.RCBR2/TR.RCBR3/TR.RCBR4) and the transmit channel blocking registers (TR.TCBR1/TR.TCBR2/TR.TCBR3/TR.TCBR4) control RCHBLK TCHBLK pins, respectively. The RCHBLK and TCHBLK pins are user-programmable outputs that can be forced either high or low during individual channels.

  • Page 89: Transmit Elastic Store

    10.12.2 Transmit Elastic Store See the TR.IOCR1 and TR.IOCR2 registers for information about clock and I/O configurations. The operation of the transmit elastic store is very similar to the receive side. If the transmit-side elastic store is enabled, a 1.544MHz or 2.048MHz clock can be applied to the TSYSCLK input.

  • Page 90: G.706 I Ntermediate Crc-4 U Pdating (E1 M Ode O Nly )

    10.13 G.706 Intermediate CRC-4 Updating (E1 Mode Only) The device can implement the G.706 CRC-4 recalculation at intermediate path points. When this mode is enabled, the data stream presented at TSERI already has the FAS/NFAS, CRC multiframe alignment word, and CRC-4 checksum in time slot 0.

  • Page 91: T1 Bit-Oriented Code (Boc) Controller

    10.14 T1 Bit-Oriented Code (BOC) Controller The transceiver contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode. 10.14.1 Transmit BOC Bits 0 to 5 in the TR.TFDL register contain the BOC message to be transmitted. Setting TR.BOCC.0 = 1 causes the transmit BOC controller to immediately begin inserting the BOC sequence into the FDL bit position.

  • Page 92: Additional (Sa) And International (Si) Bit Operation (E1 Only)

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.15 Additional (Sa) and International (Si) Bit Operation (E1 Only) When operated in the E1 mode, the transceiver provides two methods for accessing the Sa and the Si bits. The first method involves using the internal TR.RAF/TR.RNAF and TR.TAF/TR.TNAF registers (Section 10.15.1). The second method, which is covered in Section 10.15.2, involves an expanded version of the first method.

  • Page 93: Additional Hdlc Controllers In T1/E1/J1 Transceiver

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.16 Additional HDLC Controllers in T1/E1/J1 Transceiver This device has two enhanced HDLC controllers, HDLC #1 and HDLC #2. Each controller is configurable for use with time slots, Sa4 to Sa8 bits (E1 mode), or the FDL (T1 mode). Each HDLC controller has 128-byte buffers in the transmit and receive paths.

  • Page 94: Table 10-12. Hdlc Controller Registers

    TR.H2RF, HDLC #1 Receive FIFO Register TR.H1TF, HDLC #1 Transmit FIFO Register TR.H2TF, HDLC #2 Transmit FIFO Register DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver CONTROL AND CONFIGURATION General control over the transmit HDLC controllers General control over the receive HDLC controllers...

  • Page 95: Fifo Control

    10.16.2 FIFO Control The FIFO control register (TR.HxFC) controls and sets the watermarks for the transmit and receive FIFOs. Bits 3, 4, and 5 set the transmit low watermark and the lower 3 bits set the receive high watermark. When the transmit FIFO empties below the low watermark, the TLWM bit in the appropriate HDLC status register TR.SR6 or TR.SR7 is set.

  • Page 96: Fifo Information

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.16.4 FIFO Information The transmit FIFO buffer-available register indicates the number of bytes that can be written into the transmit FIFO. The count form this register informs the host as to how many bytes can be written into the transmit FIFO without overflowing the buffer.

  • Page 97: Legacy Fdl Support (T1 Mode)

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.17 Legacy FDL Support (T1 Mode) 10.17.1 Overview To provide backward compatibility to the older DS21x52 T1 device, the transceiver maintains the circuitry that existed in the previous generation of the T1 framer. In new applications, it is recommended that the HDLC controllers and BOC controller described in Section 10.14...

  • Page 98: Transmit Section

    10.17.3 Transmit Section The transmit section shifts out into the T1 data stream either the FDL (in the ESF framing mode) or the Fs bits (in the D4 framing mode) contained in the transmit FDL register (TR.TFDL). When a new value is written to TR.TFDL, it is multiplexed serially (LSB first) into the proper position in the outgoing T1 data stream.

  • Page 99: Programmable In-Band Loop Code Generation And Detection

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.19 Programmable In-Band Loop Code Generation and Detection The transceiver has the ability to generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode. To transmit a pattern, the user loads the pattern into the transmit code-definition registers (TR.TCD1 and TR.TCD2) and selects the proper length of the pattern by setting...

  • Page 100: Line Interface Unit (Liu)

    (LIC1–LIC4), which are described in the following sections. The LIU has its own T1/E1 mode-select bit and can operate independently of the framer function. The transceiver can switch between T1 or E1 networks without changing external components on the transmit or receive side.

  • Page 101: Figure 10-5. Typical Monitor Application

    10.20.2.1 Receive Level Indicator and Threshold Interrupt The device reports the signal strength at RTIP and RRING in 2.5dB increments through RL3–RL0 located in Information Register 2 (TR.INFO2). This feature is helpful when trouble-shooting line-performance problems. The device can initiate an interrupt whenever the input falls below a certain level through the input-level under-threshold indicator (TR.SR1.7).

  • Page 102: Transmitter

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.20.3 Transmitter The transceiver uses a phase-lock loop along with a precision digital-to-analog converter (DAC) to create the waveforms that are transmitted onto the E1 or T1 line. The waveforms created by the device meet the latest ETSI, ITU-T, ANSI, and AT&T specifications.

  • Page 103: Mclk Prescaler

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.21 MCLK Prescaler A 16.384MHz, 8.192MHz, 4.096MHz, 2.048MHz, or 1.544MHz clock must be applied at MCLK. ITU specification G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specifications require an accuracy of ±32ppm for T1 interfaces.

  • Page 104: Recommended Circuits

    RRING 0.1μF RECOMMENDED VALUE 1:1 (receive) and 1:2 (transmit) ±2% 600μH (min) 1.0μH (max) 40pF (max) 1.0Ω (max) 2.0Ω (max) 1.2Ω (max) 1.2Ω (max) 104 of 344 DS33R11 0.1μF 0.01μF DVDD DVSS 0.1μF 10μF TVDD TVSS 0.1μF 10μF RVDD RVSS...

  • Page 105: Figure 10-8. E1 Transmit Pulse Template

    Figure 10-8. E1 Transmit Pulse Template -0.1 -0.2 -250 Figure 10-9. T1 Transmit Pulse Template -0.1 -0.2 -0.3 -0.4 -0.5 -500 194ns 219ns -200 -150 -100 TIME (ns) MAXIMUM CURVE -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.35 0.93 1.16 T1.102/87, T1.403, CB 119 (OCT.

  • Page 106: Figure 10-10. Jitter Tolerance

    Figure 10-10. Jitter Tolerance Figure 10-11. Jitter Tolerance (E1 Mode) DEVICE TOLERANCE TR 62411 (DEC. 90) ITU-T G.823 FREQUENCY (Hz) DEVICE TOLERANCE MINIMUM TOLERANCE LEVEL AS PER ITU G.823 FREQUENCY (Hz) 106 of 344 100k 2.4k 100k...

  • Page 107: Figure 10-12. Jitter Attenuation (T1 Mode)

    Figure 10-12. Jitter Attenuation (T1 Mode) -20dB -40dB -60dB Figure 10-13. Jitter Attenuation (E1 Mode) T1 MODE FREQUENCY (Hz) TBR12 Prohibited Area E1 MODE FREQUENCY (Hz) 107 of 344 TR 62411 (Dec. 90) Prohibited Area 100K ITU G.7XX Prohibited Area 100k...

  • Page 108: T1/E1/J1 Transceiver Bert Function

    Figure 10-14. Optional Crystal Connections NOTE: C1 AND C2 SHOULD BE 5pF LOWER THAN TWO TIMES THE NOMINAL LOADING CAPACITANCE OF THE CRYSTAL TO ADJUST FOR THE INPUT CAPACITANCE OF THE DEVICE. 10.25 T1/E1/J1 TRANSCEIVER BERT FUNCTION The BERT block can generate and detect pseudorandom and repeating bit patterns. It is used to test and stress data communication links, and it is capable of generating and detecting the following patterns: The pseudorandom patterns 2E7, 2E11, 2E15, and QRSS A repetitive pattern from 1 to 32 bits in length...

  • Page 109: Figure 10-15. Simplified Diagram Of Bert In Network Direction

    Figure 10-15. Simplified Diagram of BERT in Network Direction FROM RECEIVE FRAMER PER-CHANNEL AND F-BIT (T1 MODE) MAPPING TO TRANSMIT FRAMER Figure 10-16. Simplified Diagram of BERT in Backplane Direction FROM RECEIVE FRAMER PER-CHANNEL AND F-BIT (T1 MODE) MAPPING TO TRANSMIT FRAMER BERT BERT...

  • Page 110: Bert Repetitive Pattern Set

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.25.3 BERT Repetitive Pattern Set These registers must be properly loaded for the BERT to generate and synchronize to a repetitive pattern, a pseudorandom pattern, alternating word pattern, or a Daly pattern. For a repetitive pattern that is fewer than 32 bits, the pattern should be repeated so that all 32 bits are used to describe the pattern.

  • Page 111: Payload Error-Insertion Function (T1 Mode Only)

    10.26 Payload Error-Insertion Function (T1 Mode Only) An error-insertion function is available in the transceiver and is used to create errors in the payload portion of the T1 frame in the transmit path. This function is only available in T1 mode. Errors can be inserted over the entire frame or the user can select which channels are to be corrupted.

  • Page 112: Programmable Backplane Clock Synthesizer

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.27 Programmable Backplane Clock Synthesizer The transceiver contains an on-chip clock synthesizer that generates a user-selectable clock output on the BPCLK pin, referenced to the recovered receive clock (RCLKO). The synthesizer uses a phase-locked loop to generate low-jitter clocks.

  • Page 113: T1/E1/J1 Transmit Flow Diagrams

    10.29 T1/E1/J1 Transmit Flow Diagrams Figure 10-17. T1/J1 Transmit Flow Diagram HSIE1-3 through PCPR ESCR.4 TESE TLINK H1TC.4 HDLC FDL #1 THMS1 H2TC.4 HDLC FDL #2 THMS2 TFDL Tx FDL T1TCR2.5 Zero TZSE Stuffer T1TCR1.2 FDL Mux TFDLS BOC Mux BOCC.0 SBOC T1CCR1.2 TFM T1TCR2.2 TD4YM...
  • Page 114 From BOC Mux BERT Engine T1TCR2.3 FBCT1 T1TCR2.4 FBCT2 NOEL != 0 ERC.4 CE PEICS1-3 T1CCR1.1 PDE Calculation T1TCR2.7 B8ZSE T1TCR1.1 TBL IOCR1.0 ODF CCR1.4 ODM From ESF From F-bit Mux Yellow Alarm FDL Mux ESF Yellow CRC Mux D4 bit 2 TFM T1CCR1.2 Yellow TD4YM T1TCR2.2...

  • Page 115: Figure 10-18. E1 Transmit Flow Diagram

    Figure 10-18. E1 Transmit Flow Diagram HSIE1-4 through PCPR ESCR.4 TESE LBCR1.1 PLB - PIN - SELECTOR - REGISTER TSER TSIG Hardware Signaling ESTORE Estore Mux TESO Off-Chip Connection TDATA RDATA From E1_rcv_logic Payload HDLC Loopback Mux Engine HDLC DS0 Mux #1 HDLC Sa-bit Mux #1...
  • Page 116 From Idle From Idle Code Mux Code Mux Per-Channel Per-Channel Loopback Loopback TNAF TNAF Sa-bit Mux Sa-bit Mux Si-bit Mux Si-bit Mux E1TCR1.4 TSIS E1TCR1.4 TSIS E1TCR1.0 TCRC4 E1TCR1.0 TCRC4 Si/CRC4 Mux Si/CRC4 Mux Auto E- Auto E- E1TCR2.2 AEBE E1TCR2.2 AEBE bit Gen bit Gen...

  • Page 117: Device Registers

    PORT SELECT REGISTERS CS=0, Ethernet 0000h– CST=1 Mapper 003Fh CS=1, T1/E1/J1 — CST=0 Port 1 Table 11-1 shows the register map for the DS33R11. SERIAL ARBITER BERT INTERFAC 0040h– 0080h– 00C0h– 007Fh 00BFh 013Fh — — — 117 of 344...

  • Page 118: Register Bit Maps

    Table 11-6, and Table 11-7 ID06 ID05 ID04 ID14 ID13 ID12 RLCALS1 LIN1TIE LIN1TIS TQ1IE TQ1IS 118 of 344 contain the registers of the DS33R11. ID03 ID02 ID01 ID11 ID10 ID09 REF_CLKO INTM REFCLKS C1MRPR C1HWPR C1MHPR BISTDN ID00 ID08 GL.BLC1...

  • Page 119: Arbiter Register Bit Map

    11.1.2 Arbiter Register Bit Map Table 11-3. Arbiter Register Bit Map AR.RQSC1 RQSC7 AR.TQSC1 TQSC7 11.1.3 BERT Register Bit Map Table 11-4. BERT Register Bit Map 080h 081h Reserved 082h BPCLR 083h BPCHR 084h BSPB0R BSP7 085h BSPB1R BSP15 086h BSPB2R BSP23 087h...

  • Page 120: Serial Interface Register Bit Map

    11.1.4 Serial Interface Register Bit Map Table 11-5. Serial Interface Register Bit Map 0C0h LI.TSLCR 0C1h LI.RSTPD 0C2h LI.LPBK 0C3h Reserved 0C4h LI.TPPCL 0C5h LI.TIFGC TIFG7 0C6h LI.TEPLC TPEN7 0C7h LI.TEPHC MEIMS 0C8h LI.TPPSR 0C9h LI.TPPSRL 0CAh LI.TPPSRIE 0CBh Reserved 0CCh LI.TPCR0 TPC7...
  • Page 121 114h RSPC7 LI.RSPCB0 115h LI.RSPCB1 RSPC15 116h LI.RSPCB2 RSPC23 118h LI.RBC0 RBC7 119h LI.RBC1 RBC15 11Ah LI.RBC2 RBC23 11Bh RBC31 LI.RBC3 11Ch LI.RAC0 REBC7 11Dh LI.RAC1 REBC15 11Eh LI.RAC2 REBC23 11Fh LI.RAC3 REBC31 120h LI.RHPMUU 121h LI.RHPMUS 122h LI.RX86S 123h LI.RX86LSIE 124h LI.TQLT...

  • Page 122: Ethernet Interface Register Bit Map

    11.1.5 Ethernet Interface Register Bit Map Table 11-6. Ethernet Interface Register Bit Map 140h SU.MACRADL MACRA7 141h SU.MACRADH MACRA15 142h SU.MACRD0 MACRD7 143h SU.MACRD1 MACRD15 144h MACRD23 SU.MACRD2 145h MACRD31 SU.MACRD3 146h SU.MACWD0 MACWD7 147h SU.MACWD1 MACWD15 148h SU.MACWD2 MACWD23 149h SU.MACWD3 MACD31...

  • Page 123: Mac Register Bit Map

    11.1.6 MAC Register Bit Map Table 11-7. MAC Indirect Register Bit Map SU.MACCR 0000h Reserved 31:24 0001h 23:16 0002h 15:8 Reserved 0003h BOLMT1 0004h Reserved Reserved 0005h Reserved Reserved 0006h Reserved Reserved 0007h Reserved Reserved 0008h Reserved Reserved 0009h Reserved Reserved 000Ah Reserved...
  • Page 124 112h RESERVED – Reserved initialize to FF 113h RESERVED – Reserved initialize to FF 200h SU.RxFrmCtr RXFRMC31 RXFRMC30 RXFRMC29 RXFRMC28 RXFRMC27 RXFRMC26 RXFRMC25 RXFRMC24 31:24 201h 23:16 RXFRMC23 RXFRMC22 RXFRMC21 RXFRMC20 RXFRMC19 RXFRMC18 RXFRMC17 RXFRMC16 202h 15:8 RXFRMC15 RXFRMC14 RXFRMC13 RXFRMC12 RXFRMC11 RXFRMC10 203h RXFRMC7 204h...

  • Page 125: Table 11-8. T1/E1/J1 Transceiver Register Bit Map (Active When Cst = 0)

    Table 11-8. T1/E1/J1 Transceiver Register Bit Map (Active when CST = 0) — TR.MSTRREG RSMS TR.IOCR1 RDCLKIN TR.IOCR2 — TR.T1RCR1 — TR.T1RCR2 TR.T1TCR1 TB8ZS TR.T1TCR2 — TR.T1CCR1 TR.SSIE1-T1 TR.SSIE1-E1 CH16 TR.SSIE2-T1 CH15 TR.SSIE2-E1 CH24 TR.SSIE3-T1 CH22 TR.SSIE3-E1 CH30 TR.SSIE4 TR.T1RDMR1 CH16 TR.T1RDMR2 CH24...
  • Page 126 LSPARE TR.SR3 LSPARE TR.IMR3 RAIS-CI TR.SR4 RAIS-CI TR.IMR4 — TR.SR5 — TR.IMR5 — TR.SR6 — TR.IMR6 — TR.SR7 — TR.IMR7 — TR.SR8 — TR.IMR8 — TR.SR9 — TR.IMR9 RSAOICS TR.PCPR TR.PCDR1 CH16 TR.PCDR2 CH24 TR.PCDR3 CH32 TR.PCDR4 — TR.INFO4 — TR.INFO5 —...
  • Page 127 TFPT TR.E1TCR1 Reserved TR.E1TCR2 — TR.BOCC TR.RSINFO1 CH16 TR.RSINFO2 CH24 TR.RSINFO3 — TR.RSINFO4 TR.RSCSE1 CH16 TR.RSCSE2 CH24 TR.RSCSE3 — TR.RSCSE4 GRSRE TR.SIGCR — TR.ERCNT LCVC15 TR.LCVCR1 LCVC7 TR.LCVCR2 PCVC15 TR.PCVCR1 PCVC7 TR.PCVCR2 FOS15 TR.FOSCR1 FOS7 TR.FOSCR2 EB15 TR.EBCR1 TR.EBCR2 TR.LBCR TR.PCLR1 CH16 TR.PCLR2...
  • Page 128 TR.TS1 TR.TS2 TR.TS3 TR.TS4 TR.TS5 TR.TS6 TR.TS7 TR.TS8 TR.TS9 TR.TS10 TR.TS11 TR.TS12 TR.TS13 TR.TS14 TR.TS15 TR.TS16 TR.RS1 TR.RS2 TR.RS3 TR.RS4 TR.RS5 TR.RS6 TR.RS7 TR.RS8 TR.RS9 TR.RS10 Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition. Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition. Transmit Signaling Bit Format Changes With Operating Mode.
  • Page 129 TR.RS11 TR.RS12 TR.RS13 TR.RS14 TR.RS15 TR.RS16 — TR.CCR1 — TR.CCR2 — TR.CCR3 RLT3 TR.CCR4 — TR.TDS0SEL TR.TDS0M — TR.RDS0SEL TR.RDS0M TR.LIC1 TR.LIC2 — TR.LIC3 CMIE TR.LIC4 — Reserved — TR.TLBC GRIC TR.IAAR TR.PCICR TR.TCICE1 CH16 TR.TCICE2 CH24 TR.TCICE3 CH32 TR.TCICE4 TR.RCICE1 Receive Signaling Bit Format Changes With Operating Mode.
  • Page 130 CH16 TR.RCICE2 CH24 TR.RCICE3 CH32 TR.RCICE4 TR.RCBR1 CH16 TR.RCBR2 CH24 TR.RCBR3 CH32 TR.RCBR4 TR.TCBR1 CH16 TR.TCBR2 CH24 TR.TCBR3 CH32 TR.TCBR4 NOFS TR.H1TC — TR.H1FC RHCS8 TR.H1RCS1 RHCS16 TR.H1RCS2 RHCS24 TR.H1RCS3 RHCS32 TR.H1RCS4 RCB8SE TR.H1RTSBS THCS8 TR.H1TCS1 THCS16 TR.H1TCS2 THCS24 TR.H1TCS3 THCS32 TR.H1TCS4 TCB8SE...
  • Page 131 NOFS TR.H2TC — TR.H2FC RHCS8 TR.H2RCS1 RHCS16 TR.H2RCS2 RHCS24 TR.H2RCS3 RHCS32 TR.H2RCS4 RCB8SE TR.H2RTSBS THCS8 TR.H2TCS1 THCS16 TR.H2TCS2 THCS24 TR.H2TCS3 THCS32 TR.H2TCS4 TCB8SE TR.H2TTSBS TR.H2RPBA THD7 TR.H2TF RHD7 TR.H2RF TFBA7 TR.H2TFBA TR.IBCC TR.TCD1 TR.TCD2 TR.RUPCD1 TR.RUPCD2 TR.RDNCD1 TR.RDNCD2 — TR.RSCC TR.RSCD1 TR.RSCD2 TR.RFDL...
  • Page 132 TFDL7 TR.TFDL RFDLM7 TR.RFDLM1 RFDLM7 TR.RFDLM2 — Reserved — Reserved TR.RAF TR.RNAF SiF0 TR.RSiAF SiF1 TR.RSiNAF RRAF1 TR.RRA RSa4F1 TR.RSa4 RSa5F1 TR.RSa5 RSa6F1 TR.RSa6 RSa7F1 TR.RSa7 RSa8F1 TR.RSa8 TR.TAF TR.TNAF TsiF0 TR.TSiAF TsiF1 TR.TSiNAF TRAF1 TR.TRA TSa4F1 TR.TSa4 TSa5F1 TR.TSa5 TSa6F1 TR.TSa6 TSa7F1...
  • Page 133 RPAT7 TR.BRP1 RPAT15 TR.BRP2 RPAT23 TR.BRP3 RPAT31 TR.BRP4 TR.BC1 EIB2 TR.BC2 — Reserved BBC7 TR.BBC1 BBC15 TR.BBC2 BBC23 TR.BBC3 BBC31 TR.BBC4 TR.BEC1 EC15 TR.BEC2 EC23 TR.BEC3 — TR.BIC WNOE TR.ERC TR.NOE1 — TR.NOE2 TR.NOEL1 — TR.NOEL2 RPAT6 RPAT5 RPAT4 RPAT14 RPAT13 RPAT12 RPAT22...

  • Page 134: Global Register Definitions For Ethernet Mapper

    11.2 Global Register Definitions for Ethernet Mapper Functions contained in the global registers include: framer reset, LIU reset, device ID, and BERT interrupt status. These registers are preserved to provide code compatibility with the multiport devices in this product family. The global registers bit descriptions are presented below.
  • Page 135 Register Name: Register Description: Register Address: Bit # Name Default Bit 2: REF_CLKO OFF (REF_CLKO) This bit determines if the REF_CLKO is turned off 1 = REF_CLKO is disabled and outputs an active low signal. 0 = REF_CLKO is active and in accordance with RMII/MII Selection Bit 1: INT pin mode (INTM) This bit determines the inactive mode of the INT pin.
  • Page 136 Register Name: Register Description: Register Address: Bit # Name Default Bit 4: Receive Serial Interface Clock Activity Latched Status 1 (RLCALS1) This bit is set to 1 if the receive clock for Serial Interface 1 has activity. This bit is cleared upon read. Bit 0: Transmit Serial Interface Clock Activity Latched Status 1 (TSCALS1) This bit is set to 1 if the transmit clock for Serial Interface 1 has activity.
  • Page 137 Register Name: Register Description: Register Address: Bit # Name Default Bit 4: Serial Interface 1 TX Interrupt Status (LINE1TIS) This bit is set if Serial Interface 1 Transmit has an enabled interrupt generating event. Serial Interface interrupts consist of HDLC interrupts and X.86 interrupts. Bit 0: Serial Interface 1 RX Interrupt Status (LINER1IS) This bit is set if Serial Interface 1 Receive has an enabled interrupt generating event.
  • Page 138 Register Name: Register Description: Register Address: Bit # Name Default Bit 4: Transmit Queue 1 Interrupt Enable (TQ1IE) Setting this bit to 1 enables an interrupt on TQ1IS. Bit 0: Receive Queue 1 Interrupt Enable (RQ1IE) Setting this bit to 1 enables an interrupt on RQ1IS. Register Name: Register Description: Register Address:...
  • Page 139 Register Name: Register Description: Register Address: Bit # Name Default Bit 0: BERT Interrupt Status (BIS) This bit is set to 1 if the BERT has an enabled interrupt generating event. Register Name: Register Description: Register Address: Bit # Name Default Bit 0: LINE1[0] This bit is preserved to provide software compatibility with multiport devices.
  • Page 140 Default Bit 0: BIST Enable (BISTE) If this bit is set the DS33R11 performs BIST test on the SDRAM. Normal data communication is halted while BIST enable is high. The user must reset the DS33R11 after completion of BIST test before normal dataflow can begin.
  • Page 141 Name Default Bit 1: BIST DONE (BISTDN) If this bit is set to 1, the DS33R11 has completed the BIST Test initiated by BISTE. The pass fail result is available in BISTPF. Bit 0: BIST Pass-Fail (BISTPF) This bit is equal to 0 after the DS33R11 performs BIST testing on the SDRAM and the test passes.
  • Page 142 Register Name: Register Description: Register Address: Bit # Name Default Bits 0 - 2: CAS Latency Mode (LTMOD0 - LTMOD2) These bits are used to setup CAS Latency Note: Only CAS Latency of 2 or 3 is allowed Note: This register has a nonzero default value. This should be taken into consideration when initializing the device.

  • Page 143: Arbiter Registers

    32 packets. The range of bytes will depend on the external SDRAM connected to the DS33R11. Transmit queue is the data queue for data arriving on the WAN that is sent to the MAC.

  • Page 144: Bert Registers

    11.4 BERT Registers Register Name: Register Description: Register Address: Bit # Name Default Bit 7: This bit must be kept low for proper operation. Bit 6: Performance Monitoring Update (PMU) This bit causes a performance monitoring update to be initiated. A 0 to 1 transition causes the performance monitoring registers to be updated with the latest data, and the counters reset (0 or 1).
  • Page 145 Register Name: Register Description: Register Address: Bit # Name QRSS Default Bit 6: QRSS Enable (QRSS) When 0, the pattern generator configuration is controlled by PTS, PLF[0:4], and PTF[0:4], and BSP[0:31]. When 1, the pattern generator configuration is forced to a QRSS pattern with a generating polynomial of x output bits are all zero.
  • Page 146 Register Name: Register Description: Register Address: Bit # Name BSP7 BSP6 Default Bits 0 to 7: BERT Pattern (BSP[7:0]) Lower eight bits of 32 bits. Register description follows next register. Register Name: Register Description: Register Address: Bit # Name BSP15 BSP14 Default Bits 0 to 7: BERT Pattern (BSP[15:8]) 8 bits of 32 bits.
  • Page 147 Register Name: Register Description: Register Address: Bit # Name Default Bits 3 to 5: Transmit Error Insertion Rate (TEIR[2:0]) These three bits indicate the rate at which errors are inserted in the output data stream. One out of every 10 of 0 disables error insertion at a specific rate.
  • Page 148 Register Name: Register Description: Register Address: Bit # Name Default Bit 3: Performance Monitor Update Status Latched (PMSL) This bit is set when the PMS bit transitions from 0 to 1. Bit 2: Bit Error Detected Latched (BEL) This bit is set when a bit error is detected. Bit 1: Bit Error Count Latched (BECL) This bit is set when the BEC bit transitions from 0 to 1.
  • Page 149 Register Name: Register Description: Register Address: Bit # Name BEC7 BEC6 Default Bits 0 - 7: Bit Error Count (BEC[0:7]) Lower eight bits of 24 bits. Register description below. Register Name: Register Description: Register Address: Bit # Name BEC15 BEC14 Default Bits 0 - 7: Bit Error Count (BEC[8:15]) Eight bits of a 24 bit value.
  • Page 150 Register Name: Register Description: Register Address: Bit # Name BC15 BC14 Default Bits 0 - 7: Bit Count (BC[8:15]) Eight bits of a 32 bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name BC23 BC22 Default Bits 0 - 7: Bit Count (BC[16:23]) Eight bits of a 32 bit value.

  • Page 151: Serial Interface Registers

    Default Bit 0: Transmit Data Enable Polarity (TDENPLT) If set to 1, TDEN is active low for enable. In the default mode, when TDEN is logic high, the data is enabled and output by the DS33R11. Register Name: Register Description:...

  • Page 152: Transmit Hdlc Processor Registers

    Register Name: Register Description: Register Address: Bit # Name Default Bit 0: Queue Loopback Enable (QLP) If this bit set to 1, data received on the Serial Interface is looped back to the Serial Interface transmitter. Received data will not be sent from the Serial Interface to the Ethernet Interface. Buffered packet data will remain in queue until the loopback is removed.
  • Page 153 Register Name: Register Description: Register Address: Bit # Name TIFG7 TIFG6 Default Bits 0 - 7: Transmit Inter-Frame Gapping (TIFG[7:0]) – These eight bits indicate the number of additional flags and bytes of inter-frame fill to be inserted between packets. The number of flags and bytes of inter-frame fill between packets is at least the value of TIFG[7:0] plus 1.
  • Page 154 Register Name: Register Description: Register Address: Bit # Name MEIMS TPER6 Default Bit 7: Manual Error Insert Mode Select (MEIMS) – When 0, the transmit manual error insertion signal (TMEI) will not cause errors to be inserted. When 1, TMEI will cause an error to be inserted when it transitions from a 0 to a 1. Note: Enabling TMEI does not disable error insertion using TCER[6:0] and TCEN[7:0].
  • Page 155 Register Name: Register Description: Register Address: Bit # Name Default Bit 0: Transmit Errored Packet Insertion Finished (TEPF) – This bit is set when the number of errored packets indicated by the TPEN[7:0] bits in the TEPC register have been transmitted. This bit is cleared when errored packet insertion is disabled, or a new errored packet insertion process is initiated.
  • Page 156 Register Name: Register Description: Register Address: Bit # Name TPC7 TPC6 Default Bits 0 – 7: Transmit Packet Count (TPC[7:0]) – Eight bits of 24 bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name TPC15 TPC14 Default Bits 0 –...
  • Page 157 Register Name: Register Description: Register Address: Bit # Name TBC7 TBC6 Default Bits 0 – 7: Transmit Byte Count (TBC[0:7]) – Eight bits of 32 bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name TBC15 TBC14 Default Bits 0 –...
  • Page 158 Register Name: LI.THPMUU Register Description: Serial Interface Transmit HDLC PMU Update Register Register Address: 0D6h Bit # Name Default Bit 0: Transmit PMU Update (TPMUU) This signal causes the transmit cell/packet processor block performance monitoring registers (counters) to be updated. A 0 to 1 transition causes the performance monitoring registers to be updated with the latest data, and the counters reset (0 or 1).

  • Page 159: Registers

    Transmit and Receive paths. The MAC Frame is encapsulated in the X.86 Frame for Transmit and the X.86 headers are checked for in the received data. If X.86 functionality is selected, the X.86 receiver byte boundary is provided by the RBSYNC signal and the DS33R11 provides the transmit byte synchronization TBSYNC. No HDLC encapsulation is performed.

  • Page 160: Committed Information Rate

    Register Name: Register Description: Register Address: Bit # Name TRSAPIL7 TRSAPIL6 Default Bits 0 – 7: X86 Transmit Receive Control (TRSAPIL0-7) This is the address field for the X.86 transmitter and expected value for the receiver. The register is reset to 0x01 Register Name: Register Description: Register Address:...

  • Page 161: Receive Serial Interface

    11.5.3 Receive Serial Interface Serial Receive Registers are used to control the HDLC Receiver associated with each Serial Interface. Note that throughout this document HDLC Processor is also referred to as “Packet Processor”. The receive packet processor block has seventeen registers. 11.5.3.1 Receive Serial Register Bit Descriptions Register Name: Register Description:...
  • Page 162 Register Name: Register Description: Register Address: Bit # Name RMX7 RMX6 Default Bits 0 - 7: Receive Maximum Packet Size (RMX[7:0]) Eight bits of a sixteen bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name RMX15 RMX14 Default...
  • Page 163 Register Name: Register Description: Register Address: Bit # Name REPL RAPL Default Bit 7: Receive FCS Errored Packet Latched (REPL) This bit is set when a packet with an errored FCS is detected. Bit 6: Receive Aborted Packet Latched (RAPL) This bit is set when a packet with an abort indication is detected. Bit 5: Receive Invalid Packet Detected Latched (RIPDL) This bit is set when a packet with a noninteger number of bytes is detected.
  • Page 164 Register Name: Register Description: Register Address: Bit # Name REPIE RAPIE Default Bit 7: Receive FCS Errored Packet Interrupt Enable (REPIE) This bit enables an interrupt if the REPL bit in the LI.RPPSRL register is set. 0 = interrupt disabled 1 = interrupt enabled Bit 6: Receive Aborted Packet Interrupt Enable (RAPIE) This bit enables an interrupt if the RAPL bit in the LI.RPPSRL register is set.
  • Page 165 Register Name: Register Description: Register Address: Bit # Name RPC7 RPC6 Default Bits 0 - 7: Receive Packet Count (RPC [7:0]) Eight bits of a 24-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name RPC15 RPC14 Default Bits 0 - 7: Receive Packet Count (RPC [15:8]) Eight bits of a 24-bit value.
  • Page 166 Register Name: Register Description: Register Address: Bit # Name RFPC7 RFPC6 Default Bits 0 – 7: Receive FCS Errored Packet Count (RFPC[7:0]) Eight bits of a 24-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name RFPC15 RFPC14 Default...
  • Page 167 Register Name: Register Description: Register Address: Bit # Name RAPC7 RAPC6 Default Bits 0 - 7: Receive Aborted Packet Count (RAPC [7:0]) Eight bits of a 24-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name RAPC15 RAPC14 Default...
  • Page 168 Register Name: Register Description: Register Address: Bit # Name RSPC7 RSPC6 Default Bits 0 - 7: Receive Size Violation Packet Count (RSPC [7:0]) Eight bits of a 24-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name RSPC15 RSPC14...
  • Page 169 Register Name: Register Description: Register Address: Bit # Name RBC7 RBC6 Default Bits 0 - 7: Receive Byte Count (RBC [7:0]) Eight bits of a 32-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name RBC15 RBC14 Default Bits 0 - 7: Receive Byte Count (RBC [15:8]) Eight bits of a 32-bit value.
  • Page 170 Register Name: Register Description: Register Address: Bit # Name REBC7 REBC6 Default Bits 0 - 7: Receive Aborted Byte Count (RBC [7:0]) Eight bits of a 32-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name REBC15 REBC14 Default...
  • Page 171 Register Name: LI.RHPMUU Register Description: Serial Interface Receive HDLC PMU Update Register Register Address: 120h Bit # Name Default Bit 0: Receive PMU Update (RPMUU) This signal causes the receive cell/packet processor block performance monitoring registers (counters) to be updated. A 0 to 1 transition causes the performance monitoring registers to be updated with the latest data, and the counters reset (0 or 1).
  • Page 172 Register Name: Register Description: Register Address: Bit # Name Default Bit 3: SAPI Octet not equal to LI.RX86S.SAPIHNE will generate an interrupt. Bit 2: SAPI Octet not equal to LI.RX86S.SAPILNE will generate an interrupt. Bit 1: Control not equal to LI.TRX8C generate an interrupt.
  • Page 173 Register Name: Register Description: Register Address: Bit # Name Default Bit 3: Transmit FIFO Overflow for Connection Interrupt Enable (TFOVFIE) If this bit is set, the watermark interrupt is enabled for TFOVFLS. Bit 2: Transmit Queue Overflow for Connection Interrupt Enable (TQOVFIE) If this bit is set, the watermark interrupt is enabled for TQOVFLS.

  • Page 174: Ethernet Interface Registers

    11.6 Ethernet Interface Registers The Ethernet Interface registers are used to configure RMII/MII bus operation and establish the MAC parameters as required by the user. The MAC Registers cannot be addressed directly from the Processor port. The registers below are used to perform indirect read or write operations to the MAC registers. The MAC Status Registers are shown in Table 11-7.
  • Page 175 Register Name: Register Description: Register Address: Bit # Name MACRD15 MACRD14 Default Bits 0 - 7: MAC Read Data 1 (MACRD8-15) One of four bytes of data read from the MAC. Valid after a read command has been issued and the SU.MACRWC.MCS bit is zero. Register Name: Register Description: Register Address:...
  • Page 176 Register Name: Register Description: Register Address: Bit # Name MACWD15 MACWD14 Default Bits 0 – 7: MAC Write Data 1 (MACWD8-15) One of four bytes of data to be written to the MAC. Data has been written after a write command has been issued and the SU.MACRWC.MCS bit is zero. Register Name: Register Description: Register Address:...
  • Page 177 SU.MACAWL. Address information for read operations must be located in user must also write a 1 to the MCS bit, and the DS33R11 will clear MCS when the operation is complete. Bit 0: MAC Command Status (MCS) Setting MCS in conjunction with MCRW will initiate a read or write to the MAC registers.
  • Page 178 Register Name: Register Description: Register Address: Bit # Name Default Bit 0: Queue Loopback Enable (QLP) If this bit is set to 1, data from the Ethernet Interface receive queue is looped back to the transmit queue. Buffered data from the serial interface will remain until the loopback is removed. Register Name: Register Description: Register Address:...
  • Page 179 Register Name: Register Description: Register Address: Bit # Name Default Bit 3: No Carrier Queue Flush Bar (NCFQ) If this bit is set to 1, the queue for data passing from Serial Interface to Ethernet Interface will not be flushed when loss of carrier is detected. Bit 2: Transmit Packet Deferred Fail Control Enable (TPDFCB) If this bit if set to 1, the current frame is transmitted immediately instead of being deferred.
  • Page 180 Register Name: Register Description: Register Address: Bit # Name Default Bit 7: Under Run (UR) When this bit is set to 1, the frame was aborted due to a data under run condition of the transmit buffer. Bit 6: Excessive Collisions (EC) When this bit is set to 1, a frame has been aborted after 16 successive collisions while attempting to transmit the current frame.
  • Page 181 Register Name: Register Description: Register Address: Bit # Name Default Bits 0 - 7: Frame Length (FL[0:7]) These 8 bits are the low byte of the length (in bytes) of the received frame, with FCS and Padding. If Automatic Pad Stripping is enabled, this value is the length of the received packet without PCS or Pad bytes.
  • Page 182 Register Name: Register Description: Register Address: Bit # Name Default Bit 7: Missed Frame (MF) This bit is set to 1 if the packet is not successfully received from the MAC by the packet Arbiter. Bit 4: Broadcast Frame (BF) This bit is set to 1 if the current frame is a broadcast frame. Bit 3: Multicast Frame (MCF) This bit is set to 1 if the current frame is a multicast frame.
  • Page 183 Register Name: Register Description: Register Address: Bit # Name RMPS7 RMPS6 Default Bits 7- 0: Receiver Maximum Frame (RMPS[0:7]) Eight bits of sixteen bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name RMPS15 RMPS14 Default Bits 7- 0: Receiver Maximum Frame (RMPS[8:15]) This value is the receiver’s maximum frame size (in bytes), up to a maximum of 2016 bytes.
  • Page 184 Register Name: Register Description: Register Address: Bit # Name Default Bit 3: Receive FIFO Overflow Interrupt Enable (RFOVFIE) If this bit is set, the interrupt is enabled for RFOVFLS. Bit 2: Receive Queue Overflow Interrupt Enable (RQVFIE) If this bit is set, the interrupt is enabled for RQOVFLS.
  • Page 185 Register Name: Register Description: Register Address: Bit # Name UCFR Default Bit 6: Uncontrolled Control Frame Reject (UCFR) When set to 1, Control Frames other than Pause Frames are allowed. When this bit is equal to zero, nonpause control frames are rejected. Bit 5: Control Frame Reject (CFRR) When set to 1, control frames are allowed.

  • Page 186: Mac Registers

    11.6.2 MAC Registers The control Registers related to the control of the individual Mac’s are shown in the following Table. The DS33R11 keeps statistics for the packet traffic sent and received. The register address map is shown in the following Table.
  • Page 187 Bit 12: Late Collision Control (LCC) When set to 1, enables retransmission of a collided packet even after the collision period. When this bit is clear, retransmission of late collisions is disabled. Bit 10: Disable Retry (DRTY) When set to 1, the MAC makes only a single attempt to transmit each frame. If a collision occurs, the MAC ignores the current frame and proceeds to the next frame.
  • Page 188 Bit 0: MII Busy (MIIB) This bit is set to 1 by the DS33R11 during execution of a MII management instruction through the MDIO interface, and is set to zero when the DS33R11 has completed the instruction. The user should read this bit and ensure that it is equal to zero prior to beginning a MDIO instruction.
  • Page 189 Register Name: Register Description: Register Address: 0018h: Bit # Name Reserved Reserved Default 0019h: Bit # Name Reserved Reserved Default 001Ah: Bit # Name MIID15 MIID14 Default 001Bh: Bit # Name MIID07 MIID06 Default Bits 0 – 15: MII (MDIO) Data (MIID[00:15]) These two bytes contain the data to be written to or the data read from the MII management interface (MDIO).
  • Page 190 Bit 0: Flow Control Busy (FCB) The host can set this bit to 1 in order to initiate transmission of a pause frame. During transmission of a pause frame, this bit remains set. The DS33R11 will clear this bit when transmission of the pause frame has been completed.
  • Page 191 Register Name: Register Description: Register Address: 0100h: Bit # Name Reserved Reserved Default 0101h: Bit # Name Reserved Reserved Default 0102h: Bit # Name Reserved Reserved Default 0103h: Bit # Name MXFRM4 MXFRM3 Default Bits 3 - 13: Maximum Frame Size (MXFRM[0:10]) These bits indicate the maximum packet size value. All transmitted frames larger than this value are counted as long frames.
  • Page 192 Register Name: Register Description: Register Address: 010Ch: Bit # Name Reserved Reserved Default 010Dh: Bit # Name Reserved Reserved Default 010Eh: Bit # Name Reserved Reserved Default 010Fh: Bit # Name Reserved Reserve Default Note – Addresses 10Ch through 10Fh must each be initialized with all 1’s (FFh) for proper software-mode operation.
  • Page 193 Register Name: Register Description: Register Address: 0110h: Bit # Name Reserved Reserved Default 0111h: Bit # Name Reserved Reserved Default 0112h: Bit # Name Reserved Reserved Default 0113h: Bit # Name Reserved Reserve Default Note – Addresses 110h through 113h must each be initialized with all 1’s (FFh) for proper software-mode operation.
  • Page 194 Register Name: Register Description: Register Address: 0200h: Bit # Name RXFRMC31 RXFRMC30 Default 0201h: Bit # Name RXFRMC23 RXFRMC22 Default 0202h: Bit # Name RXFRMC15 RXFRMC14 Default 0203h: Bit # Name RXFRMC7 RXFRMC6 Default Bits 0 - 31: All Frames Received Counter (RXFRMC[0:31]) 32 bit value indicating the number of frames received.
  • Page 195 Register Name: Register Description: Register Address: 0204h: Bit # Name RXFRMOK31 RXFRMOK30 Default 0205h: Bit # Name RXFRMOK23 RXFRMOK22 Default 0206h: Bit # Name RXFRMOK15 RXFRMOK14 Default 0207h: Bit # Name RXFRMOK7 RXFRMOK6 Default Bits 0 - 31: Frames Received OK Counter (RXFRMOK[0:31]) 32 bit value indicating the number of frames received and determined to be valid.
  • Page 196 Register Name: Register Description: Register Address: 0300h: Bit # Name TXFRMC31 TXFRMC30 Default 0301h: Bit # Name TXFRMC23 TXFRMC22 Default 0302h: Bit # Name TXFRMC15 TXFRMC14 Default 0303h: Bit # Name TXFRMC7 TXFRMC6 Default Bits 0 - 31: All Frames Transmitted Counter (TXFRMC[0:31]) 32 bit value indicating the number of frames transmitted.
  • Page 197 Register Name: Register Description: Register Address: 0308h: Bit # Name TXBYTEC31 TXBYTEC30 Default 0309h: Bit # Name TXBYTEC23 TXBYTEC22 Default 030Ah: Bit # Name TXBYTEC15 TXBYTEC14 Default 030Bh: Bit # Name TXBYTEC7 TXBYTEC6 Default Bits 0 - 31: All Bytes Transmitted Counter (TXBYTEC[0:31]) 32 bit value indicating the number of bytes transmitted.
  • Page 198 Register Name: Register Description: Register Address: 030Ch: Bit # Name TXBYTEOK31 TXBYTEOK30 Default 030Dh: Bit # Name TXBYTEOK23 TXBYTEOK22 Default 030Eh: Bit # Name TXBYTEOK15 TXBYTEOK14 Default 030Fh: Bit # Name TXBYTEOK7 TXBYTEOK6 Default Bits 0 - 31: Bytes Transmitted OK Counter (TXBYTEOK[0:31]) 32 bit value indicating the number of bytes transmitted and determined to be valid.
  • Page 199 Register Name: Register Description: Register Address: 0334h: Bit # Name TXFRMU31 TXFRMU30 Default 0335h: Bit # Name TXFRMU23 TXFRMU22 Default 0336h: Bit # Name TXFRMU15 TXFRMU14 Default 0337h: Bit # Name TXFRMU7 TXFRMU6 Default Bits 0 - 31: Frames Aborted Due to FIFO Under Run Counter (TXFRMU[0:31]) 32 bit value indicating the number of frames aborted due to FIFO under run.
  • Page 200 Register Name: Register Description: Register Address: 0338h: Bit # Name TXFRMBD31 TXFRMBD30 Default 0339h: Bit # Name TXFRMBD23 TXFRMBD22 Default 033Ah: Bit # Name TXFRMBD15 TXFRMBD14 Default 033Bh: Bit # Name TXFRMBD7 TXFRMBD6 Default Bits 0 to 31: All Frames Aborted Counter (TXFRMBD[0:31]) 32 bit value indicating the number of frames aborted due to any reason.

  • Page 201: T1/E1/J1 Transceiver Registers

    11.7 T1/E1/J1 Transceiver Registers TR.MSTRREG Register Name: Register Description: Master Mode Register Register Address: Bit # Name — — Default Bits 2 – 3: Test Mode Bits (TEST0, TEST1) Test modes are used to force the output pins of the transceiver into known states.
  • Page 202 Register Name: TR.IOCR1 Register Description: I/O Configuration Register 1 Register Address: Bit # Name RSMS RSMS2 Default Bit 7: RSYNC Multiframe Skip Control (RSMS) Useful in framing format conversions from D4 to ESF. This function is not available when the receive-side elastic store is enabled. RSYNC must be set to output multiframe pulses (TR.IOCR1.5 = 1 and TR.IOCR1.4 = 0).
  • Page 203 Register Name: TR.IOCR2 Register Description: I/O Configuration Register 2 Register Address: Bit # Name RCLKINV TCLKINV Default Bit 7: RCLKO Invert (RCLKINV) 0 = no inversion 1 = inverts signal on RCLKO output. Bit 6: TCLKT Invert (TCLKINV) 0 = no inversion 1 = inverts signal on TCLKT input.
  • Page 204 Register Name: TR.T1RCR1 Register Description: T1 Receive Control Register 1 Register Address: Bit # Name — Default Bit 6: Auto Resync Criteria (ARC) 0 = resync on OOF or RCL event 1 = resync on OOF only Bits 4- 5: Out-of-Frame Select Bits (OOF2, OOF1) OOF2 OOF1 Out-Of-Frame Criteria...
  • Page 205 Register Name: TR.T1RCR2 Register Description: T1 Receive Control Register 2 Register Address: Bit # Name — Default Bit 6: Receive Frame Mode Select (RFM) 0 = D4 framing mode 1 = ESF framing mode Bit 5: Receive B8ZS Enable (RB8ZS) 0 = B8ZS disabled 1 = B8ZS enabled Bit 4: Receive SLC-96 Enable (RSLC96).
  • Page 206 Register Name: TR.T1TCR1 Register Description: T1 Transmit Control Register 1 Register Address: Bit # Name TFPT Default Bit 7: Transmit Japanese CRC6 Enable (TJC) 0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation) 1 = use Japanese standard JT–G704 CRC6 calculation Bit 6: Transmit F-Bit Pass-Through (TFPT) 0 = F bits sourced internally 1 = F bits sampled at TSERI...
  • Page 207 Register Name: TR.T1TCR2 Register Description: T1 Transmit Control Register 2 Register Address: Bit # Name TB8ZS TSLC96 Default Bit 7: Transmit B8ZS Enable (TB8ZS) 0 = B8ZS disabled 1 = B8ZS enabled Bit 6: Transmit SLC-96/Fs-Bit Insertion Enable (TSLC96). Only set this bit to a 1 in D4 framing applications. Must be set to 1 to source the Fs pattern from the TR.TFDL register.
  • Page 208 Register Name: TR.T1CCR1 Register Description: T1 Common Control Register 1 Register Address: Bit # Name — — Default Bit 4: Transmit RAI-CI Enable (TRAI-CI). Setting this bit causes the ESF RAI-CI code to be transmitted in the FDL bit position. 0 = do not transmit the ESF RAI-CI code 1 = transmit the ESF RAI-CI code Bit 3: Transmit AIS-CI Enable (TAIS-CI).
  • Page 209 Register Name: TR.SSIE1 (E1 Mode) Register Description: Software Signaling Insertion Enable 1 Register Address: Bit # Name Default Bits 1 – 7: Software Signaling-Insertion Enable for Channels 1 to 7 (CH1 to CH7). These bits determine which channels are to have signaling inserted from the transmit signaling registers. 0 = do not source signaling data from the TR.TSx registers for this channel 1 = source signaling data from the TR.TSx registers for this channel Bit 0: Upper CAS Align/Alarm Word (UCAW).
  • Page 210 Register Name: TR.SSIE3 (T1 Mode) Register Description: Software Signaling-Insertion Enable 3 Register Address: Bit # Name CH24 CH23 Default Bits 0 – 7: Software Signaling Insertion Enable for Channels 17 to 24 (CH17 to CH24). These bits determine which channels are to have signaling inserted from the transmit signaling registers. 0 = do not source signaling data from the TR.TSx registers for this channel 1 = source signaling data from the TR.TSx registers for this channel Register Name:...
  • Page 211 Register Name: TR.T1RDMR1 Register Description: T1 Receive Digital-Milliwatt Enable Register 1 Register Address: Bit # Name Default Bits 0 - 7: Receive Digital-Milliwatt Enable for Channels 1 to 8 (CH1 to CH8) 0 = do not affect the receive data associated with this channel 1 = replace the receive data associated with this channel with digital-milliwatt code Register Name: TR.T1RDMR2...
  • Page 212 Register Name: TR.IDR Register Description: Device Identification Register Register Address: Bit # Name Default Bits 4 - 7: Device ID (ID4 to ID7). The upper four bits of TR.IDR are used to display the transceiver ID. Bits 0 – 3: Chip Revision Bits (ID0 to ID3). The lower four bits of TR.IDR are used to display the die revision of the chip.
  • Page 213 Register Name: TR.INFO2 Register Description: Information Register 2 Register Address: Bit # Name BSYNC Default Bit 7: BERT Real-Time Synchronization Status (BSYNC). Real-time status of the synchronizer (this bit is not latched). This bit is set when the incoming pattern matches for 32 consecutive bit positions. It is cleared when six or more bits out of 64 are received in error.
  • Page 214 Register Name: TR.INFO3 Register Description: Information Register 3 Register Address: Bit # Name — — Default Bit 2: CRC Resync Criteria Met Event (CRCRC). Set when 915/1000 codewords are received in error. Bit 1: FAS Resync Criteria Met Event (FASRC). Set when three consecutive FAS words are received in error. Note: During a CRC resync the FAS synchronizer is brought online to verify the FAS alignment.
  • Page 215 Register Name: TR.SR1 Register Description: Status Register 1 Register Address: Bit # Name ILUT TIMER Default Bit 7: Input Level Under Threshold (ILUT). This bit is set whenever the input level at RTIP and RRING falls below the threshold set by the value in TR.CCR4.4 through TR.CCR4.7. The level must remain below the programmed threshold for approximately 50ms for this bit to be set.
  • Page 216 Register Name: TR.IMR1 Register Description: Interrupt Mask Register 1 Register Address: Bit # Name ILUT TIMER Default Bit 7: Input Level Under Threshold (ILUT) 0 = interrupt masked 1 = interrupt enabled Bit 6: Timer Event (TIMER) 0 = interrupt masked 1 = interrupt enabled Bit 5: Receive Signaling Change-of-State Event (RSCOS) 0 = interrupt masked...
  • Page 217 Register Name: TR.SR2 Register Description: Status Register 2 Register Address: Bit # Name RYELC RUA1C Default Bit 7: Receive Yellow Alarm Clear Event (RYELC) (T1 Only). Set when the receive Yellow Alarm condition is no longer detected. Bit 6: Receive Unframed All-Ones Clear Event (RUA1C). Set when the unframed all 1s condition is no longer detected.
  • Page 218 Register Name: TR.IMR2 Register Description: Interrupt Mask Register 2 Register Address: Bit # Name RYELC RUA1C Default Bit 7: Receive Yellow Alarm Clear Event (RYELC) 0 = interrupt masked 1 = interrupt enabled Bit 6: Receive Unframed All-Ones Condition Clear Event (RUA1C) 0 = interrupt masked 1 = interrupt enabled Bit 5: Framer Receive Carrier Loss Condition Clear (FRCLC)
  • Page 219 Register Name: TR.SR3 Register Description: Status Register 3 Register Address: Bit # Name LSPARE Default Bit 7: Spare Code Detected Condition (LSPARE) (T1 Only). Set when the spare code as defined in the TR.RSCD1/2 registers is being received. See Section 9.7.
  • Page 220 Register Name: TR.IMR3 Register Description: Interrupt Mask Register 3 Register Address: Bit # Name LSPARE Default Bit 7: Spare Code Detected Condition (LSPARE) 0 = interrupt masked 1 = interrupt enabled—interrupts on rising and falling edges Bit 6: Loop-Down Code-Detected Condition (LDN) 0 = interrupt masked 1 = interrupt enabled—interrupts on rising and falling edges Bit 5: Loop-Up Code-Detected Condition (LUP)
  • Page 221 Register Name: TR.SR4 Register Description: Status Register 4 Register Address: Bit # Name RAIS-CI RSAO Default Bit 7: Receive AIS-CI Event (RAIS-CI) (T1 Only). Set when the receiver detects the AIS-CI pattern as defined in ANSI T1.403. Bit 6: Receive Signaling All-Ones Event (RSAO) (E1 Only). Set when the contents of time slot 16 contains fewer than three 0s over 16 consecutive frames.
  • Page 222 Register Name: TR.IMR4 Register Description: Interrupt Mask Register 4 Register Address: Bit # Name RAIS-CI RSAO Default Bit 7: Receive AIS-CI Event (RAIS-CI) 0 = interrupt masked 1 = interrupt enabled Bit 6: Receive Signaling All-Ones Event (RSAO) 0 = interrupt masked 1 = interrupt enabled Bit 5: Receive Signaling All-Zeros Event (RSAZ) 0 = interrupt masked...
  • Page 223 Register Name: TR.SR5 Register Description: Status Register 5 Register Address: Bit # Name — — Default Bit 5: Transmit Elastic Store Full Event (TESF). Set when the transmit elastic store buffer fills and a frame is deleted. Bit 4: Transmit Elastic Store Empty Event (TESEM). Set when the transmit elastic store buffer empties and a frame is repeated.
  • Page 224 Register Name: TR.IMR5 Register Description: Interrupt Mask Register 5 Register Address: Bit # Name — — Default Bit 5: Transmit Elastic Store Full Event (TESF) 0 = interrupt masked 1 = interrupt enabled Bit 4: Transmit Elastic Store Empty Event (TESEM) 0 = interrupt masked 1 = interrupt enabled Bit 3: Transmit Elastic Store Slip-Occurrence Event (TSLIP)
  • Page 225 Register Name: TR.SR6, TR.SR7 Register Description: HDLC #1 Status Register 6 HDLC #2 Status Register 7 Register Address: 20h, 22h Bit # Name — TMEND Default Bit 6: Transmit Message-End Event (TMEND). Set when the transmit HDLC controller has finished sending a message.
  • Page 226 Register Name: TR.IMR6, TR.IMR7 Register Description: HDLC # 1 Interrupt Mask Register 6 HDLC # 2 Interrupt Mask Register 7 Register Address: 21h, 23h Bit # Name — TMEND Default Bit 6: Transmit Message-End Event (TMEND) 0 = interrupt masked 1 = interrupt enabled Bit 5: Receive Packet-End Event (RPE) 0 = interrupt masked...
  • Page 227 Register Name: TR.INFO5, TR.INFO6 Register Description: HDLC #1 Information Register HDLC #2 Information Register Register Address: 2Eh, 2Fh Bit # Name — — Default Bit 5: Transmit FIFO Empty (TEMPTY). A real-time bit that is set high when the FIFO is empty. Bit 4: Transmit FIFO Full (TFULL).
  • Page 228 Register Name: TR.SR8 Register Description: Status Register 8 Register Address: Bit # Name — — Default Bit 5: BOC Clear Event (BOCC). Set when 30 FDL bits occur without an abort sequence. Bit 4: RFDL Abort Detect Event (RFDLAD). Set when eight consecutive 1s are received on the FDL. Bit 3: RFDL Register Full Event (RFDLF).
  • Page 229 Register Name: TR.SR9 Register Description: Status Register 9 Register Address: Bit # Name — BBED Default Bit 6: BERT Bit-Error Detected (BED) Event (BBED). A latched bit that is set when a bit error is detected. The receive BERT must be in synchronization for it to detect bit errors. Cleared when read. Bit 5: BERT Bit-Counter Overflow Event (BBCO).
  • Page 230 Register Name: TR.IMR9 Register Description: Interrupt Mask Register 9 Register Address: Bit # Name — BBED Default Bit 6: Bit-Error Detected Event (BBED) 0 = interrupt masked 1 = interrupt enabled Bit 5: BERT Bit-Counter Overflow Event (BBCO) 0 = interrupt masked 1 = interrupt enabled Bit 4: BERT Error-Counter Overflow Event (BECO) 0 = interrupt masked...
  • Page 231 Register Name: TR.PCPR Register Description: Per-Channel Pointer Register Register Address: Bit # Name RSAOICS RSRCS Default Bit 7: Receive Signaling All-Ones Insertion Channel Select (RSAOICS) Bit 6: Receive Signaling Reinsertion Channel Select (RSRCS) Bit 5: Receive Fractional Channel Select (RFCS) Bit 4: Bert Receive Channel Select (BRCS) Bit 3: Transmit Hardware Signaling Channel Select (THSCS) Bit 2: Payload Error Insert Channel Select (PEICS)
  • Page 232 Register Name: TR.PCDR1 Register Description: Per-Channel Data Register 1 Register Address: Bit # Name — — Default Register Name: TR.PCDR2 Register Description: Per-Channel Data Register 2 Register Address: Bit # Name — — Default CH16 CH15 Register Name: TR.PCDR3 Register Description: Per-Channel Data Register 3 Register Address: Bit #...
  • Page 233 Register Name: TR.INFO7 Register Description: Information Register 7 (Real-Time, Non-Latched Register) Register Address: Bit # Name CSC5 CSC4 Default Bits 3 – 7: CRC4 Sync Counter Bits (CSC0, CSC2 to CSC4). The CRC4 sync counter increments each time the 8ms CRC4 multiframe search times out. The counter is cleared when the framer has successfully obtained synchronization at the CRC4 level.
  • Page 234 Register Name: TR.E1RCR1 Register Description: E1 Receive Control Register 1 Register Address: Bit # Name RSERC RSIGM Default Bit 7: RSERO Control (RSERC) 0 = allow RSERO to output data as received under all conditions 1 = force RSERO to 1 under loss-of-frame alignment conditions Bit 6: Receive Signaling Mode Select (RSIGM) 0 = CAS signaling mode 1 = CCS signaling mode...
  • Page 235 Register Name: TR.E1TCR1 Register Description: E1 Transmit Control Register 1 Register Address: Bit # Name TFPT T16S Default Bit 7: Transmit Time Slot 0 Pass-Through (TFPT) 0 = FAS bits/Sa bits/remote alarm sourced internally from the TR.TAF and TR.TNAF registers 1 = FAS bits/Sa bits/remote alarm sourced from TSERI Bit 6: Transmit Time Slot 16 Data Select (T16S) 0 = time slot 16 determined by the TR.SSIEx registers and the THSCS function in the TR.PCPR register...
  • Page 236 Register Name: TR.E1TCR2 Register Description: E1 Transmit Control Register 2 Register Address: Bit # Name Default Bit 2: Automatic E-Bit Enable (AEBE) 0 = E-bits not automatically set in the transmit direction 1 = E-bits automatically set in the transmit direction Bit 1: Automatic AIS Generation (AAIS) 0 = disabled 1 = enabled...
  • Page 237 CH14 CH24 CH23 CH22 CH30 Setting any of the CH1–CH30 bits in the TR.RSCSE1– TR.RSCSE4 registers causes an interrupt when that channel’s signaling data changes state. DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver CH13 CH12 CH11 CH21 CH20 CH19 CH29...
  • Page 238 Register Name: TR.SIGCR Register Description: Signaling Control Register Register Address: Bit # Name GRSRE — Default Bit 7: Global Receive Signaling Reinsertion Enable (GRSRE). This bit allows the user to reinsert all signaling channels without programming all channels through the per-channel function. 0 = do not reinsert all signaling 1 = reinsert all signaling Bit 4: Receive Freeze Enable (RFE).
  • Page 239 Register Name: TR.ERCNT Register Description: Error-Counter Configuration Register Register Address: Bit # Name — MECU Default Bit 6: Manual Error-Counter Update (MECU). When enabled by TR.ERCNT.4, the changing of this bit from a 0 to a 1 allows the next clock cycle to load the error-counter registers with the latest counts and reset the counters. The user must wait a minimum of 1.5 RCLKO clock periods before reading the error count registers to allow for proper update.
  • Page 240 Register Name: TR.LCVCR1 Register Description: Line-Code Violation Count Register 1 Register Address: Bit # Name LCVC15 LCVC14 Default Bits 0 – 7: Line-Code Violation Counter Bits 8 to 15 (LCVC8 to LCVC15). LCVC15 is the MSB of the 16-bit code violation count. Register Name: TR.LCVCR2 Register Description:...
  • Page 241 Register Name: TR.FOSCR1 Register Description: Frames Out-of-Sync Count Register 1 Register Address: Bit # Name FOS15 FOS14 Default Bits 0 – 7: Frames Out-of-Sync Counter Bits 8 to 15 (FOS8 to FOS15). FOS15 is the MSB of the 16-bit frames out-of-sync count.
  • Page 242 Register Name: TR.LBCR Register Description: Loopback Control Register Register Address: Bit # Name — — Default Bit 4: Line Interface Unit Mux Control (LIUC). This is a software version of the LIUC pin. When the LIUC pin is connected high, the LIUC bit has control. When the LIUC pin is connected low, the framer and LIU are separated and the LIUC bit has no effect.
  • Page 243 Register Name: TR.PCLR1 Register Description: Per-Channel Loopback Enable Register 1 Register Address: Bit # Name Default Bits 0 – 7: Per-Channel Loopback Enable for Channels 1 to 8 (CH1 to CH8) 0 = loopback disabled 1 = enable loopback; source data from the corresponding receive channel Register Name: TR.PCLR2 Register Description:...
  • Page 244 Register Name: TR.ESCR Register Description: Elastic Store Control Register Register Address: Bit # Name TESALGN TESR Default Bit 7: Transmit Elastic Store Align (TESALGN). Setting this bit from a 0 to a 1 forces the transmit elastic store’s write/read pointers to a minimum separation of half a frame. No action is taken if the pointer separation is already greater or equal to half a frame.
  • Page 245 CH20-B CH20-C CH22-A CH22-B CH22-C CH24-A CH24-B CH24-C CH26-A CH26-B CH26-C CH28-A CH28-B CH28-C CH30-A CH30-B CH30-C DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver CH2-D CH1-A CH1-B CH4-D CH3-A CH3-B CH6-D CH5-A CH5-B CH8-D CH7-A CH7-B CH10-D CH9-A CH9-B CH12-D...
  • Page 246 Register Name: TR.TS1 to TR.TS16 Register Description: Transmit Signaling Registers (E1 Mode, CCS Format) Register Address: 50h to 5Fh (MSB) DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 246 of 344 (LSB) TS10 TS11 TS12 TS13 TS14 TS15 TS16...
  • Page 247 CH14-B CH14-C CH16-A CH16-B CH16-C CH18-A CH18-B CH18-C CH20-A CH20-B CH20-C CH22-A CH22-B CH22-C CH24-A CH24-B CH24-C DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver CH2-D CH1-A CH1-B CH4-D CH3-A CH3-B CH6-D CH5-A CH5-B CH8-D CH7-A CH7-B CH10-D CH9-A CH9-B CH12-D...
  • Page 248 CH22-A CH22-B CH22-A CH24-A CH24-B CH24-A Note: In D4 format, TR.TS1– TR.TS12 contain signaling data for two frames. Bold type indicates data for second frame. DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver CH1-A CH1-B CH2-B CH3-A CH3-B CH4-B CH5-A CH5-B...
  • Page 249 CH22-A CH22-B CH22-A CH24-A CH24-B CH24-A Note: In D4 format, TR.TS1– TR.TS12 contain signaling data for two frames. Bold type indicates data for second frame. DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver CH2-D CH1-A CH1-B CH4-D CH3-A CH3-B CH6-D CH5-A...
  • Page 250 CH30-A CH30-B CH30-C Register Name: TR.RS1 to TR.RS16 Register Description: Receive Signaling Registers (E1 Mode, CCS Format) Register Address: 60h to 6Fh (MSB) DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver CH2-D CH1-A CH1-B CH4-D CH3-A CH3-B CH6-D CH5-A CH5-B CH8-D...
  • Page 251 TCSS0 The TCLKT pin is always the source of transmit clock. Switch to the clock present at RCLKO when the signal at the TCLKT pin fails to transition after 1 channel time. Use the scaled signal present at MCLK as the transmit clock. The TCLKT pin is ignored.
  • Page 252 Register Name: TR.CCR2 Register Description: Common Control Register 2 Register Address: Bit # Name — — Default Bits 1 – 2: Backplane Clock Selects (BPCS0, BPCS1) BPCS1 BPCS0 BPCLK Frequency (MHz) Bit 0: Backplane Clock Enable (BPEN) 0 = disable BPCLK pin (pin held at logic 0) 1 = enable BPCLK pin Register Name: TR.CCR3...
  • Page 253 Register Name: TR.CCR4 Register Description: Common Control Register 4 Register Address: Bit # Name RLT3 RLT2 Default Bits 4 – 7: Receive Level Threshold Bits (RLT0 to RLT3) RLT3 RLT2 RLT1 Register Name: TR.TDS0SEL Register Description: Transmit Channel Monitor Select Register Address: Bit # Name...
  • Page 254 Register Name: TR.TDS0M Register Description: Transmit DS0 Monitor Register Register Address: Bit # Name Default Bits 0 – 7: Transmit DS0 Channel Bits (B1 to B8). Transmit channel data that has been selected by the transmit channel monitor select register. B8 is the LSB of the DS0 channel (last bit to be transmitted). Register Name: TR.RDS0SEL Register Description:...
  • Page 255 Register Name: TR.LIC1 Register Description: Line Interface Control 1 Register Address: Bit # Name Default Bits 5 – 7: Line Build-Out Select (L0 to L2). When using the internal termination, the user needs only to select 000 for 75Ω operation or 001 for 120Ω operation below. This selects the proper voltage levels for 75Ω or 120Ω operation.
  • Page 256 Register Name: TR.TLBC Register Description: Transmit Line Build-Out Control Register Address: Bit # Name — AGCE Default Bit 6: Automatic Gain Control Enable (AGCE). 0 = use Transmit AGC, TR.TLBC bits 0–5 are “don’t care” 1 = do not use Transmit AGC, TR.TLBC bits 0–5 set nominal level Bits 0–5: Gain Control Bits (GC0–GC5).
  • Page 257 Register Name: TR.LIC2 Register Description: Line Interface Control 2 Register Address: Bit # Name LIRST Default Bit 7: E1/T1 Select (ETS) 0 = T1 mode selected 1 = E1 mode selected Bit 6: Line Interface Reset (LIRST). Setting this bit from a 0 to a 1 initiates an internal reset that resets the clock recovery state machine and recenters the jitter attenuator.
  • Page 258 Register Name: TR.LIC3 Register Description: Line Interface Control 3 Register Address: Bit # Name TCES — Default Bit 6: Transmit-Clock Edge Select (TCES). Selects which TDCLKI edge to sample TPOSI and TNEGI. 0 = sample TPOSI and TNEGI on falling edge of TDCLKI 1 = sample TPOSI and TNEGI on rising edge of TDCLKI Bit 5: Receive-Clock Edge Select (RCES).
  • Page 259 Register Name: TR.LIC4 Register Description: Line Interface Control 4 Register Address: Bit # Name CMIE CMII Default Bit 7: CMI Enable (CMIE) 0 = disable CMI mode 1 = enable CMI mode Bit 6: CMI Invert (CMII) 0 = CMI normal at TTIP and RTIP 1 = invert CMI signal at TTIP and RTIP Bits 4 –...
  • Page 260 Register Name: TR.IAAR Register Description: Idle Array Address Register Register Address: Bit # Name GRIC GTIC Default Bit 7: Global Receive-Idle Code (GRIC). Setting this bit causes all receive channels to be set to the idle code written to the TR.PCICR register. This bit must be set = 0 for read operations. The value in bits IAA0–IAA5 must be a valid transmit channel (01h to 20h for E1 mode;...
  • Page 261 Register Name: TR.TCICE2 Register Description: Transmit-Channel Idle-Code Enable Register 2 Register Address: Bit # Name CH16 CH15 Default Bits 0 – 7: Transmit Channels 9 to 16 Code Insertion Control Bits (CH9 to CH16) 0 = do not insert data from the idle-code array into the transmit data stream 1 = insert data from the idle code-array into the transmit data stream Register Name: TR.TCICE3...
  • Page 262 Register Name: TR.RCICE2 Register Description: Receive-Channel Idle-Code Enable Register 2 Register Address: Bit # Name CH16 CH15 Default Bits 0 – 7: Receive Channels 9 to 16 Code Insertion Control Bits (CH9 to CH16) 0 = do not insert data from the idle-code array into the receive data stream 1 = insert data from the idle-code array into the receive data stream Register Name: TR.RCICE3...
  • Page 263 Register Name: TR.RCBR2 Register Description: Receive Channel Blocking Register 2 Register Address: Bit # Name CH16 CH15 Default Bits 0 – 7: Receive Channels 9 to 16 Channel Blocking Control Bits (CH9 to CH16) 0 = force the RCHBLK pin to remain low during this channel time 1 = force the RCHBLK pin high during this channel time Register Name: TR.RCBR3...
  • Page 264 Register Name: TR.TCBR1 Register Description: Transmit Channel Blocking Register 1 Register Address: Bit # Name Default Bits 0 – 7: Transmit Channels 1 to 8 Channel Blocking Control Bits (CH1 to CH8) 0 = force the TCHBLK pin to remain low during this channel time 1 = force the TCHBLK pin high during this channel time Register Name: TR.TCBR2...
  • Page 265 Register Name: TR.H1TC, TR.H2TC Register Description: HDLC #1 Transmit Control HDLC #2 Transmit Control Register Address: 90h, A0h Bit # Name NOFS TEOML Default Bit 7: Number of Flags Select (NOFS) 0 = send one flag between consecutive messages 1 = send two flags between consecutive messages Bit 6: Transmit End of Message and Loop (TEOML).
  • Page 266 Register Name: TR.H1FC, TR.H2FC Register Description: HDLC # 1 FIFO Control HDLC # 2 FIFO Control Register Address: 91h, A1h Bit # Name — — Default Bits 3 – 5: Transmit FIFO Low-Watermark Select (TFLWM0 to TFLWM2) TFLWM2 TFLWM1 TFLWM0 Bits 0 –...
  • Page 267 Register Name: TR.H1RCS1, TR.H1RCS2, TR.H1RCS3, TR.H1RCS4 TR.H2RCS1, TR.H2RCS2, TR.H2RCS3, TR.H2RCS4 Register Description: HDLC # 1 Receive Channel Select HDLC # 2 Receive Channel Select Register Address: 92h, 93h, 94h, 95h A2h, A3h, A4h, A5h Bit # Name RHCS7 RHCS6 Default Bit 7: Receive HDLC Channel Select Bit 7 (RHCS7).
  • Page 268 Register Name: TR.H1RTSBS, TR.H2RTSBS Register Description: HDLC # 1 Receive Time Slot Bits/Sa Bits Select HDLC # 2 Receive Time Slot Bits/Sa Bits Select Register Address: 96h, A6h Bit # Name RCB8SE RCB7SE Default Bit 7: Receive Channel Bit 8 Suppress Enable (RCB8SE). MSB of the channel. Set to 1 to stop this bit from being used.
  • Page 269 Register Name: TR.H1TCS1, TR.H1TCS2, TR.H1TCS3, TR.H1TCS4 TR.H2TCS1, TR.H2TCS2, TR.H2TCS3, TR.H2TCS4 Register Description: HDLC # 1 Transmit Channel Select HDLC # 2 Transmit Channel Select Register Address: 97h, 98h, 99h, 9Ah A7h, A8h, A9h, AAh Bit # Name THCS7 THCS6 Default Bit 7: Transmit HDLC Channel Select Bit 7 (THCS7).
  • Page 270 Register Name: TR.H1TTSBS, TR.H2TTSBS Register Description: HDLC # 1 Transmit Time Slot Bits/Sa Bits Select HDLC # 2 Transmit Time Slot Bits/Sa Bits Select Register Address: 9Bh, ABh Bit # Name TCB8SE TCB7SE Default Bit 7: Transmit Channel Bit 8 Suppress Enable (TCB1SE). MSB of the channel. Set to 1 to stop this bit from being used.
  • Page 271 Register Name: TR.H1TF, TR.H2TF Register Description: HDLC # 1 Transmit FIFO HDLC # 2 Transmit FIFO Register Address: 9Dh, ADh Bit # Name THD7 THD6 Default Bit 7: Transmit HDLC Data Bit 7 (THD7). MSB of an HDLC packet data byte. Bit 6: Transmit HDLC Data Bit 6 (THD6) Bit 5: Transmit HDLC Data Bit 5 (THD5) Bit 4: Transmit HDLC Data Bit 4 (THD4)
  • Page 272 Register Name: TR.H1TFBA, TR.H2TFBA Register Description: HDLC # 1 Transmit FIFO Buffer Available HDLC # 2 Transmit FIFO Buffer Available Register Address: 9Fh, Afh Bit # Name TFBA7 TFBA6 Default Bits 0 – 7: Transmit FIFO Bytes Available (TFBAO to TFBA7). TFBA0 is the LSB. Register Name: TR.IBCC Register Description:...
  • Page 273 Register Name: TR.TCD1 Register Description: Transmit Code-Definition Register 1 Register Address: Bit # Name Default Bit 7: Transmit Code-Definition Bit 7 (C7). First bit of the repeating pattern. Bits 3 – 6: Transmit Code-Definition Bits 3–6 (C3–C6) Bit 2: Transmit Code-Definition Bit 2 (C2). A don’t care if a 5-bit length is selected. Bit 1: Transmit Code-Definition Bit 1 (C1).
  • Page 274 Register Name: TR.RUPCD1 Register Description: Receive Up-Code Definition Register 1 Register Address: Bit # Name Default Note: Writing this register resets the detector’s integration period. Bit 7: Receive Up-Code Definition Bit 7 (C7). First bit of the repeating pattern. Bit 6: Receive Up-Code Definition Bit 6 (C6). A don’t care if a 1-bit length is selected. Bit 5: Receive Up-Code Definition Bit 5 (C5).
  • Page 275 Register Name: TR.RDNCD1 Register Description: Receive Down-Code Definition Register 1 Register Address: Bit # Name Default Note: Writing this register resets the detector’s integration period. Bit 7: Receive Down-Code Definition Bit 7 (C7). First bit of the repeating pattern. Bit 6: Receive Down-Code Definition Bit 6 (C6). A don’t care if a 1-bit length is selected. Bit 5: Receive Down-Code Definition Bit 5 (C5).
  • Page 276 Register Name: TR.RSCC Register Description: In-Band Receive Spare Control Register Register Address: Bit # Name — — Default Bits 3 – 7: Unused, must be set to 0 for proper operation Bits 0 – 2: Receive Spare Code Length Definition Bits (RSC0 to RSC2) RSC2 RSC1 RSC0...
  • Page 277 Register Name: TR.RSCD1 Register Description: Receive Spare-Code Definition Register 1 Register Address: Bit # Name Default Note: Writing this register resets the detector’s integration period. Bit 7: Receive Spare-Code Definition Bit 7 (C7). First bit of the repeating pattern. Bit 6: Receive Spare-Code Definition Bit 6 (C6). A don’t care if a 1-bit length is selected. Bit 5: Receive Spare-Code Definition Bit 5 (C5).
  • Page 278 Register Name: TR.RFDL (TR.BOCC.4 = 1) Register Description: Receive FDL Register Register Address: Bit # Name — — Default RFDL register bit definitions when TR.BOCC.4 = 1: Bit 5: BOC Bit 5 (RBOC5) Bit 4: BOC Bit 4 (RBOC4) Bit 3: BOC Bit 3 (RBOC3) Bit 2: BOC Bit 2 (RBOC2) Bit 1: BOC Bit 1 (RBOC1) Bit 0: BOC Bit 0 (RBOC0)
  • Page 279 Register Name: TR.TFDL Register Description: Transmit FDL Register Register Address: Bit # Name TFDL7 TFDL6 Default Note: Also used to insert Fs framing pattern in D4 framing mode. The transmit FDL register (TR.TFDL) contains the FDL information that is to be inserted on a byte basis into the outgoing T1 data stream.
  • Page 280 Register Name: TR.RAF Register Description: Receive Align Frame Register Register Address: Bit # Name Default Bit 7: International Bit (Si) Bit 6: Frame Alignment Signal Bit (0) Bit 5: Frame Alignment Signal Bit (0) Bit 4: Frame Alignment Signal Bit (1) Bit 3: Frame Alignment Signal Bit (1) Bit 2: Frame Alignment Signal Bit (0) Bit 1: Frame Alignment Signal Bit (1)
  • Page 281 Register Name: TR.RSiAF Register Description: Received Si Bits of the Align Frame Register Address: Bit # Name SiF0 SiF2 Default Bit 7: Si Bit of Frame 0 (SiF0) Bit 6: Si Bit of Frame 2 (SiF2) Bit 5: Si Bit of Frame 4 (SiF4) Bit 4: Si Bit of Frame 6 (SiF6) Bit 3: Si Bit of Frame 8 (SiF8) Bit 2: Si Bit of Frame 10 (SiF10)
  • Page 282 Register Name: TR.RRA Register Description: Received Remote Alarm Register Address: Bit # Name RRAF1 RRAF3 Default Bit 7: Remote Alarm Bit of Frame 1 (RRAF1) Bit 6: Remote Alarm Bit of Frame 3 (RRAF3) Bit 5: Remote Alarm Bit of Frame 5 (RRAF5) Bit 4: Remote Alarm Bit of Frame 7 (RRAF7) Bit 3: Remote Alarm Bit of Frame 9 (RRAF9) Bit 2: Remote Alarm Bit of Frame 11 (RRAF11)
  • Page 283 Register Name: TR.RSa5 Register Description: Received Sa5 Bits Register Address: Bit # Name RSa5F1 RSa5F3 Default Bit 7: Sa5 Bit of Frame 1 (RSa5F1) Bit 6: Sa5 Bit of Frame 3 (RSa5F3) Bit 5: Sa5 Bit of Frame 5 (RSa5F5) Bit 4: Sa5 Bit of Frame 7 (RSa5F7) Bit 3: Sa5 Bit of Frame 9 (RSa5F9) Bit 2: Sa5 Bit of Frame 11 (RSa5F11)
  • Page 284 Register Name: TR.RSa7 Register Description: Received Sa7 Bits Register Address: Bit # Name RSa7F1 Rsa7F3 Default Bit 7: Sa7 Bit of Frame 1(RSa4F1) Bit 6: Sa7 Bit of Frame 3 (RSa7F3) Bit 5: Sa7 Bit of Frame 5 (RSa7F5) Bit 4: Sa7 Bit of Frame 7 (RSa7F7) Bit 3: Sa7 Bit of Frame 9 (RSa7F9) Bit 2: Sa7 Bit of Frame 11 (RSa7F11) Bit 1: Sa7 Bit of Frame 13 (RSa7F13)
  • Page 285 Register Name: TR.TAF Register Description: Transmit Align Frame Register Register Address: Bit # Name Default Bit 7: International Bit (Si) Bit 6: Frame Alignment Signal Bit (0) Bit 5: Frame Alignment Signal Bit (0) Bit 4: Frame Alignment Signal Bit (1) Bit 3: Frame Alignment Signal Bit (1) Bit 2: Frame Alignment Signal Bit (0) Bit 1: Frame Alignment Signal Bit (1)
  • Page 286 Register Name: TR.TSiAF Register Description: Transmit Si Bits of the Align Frame Register Address: Bit # Name TSiF0 TSiF2 Default Bit 7: Si Bit of Frame 0 (TSiF0) Bit 6: Si Bit of Frame 2 (TSiF2) Bit 5: Si Bit of Frame 4 (TSiF4) Bit 4: Si Bit of Frame 6 (TSiF6) Bit 3: Si Bit of Frame 8 (TSiF8) Bit 2: Si Bit of Frame 10 (TSiF10)
  • Page 287 Register Name: TR.TRA Register Description: Transmit Remote Alarm Register Address: Bit # Name TRAF1 TRAF3 Default Bit 7: Remote Alarm Bit of Frame 1 (TRAF1) Bit 6: Remote Alarm Bit of Frame 3 (TRAF3) Bit 5: Remote Alarm Bit of Frame 5 (TRAF5) Bit 4: Remote Alarm Bit of Frame 7 (TRAF7) Bit 3: Remote Alarm Bit of Frame 9 (TRAF9) Bit 2: Remote Alarm Bit of Frame 11 (TRAF11)
  • Page 288 Register Name: TR.TSa5 Register Description: Transmitted Sa5 Bits Register Address: Bit # Name TSa5F1 TSa5F3 Default Bit 7: Sa5 Bit of Frame 1 (TSa5F1) Bit 6: Sa5 Bit of Frame 3 (TSa5F3) Bit 5: Sa5 Bit of Frame 5 (TSa5F5) Bit 4: Sa5 Bit of Frame 7 (TSa5F7) Bit 3: Sa5 Bit of Frame 9 (TSa5F9) Bit 2: Sa5 Bit of Frame 11 (TSa5F11)
  • Page 289 Register Name: TR.TSa7 Register Description: Transmit Sa7 Bits Register Address: Bit # Name TSa7F1 TSa7F3 Default Bit 7: Sa7 Bit of Frame 1 (TSa4F1) Bit 6: Sa7 Bit of Frame 3 (TSa7F3) Bit 5: Sa7 Bit of Frame 5 (TSa7F5) Bit 4: Sa7 Bit of Frame 7 (TSa7F7) Bit 3: Sa7 Bit of Frame 9 (TSa7F9) Bit 2: Sa7 Bit of Frame 11 (TSa7F11)
  • Page 290 Register Name: TR.TSACR Register Description: Transmit Sa Bit Control Register Register Address: Bit # Name SiAF SiNAF Default Bit 7: International Bit in Align Frame Insertion Control Bit (SiAF) 0 = do not insert data from the TR.TSiAF register into the transmit data stream 1 = insert data from the TR.TSiAF register into the transmit data stream Bit 6: International Bit in Nonalign Frame Insertion Control Bit (SiNAF) 0 = do not insert data from the TR.TSiNAF register into the transmit data stream...
  • Page 291 Register Name: TR.BRP1 Register Description: BERT Repetitive Pattern Set Register 1 Register Address: Bit # Name RPAT7 RPAT6 Default Bits 0 – 7: BERT Repetitive Pattern Set Bits 0 to 7 (RPAT0 to RPAT7) RPAT0 is the LSB of the 32-bit repetitive pattern set.
  • Page 292 Register Name: TR.BC1 Register Description: BERT Control Register 1 Register Address: Bit # Name TINV Default Bit 7: Transmit Pattern Load (TC). A low-to-high transition loads the pattern generator with the pattern that is to be generated. This bit should be toggled from low to high whenever the host wishes to load a new pattern. Must be cleared and set again for subsequent loads.
  • Page 293 Register Name: TR.BC2 Register Description: BERT Control Register 2 Register Address: Bit # Name EIB2 EIB1 Default Bits 5 – 7: Error Insert Bits 0 to 2 (EIB0 to EIB2). Automatically inserts bit errors at the prescribed rate into the generated data pattern.
  • Page 294 Register Name: TR.BBC1 Register Description: BERT Bit Count Register 1 Register Address: Bit # Name BBC7 BBC6 Default Bits 0 – 7: BERT Bit Counter Bits 0 to 7 (BBC0 to BBC7). BBC0 is the LSB of the 32-bit counter. Register Name: TR.BBC2 Register Description:...
  • Page 295 Register Name: TR.BEC1 Register Description: BERT Error-Count Register 1 Register Address: Bit # Name Default Bits 0 – 7: Error Counter Bits 0 to 7 (EC0 to EC7). EC0 is the LSB of the 24-bit counter. Register Name: TR.BEC2 Register Description: BERT Error-Count Register 2 Register Address: Bit #...
  • Page 296 Register Name: TR.BIC Register Description: BERT Interface Control Register Register Address: Bit # Name — RFUS Default Bit 6: Receive Framed/Unframed Select (RFUS) 0 = BERT is not sent data from the F-bit position (framed) 1 = BERT is sent data from the F-bit position (unframed) Bit 4: Transmit Byte-Align Toggle (TBAT).
  • Page 297 Register Name: TR.ERC Register Description: Error-Rate Control Register Register Address: Bit # Name WNOE — Default Bit 7: Write NOE Registers (WNOE). If the host wishes to update to the TR.NOEx registers, this bit must be toggled from a 0 to a 1 after the host has already loaded the prescribed error count into the TR.NOEx registers. The toggling of this bit causes the error count loaded into the TR.NOEx registers to be loaded into the error- insertion circuitry on the next clock cycle.
  • Page 298 Register Name: TR.NOE1 Register Description: Number-of-Errors 1 Register Address: Bit # Name Default Bits 0 – 7: Number-of-Errors Counter Bits 0 to 7 (C0 to C7). Bit C0 is the LSB of the 10-bit counter. Register Name: TR.NOE2 Register Description: Number-of-Errors 2 Register Address: Bit #...

  • Page 299: Number-Of-Errors Left Register

    11.7.1 Number-of-Errors Left Register The host can read the TR.NOELx registers at any time to determine how many errors are left to be inserted. Register Name: TR.NOEL1 Register Description: Number-of-Errors Left 1 Register Address: Bit # Name Default Bits 0 – 7: Number-of-Errors Left Counter Bits 0 to 7 (C0 to C7). Bit C0 is the LSB of the 10-bit counter. Register Name: TR.NOEL2 Register Description:...

  • Page 300: Functional Timing

    TSERO data. The “shaded bits” are not clocked by the DS33R11. The TDEN must occur one bit before the effected bit in the TSERO stream. Note that polarity of the TDEN is selectable through LI.TSLCR.

  • Page 301: Mii And Rmii Interfaces

    8 bits. For the serial receiver interface, RBSYNC is used to provide byte boundary indication to the DS33R11 when X.86 (LAPS) mode is used. The...

  • Page 302: Figure 12-6. Mii Transmit Half Duplex With A Collision Functional Timing

    In Half-Duplex (DTE) Mode, the DS33R11 supports CRS and COL signals. CRS is active when the PHY detects transmit or receive activity. If there is a collision as indicated by the COL input, the DS33R11 will replace the data nibbles with jam nibbles. After a “random“ time interval, the packet is retransmitted. The MAC will try to send the packet a maximum of 16 times.

  • Page 303: T Ransceiver T1 M Ode F Unctional T Iming

    RMII Receive data on RXD[1:0] is expected to be synchronous with the rising edge of the 50 MHz REF_CLK. The data is only valid if CRS_DV is high. The external PHY asynchronously drives CRS_DV low during carrier loss. Figure 12-9. RMII Receive Interface Functional Timing REFCLK RXD[1:0] CRS_DV...

  • Page 304: Figure 12-12. Receive-Side Boundary Timing (Elastic Store Disabled)

    Figure 12-12. Receive-Side Boundary Timing (Elastic Store Disabled) RCLKO CHANNEL 23 RSERO RSYNC RFSYNC CHANNEL 23 RSIG RCHCLK RCHBLK 1 NOTE 1: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24. Figure 12-13. Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled) RSYSCLK CHANNEL 23 RSERO RSYNC RMSYNC...

  • Page 305: Figure 12-14. Receive-Side 2.048Mhz Boundary Timing (Elastic Store Enabled)

    Figure 12-14. Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled) RSYSCLK CHANNEL 31 RSER O RSYNC RMSYNC RSYNC RSIG RCHCLK RCHBLK NOTE 1: RSERO DATA IN CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 ARE FORCED TO 1. NOTE 2: RSYNC IS IN THE OUTPUT MODE (TR.IOCR1.4 = 0). NOTE 3: RSYNC IS IN THE INPUT MODE (TR.IOCR1.4 = 1).

  • Page 306: Figure 12-16. Transmit-Side Esf Timing

    Figure 12-16. Transmit-Side ESF Timing FRAME# TSYNC TSSYNC TSYNC TSYNC NOTE 1: TSYNC IN FRAME MODE (TR.IOCR1.2 = 0) AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (TR.IOCR1.3 = 0). NOTE 2: TSYNC IN FRAME MODE (TR.IOCR1.2 = 0) AND DOUBLE-WIDE FRAME SYNC IS ENABLED (TR.IOCR1.3 = 1). NOTE 3: TSYNC IN MULTIFRAME MODE (TR.IOCR1.2 = 1).

  • Page 307: Figure 12-18. Transmit-Side 1.544Mhz Boundary Timing (Elastic Store Enabled)

    Figure 12-18. Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled) TSYSCLK CHANNEL 23 TSERI TSSYNC CHANNEL 23 TSIG TCHCLK TCHBLK NOTE 1: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24 (IF THE TPCSI BIT IS SET, THEN THE SIGNALING DATA AT TSIG IS IGNORED DURING CHANNEL 24).

  • Page 308: Figure 12-20. Receive-Side Timing

    12.4 E1 Mode Figure 12-20. Receive-Side Timing FRAME# RFSYNC RSYNC RSYNC NOTE 1: RSYNC IN FRAME MODE (TR.IOCR1.5 = 0). NOTE 2: RSYNC IN MULTIFRAME MODE (TR.IOCR1.5 = 1). NOTE 3: THIS DIAGRAM ASSUMES THE CAS MF BEGINS IN THE RAF FRAME. Figure 12-21.

  • Page 309: Figure 12-22. Receive-Side Boundary Timing, Rsysclk = 1.544Mhz (E-Store Enabled)

    Figure 12-22. Receive-Side Boundary Timing, RSYSCLK = 1.544MHz (E-Store Enabled) RSYSCLK CHANNEL 23/31 RSERO RSYNC RMSYNC RSYNC RCHCLK RCHBLK NOTE 1: DATA FROM THE E1 CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS DROPPED (CHANNEL 2 FROM THE E1 LINK IS MAPPED TO CHANNEL 1 OF THE T1 LINK, ETC.) AND THE F-BIT POSITION IS ADDED (FORCED TO ON 1).

  • Page 310: Figure 12-24. G.802 Timing, E1 Mode Only

    Figure 12-24. G.802 Timing, E1 Mode Only 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TS # RSYNC TSYNC...

  • Page 311: Figure 12-26. Transmit-Side Boundary Timing (Elastic Store Disabled)

    Figure 12-26. Transmit-Side Boundary Timing (Elastic Store Disabled) TCLKT TSERI TSYNC TSYNC TSIG TCHCLK TCHBLK NOTE 1: TSYNC IS IN THE OUTPUT MODE (TR.IOCR1.1 = 1). NOTE 2: TSYNC IS IN THE INPUT MODE (TR.IOCR1.1 = 0). NOTE 3: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 2. NOTE 5: THE SIGNALING DATA AT TSIG DURING CHANNEL 1 IS NORMALLY OVERWRITTEN IN THE TRANSMIT FORMATTER WITH THE CAS MF ALIGNMENT NIBBLE (0000).

  • Page 312: Figure 12-28. Transmit-Side Boundary Timing, Tsysclk = 2.048Mhz (Elastic Store Enabled)

    Figure 12-28. Transmit-Side Boundary Timing, TSYSCLK = 2.048MHz (Elastic Store Enabled) TSYSCLK CHANNEL 31 TSERI TSSYNC CHANNEL 31 TSIG TCHCLK TCHBLK NOTE 1: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 31. CHANNEL 32 LSB MSB CHANNEL 32 312 of 344 CHANNEL 1 CHANNEL 1...

  • Page 313: Operating Parameters

    13 OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Lead with Respect to V Supply Voltage (VDD3.3) Range with Respect to V Supply Voltage (VDD1.8) with Respect to V Ambient Operating Temperature Range………………………………...………………………………...-40°C to +85°C Junction Operating Temperature Range…………………………………...………………………………-40°C to +125°C Storage Temperature Range……………………………………………………………………………..…-55°C to +125°C Soldering Temperature………………………………………………………...See IPC/JEDEC J-STD-020 Specification These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operation...

  • Page 314: Table 13-3. Thermal Characteristics

    13.1 Thermal Characteristics Table 13-3. Thermal Characteristics PARAMETER Ambient Temperature (Note 1) Junction Temperature (Note 2) Theta-JA ( θ ) in Still Air for 256-Pin 27mm BGA (Notes 2, 3) Note 1: The package is mounted on a four-layer JEDEC standard test board. Note 2: Value guaranteed by design (GBD).

  • Page 315: Figure 13-1. Transmit Mii Interface Timing

    13.2 MII Interface Table 13-5. Transmit MII Interface (Note 1, Figure 13-1) PARAMETER TX_CLK Period TX_CLK Low Time TX_CLK High Time TX_CLK to TXD, TX_EN Delay Note 1: Timing parameters in this table are guaranteed by design (GBD). Figure 13-1. Transmit MII Interface Timing TX_CLK TXD[3:0] TX_EN...

  • Page 316: Figure 13-2. Receive Mii Interface Timing

    Table 13-6. Receive MII Interface (Note 1, Figure 13-2) PARAMETER RX_CLK Period RX_CLK Low Time RX_CLK High Time RXD, RX_DV to RX_CLK Setup Time RX_CLK to RXD, RX_DV Hold Time Note 1: Timing parameters in this table are guaranteed by design (GBD). Figure 13-2.

  • Page 317: Figure 13-3. Transmit Rmii Interface Timing

    13.3 RMII Interface Table 13-7. Transmit RMII Interface (Note 1, Figure 13-3) PARAMETER REF_CLK Frequency REF_CLK Period REF_CLK Low Time REF_CLK High Time REF_CLK to TXD, TX_EN Delay Note 1: Timing parameters in this table are guaranteed by design (GBD). Figure 13-3.

  • Page 318: Figure 13-4. Receive Rmii Interface Timing

    Table 13-8. Receive RMII Interface (Note 1, Figure 13-4) PARAMETER REF_CLK Frequency REF_CLK Period REF_CLK Low Time REF_CLK High Time RXD, CRS_DV to REF_CLK Setup Time REF_CLK to RXD, CRS_DV Hold Time Note 1: Timing parameters in this table are guaranteed by design (GBD). Figure 13-4.

  • Page 319: Figure 13-5. Mdio Interface Timing

    13.4 MDIO Interface Table 13-9. MDIO Interface (Note 1, Figure 13-5) PARAMETER MDC Frequency MDC Period MDC Low Time MDC High Time MDC to MDIO Output Delay MDIO Setup Time MDIO Hold Time Note 1: Timing parameters in this table are guaranteed by design (GBD). Figure 13-5.

  • Page 320: Figure 13-6. Transmit Wan Interface Timing

    13.5 Transmit WAN Interface Table 13-10. Transmit WAN Interface (Note 1, Figure 13-6) PARAMETER TCLKE Frequency TCLKE Period TCLKE Low Time TCLKE High Time TCLKE to TSERO Output Delay TCLKE to TBSYNC Setup Time TBSYNC Hold Time TCLKE to TDEN Output Delay Note 1: Timing parameters in this table are guaranteed by design (GBD).

  • Page 321: Figure 13-7. Receive Wan Interface Timing

    13.6 Receive WAN Interface Table 13-11. Receive WAN Interface (Note 1, Figure 13-7) PARAMETER RCLKI Frequency RCLKI Period RCLKI Low Time RCLKI High Time RSERI Setup Time RDEN Setup Time RBSYNC Setup Time RDEN Setup Time RBSYNC Setup Time RSERI Hold Time RBSYNC Hold Time RDEN Hold Time RBSYNC Hold Time...

  • Page 322: 13.7 Sdram T

    13.7 SDRAM Timing Table 13-12. SDRAM Interface Timing (Note 1, Figure 13-8) PARAMETER SDCLKO Period SDCLKO Duty Cycle SDCLKO to SDATA Valid Write to SDRAM SDCLKO to SDATA Drive On Write to SDRAM SDCLKO to SDATA Invalid Write to SDRAM SDCLKO to SDATA Drive Off Write to SDRAM SDATA to SDCLKO Setup Time...

  • Page 323: Figure 13-8. Sdram Interface Timing

    Figure 13-8. SDRAM Interface Timing SDCLKO (output) SDATA (output) SDATA (input) SRAS, SCAS, SWE, SDCS (output) SDA, SBA (output) SDMASK (output) 323 of 344...

  • Page 324: B Us Ac C Haracteristics

    13.8 Microprocessor Bus AC Characteristics Table 13-13. AC Characteristics—Microprocessor Bus Timing (VDD3.3 = 3.3V ± 5%, VDD1.8 = 1.8V ± 5%, T Figure 13-12) PARAMETER Setup Time for A[12:0] Valid to CS Active Setup Time for CS Active to Either RD or WR Active Delay Time from either RD or DS Active to DATA[7:0] Valid Hold Time from either RD or WR Inactive to CS Inactive...

  • Page 325: Figure 13-9. Intel Bus Read Timing (Modec = 00)

    Figure 13-9. Intel Bus Read Timing (MODEC = 00) ADDR[12:0] DATA[7:0] Figure 13-10. Intel Bus Write Timing (MODEC = 00) ADDR[12:0] DATA[7:0] CS/CST Address Valid Data Valid Address Valid 325 of 344...

  • Page 326: Figure 13-11. Motorola Bus Read Timing (Modec = 01)

    Figure 13-11. Motorola Bus Read Timing (MODEC = 01) ADDR[12:0] DATA[7:0] CS/CST Figure 13-12. Motorola Bus Write Timing (MODEC = 01) ADDR[12:0] DATA[7:0] CS/CST Address Valid Data Valid Address Valid 326 of 344...

  • Page 327: Table 13-14. Ac Characteristics: Receive Side

    13.9 AC Characteristics: Receive-Side Table 13-14. AC Characteristics: Receive Side = 3.3V ± 5%, T = -40°C to +85°C.) (Note 1, PARAMETER RDCLKO Period RDCLKO Pulse Width RDCLKO Pulse Width RDCLKI Period RDCLKI Pulse Width RSYSCLK Period RSYSCLK Pulse Width RSYNC Setup to RSYSCLK Falling RSYNC Pulse Width RPOSI/RNEGI Setup to RDCLKI Falling...

  • Page 328: Figure 13-13. Receive-Side Timing

    Figure 13-13. Receive-Side Timing RCLKO RSERO / RDATA / RSIG RSYNC RFSYNC / RMSYNC RCHCLK RCHBLK NOTE 1: RSYNC IS IN THE OUTPUT MODE. NOTE 2: NO RELATIONSHIP BETWEEN RCHCLK AND RCHBLK AND OTHER SIGNALS IS IMPLIED. t D1 1ST FRAME BIT t D2 t D2 t D2...

  • Page 329: Figure 13-14. Receive-Side Timing, Elastic Store Enabled

    Figure 13-14. Receive-Side Timing, Elastic Store Enabled RSYSCLK t D3 RSERO / RSIG RCHCLK RCHBLK RMSYNC RSYNC RSYNC NOTE 1: RSYNC IS IN THE OUTPUT MODE. NOTE 2: RSYNC IS IN THE INPUT MODE. NOTE 3: F-BIT WHEN MSTRREG.1 = 0, MSB OF TS0 WHEN MSTREG.1 = 1. SEE NOTE 3 t D4 t D4...

  • Page 330: Figure 13-15. Receive Line Interface Timing

    Figure 13-15. Receive Line Interface Timing RDCLKO t DD RPOSO, RNEGO RDCLKI RPOSI, RNEGI t SU t HD 330 of 344 t LP t CP...

  • Page 331: B Ackplane C Lock T Iming

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 13.10 AC Characteristics: Backplane Clock Timing Table 13-15. AC Characteristics: Backplane Clock Synthesis = 3.3V ± 5%, T = -40°C to +85°C.) (Note 1, (Figure 13-16) PARAMETER SYMBOL CONDITIONS UNITS Delay RCLKO to BPCLK Note: Timing parameters in this table are guaranteed by design (GBD).

  • Page 332: Table 13-16. Ac Characteristics: Transmit Side

    13.11 AC Characteristics: Transmit Side Table 13-16. AC Characteristics: Transmit Side = 3.3V ± 5%, T = 0°C to +85°C.) (Note 1, PARAMETER TCLKT Period TCLKT Pulse Width TDCLKI Period TDCLKI Pulse Width TSYSCLK Period TSYSCLK Pulse Width TSYNC or TSSYNC Setup to TCLKT or TSYSCLK Falling TSYNC or TSSYNC Pulse Width TSERI, TSIG, TDATA, TPOSI, TNEGI...

  • Page 333: Figure 13-17. Transmit-Side Timing

    Figure 13-17. Transmit-Side Timing TCLKT TESO TSERI / TSIG / TDATA TCHCLK TCHBLK TSYNC TSYNC TLCLK TLINK NOTE 1: TSYNC IS IN THE OUTPUT MODE (IOCR1.1 = 1). NOTE 2: TSYNC IS IN THE INPUT MODE (IOCR1.1 = 0). NOTE 3: TSERI IS SAMPLED ON THE FALLING EDGE OF TCLKT WHEN THE TRANSMIT-SIDE ELASTIC STORE IS DISABLED. NOTE 4: TCHCLK AND TCHBLK ARE SYNCHRONOUS WITH TCLKT WHEN THE TRANSMIT-SIDE ELASTIC STORE IS DISABLED.

  • Page 334: Figure 13-18. Transmit-Side Timing, Elastic Store Enabled

    Figure 13-18. Transmit-Side Timing, Elastic Store Enabled TSYSCLK TSERI TCHCLK TCHBLK TSSYNC NOTE 1: TSERI IS ONLY SAMPLED ON THE FALLING EDGE OF TSYSCLK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS ENABLED. NOTE 2: TCHCLK AND TCHBLK ARE SYNCHRONOUS WITH TSYSCLK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS ENABLED. Figure 13-19.

  • Page 335: Figure 13-20. Jtag Interface Timing Diagram

    13.12 JTAG Interface Timing Table 13-17. JTAG Interface Timing (VDD3.3 = 3.3V ± 5%,VDD1.8 = 1.8V ± 5%, T PARAMETER JTCLK Clock Period JTCLK Clock High:Low Time (Note 2) JTCLK to JTDI, JTMS Setup Time JTCLK to JTDI, JTMS Hold Time JTCLK to JTDO Delay JTCLK to JTDO HIZ Delay JTRST Width Low Time...

  • Page 336: Jtag Information

    14 JTAG INFORMATION The DS33R11 contains two JTAG ports. Port 1 is for the Ethernet Mapper, and Port 2 is for the T1/E1/J1 Transceiver. Because of this, this device requires special consideration during JTAG test design. For more information on performing JTAG testing using this device, go to www.maxim-ic.com/support.

  • Page 337: Jtag Tap Controller State Machine Description

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 14.1 JTAG TAP Controller State Machine Description This section covers the details on the operation of the Test Access Port (TAP) Controller State Machine. The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK.
  • Page 338 DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Update-DR A falling edge on JTCLK while in the Update-DR state will latch the data from the shift register path of the test registers into the data output latches. This prevents changes at the parallel output due to changes in the shift register.

  • Page 339: Figure 14-2. Tap Controller State Diagram

    Figure 14-2. TAP Controller State Diagram Test Logic Reset Run Test/ Idle 14.2 Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS LOW will shift the data one stage towards the serial output at JTDO.

  • Page 340: Table 14-1. Instruction Codes For Ieee 1149.1 Architecture

    Table 14-1. Instruction Codes for IEEE 1149.1 Architecture INSTRUCTION SAMPLE:PRELOAD BYPASS EXTEST CLAMP HIGHZ IDCODE SAMPLE:PRELOAD This is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The digital I/Os of the device can be sampled at the boundary scan register without interfering with the normal operation of the device by using the Capture-DR state.

  • Page 341: Identification Register

    14.3 JTAG ID Codes Table 14-2. ID Code Structure REVISION DEVICE ID[31:28] Ethernet 0000 Mapper T1/E1/J1 0000 Transceiver 14.4 Test Registers IEEE 1149.1 requires a minimum of two test registers: the bypass register and the boundary scan register. An optional test register has been included with the DS26521 design. This test register is the identification register and is used in conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.

  • Page 342: Figure 14-3. Jtag Functional Timing

    14.5 JTAG Functional Timing This functional timing for the JTAG circuits shows: • The JTAG controller starting from reset state. • Shifting out the first 4 LSB bits of the IDCODE. • Shifting in the BYPASS instruction (111) while shifting out the mandatory X01 pattern. •...

  • Page 343: Package Information

    DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 15 PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a link to the latest package outline information.) 15.1 256-Ball BGA (27mm x 27mm) (56-G6004-001)

  • Page 344: Document Revision History

    M a x i m I n t e g r a t e d P r o d u c t s , 1 2 0 S a n G a b r i e l D r i v e , S u n n y v a l e , C A 9 4 0 8 6 4 0 8 - 7 3 7 - 7 6 0 0 The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.

Table of Contents