Marvell Integrated Controller 88F6281 Hardware Specifications
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Marvell Integrated Controller 88F6281 Hardware Specifications

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88F6281
Integrated Controller

Hardware Specifications

Marvell.
Moving Forward Faster
Doc. No. MV-S104859-U0, Rev. E
December 2, 2008, Preliminary
Document Classification: Proprietary Information

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Summary of Contents for Marvell Integrated Controller 88F6281

  • Page 1: Hardware Specifications

    88F6281 Integrated Controller Hardware Specifications Marvell. Moving Forward Faster Doc. No. MV-S104859-U0, Rev. E December 2, 2008, Preliminary Document Classification: Proprietary Information...

  • Page 2: Document Status

    88F6281 Hardware Specifications Document Conventions Note: Provides related information or information of special importance. Caution: Indicates potential damage to hardware or software, or loss of data. Warning: Indicates a risk of personal injury. Document Status Doc Status: Preliminary For more information, visit our website at: Disclaimer No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell.

  • Page 3: Product Overview

    PRODUCT OVERVIEW ® The Marvell 88F6281 is a high-performance, highly integrated controller. The 88F6281 is based on the Marvell proprietary, ARMv5TE-compliant, high-speed Sheeva Processor Sheeva™ JTAG Interface 16 KB-I, 16 KB-D Up to 1.5 GHz Memory External DDR 800 MHz Security Engine AES/DES/ 3DES...

  • Page 4: Features

    88F6281 Hardware Specifications FEATURES The 88F6281 includes: • High-performance CPU core, running at up to 1.5 GHz, with integrated, four-way, set-associative L1 16-KB I-cache/16-KB D-cache and unified, 256-KB, four-way, set-associative L2 cache • High-bandwidth dual-port DDR2 memory interface (16-bit DDR2 SDRAM @ up to 800 MHz data rate) •...
  • Page 5 • Priority queuing on receive based on Destination Address (DA), VLAN Tag, and IP TOS • Layer 2/3/4 frame encapsulation detection • TCP/IP checksum on receive and transmit • Supports proprietary 200 Mbps Marvell MII (MMII) interface • Supports four modes: Port 0 RGMII, Port 1 RGMII Port 0 RGMII, Port 1 MII/MMII Port 0 MII/MMII, port 1 RGMII...
  • Page 6 88F6281 Hardware Specifications S-specific features • Sample rates of 44.1/48/96 kHz • S input and I S output operate at the same sample rate • 16/24-bit depths • S in and I S out support independent bit depths (16 bit/24 bit) •...
  • Page 7 PCI Express Mini Card Wi-Fi SD Card USB Host A/D – D/A Copyright © 2008 Marvell December 2, 2008, Preliminary SATA Port Multiplier 88F6281 Audio GbE PHY Usage Model Example: VoIP Gateway Document Classification: Proprietary Information Features On Board DDR2 SPI Flash (op.) NAND Flash Doc.

  • Page 8: Table Of Contents

    88F6281 Hardware Specifications Table of Contents Product Overview ... 3 Features... 4 Preface...15 About this Document ...15 Related Documentation...15 Document Conventions ...16 Pin and Signal Descriptions ... 17 Pin Logic ...18 Pin Descriptions ...19 Internal Pull-up and Pull-down Pins ...48 Unused Interface Strapping...
  • Page 9 Electrical Specifications (Preliminary) ... 75 Absolute Maximum Ratings ...75 Recommended Operating Conditions ...77 Thermal Power Dissipation ...79 Current Consumption ...80 DC Electrical Specifications ...81 AC Electrical Specifications ...86 Differential Interface Electrical Characteristics...118 Thermal Data (Preliminary) ...129 Package ...130 Part Order Numbering/Package Marking ...132 11.1 Part Order Numbering ...132 11.2...

  • Page 10: List Of Tables

    88F6281 Hardware Specifications List of Tables Pin and Signal Descriptions ... 17 Table 1: Pin Functions and Assignments Table Key ...19 Table 2: Interface Pin Prefix Codes ...19 Table 3: Power Pin Assignments ...21 Table 4: Miscellaneous Pin Assignments ...23 Table 5: DDR SDRAM Interface Pin Assignments ...24 Table 6:...
  • Page 11 JTAG Interface ... 73 Table 33: Supported JTAG Instructions...73 Table 34: IDCODE Register Map ...74 Electrical Specifications (Preliminary) ... 75 Table 35: Absolute Maximum Ratings ...75 Table 36: Recommended Operating Conditions...77 Table 37: Thermal Power Dissipation ...79 Table 38: Current Consumption...80 Table 39: General 3.3V Interface (CMOS) DC Electrical Specifications...81 Table 40:...
  • Page 12 88F6281 Hardware Specifications Package ...130 Table 73: HSBGA 288-pin Package Dimensions ...131 Part Order Numbering/Package Marking...132 Table 74: 88F6281 Part Order Options ...132 Revision History ...134 Table 75: Revision History ...134 Doc. No. MV-S104859-U0 Rev. E Page 12 Document Classification: Proprietary Information Copyright ©...

  • Page 13: List Of Figures

    List of Figures Pin and Signal Descriptions ... 17 Figure 1: 88F6281 Pin Logic Diagram ...18 Unused Interface Strapping... 49 88F6281 Pin Map and Pin List ... 50 Pin Multiplexing ... 51 Clocking... 60 System Power Up/Down and Reset Settings ... 63 Figure 2: Power-Up Sequence Example...64 Figure 3:...
  • Page 14 88F6281 Hardware Specifications Figure 28: Inter-IC Sound (I2S) Test Circuit ...107 Figure 29: Inter-IC Sound (I2S) Output Delay AC Timing Diagram ...108 Figure 30: Inter-IC Sound (I2S) Input AC Timing Diagram ...108 Figure 31: TDM Interface Test Circuit ...109 Figure 32: TDM Interface Output Delay AC Timing Diagram...110 Figure 33: TDM Interface Input Delay AC Timing Diagram...110...

  • Page 15: Preface

    Preface About this Document This datasheet provides the hardware specifications for the 88F6281 integrated controller. The hardware specifications include detailed pin information, configuration settings, electrical characteristics and physical specifications. This datasheet is intended to be the basic source of information for designers of new systems. In this document, the “88F6281”...

  • Page 16: Document Conventions

    88F6281 Hardware Specifications RFC 1321 (The MD5 Message-Digest Algorithm) RFC 1851 – The ESP Triple DES Transform RFC 2104 (HMAC: Keyed-Hashing for Message Authentication). RFC 2405 – The ESP DES-CBC Cipher Algorithm With Explicit IV IEEE standard, 802.3-2000 Clause 14 ANSI standard X3.263-1995 See the Marvell Extranet website for the latest product documentation.

  • Page 17: Pin And Signal Descriptions

    Pin and Signal Descriptions This section provides the pin logic diagram for the 88F6281 device and a detailed description of the pin assignments and their functionality. Copyright © 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Pin and Signal Descriptions Doc.

  • Page 18: Pin Logic

    88F6281 Hardware Specifications Pin Logic Figure 1: 88F6281 Pin Logic Diagram VDD_CPU VDDO VDD_GE_A VDD_GE_B VDD_M CPU_PLL_AVDD CPU_PLL_AVSS CORE_PLL_AVDD CORE_PLL_AVSS Power XTAL_AVDD XTAL_AVSS PEX_AVDD SATA0_AVDD SATA1_AVDD USB_AVDD RTC_AVDD RTC_AVSS SSCG_AVDD SSCG_AVSS MPP[49:0] NF_IO[7:0] NF_CLE NAND NF_ALE Flash NF_CEn NF_REn NF_WEn JT_CLK JT_TDI JT_TDO...

  • Page 19: Pin Descriptions

    Pin Descriptions This section details all the pins for the different interfaces providing a functional description of each pin and pin attributes. Table 1<Default ¬¹ Font> Table 1: Pin Functions and Assignments Table Key Te r m <n> Analog Calib CMOS HCSL Power...
  • Page 20 88F6281 Hardware Specifications Table 2: Interface Pin Prefix Codes (Continued) In t e r f a c e NAND Flash TWSI UART Audio SDIO Doc. No. MV-S104859-U0 Rev. E Page 20 P re fi x RTC_ UA0_ UA1_ SPI_ TDM_ PTP_ Document Classification: Proprietary Information Copyright ©...

  • Page 21: Power Supply Pins

    1.2.1 Power Supply Pins Table 3 provides the voltage levels for the various interface pins. These do not include the analog power supplies for the PLLs or PHYs which are explicitly mentioned in the other pin description tables. Table 3: Power Pin Assignments P i n N a m e I /O...
  • Page 22 88F6281 Hardware Specifications Table 3: Power Pin Assignments (Continued) P i n N a m e I /O Pi n Ty p e PEX_AVDD Power SATA0_AVDD Power SATA1_AVDD USB_AVDD Power RTC_AVDD Power RTC_AVSS Doc. No. MV-S104859-U0 Rev. E Page 22 D es c r ip t i o n PCI Express PHY quiet power supply 1.8V NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design...

  • Page 23: Table 4: Miscellaneous Pin Assignments

    1.2.2 Miscellaneous Pin Assignment The Miscellaneous signal list contains clock and reset, test, and related signals. Table 4: Miscellaneous Pin Assignments P i n N a m e I /O Pi n Ty pe REF_CLK_XIN Analog XOUT Analog SYSRSTn CMOS SYSRST_OUTn CMOS PEX_RST_OUTn...

  • Page 24: Table 5: Ddr Sdram Interface Pin Assignments

    88F6281 Hardware Specifications 1.2.3 DDR SDRAM Interface Pin Assignments Table 5: DDR SDRAM Interface Pin Assignments P i n N a m e I /O Pi n Ty pe M_CLKOUT SSTL M_CLKOUTn M_CKE SSTL M_RASn SSTL M_CASn SSTL M_WEn SSTL M_A[14:0] SSTL M_BA[2:0]...
  • Page 25 Table 5: DDR SDRAM Interface Pin Assignments (Continued) P i n N a m e I /O Pi n Ty pe M_STARTBURST SSTL M_START SSTL BURST_IN M_PCAL Calib M_NCAL Calib Copyright © 2008 Marvell December 2, 2008, Preliminary P ow e r D e s cr ip t i o n R a i l VDD_M...

  • Page 26: Table 6: Pci Express Interface Pin Assignments

    88F6281 Hardware Specifications 1.2.4 PCI Express Interface Pin Assignments Table 6: PCI Express Interface Pin Assignments P i n N a m e I / O P in Ty p e PEX_CLK_P/N HCSL PEX_TX_P/N PEX_RX_P/N PEX_ISET Analog Doc. No. MV-S104859-U0 Rev. E Page 26 P o w e r D e s c r i p t io n...

  • Page 27: Table 7: Sata Port Interface Pin Assignment

    1.2.5 SATA Interface Pin Assignments Table 7: SATA Port Interface Pin Assignment P i n N a m e I /O Pi n Ty p e SATA0_T_P/N SATA1_T_P/N SATA0_R_P/N SATA1_R_P/N SATA0_PRESENTn CMOS SATA1_PRESENTn SATA0_ACTn CMOS SATA1_ACTn Copyright © 2008 Marvell December 2, 2008, Preliminary P ow e r R a i l D e s c r i p t io n...

  • Page 28: Table 8: Gigabit Ethernet Port0/1 Interface Pin Assignments

    88F6281 Hardware Specifications 1.2.6 Gigabit Ethernet Port Interface Pin Assignments For additional information about the Gigabit Ethernet port pin functions refer to Ethernet (GbE) Pins Multiplexing on MPP, on page Table 8: Gigabit Ethernet Port0/1 Interface Pin Assignments P i n N a m e I / O P in Ty p e...
  • Page 29 Table 8: Gigabit Ethernet Port0/1 Interface Pin Assignments (Continued) P i n N a m e I / O P in Ty p e GE_RXD[3:0] CMOS GE_RXCTL CMOS GE_RXCLK CMOS Port1—Multiplexed GbE Pins MPP[23:20]/ CMOS GE1[3:0] Copyright © 2008 Marvell December 2, 2008, Preliminary P o w e r D e s c r i p t io n...
  • Page 30 88F6281 Hardware Specifications Table 8: Gigabit Ethernet Port0/1 Interface Pin Assignments (Continued) P i n N a m e I / O P in Ty p e MPP[27:24]/ CMOS GE1[7:4] MPP[28]/GE1[8] CMOS MPP[29]/GE1[9] CMOS MPP[30]/GE1[10] CMOS MPP[31]/GE1[11] CMOS Doc. No. MV-S104859-U0 Rev. E Page 30 P o w e r D e s c r i p t io n...
  • Page 31 Table 8: Gigabit Ethernet Port0/1 Interface Pin Assignments (Continued) P i n N a m e I / O P in Ty p e MPP[32]/GE1[12] CMOS MPP[33]/GE1[13] CMOS MPP[34]/GE1[14] CMOS MPP[35]/GE1[15] CMOS Copyright © 2008 Marvell December 2, 2008, Preliminary P o w e r D e s c r i p t io n R a il...

  • Page 32: Table 9: Serial Management Interface (Smi) Pin Assignments

    88F6281 Hardware Specifications 1.2.7 Serial Management Interface (SMI) Interface Pin Assignments Table 9: Serial Management Interface (SMI) Pin Assignments P i n N a m e I / O P in Ty p e GE_MDC CMOS/ GE_MDIO CMOS Doc. No. MV-S104859-U0 Rev. E Page 32 P o w e r D e s c r i p t io n...

  • Page 33: Table 10: Usb 2.0 Interface Pin Assignments

    1.2.8 USB 2.0 Interface Pin Assignments Table 10: USB 2.0 Interface Pin Assignments P i n N a m e I / O Pi n Ty p e USB_DP USB_DM Copyright © 2008 Marvell December 2, 2008, Preliminary P ow e r D e s c r ip t i o n R ai l USB_AVDD...

  • Page 34: Table 11: Jtag Pin Assignment

    88F6281 Hardware Specifications 1.2.9 JTAG Interface Pin Assignment Table 11: JTAG Pin Assignment P i n N a m e I / O P in Ty p e JT_CLK CMOS JT_RSTn CMOS JT_TMS_CPU CMOS JT_TMS_CORE CMOS JT_TDO CMOS JT_TDI CMOS 1.

  • Page 35: Table 12: Rtc Interface Pin Assignments

    1.2.10 Real Time Clock (RTC) Interface Pin Assignments Table 12: RTC Interface Pin Assignments P i n N a m e I / O P in Ty p e RTC_XIN Analog RTC_XOUT Analog Copyright © 2008 Marvell December 2, 2008, Preliminary P o w e r D e s c r i p t io n R a il...

  • Page 36: Table 13: Nand Flash Interface Pin Assignment

    88F6281 Hardware Specifications 1.2.11 NAND Flash Interface Pin Assignment Table 13: NAND Flash Interface Pin Assignment P i n N a m e I / O P in Ty p e NF_IO[7:0] CMOS NF_CLE CMOS NF_ALE CMOS NF_CEn CMOS NF_REn CMOS NF_WEn CMOS...

  • Page 37: Table 14: Mpp Interface Pin Assignment

    1.2.12 MPP Interface Pin Assignment Table 14: MPP Interface Pin Assignment P i n N a m e I / O P in Ty p e MPP[19:0] CMOS MPP[35:20] CMOS MPP[49:36] CMOS The various functionalities of the MPP pins are detailed in on page 51 Note Copyright ©...

  • Page 38: Table 15: Two-Wire Serial Interface (Twsi) Interface Pin Assignment

    88F6281 Hardware Specifications 1.2.13 Two-Wire Serial Interface (TWSI) Interface All of the TWSI signals are multiplexed on the MPP pins (see on page 51 Note Table 15: Two-Wire Serial Interface (TWSI) Interface Pin Assignment P i n N a m e I / O P in Ty p e...

  • Page 39: Uart Interface

    1.2.14 UART Interface All of the UART signals are multiplexed on the MPP pins (see on page 51 Note Table 16: UART Port 0/1 Interface Pin Assignment P i n N a m e I / O P in Ty p e UA0/1_RXD CMOS UA0/1_TXD...

  • Page 40: Table 17: Audio (S/Pdif / I 2 S) Interface Signal Assignment

    88F6281 Hardware Specifications 1.2.15 Audio (S/PDIF / I All of the Audio signals are multiplexed on the MPP pins (see Multiplexing, on page If the Audio interface is not used, leave all of the signals unconnected. Note The Audio signals are powered on VDDO or on VDD_GE_B, based on the pin multiplexing option.

  • Page 41: Table 18: Serial Peripheral Interface (Spi) Interface Signal Assignment

    1.2.16 Serial Peripheral Interface (SPI) Interface All of the SPI signals are multiplexed on the MPP pins (see on page 51 Note Table 18: Serial Peripheral Interface (SPI) Interface Signal Assignment Pin Name Pin Type SPI_MOSI CMOS SPI_MISO CMOS SPI_SCK CMOS SPI_CSn CMOS...

  • Page 42: Table 19: Secure Digital Input/Output (Sdio) Interface Signal Assignment

    88F6281 Hardware Specifications 1.2.17 Secure Digital Input/Output (SDIO) Interface All of the SDIO signals are multiplexed on the MPP pins (see on page 51 Note Table 19: Secure Digital Input/Output (SDIO) Interface Signal Assignment Pin Name Pin Type SD_CLK CMOS SD_CMD CMOS SD_D[3:0]...

  • Page 43: Table 20: Time Division Multiplexing (Tdm) Interface Signal Assignment

    1.2.18 Time Division Multiplexing (TDM) Interface All of the TDM signals are multiplexed on the MPP pins (see Multiplexing, on page The TDM signals are powered on VDDO or on VDD_GE_B, based on the pin Note multiplexing option (see Table 20: Time Division Multiplexing (TDM) Interface Signal Assignment Pin Name Pin Type TDM_CH0_TX_...
  • Page 44 88F6281 Hardware Specifications Table 20: Time Division Multiplexing (TDM) Interface Signal Assignment (Continued) Pin Name Pin Type TDM_SPI_MOSI CMOS TDM_SPI_MISO CMOS Doc. No. MV-S104859-U0 Rev. E Page 44 Description Power Rail VDDO/ Serial SPI data from the host to the codec for register access. VDD_GE_B When TDM_SPI_CS is asserted low, the data is driven from the host on the negative edge of TDM_SPI_SCK.

  • Page 45: Table 21: Transport Stream (Ts) Interface Signal Assignment

    1.2.19 Transport Stream (TS) Interface All of the TS signals are multiplexed on the MPP pins (see Multiplexing, on page The TS signals are powered on VDDO or on VDD_GE_B based on the pin Note multiplexing option (see Table 21: Transport Stream (TS) Interface Signal Assignment Pin Name Pin Type TSMP[0]...
  • Page 46 88F6281 Hardware Specifications Table 21: Transport Stream (TS) Interface Signal Assignment (Continued) Pin Name Pin Type TSMP[7] CMOS TSMP[8] CMOS TSMP[9] CMOS TSMP[10] CMOS TSMP[11] CMOS TSMP[12] CMOS Doc. No. MV-S104859-U0 Rev. E Page 46 Description Power Rail • Parallel Mode: VDDO/ TS0_DATA[2]: Port0 TS Data bit 2 VDD_GE_B...

  • Page 47: Table 22: Precise Timing Protocol (Ptp) Interface Signal Assignment

    1.2.20 Precise Timing Protocol (PTP) Interface All of the PTP signals are multiplexed on the MPP pins (see on page 51 Note Table 22: Precise Timing Protocol (PTP) Interface Signal Assignment Pin Name Pin Type PTP_CLK CMOS PTP_EVENT_REQ CMOS PTP_TRIG_GEN CMOS Copyright ©...

  • Page 48: Internal Pull-Up And Pull-Down Pins

    88F6281 Hardware Specifications Internal Pull-up and Pull-down Pins Some pins of the device package are connected to internal pull-up and pull-down resistors. When these pins are Not Connected (NC) on the system board, these resistors set the default value for input and sample at reset configuration pins.

  • Page 49: Unused Interface Strapping

    Unused Interface Strapping Table 24 lists the signal strapping to be used for systems in which some of the device interfaces are unused (not connected). Table 24: Unused Interface Strapping U n u s e d I n t e r f a c e Str a pp i ng Ethernet SMI Pull up GE_MDIO.

  • Page 50: 88F6281 Pin Map And Pin List

    88F6281 Hardware Specifications 88F6281 Pin Map and Pin List The 88F6281 pin list is provided as an Excel file attachment. To open the attached Excel pin list file, double-click the pin icons below: 88F6281 Pin Map and Pin List.xls File attachments are only supported by Adobe Reader 6.0 and above. To download the latest version of free Adobe Reader go to http://www.adobe.com.

  • Page 51: Pin Multiplexing

    Pin Multiplexing Multi-Purpose Pins Functional Summary The 88F6281 device contains 50 Multi-Purpose Pins (MPP). Each one can be assigned to a different functionality through the MPP Control register. General Purpose pins: MPP[5:0] and MPP[49:7]: • GPIO (input/output): MPP[0], MPP[4], MPP[9:8], MPP[11], MPP[17:13], MPP[32:20], and MPP[49:34] •...

  • Page 52: Table 25: Mpp Functionality

    88F6281 Hardware Specifications MPP pins can be assigned to different functionalities through the MPP Control register, as shown in Table Table 25: MPP Functionality M P P [ 1 9 : 0 ] : GPIO SATA LEDs NAND flash TWSI UART SDIO Table 26...

  • Page 53: Table 26: Mpp Function Summary

    Table 26: MPP Function Summary Pin name GPIO[0] NF_IO[2] MPP[0] (in/out) (in/out) GPO[1] (out NF_IO[3] MPP[1] only) (in/out) GPO[2] (out NF_IO[4] MPP[2] only) (in/out) GPO[3] (out NF_IO[5] MPP[3] only) (in/out) GPIO[4] NF_IO[6] MPP[4] (in/out) (in/out) GPO[5] (out NF_IO[7] MPP[5] only) (in/out) SYSRST_O MPP[6]...
  • Page 54 88F6281 Hardware Specifications Table 26: MPP Function Summary (Continued) Pin name GPO[18] NF_IO[0] MPP[18] (out only) (in/out) GPO[19] NF_IO[1] MPP[19] (out only) (in/out) GPIO[20] TSMP[0] TDM_CH0_ MPP[20] (in/out) (in/out) TX_QL (out) GPIO[21] TSMP[1] TDM_CH0_ MPP[21] (in/out) (in/out) RX_QL (out) GPIO[22] TSMP[2] TDM_CH2_ MPP[22]...
  • Page 55 Table 26: MPP Function Summary (Continued) Pin name GPIO[36] TSMP[0] MPP[36] (in/out) (in/out) GPIO[37] TSMP[1] TDM_CH2_ MPP[37] (in/out) (in/out) TX_QL (out) GPIO[38] TSMP[2] TDM_CH2_ MPP[38] (in/out) (in/out) RX_QL (out) GPIO[39] TSMP[3] MPP[39] (in/out) (in/out) GPIO[40] TSMP[4] MPP[40] (in/out) (in/out) GPIO[41] TSMP[5] MPP[41] (in/out)
  • Page 56 88F6281 Hardware Specifications For MPPs assigned as NAND flash and SPI flash, wake-up mode after reset depends on Boot mode (see the Boot Device field in Configuration, on page Note • • Pin MPP[6] wakes up after reset in 0x1 mode (SYSRST_OUTn) Pin MPP[7] wakes up after reset: •...

  • Page 57: Gigabit Ethernet (Gbe) Pins Multiplexing On Mpp

    Gigabit Ethernet (GbE) Pins Multiplexing on MPP The 88F6281 has 14 dedicated pins for its GbE port. (12 RGMII pins, an MDC pin, and an MDIO pin). For the 88F6281, additional GbE interface pins are multiplexed on the MPPs, to serve as the following interfaces to an external PHY or switch.
  • Page 58 88F6281 Hardware Specifications Table 27: Ethernet Ports Pins Multiplexing (Continued) Pin Name 1x GMII MPP_34 / GE1[14] MPP_35 / GE1[15] When using Gigabit Ethernet signals on MPPs, all relevant Gigabit Ethernet signals (except those marked as NA) must be implemented. For example, if using MII, and the chosen PHY does not have an MII_RXERR out signal, the MII_RX_ERR (in) (MPP[35]) Note must still be configured accordingly and must have a pull-down resistor.

  • Page 59: Tsmp (Ts Multiplexing Pins) On Mpp

    TSMP (TS Multiplexing Pins) on MPP The TS interface can be configured to one of five modes: One or two serial in interfaces One or two serial out interfaces Serial in and serial out interface Parallel in interface Parallel out interface In parallel in or serial in mode, all TS signals are inputs.

  • Page 60: Clocking

    88F6281 Hardware Specifications Clocking Table 29 lists the clocks in the 88F6281. Table 29: 88F6281Clocks C l o ck Ty p e CPU PLL Core PLL PEX PHY USB PHY PLL Doc. No. MV-S104859-U0 Rev. E Page 60 D e s c r i p t i o n •...

  • Page 61: Table 30: Supported Clock Combinations

    Table 29: 88F6281Clocks (Continued) C l o ck Ty p e SATA PHY PLL The following table lists the supported combinations of the CPU_CLK Frequency select, CPU_CLK to DDR CLK ratio, and to CPU_CLK to CPU L2 clock ratio (see Configuration, on page Table 30: Supported Clock Combinations D D R C l o c k...

  • Page 62: Spread Spectrum Clock Generator (Sscg)

    88F6281 Hardware Specifications Spread Spectrum Clock Generator (SSCG) The SSCG (Spread Spectrum Clock Generator) may be used to generate the spread spectrum clock for the PLL input. See enable/bypass configuration settings. The SSCG block can be configured to perform up spread, down spread and center spread. The modulation frequency is configurable.

  • Page 63: System Power Up/Down And Reset Settings

    System Power Up/Down and Reset Settings This section provides information about the device power-up/down sequence and configuration at reset. Power-Up/Down Sequence Requirements 6.1.1 Power-Up Sequence Requirements These guidelines must be applied to meet the 88F6281 device power-up requirements: The non-core voltages (I/O and Analog) as listed in level before the core voltages reach 70% of their voltage level.

  • Page 64: Hardware Reset

    88F6281 Hardware Specifications Figure 2: Power-Up Sequence Example Voltage Reset(s) Clock(s) It is the designer's responsibility to verify that the power sequencing requirements of other components are also met. Although the non-core voltages can be powered up any time before the core Note voltages, allow a reasonable time limitation (for example, 100 ms) between the first non-core voltage power-up and the last core voltage power-up.

  • Page 65: Power On Reset (Por)

    Reset (SYSRSTn signal) must be active for a minimum length of 5 ms. core power, I/O power, and analog power must be stable (VDD +/- 5%) during that time and onward. Note 6.2.1 Reset Out Signal The device has an optional SYSRST_OUTn output signal, multiplexed on an MPP pin, that is used as a reset request from the device to the board reset logic.

  • Page 66: Pci Express Reset

    88F6281 Hardware Specifications PCI Express Reset 6.3.1 PCI Express Root Complex Reset As a Root Complex, the device may generate a Hot Reset to the PCI Express port. Upon CPU setting the PCI Express Control register’s <conf_mstr_hot_reset> bit, the PCI Express unit sends a Hot Reset indication to the Endpoint, see the PCI Express Interface section in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications.

  • Page 67: Table 32: Reset Configuration

    If external logic is used instead of pull-up and pull-down resistors, the logic must drive all of these signals to the desired values during SYSRSTn assertion. To prevent bus contention on these pins, the external logic must float the bus no later Note than the third TCLK cycle after SYSRSTn de-assertion.
  • Page 68 88F6281 Hardware Specifications Table 32: Reset Configuration (Continued) P in C on fi g ur a tio n F u n ct io n MPP[33], CPU_CLK to DDR CLK Ratio NF_ALE, 0x0–0x3 = Reserved NF_REn, 0x4 = 3:1 NF_CLE 0x5 = Reserved 0x6 = 4:1 0x7 = 4.5:1 0x8 = 5:1...
  • Page 69 Table 32: Reset Configuration (Continued) P in C on fi g ur a tio n F u n ct io n GE_TXD[2:0] Boot Device 0x0 = Reserved 0x1 = Reserved 0x2 = Boot from SPI flash (SPI_CSn on MPP[7]) 0x3 = Reserved 0x4 = Boot from SPI flash (SPI_CSn on MPP[0]) 0x5 = Boot from NAND flash 0x6 = Boot from SATA...

  • Page 70: Serial Rom Initialization

    88F6281 Hardware Specifications Table 32: Reset Configuration (Continued) P in C on fi g ur a tio n F u n ct io n MPP[18] Reserved NOTE: MUST be externally pulled down to 0x0 during reset. Serial ROM Initialization The device supports initialization of ALL of its internal and configuration registers through the TWSI master interface.

  • Page 71: Boot Sequence

    The serial ROM initialization logic reads eight bytes at a time. It performs address decoding on the 32-bit address being read, and based on address decoding result, writes the next four bytes to the required target. The Serial Initialization Last Data Register contains the expected value of last serial data item (default value is 0xFFFFFFFF).
  • Page 72 88F6281 Hardware Specifications Upon completing the above sequence, the internal CPU reset is de-asserted, and the CPU starts executing boot code from the boot device (SPI flash, NAND flash, or internal Boot ROM), according to sample at reset setting, see For bootROM details, see the BootROM section in the Functional Specifications.

  • Page 73: Jtag Interface

    JTAG Interface To enable board testing, the device supports a test mode operation through its JTAG boundary scan interface. The JTAG interface is IEEE 1149.1 standard compliant. It supports mandatory and optional boundary scan instructions. TAP Controller The Test Access Port (TAP) is constructed with a 5-pin interface and a 16-state Finite State Machine (FSM), as defined by IEEE JTAG standard 1149.1.

  • Page 74: Bypass Register

    88F6281 Hardware Specifications Bypass Register The Bypass register (BR) is a single bit serial shift register that connects TDI to TDO, when the IR holds the Bypass command, and the TAP FSM is in Shift-DR state. Data that is driven on the TDI input pin is shifted out one cycle later on the TDO output pin.

  • Page 75: Electrical Specifications (Preliminary)

    Electrical Specifications (Preliminary) The numbers specified in this section are PRELIMINARY and SUBJECT TO CHANGE. Note Absolute Maximum Ratings Table 35: Absolute Maximum Ratings P a r a m e t e r M i n -0.5 VDD_CPU -0.5 CPU_PLL_AVDD -0.5 CORE_PLL_AVDD SSCG_AVDD...
  • Page 76 88F6281 Hardware Specifications Table 35: Absolute Maximum Ratings (Continued) P a r a m e t e r M i n RTC_AVDD -0.5 Exposure to conditions at or beyond the maximum rating may damage the device. Operation beyond the recommended operating conditions Caution recommended nor guaranteed.

  • Page 77: Recommended Operating Conditions

    Recommended Operating Conditions Table 36: Recommended Operating Conditions P a r a m e t e r M in 0.95 VDD_CPU 1.05 CPU_PLL_AVDD CORE_PLL_AVDD SSCG_AVDD VDD_GE_A 3.15 VDD_GE_B VDD_M VDDO 3.15 VHV (during eFuse 2.375 Burning mode) VHV (during eFuse 0.95 Reading mode) PEX_AVDD...
  • Page 78 88F6281 Hardware Specifications Table 36: Recommended Operating Conditions (Continued) P a r a m e t e r M in XTAL_AVDD RTC_AVDD Operation beyond the recommended operating conditions is neither recommended nor guaranteed. Caution Doc. No. MV-S104859-U0 Rev. E Page 78 Ty p M a x Units...

  • Page 79: Thermal Power Dissipation

    Thermal Power Dissipation Before designing a system, Marvell recommends reading application note AN-63: Thermal Management for Marvell Technology Products. This application note presents basic concepts of thermal management for integrated circuits (ICs) and includes Note guidelines to ensure optimal operating conditions for Marvell Technology's products. The purpose of the Thermal Power Dissipation table is to support system engineering in thermal design.

  • Page 80: Current Consumption

    88F6281 Hardware Specifications Current Consumption The purpose of the Current Consumption table is to support board power design and power module selection. Table 38: Current Consumption In t e r f a c e Core (VDD 1.0V) Embedded CPU (VDD_CPU 1.1V) RGMII 1.8V or 3.3V interface GMII 3.3V interface MII/MMII 3.3V interface...

  • Page 81: Dc Electrical Specifications

    DC Electrical Specifications Section 1.3, Internal Pull-up and Pull-down Pins, on page 48 pullup/pulldown information. Note 8.5.1 General 3.3V (CMOS) DC Electrical Specifications The DC electrical specifications in JTAG RGMII (10/100 Mbps)/GMII/MII/MMII Secure Digital Input/Output (SDIO) S/PDIF / I S (Audio) Transport Stream (TS) NAND flash UART...

  • Page 82: Table 40: Rgmii 1.8V Interface (Cmos) Dc Electrical Specifications

    88F6281 Hardware Specifications 8.5.2 RGMII, SMI and REF_CLK_XIN 1.8V (CMOS) DC Electrical Specifications In the following table, for the RGMII interface, VDDIO means the VDD_GE_A power rail. In the following table, for the REF_CLK_XIN pin, VDDIO means the XTAL_AVDD power rail. Table 40: RGMII 1.8V Interface (CMOS) DC Electrical Specifications Param eter Sym bol...

  • Page 83: Table 41: Sdram Ddr2 Interface Dc Electrical Specifications

    8.5.3 SDRAM DDR2 Interface DC Electrical Specifications In the following table, VREF is VDD_M/2 and VDDIO means the VDD_M power rail. Table 41: SDRAM DDR2 Interface DC Electrical Specifications Parameter Input low level Input high level Output low level Output high level Rtt effective impedance value Deviation of VM w ith respect to VDDQ/2 Input leakage current...

  • Page 84: Table 42: Twsi Interface 3.3V Dc Electrical Specifications

    88F6281 Hardware Specifications 8.5.4 Two-Wire Serial Interface (TWSI) 3.3V DC Electrical Specifications In the following table, VDDIO means the VDDO power rail. Table 42: TWSI Interface 3.3V DC Electrical Specifications Param eter Sym bol Input low level Input high level Output low level Input leakage current Pin capacitance...

  • Page 85: Table 44: Tdm Interface 3.3V Dc Electrical Specifications

    8.5.6 Time Division Multiplexing (TDM) 3.3V DC Electrical Specifications In the following table VDDIO means the either the VDDO or the VDD_GE_B power rail, depending on which MPP pins are configured for the TDM interface. Table 44: TDM Interface 3.3V DC Electrical Specifications Param eter Sym bol Input low level...

  • Page 86: Ac Electrical Specifications

    88F6281 Hardware Specifications AC Electrical Specifications Section 8.7, Differential Interface Electrical Characteristics, on page 118 specifications. 8.6.1 Reference Clock AC Timing Specifications Table 45: Reference Clock AC Timing Specifications D e s c r i p t io n C P U a n d C o r e R e f e r e n c e C l o c k Frequency Clock duty cycle Slew rate...
  • Page 87 Table 45: Reference Clock AC Timing Specifications (Continued) D e s c r i p t io n T D M _ S PI O u tp ut C lo c k TDM_SPI output clock S M I M a s t e r M o d e R e f e r e n c e C l o ck SMI output MDC clock T WS I M a s t er M o d e R e fe re n c e C lo c k SCK output clock...

  • Page 88: Table 46: Sdram Ddr2 Interface Ac Timing Table

    88F6281 Hardware Specifications 8.6.2 SDRAM DDR2 Interface AC Timing 8.6.2.1 SDRAM DDR2 Interface AC Timing Table Table 46: SDRAM DDR2 Interface AC Timing Table Description Clock frequency DQ and DM valid output time before DQS transition DQ and DM valid output time after DQS transition DQ and DM output pulse w idth DQS output high pulse w idth DQS output low pulse w idth...

  • Page 89: Table 47: Sdram Ddr2 Interface Address Timing Table

    Table 47: SDRAM DDR2 Interface Address Timing Table Description Address and Control valid output time before CLK-CLkn rising edge Address and Control valid output time after CLK-CLKn rising edge Address and Control valid output time before CLK-CLkn rising edge Address and Control valid output time after CLK-CLKn rising edge Notes: General comment: All timing values w ere measured from vref to vref, unless otherw ise specified.

  • Page 90: Table 48: Sdram Ddr2 Clock Specifications

    88F6281 Hardware Specifications 8.6.2.2 SDRAM DDR2 Clock Specifications Table 48: SDRAM DDR2 Clock Specifications Description Clock period jitter Clock perior jitter during DLL locking period Cycle to cycle clock period jitter Cycle to cycle clock period jitter during DLL locking period Cumulative error across 2 cycles Cumulative error across 3 cycles Cumulative error across 4 cycles...

  • Page 91: Figure 5: Sdram Ddr2 Interface Test Circuit

    8.6.2.3 SDRAM DDR2 Interface Test Circuit Figure 5: SDRAM DDR2 Interface Test Circuit 8.6.2.4 SDRAM DDR2 Interface AC Timing Diagrams Figure 6: SDRAM DDR2 Interface Write AC Timing Diagram CLKn DQSn Copyright © 2008 Marvell December 2, 2008, Preliminary Test Point 50 ohm tDSH tDSS...

  • Page 92: Figure 7: Sdram Ddr2 Interface Address And Control Ac Timing Diagram

    88F6281 Hardware Specifications Figure 7: SDRAM DDR2 Interface Address and Control AC Timing Diagram CLKn ADDRESS/ CONTROL Figure 8: SDRAM DDR2 Interface Read AC Timing Diagram DQSn Doc. No. MV-S104859-U0 Rev. E Page 92 tIPW tAOVB tAOVA tDSI Document Classification: Proprietary Information tDHI Copyright ©...

  • Page 93: Table 49: Rgmii 10/100/1000 Ac Timing Table At 1.8V

    8.6.3 Reduced Gigabit Media Independent Interface (RGMII) AC Timing 8.6.3.1 RGMII AC Timing Table Table 49: RGMII 10/100/1000 AC Timing Table at 1.8V Clock frequency Data to Clock output skew Data to Clock input skew Clock cycle duration Duty cycle for Gigabit Duty cycle for 10/100 Megabit Notes: General comment: All values w ere measured from vddio/2 to vddio/2, unless otherw ise specified.

  • Page 94: Figure 9: Rgmii Test Circuit

    88F6281 Hardware Specifications 8.6.3.2 RGMII Test Circuit Figure 9: RGMII Test Circuit 8.6.3.3 RGMII AC Timing Diagram Figure 10: RGMII AC Timing Diagram Doc. No. MV-S104859-U0 Rev. E Page 94 Test Point CLOCK (At Transmitter) DATA CLOCK (At Receiver) DATA Document Classification: Proprietary Information TskewT TskewR...

  • Page 95: Table 51: Gmii Ac Timing Table

    8.6.4 Gigabit Media Independent Interface (GMII) AC Timing 8.6.4.1 GMII AC Timing Table Table 51: GMII AC Timing Table Description GTX_CLK cycle time RX_CLK cycle time GTX_CLK and RX_CLK high level w idth GTX_CLK and RX_CLK low level w idth GTX_CLK and RX_CLK rise time GTX_CLK and RX_CLK fall time Data input setup time relative to RX_CLK rising edge...

  • Page 96: Figure 12: Gmii Output Ac Timing Diagram

    88F6281 Hardware Specifications 8.6.4.3 GMII AC Timing Diagrams Figure 12: GMII Output AC Timing Diagram GTX_CLK TXD, TX_EN, TX_ER Figure 13: GMII Input AC Timing Diagram RX_CLK RXD, RX_EN, RX_ER Doc. No. MV-S104859-U0 Rev. E Page 96 tLOW tHIGH tOVB tOVA tLOW tHIGH...

  • Page 97: Table 52: Mii/Mmii Mac Mode Ac Timing Table

    8.6.5 Media Independent Interface/Marvell Media Independent Interface (MII/MMII) AC Timing 8.6.5.1 MII/MMII MAC Mode AC Timing Table Table 52: MII/MMII MAC Mode AC Timing Table Description Data input setup relative to RX_CLK rising edge Data input hold relative to RX_CLK rising edge Data output delay relative to MII_TX_CLK rising edge Notes: General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified.

  • Page 98: Figure 16: Mii/Mmii Mac Mode Input Ac Timing Diagram

    88F6281 Hardware Specifications Figure 16: MII/MMII MAC Mode Input AC Timing Diagram RX_CLK RXD, RX_EN, RX_ER Doc. No. MV-S104859-U0 Rev. E Page 98 Document Classification: Proprietary Information Vih(min) Vih(min) Vil(max) Copyright © 2008 Marvell December 2, 2008, Preliminary...

  • Page 99: Table 53: Smi Master Mode Ac Timing Table

    8.6.6 Serial Management Interface (SMI) AC Timing 8.6.6.1 SMI Master Mode AC Timing Table Table 53: SMI Master Mode AC Timing Table Description MDC clock frequency MDC clock duty cycle MDIO input setup time relative to MDC rise time MDIO input hold time relative to MDC rise time MDIO output valid before MDC rise time MDIO output valid after MDC rise time Notes:...

  • Page 100: Figure 18: Mdc Master Mode Test Circuit

    88F6281 Hardware Specifications Figure 18: MDC Master Mode Test Circuit 8.6.6.3 SMI Master Mode AC Timing Diagrams Figure 19: SMI Master Mode Output AC Timing Diagram MDIO Figure 20: SMI Master Mode Input AC Timing Diagram MDIO Doc. No. MV-S104859-U0 Rev. E Page 100 Test Point tOVB...

  • Page 101: Table 54: Jtag Interface Ac Timing Table

    8.6.7 JTAG Interface AC Timing 8.6.7.1 JTAG Interface AC Timing Table Table 54: JTAG Interface AC Timing Table Description JTClk frequency JTClk minimum pulse w idth JTClk rise/fall slew rate JTRSTn active time TMS, TDI input setup relative to JTClk rising edge TMS, TDI input hold relative to JTClk rising edge JTClk falling edge to TDO output delay Notes:...

  • Page 102: Figure 22: Jtag Interface Output Delay Ac Timing Diagram

    88F6281 Hardware Specifications 8.6.7.3 JTAG Interface AC Timing Diagrams Figure 22: JTAG Interface Output Delay AC Timing Diagram JTCK Figure 23: JTAG Interface Input AC Timing Diagram JTCK TMS,TDI Doc. No. MV-S104859-U0 Rev. E Page 102 Tprop (max) Tprop (min) Tsetup Thold Document Classification: Proprietary Information...

  • Page 103: Table 55: Twsi Master Ac Timing Table

    8.6.8 Two-Wire Serial Interface (TWSI) AC Timing 8.6.8.1 TWSI AC Timing Table Table 55: TWSI Master AC Timing Table Description SCK clock frequency SCK minimum low level w idth SCK minimum high level w idth SDA input setup time relative to SCK rising edge SDA input hold time relative to SCK falling edge SDA and SCK rise time SDA and SCK fall time...

  • Page 104: Figure 24: Twsi Test Circuit

    88F6281 Hardware Specifications 8.6.8.2 TWSI Test Circuit Figure 24: TWSI Test Circuit Test Point 8.6.8.3 TWSI AC Timing Diagrams Figure 25: TWSI Output Delay AC Timing Diagram Figure 26: TWSI Input AC Timing Diagram Doc. No. MV-S104859-U0 Rev. E Page 104 VDDIO tHIGH tLOW...

  • Page 105: Table 57: S/Pdif Ac Timing Table

    8.6.9 Sony/Philips Digital Interconnect Format (S/PDIF) AC Timing 8.6.9.1 S/PDIF AC Timing Table Table 57: S/PDIF AC Timing Table Description Output frequency accuracy Input frequency accuracy Output jitter - total peak-to-peak Jitter transfer gain Input jitter - total peak-to-peak Notes: General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified.

  • Page 106: Figure 27: S/Pdif Test Circuit

    88F6281 Hardware Specifications 8.6.9.2 S/PDIF Test Circuit Figure 27: S/PDIF Test Circuit Doc. No. MV-S104859-U0 Rev. E Page 106 Test Point Document Classification: Proprietary Information Copyright © 2008 Marvell December 2, 2008, Preliminary...

  • Page 107: Table 58: Inter-Ic Sound (I2S) Ac Timing Table

    8.6.10 Inter-IC Sound Interface (I 8.6.10.1 Inter-IC Sound (I Table 58: Inter-IC Sound (I S) AC Timing Table Description I2SBCLK clock frequency I2SBCLK clock high/low level pulse w idth I2SDI input setup time relative to I2SBCLK rise time I2SDI input hold time relative to I2SBCLK rise time I2SDO, I2SLRCLK output delay relative to I2SBCLK rise time Notes: General comment: All timing values w ere measured from VIL(max) and VIH(min) levels, unless otherw ise specified.

  • Page 108: Figure 29: Inter-Ic Sound (I2S) Output Delay Ac Timing Diagram

    88F6281 Hardware Specifications 8.6.10.3 Inter-IC Sound (I Figure 29: Inter-IC Sound (I I2SBCLK I2SDO, I2SLRCLK Figure 30: Inter-IC Sound (I I2SBCLK I2SDI Doc. No. MV-S104859-U0 Rev. E Page 108 S) AC Timing Diagrams S) Output Delay AC Timing Diagram tODmin tODmax S) Input AC Timing Diagram Document Classification: Proprietary Information...

  • Page 109: Table 59: Tdm Interface Ac Timing Table

    8.6.11 Time Division Multiplexing (TDM) Interface AC Timing 8.6.11.1 TDM Interface AC Timing Table Table 59: TDM Interface AC Timing Table Description PCLK cycle time PCLK duty cycle PCLK rise/fall time DTX and FSYNC valid after PCLK rising edge DRX and FSYNC setup time relative to PCLK falling edge DRX and FSYNC hold time relative to PCLK falling edge Notes: General comment: All values w ere measured from vddio/2 to vddio/2, unless otherw ise specified.

  • Page 110: Figure 32: Tdm Interface Output Delay Ac Timing Diagram

    88F6281 Hardware Specifications 8.6.11.3 TDM Interface Timing Diagrams Figure 32: TDM Interface Output Delay AC Timing Diagram PCLK Figure 33: TDM Interface Input Delay AC Timing Diagram PCLK Doc. No. MV-S104859-U0 Rev. E Page 110 Document Classification: Proprietary Information Copyright © 2008 Marvell December 2, 2008, Preliminary...

  • Page 111: Table 60: Spi (Master Mode) Ac Timing Table

    8.6.12 Serial Peripheral Interface (SPI) AC Timing 8.6.12.1 SPI (Master Mode) AC Timing Table Table 60: SPI (Master Mode) AC Timing Table Description SCLK clock frequency SCLK high time SCLK low time SCLK slew rate Data out valid relative to SCLK falling edge CS active before SCLK rising edge CS not active after SCLK rising edge Data in setup time relative to SCLK rising edge...

  • Page 112: Figure 35: Spi (Master Mode) Output Ac Timing Diagram

    88F6281 Hardware Specifications 8.6.12.3 SPI (Master Mode) Timing Diagrams Figure 35: SPI (Master Mode) SCLK Data Figure 36: SPI (Master Mode) SCLK Data in Doc. No. MV-S104859-U0 Rev. E Page 112 Output AC Timing Diagram tDOVmin tDOVmax tCSB Input AC Timing Diagram Document Classification: Proprietary Information tCSA Copyright ©...

  • Page 113: Table 61: Sdio Host In High Speed Mode Ac Timing Table

    8.6.13 Secure Digital Input/Output (SDIO) Interface AC Timing 8.6.13.1 Secure Digital Input/Output (SDIO) AC Timing Table Table 61: SDIO Host in High Speed Mode AC Timing Table Description Clock frequency in Data Transfer Mode Clock high/low level pulse w idth Clock rise/fall time CMD, DAT output valid before CLK rising edge CMD, DAT output valid after CLK rising edge...

  • Page 114: Figure 38: Sdio Host In High Speed Mode Output Ac Timing Diagram

    88F6281 Hardware Specifications 8.6.13.3 Secure Digital Input/Output (SDIO) AC Timing Diagrams Figure 38: SDIO Host in High Speed Mode Output AC Timing Diagram DAT, Figure 39: SDIO Host in High Speed Mode Input AC Timing Diagram DAT, Doc. No. MV-S104859-U0 Rev. E Page 114 tDOVB tDOVA tISU...

  • Page 115: Table 62: Transport Stream Output Interface Ac Timing Table

    8.6.14 Transport Stream (TS) Interface AC Timing 8.6.14.1 Transport Stream Interface AC Timing Table Table 62: Transport Stream Output Interface AC Timing Table Description Clock frequency Clock minimum low level w idth Clock minimum high level w idth Data output valid after Clock rising edge Notes: General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified.

  • Page 116: Figure 40: Transport Stream Interface Test Circuit

    88F6281 Hardware Specifications 8.6.14.2 Transport Stream Interface Test Circuit Figure 40: Transport Stream 8.6.14.3 Transport Stream Interface Timing Diagrams Figure 41: Transport Stream Clock Data Out Doc. No. MV-S104859-U0 Rev. E Page 116 Interface Test Circuit Test Point Output Interface AC Timing Diagram tHIGH tLOW tOV(min)

  • Page 117: Figure 42: Transport Stream Input Interface Ac Timing Diagram

    Figure 42: Transport Stream Clock Data In Copyright © 2008 Marvell December 2, 2008, Preliminary Input Interface AC Timing Diagram tLOW tHIGH Document Classification: Proprietary Information Electrical Specifications AC Electrical Specifications Vih(min) Vil(max) Vih(min) Vil(max) Doc. No. MV-S104859-U0 Rev. E Page 117...

  • Page 118: Differential Interface Electrical Characteristics

    88F6281 Hardware Specifications Differential Interface Electrical Characteristics This section provides the reference clock, AC, and DC characteristics for the following differential interfaces: PCI Express Interface Electrical Characteristics SATA Interface Electrical Characteristics USB Electrical Characteristics 8.7.1 Differential Interface Reference Clock Characteristics 8.7.1.1 PCI Express Interface Differential Reference Clock Characteristics Table 64: PCI Express Interface Differential Reference Clock Characteristics...

  • Page 119: Table 65: Pci Express Interface Spread Spectrum Requirements

    PCI Express Interface Spread Spectrum Requirements Table 65: PCI Express Interface Spread Spectrum Requirements Sym bol Fmod Fspread Notes: 1. Defined on linear sw eep or “Hershey’s Kiss” (US Patent 5,631,920) modulations. Copyright © 2008 Marvell December 2, 2008, Preliminary Differential Interface Electrical Characteristics Units 33.0...

  • Page 120: Table 66: Pci Express Interface Driver And Receiver Characteristics

    88F6281 Hardware Specifications 8.7.2 PCI Express Interface Electrical Characteristics 8.7.2.1 PCI Express Interface Driver and Receiver Characteristics Table 66: PCI Express Interface Driver and Receiver Characteristics Description Baud rate Unit interval Baud rate tolerance Differential peak to peak output voltage Minimum TX eye w idth Differential return loss Common mode return loss...

  • Page 121: Figure 43: Pci Express Interface Test Circuit

    8.7.2.2 PCI Express Interface Test Circuit Figure 43: PCI Express Interface Test Circuit When measuring Transmitter output parameters, C_TX is an optional portion of the Test/Measurement load. When used, the value of C_TX must be in the range of 75 nF to 200 nF. C_TX must not be used when the Test/Measurement load is placed in the Receiver package reference plane.
  • Page 122 88F6281 Hardware Specifications 8.7.3 SATA Interface Electrical Characteristics The driver and receiver characteristics for the SATA-I Interface Gen1i Mode and the SATA-II Interface Gen2i Mode are provided in the following sections. Doc. No. MV-S104859-U0 Rev. E Page 122 Document Classification: Proprietary Information Copyright ©...

  • Page 123: Table 67: Sata-I Interface Gen1I Mode Driver And Receiver Characteristics

    8.7.3.1 SATA-I Interface Gen1i Mode Driver and Receiver Characteristics Table 67: SATA-I Interface Gen1i Mode Driver and Receiver Characteristics Description Baud Rate Baud rate tolerance Spread spectrum modulation frequency Spread spectrum modulation Deviation Unit Interval Differential impedance Single ended impedance Differential return loss (75 MHz-150 MHz) Differential return loss (150 MHz-300 MHz) Differential return loss (300 MHz-1.2 GHz)

  • Page 124: Table 68: Sata-Ii Interface Gen2I Mode Driver And Receiver Characteristics

    88F6281 Hardware Specifications 8.7.3.2 SATA-II Interface Gen2i Mode Driver and Receiver Characteristics Table 68: SATA-II Interface Gen2i Mode Driver and Receiver Characteristics Description Baud Rate Baud rate tolerance Spread spectrum modulation frequency Spread spectrum modulation Deviation Unit Interval Output differential voltage Differential return loss (150 MHz-300 MHz) Differential return loss (300 MHz-600 MHz) Differential return loss (600 MHz-2.4 GHz)

  • Page 125: Usb Electrical Characteristics

    8.7.4 USB Electrical Characteristics 8.7.4.1 Driver and Receiver Characteristics Table 69: USB Low Speed Driver and Receiver Characteristics Description Baud Rate Baud rate tolerance Ouput single ended high Ouput single ended low Output signal crossover voltage Data fall time Data rise time Rise and fall time matching Source jitter total: to next transition Source jitter total: for paired transitions...

  • Page 126: Table 70: Usb Full Speed Driver And Receiver Characteristics

    88F6281 Hardware Specifications Table 70: USB Full Speed Driver and Receiver Characteristics Description Baud Rate Baud rate tolerance Ouput single ended high Ouput single ended low Output signal crossover voltage Output rise time Output fall time Source jitter total: to next transition Source jitter total: for paired transitions Source jitter for differential transition to SE0 transition Input single ended high...

  • Page 127: Table 71: Usb High Speed Driver And Receiver Characteristics

    Table 71: USB High Speed Driver and Receiver Characteristics Description Baud Rate Baud rate tolerance Data signaling high Data signaling low Data rise time Data fall time Data source jitter Differential input signaling levels Data signaling common mode voltage range Receiver jitter tolerance Notes: General Comment: For more information, refer to Universal Serial Bus Specification, Revision 2.0, April 2000.

  • Page 128: Figure 45: High Speed Tx Eye Diagram Pattern Template

    88F6281 Hardware Specifications Figure 45: High Speed TX Eye Diagram Pattern Template +525mV +475mV +300mV -300mV -475mV -525mV Figure 46: High Speed RX Eye Diagram Pattern Template +525mV +475mV +175mV -175mV -475mV -525mV Doc. No. MV-S104859-U0 Rev. E Page 128 7.5% 37.5% 62.5%...

  • Page 129: Thermal Data (Preliminary)

    Thermal Data (Preliminary) Table 72 provides the package thermal data for the device. This data is derived from simulations that were run according to the JEDEC standard. The thermal parameters are preliminary and subject to change. Note The documents listed below provide a basic understanding of thermal management of integrated circuits (ICs) and guidelines to ensure optimal operating conditions for Marvell products.

  • Page 130: Package

    88F6281 Hardware Specifications Package This section provides the 88F6281 package drawing and dimensions. Figure 47: HSBGA 288-pin Package and Dimensions Doc. No. MV-S104859-U0 Rev. E Page 130 Document Classification: Proprietary Information Copyright © 2008 Marvell December 2, 2008, Preliminary...

  • Page 131: Table 73: Hsbga 288-Pin Package Dimensions

    Table 73: HSBGA 288-pin Package Dimensions Package Body size Ball pitch Total thickness Mold thickness Substrate thickness Ball diameter Standoff Ball width Mold area H/S exposed size H/S flatness H/S shift with substrate edge H/S shift with mold area Chamfer Package edge tolerance Substrate flatness Mold flatness...

  • Page 132: Part Order Numbering/Package Marking

    88F6281 Hardware Specifications Part Order Numbering/Package Marking 11.1 Part Order Numbering Figure 48 shows the part order numbering scheme for the 88F6281. Refer to Marvell Field Application Engineers (FAEs) or representatives for further information when ordering parts. Figure 48: Sample Part Number 88F6281 Part number 88F6281...

  • Page 133: Package Marking

    11.2 Package Marking Figure 49 shows a sample Commercial package marking and pin 1 location for the 88F6281. Figure 49: Commercial Package Marking and Pin 1 Location Country of origin code (Contained in the mold ID or marked as the last line on the package.) Part number and die revision code...

  • Page 134: A Revision History

    88F6281 Hardware Specifications Revision History Table 75: Revision History R e v i s io n D a te December 2, 2008 1. In Figure 1, 88F6281 Pin Logic Diagram, on page note under the figure, stating that the pin is an input when used the MII/MMII Transmit Clock. 2.
  • Page 135 Table 75: Revision History (Continued) R e v i s io n D a te 17. In Table 36, Recommended Operating Conditions, on page • For VHV, revised the two parameters to VHV (during eFuse Burning mode) and VHV (during eFuse Reading mode) and added notes in the comments column for both VHV voltages.
  • Page 136 88F6281 Hardware Specifications Table 75: Revision History (Continued) R e v i s io n D a te 17. In Section 4.1, Multi-Purpose Pins Functional Summary, on page • Changed all references to MPP[0] and MPP[11] from GPI to GPIO. •...
  • Page 137 Table 75: Revision History (Continued) R e v i s io n D a te 38. Revised Figure 25, TWSI Output Delay AC Timing Diagram, on page 104 falling edge, as shown in the two tables that proceed the figure. 39.
  • Page 138 THIS PAGE IS INTENTIONALLY LEFT BLANK.
  • Page 140 Contact I NFORMATION Marvell Semiconductor, Inc. 5488 Marvell Lane Santa Clara, CA 95054, USA Tel: 1.408.222.2500 Fax: 1.408.752.9028 www.marvell.com Marvell. Moving Forward Faster...

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