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Pin No.
Pin Name
76
MDATA [15:0]
77
VSS
78
MDATA [15:0]
79
LDQM
80
UDQM
81
VDD
82
MWE
83
VSS
84
SD-CLK
85
SD-CAS
86
SD-RAS
87
VDD
88
SD-CS [1:0]
89
VSS
90
SD-CS [1:0]
91
VDD
92
EDO-CAS
93
VSS
94
EDO-RAS
95
VDD
96
MADDR [20:0]
97
VSS
98 to 100
MADDR [20:0]
101
VDD
102
MADDR [20:0]
103
VSS
104 to 106 MADDR [20:0]
107
VDD
108
MADDR [20:0]
109
VSS
110 to 112 MADDR [20:0]
113
VDD
114
MADDR [20:0]
115
VSS
116
MADDR [20:0]
117
VDD
118
MADDR [20:0]
119
VSS
120 to 122 MADDR [20:0]
123
VDD
124
MADDR [20:0]
125
VSS
126, 127
MADDR [20:0]
128
ROM-CS
129
PIO [10:0]
133
PIO [10:0]
134
VDD
136
VSS
138
PIO [10:0]
I/O
I/O
Memory address.
—
Ground for core logic and I/O signals.
I/O
Memory address.
O
SDRAM LDQM.
O
SDRAM UDQM.
—
3.3-V supply voltage for core logic and I/O signals.
O
SDRAM/EDO write enable. Decoder asserts active LOW to request a write operation
to the SDRAM array.
—
Ground for core logic and I/O signals.
O
SDRAM system clock.
O
Active LOW SDRAM column address.
O
Active LOW SDRAM row address.
—
3.3-V supply voltage for core logic and I/O signals.
O
Active LOW SDRAM bank select.
—
Ground for core logic and I/O signals.
O
Active LOW SDRAM bank select.
—
3.3-V supply voltage for core logic and I/O signals.
O
Active LOW EDO DRAM column address strobe.
—
Ground for core logic and I/O signals.
O
Active LOW EDO DRAM row address strobe.
—
3.3-V supply voltage for core logic and I/O signals.
O
Memory address.
—
Ground for core logic and I/O signals.
O
Memory address.
—
3.3-V supply voltage for core logic and I/O signals.
O
Memory address.
—
Ground for core logic and I/O signals.
O
Memory address.
—
3.3-V supply voltage for core logic and I/O signals.
O
Memory address.
—
Ground for core logic and I/O signals.
O
Memory address.
—
3.3-V supply voltage for core logic and I/O signals.
O
Memory address.
—
Ground for core logic and I/O signals.
O
Memory address.
—
3.3-V supply voltage for core logic and I/O signals.
O
Memory address.
—
Ground for core logic and I/O signals.
O
Memory address.
—
3.3-V supply voltage for core logic and I/O signals.
O
Memory address.
—
Ground for core logic and I/O signals.
O
Memory address.
O
ROM chip select. Open drain signal, must be pulled-up to 3.3 volts.
I/O
Programmable I/O pins.
I/O
Programmable I/O pins.
—
3.3-V supply voltage for core logic and I/O signals.
—
Ground for core logic and I/O signals.
I/O
Programmable I/O pins.
Function
57
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